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jzuckermanjzuckerman
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✨ support 2 memory tiles on VCU118 board
1 parent 23856d9 commit 5d1076f

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7 files changed

+332
-29
lines changed

7 files changed

+332
-29
lines changed

‎constraints/xilinx-vcu118-xcvu9p/mig.tcl

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,7 +3,7 @@
33
create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name mig
44

55
set_property -dict [list \
6-
CONFIG.C0_CLOCK_BOARD_INTERFACE {default_250mhz_clk1} \
6+
CONFIG.C0_CLOCK_BOARD_INTERFACE {Custom} \
77
CONFIG.C0.DDR4_TimePeriod {1600} \
88
CONFIG.C0.DDR4_InputClockPeriod {4000} \
99
CONFIG.C0.DDR4_CLKOUT0_DIVIDE {8} \

‎constraints/xilinx-vcu118-xcvu9p/xilinx-vcu118-xcvu9p-eth-constraints.xdc

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -11,6 +11,7 @@ set_false_path -to [get_pins -hier -filter { name =~ */reset_sync_*/*/PRE}]
1111

1212
# Recover clock names after elaboration
1313
set clkm_elab [get_clocks -of_objects [get_nets clkm]]
14+
set clkm_elab1 [get_clocks -of_objects [get_nets clkm1]]
1415
set refclk_elab [get_clocks -of_objects [get_nets chip_refclk]]
1516
set clk125m_elab [get_clocks -of_objects [get_nets -hierarchical clk125m]]
1617

@@ -19,3 +20,4 @@ set clk125m_elab [get_clocks -of_objects [get_nets -hierarchical clk125m]]
1920

2021
set_clock_groups -asynchronous -group [get_clocks ${clk125m_elab}] -group [get_clocks ${refclk_elab}]
2122
set_clock_groups -asynchronous -group [get_clocks ${clk125m_elab}] -group [get_clocks ${clkm_elab}]
23+
set_clock_groups -asynchronous -group [get_clocks ${clk125m_elab}] -group [get_clocks ${clkm_elab1}]

‎constraints/xilinx-vcu118-xcvu9p/xilinx-vcu118-xcvu9p-mig-pins.xdc

Lines changed: 120 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -119,3 +119,123 @@ set_property PACKAGE_PIN M20 [get_ports "c0_ddr4_dqs_t[6]"]
119119
set_property PACKAGE_PIN H24 [get_ports "c0_ddr4_dqs_t[7]"]
120120
set_property PACKAGE_PIN C8 [get_ports "c0_ddr4_odt"]
121121
set_property PACKAGE_PIN N20 [get_ports "c0_ddr4_reset_n"]
122+
123+
#-----------------------------------------------------------
124+
# DDR4 C1
125+
#-----------------------------------------------------------
126+
127+
set_property PACKAGE_PIN AN25 [get_ports "c1_ddr4_act_n"]
128+
set_property PACKAGE_PIN AM27 [get_ports "c1_ddr4_adr[0]"]
129+
set_property PACKAGE_PIN AR28 [get_ports "c1_ddr4_adr[10]"]
130+
set_property PACKAGE_PIN AR27 [get_ports "c1_ddr4_adr[11]"]
131+
set_property PACKAGE_PIN AV25 [get_ports "c1_ddr4_adr[12]"]
132+
set_property PACKAGE_PIN AT25 [get_ports "c1_ddr4_adr[13]"]
133+
set_property PACKAGE_PIN AV28 [get_ports "c1_ddr4_adr[14]"]
134+
set_property PACKAGE_PIN AU26 [get_ports "c1_ddr4_adr[15]"]
135+
set_property PACKAGE_PIN AV26 [get_ports "c1_ddr4_adr[16]"]
136+
set_property PACKAGE_PIN AL27 [get_ports "c1_ddr4_adr[1]"]
137+
set_property PACKAGE_PIN AP26 [get_ports "c1_ddr4_adr[2]"]
138+
set_property PACKAGE_PIN AP25 [get_ports "c1_ddr4_adr[3]"]
139+
set_property PACKAGE_PIN AN28 [get_ports "c1_ddr4_adr[4]"]
140+
set_property PACKAGE_PIN AM28 [get_ports "c1_ddr4_adr[5]"]
141+
set_property PACKAGE_PIN AP28 [get_ports "c1_ddr4_adr[6]"]
142+
set_property PACKAGE_PIN AP27 [get_ports "c1_ddr4_adr[7]"]
143+
set_property PACKAGE_PIN AN26 [get_ports "c1_ddr4_adr[8]"]
144+
set_property PACKAGE_PIN AM26 [get_ports "c1_ddr4_adr[9]"]
145+
set_property PACKAGE_PIN AR25 [get_ports "c1_ddr4_ba[0]"]
146+
set_property PACKAGE_PIN AU28 [get_ports "c1_ddr4_ba[1]"]
147+
set_property PACKAGE_PIN AU27 [get_ports "c1_ddr4_bg"]
148+
set_property PACKAGE_PIN AT27 [get_ports "c1_ddr4_ck_c"]
149+
set_property PACKAGE_PIN AT26 [get_ports "c1_ddr4_ck_t"]
150+
set_property PACKAGE_PIN AW28 [get_ports "c1_ddr4_cke"]
151+
set_property PACKAGE_PIN AY29 [get_ports "c1_ddr4_cs_n"]
152+
set_property PACKAGE_PIN BE32 [get_ports "c1_ddr4_dm_dbi_n[0]"]
153+
set_property PACKAGE_PIN BB31 [get_ports "c1_ddr4_dm_dbi_n[1]"]
154+
set_property PACKAGE_PIN AV33 [get_ports "c1_ddr4_dm_dbi_n[2]"]
155+
set_property PACKAGE_PIN AR32 [get_ports "c1_ddr4_dm_dbi_n[3]"]
156+
set_property PACKAGE_PIN BC34 [get_ports "c1_ddr4_dm_dbi_n[4]"]
157+
set_property PACKAGE_PIN BE40 [get_ports "c1_ddr4_dm_dbi_n[5]"]
158+
set_property PACKAGE_PIN AY37 [get_ports "c1_ddr4_dm_dbi_n[6]"]
159+
set_property PACKAGE_PIN AV35 [get_ports "c1_ddr4_dm_dbi_n[7]"]
160+
set_property PACKAGE_PIN BD30 [get_ports "c1_ddr4_dq[0]"]
161+
set_property PACKAGE_PIN BA30 [get_ports "c1_ddr4_dq[10]"]
162+
set_property PACKAGE_PIN BA31 [get_ports "c1_ddr4_dq[11]"]
163+
set_property PACKAGE_PIN AW31 [get_ports "c1_ddr4_dq[12]"]
164+
set_property PACKAGE_PIN AW32 [get_ports "c1_ddr4_dq[13]"]
165+
set_property PACKAGE_PIN AY32 [get_ports "c1_ddr4_dq[14]"]
166+
set_property PACKAGE_PIN AY33 [get_ports "c1_ddr4_dq[15]"]
167+
set_property PACKAGE_PIN AV30 [get_ports "c1_ddr4_dq[16]"]
168+
set_property PACKAGE_PIN AW30 [get_ports "c1_ddr4_dq[17]"]
169+
set_property PACKAGE_PIN AU33 [get_ports "c1_ddr4_dq[18]"]
170+
set_property PACKAGE_PIN AU34 [get_ports "c1_ddr4_dq[19]"]
171+
set_property PACKAGE_PIN BE30 [get_ports "c1_ddr4_dq[1]"]
172+
set_property PACKAGE_PIN AT31 [get_ports "c1_ddr4_dq[20]"]
173+
set_property PACKAGE_PIN AU32 [get_ports "c1_ddr4_dq[21]"]
174+
set_property PACKAGE_PIN AU31 [get_ports "c1_ddr4_dq[22]"]
175+
set_property PACKAGE_PIN AV31 [get_ports "c1_ddr4_dq[23]"]
176+
set_property PACKAGE_PIN AR33 [get_ports "c1_ddr4_dq[24]"]
177+
set_property PACKAGE_PIN AT34 [get_ports "c1_ddr4_dq[25]"]
178+
set_property PACKAGE_PIN AT29 [get_ports "c1_ddr4_dq[26]"]
179+
set_property PACKAGE_PIN AT30 [get_ports "c1_ddr4_dq[27]"]
180+
set_property PACKAGE_PIN AP30 [get_ports "c1_ddr4_dq[28]"]
181+
set_property PACKAGE_PIN AR30 [get_ports "c1_ddr4_dq[29]"]
182+
set_property PACKAGE_PIN BD32 [get_ports "c1_ddr4_dq[2]"]
183+
set_property PACKAGE_PIN AN30 [get_ports "c1_ddr4_dq[30]"]
184+
set_property PACKAGE_PIN AN31 [get_ports "c1_ddr4_dq[31]"]
185+
set_property PACKAGE_PIN BE34 [get_ports "c1_ddr4_dq[32]"]
186+
set_property PACKAGE_PIN BF34 [get_ports "c1_ddr4_dq[33]"]
187+
set_property PACKAGE_PIN BC35 [get_ports "c1_ddr4_dq[34]"]
188+
set_property PACKAGE_PIN BC36 [get_ports "c1_ddr4_dq[35]"]
189+
set_property PACKAGE_PIN BD36 [get_ports "c1_ddr4_dq[36]"]
190+
set_property PACKAGE_PIN BE37 [get_ports "c1_ddr4_dq[37]"]
191+
set_property PACKAGE_PIN BF36 [get_ports "c1_ddr4_dq[38]"]
192+
set_property PACKAGE_PIN BF37 [get_ports "c1_ddr4_dq[39]"]
193+
set_property PACKAGE_PIN BE33 [get_ports "c1_ddr4_dq[3]"]
194+
set_property PACKAGE_PIN BD37 [get_ports "c1_ddr4_dq[40]"]
195+
set_property PACKAGE_PIN BE38 [get_ports "c1_ddr4_dq[41]"]
196+
set_property PACKAGE_PIN BC39 [get_ports "c1_ddr4_dq[42]"]
197+
set_property PACKAGE_PIN BD40 [get_ports "c1_ddr4_dq[43]"]
198+
set_property PACKAGE_PIN BB38 [get_ports "c1_ddr4_dq[44]"]
199+
set_property PACKAGE_PIN BB39 [get_ports "c1_ddr4_dq[45]"]
200+
set_property PACKAGE_PIN BC38 [get_ports "c1_ddr4_dq[46]"]
201+
set_property PACKAGE_PIN BD38 [get_ports "c1_ddr4_dq[47]"]
202+
set_property PACKAGE_PIN BB36 [get_ports "c1_ddr4_dq[48]"]
203+
set_property PACKAGE_PIN BB37 [get_ports "c1_ddr4_dq[49]"]
204+
set_property PACKAGE_PIN BC33 [get_ports "c1_ddr4_dq[4]"]
205+
set_property PACKAGE_PIN BA39 [get_ports "c1_ddr4_dq[50]"]
206+
set_property PACKAGE_PIN BA40 [get_ports "c1_ddr4_dq[51]"]
207+
set_property PACKAGE_PIN AW40 [get_ports "c1_ddr4_dq[52]"]
208+
set_property PACKAGE_PIN AY40 [get_ports "c1_ddr4_dq[53]"]
209+
set_property PACKAGE_PIN AY38 [get_ports "c1_ddr4_dq[54]"]
210+
set_property PACKAGE_PIN AY39 [get_ports "c1_ddr4_dq[55]"]
211+
set_property PACKAGE_PIN AW35 [get_ports "c1_ddr4_dq[56]"]
212+
set_property PACKAGE_PIN AW36 [get_ports "c1_ddr4_dq[57]"]
213+
set_property PACKAGE_PIN AU40 [get_ports "c1_ddr4_dq[58]"]
214+
set_property PACKAGE_PIN AV40 [get_ports "c1_ddr4_dq[59]"]
215+
set_property PACKAGE_PIN BD33 [get_ports "c1_ddr4_dq[5]"]
216+
set_property PACKAGE_PIN AU38 [get_ports "c1_ddr4_dq[60]"]
217+
set_property PACKAGE_PIN AU39 [get_ports "c1_ddr4_dq[61]"]
218+
set_property PACKAGE_PIN AV38 [get_ports "c1_ddr4_dq[62]"]
219+
set_property PACKAGE_PIN AV39 [get_ports "c1_ddr4_dq[63]"]
220+
set_property PACKAGE_PIN BC31 [get_ports "c1_ddr4_dq[6]"]
221+
set_property PACKAGE_PIN BD31 [get_ports "c1_ddr4_dq[7]"]
222+
set_property PACKAGE_PIN BA32 [get_ports "c1_ddr4_dq[8]"]
223+
set_property PACKAGE_PIN BB33 [get_ports "c1_ddr4_dq[9]"]
224+
set_property PACKAGE_PIN BF31 [get_ports "c1_ddr4_dqs_c[0]"]
225+
set_property PACKAGE_PIN BA34 [get_ports "c1_ddr4_dqs_c[1]"]
226+
set_property PACKAGE_PIN AV29 [get_ports "c1_ddr4_dqs_c[2]"]
227+
set_property PACKAGE_PIN AP32 [get_ports "c1_ddr4_dqs_c[3]"]
228+
set_property PACKAGE_PIN BF35 [get_ports "c1_ddr4_dqs_c[4]"]
229+
set_property PACKAGE_PIN BF39 [get_ports "c1_ddr4_dqs_c[5]"]
230+
set_property PACKAGE_PIN BA36 [get_ports "c1_ddr4_dqs_c[6]"]
231+
set_property PACKAGE_PIN AW38 [get_ports "c1_ddr4_dqs_c[7]"]
232+
set_property PACKAGE_PIN BF30 [get_ports "c1_ddr4_dqs_t[0]"]
233+
set_property PACKAGE_PIN AY34 [get_ports "c1_ddr4_dqs_t[1]"]
234+
set_property PACKAGE_PIN AU29 [get_ports "c1_ddr4_dqs_t[2]"]
235+
set_property PACKAGE_PIN AP31 [get_ports "c1_ddr4_dqs_t[3]"]
236+
set_property PACKAGE_PIN BE35 [get_ports "c1_ddr4_dqs_t[4]"]
237+
set_property PACKAGE_PIN BE39 [get_ports "c1_ddr4_dqs_t[5]"]
238+
set_property PACKAGE_PIN BA35 [get_ports "c1_ddr4_dqs_t[6]"]
239+
set_property PACKAGE_PIN AW37 [get_ports "c1_ddr4_dqs_t[7]"]
240+
set_property PACKAGE_PIN BB29 [get_ports "c1_ddr4_odt"]
241+
set_property PACKAGE_PIN BD35 [get_ports "c1_ddr4_reset_n"]

‎constraints/xilinx-vcu118-xcvu9p/xilinx-vcu118-xcvu9p.xdc

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -18,18 +18,29 @@ set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_p]
1818
set_property PACKAGE_PIN D12 [get_ports c0_sys_clk_n]
1919
set_property IOSTANDARD DIFF_SSTL12 [get_ports c0_sys_clk_n]
2020

21+
set_property PACKAGE_PIN AW26 [get_ports c1_sys_clk_p]
22+
set_property IOSTANDARD DIFF_SSTL12 [get_ports c1_sys_clk_p]
23+
24+
set_property PACKAGE_PIN AW27 [get_ports c1_sys_clk_n]
25+
set_property IOSTANDARD DIFF_SSTL12 [get_ports c1_sys_clk_n]
26+
2127
set_property PACKAGE_PIN L19 [get_ports reset]
2228
set_property IOSTANDARD LVCMOS12 [get_ports reset]
2329

2430
create_clock -period 4.0 [get_ports c0_sys_clk_p]
2531
set_input_jitter [get_clocks -of_objects [get_ports c0_sys_clk_p]] 0.05
2632

33+
create_clock -period 4.0 [get_ports c1_sys_clk_p]
34+
set_input_jitter [get_clocks -of_objects [get_ports c1_sys_clk_p]] 0.05
35+
2736
# Recover elaborated clock name
2837
set clkm_elab [get_clocks -of_objects [get_nets clkm]]
38+
set clkm_elab1 [get_clocks -of_objects [get_nets clkm1]]
2939
set refclk_elab [get_clocks -of_objects [get_nets chip_refclk]]
3040

3141
# Declare asynchronous clocks
32-
set_clock_groups -asynchronous -group [get_clocks ${clkm_elab}] -group [get_clocks ${refclk_elab}]
42+
set_clock_groups -asynchronous -group [get_clocks ${clkm_elab}] -group [get_clocks ${refclk_elab}] \
43+
-group [get_clocks ${clkm_elab1}]
3344

3445

3546
# --- False paths

‎socs/xilinx-vcu118-xcvu9p/testbench.vhd

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -46,6 +46,22 @@ architecture behav of testbench is
4646
c0_ddr4_dq : inout std_logic_vector(63 downto 0);
4747
c0_ddr4_dqs_c : inout std_logic_vector(7 downto 0);
4848
c0_ddr4_dqs_t : inout std_logic_vector(7 downto 0);
49+
c1_sys_clk_p : in std_logic;
50+
c1_sys_clk_n : in std_logic;
51+
c1_ddr4_act_n : out std_logic;
52+
c1_ddr4_adr : out std_logic_vector(16 downto 0);
53+
c1_ddr4_ba : out std_logic_vector(1 downto 0);
54+
c1_ddr4_bg : out std_logic_vector(0 downto 0);
55+
c1_ddr4_cke : out std_logic_vector(0 downto 0);
56+
c1_ddr4_odt : out std_logic_vector(0 downto 0);
57+
c1_ddr4_cs_n : out std_logic_vector(0 downto 0);
58+
c1_ddr4_ck_t : out std_logic_vector(0 downto 0);
59+
c1_ddr4_ck_c : out std_logic_vector(0 downto 0);
60+
c1_ddr4_reset_n : out std_logic;
61+
c1_ddr4_dm_dbi_n : inout std_logic_vector(7 downto 0);
62+
c1_ddr4_dq : inout std_logic_vector(63 downto 0);
63+
c1_ddr4_dqs_c : inout std_logic_vector(7 downto 0);
64+
c1_ddr4_dqs_t : inout std_logic_vector(7 downto 0);
4965
gtrefclk_p : in std_logic;
5066
gtrefclk_n : in std_logic;
5167
txp : out std_logic;
@@ -71,6 +87,8 @@ architecture behav of testbench is
7187
signal reset : std_ulogic := '1';
7288
signal c0_sys_clk_p : std_logic := '0';
7389
signal c0_sys_clk_n : std_logic := '1';
90+
signal c1_sys_clk_p : std_logic := '0';
91+
signal c1_sys_clk_n : std_logic := '1';
7492

7593
-- DDR4
7694
signal c0_ddr4_act_n : std_logic;
@@ -87,6 +105,20 @@ architecture behav of testbench is
87105
signal c0_ddr4_dq : std_logic_vector(63 downto 0);
88106
signal c0_ddr4_dqs_c : std_logic_vector(7 downto 0);
89107
signal c0_ddr4_dqs_t : std_logic_vector(7 downto 0);
108+
signal c1_ddr4_act_n : std_logic;
109+
signal c1_ddr4_adr : std_logic_vector(16 downto 0);
110+
signal c1_ddr4_ba : std_logic_vector(1 downto 0);
111+
signal c1_ddr4_bg : std_logic_vector(0 downto 0);
112+
signal c1_ddr4_cke : std_logic_vector(0 downto 0);
113+
signal c1_ddr4_odt : std_logic_vector(0 downto 0);
114+
signal c1_ddr4_cs_n : std_logic_vector(0 downto 0);
115+
signal c1_ddr4_ck_t : std_logic_vector(0 downto 0);
116+
signal c1_ddr4_ck_c : std_logic_vector(0 downto 0);
117+
signal c1_ddr4_reset_n : std_logic;
118+
signal c1_ddr4_dm_dbi_n : std_logic_vector(7 downto 0);
119+
signal c1_ddr4_dq : std_logic_vector(63 downto 0);
120+
signal c1_ddr4_dqs_c : std_logic_vector(7 downto 0);
121+
signal c1_ddr4_dqs_t : std_logic_vector(7 downto 0);
90122

91123
-- SGMII Ethernet
92124
signal gtrefclk_p : std_logic := '0';
@@ -119,12 +151,18 @@ begin
119151
reset <= '0' after 2500 ns;
120152
c0_sys_clk_p <= not c0_sys_clk_p after 2 ns;
121153
c0_sys_clk_n <= not c0_sys_clk_n after 2 ns;
154+
c1_sys_clk_p <= not c1_sys_clk_p after 2 ns;
155+
c1_sys_clk_n <= not c1_sys_clk_n after 2 ns;
122156

123157
-- DDR4 (memory simulation model does not emulate DDR behavior)
124158
c0_ddr4_dm_dbi_n <= (others => 'Z');
125159
c0_ddr4_dq <= (others => 'Z');
126160
c0_ddr4_dqs_c <= (others => 'Z');
127161
c0_ddr4_dqs_t <= (others => 'Z');
162+
c1_ddr4_dm_dbi_n <= (others => 'Z');
163+
c1_ddr4_dq <= (others => 'Z');
164+
c1_ddr4_dqs_c <= (others => 'Z');
165+
c1_ddr4_dqs_t <= (others => 'Z');
128166

129167
-- Ethernet (We do not simulate any model of the PHY to speedup RTL simulation)
130168
gtrefclk_p <= not gtrefclk_p after 800 ps;
@@ -163,6 +201,22 @@ begin
163201
c0_ddr4_dq => c0_ddr4_dq,
164202
c0_ddr4_dqs_c => c0_ddr4_dqs_c,
165203
c0_ddr4_dqs_t => c0_ddr4_dqs_t,
204+
c1_sys_clk_p => c1_sys_clk_p,
205+
c1_sys_clk_n => c1_sys_clk_n,
206+
c1_ddr4_act_n => c1_ddr4_act_n,
207+
c1_ddr4_adr => c1_ddr4_adr,
208+
c1_ddr4_ba => c1_ddr4_ba,
209+
c1_ddr4_bg => c1_ddr4_bg,
210+
c1_ddr4_cke => c1_ddr4_cke,
211+
c1_ddr4_odt => c1_ddr4_odt,
212+
c1_ddr4_cs_n => c1_ddr4_cs_n,
213+
c1_ddr4_ck_t => c1_ddr4_ck_t,
214+
c1_ddr4_ck_c => c1_ddr4_ck_c,
215+
c1_ddr4_reset_n => c1_ddr4_reset_n,
216+
c1_ddr4_dm_dbi_n => c1_ddr4_dm_dbi_n,
217+
c1_ddr4_dq => c1_ddr4_dq,
218+
c1_ddr4_dqs_c => c1_ddr4_dqs_c,
219+
c1_ddr4_dqs_t => c1_ddr4_dqs_t,
166220
gtrefclk_p => gtrefclk_p,
167221
gtrefclk_n => gtrefclk_n,
168222
txp => txp,

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