From 4c1585d1ee97ec8973a6b6fc52d3cc67d036eb79 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 11:03:22 -0700 Subject: [PATCH 01/12] Better numpy install --- test/test-pypl.sh | 2 +- test/test-regress.sh | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/test/test-pypl.sh b/test/test-pypl.sh index 450a3f3..1b21d6c 100755 --- a/test/test-pypl.sh +++ b/test/test-pypl.sh @@ -63,7 +63,7 @@ fftgen=$(cd $test/..; pwd) # Need numpy for python part of perl v. python tests # FIXME/TODO when we get rid of the python option this is no longer necessary. -pip install numpy || echo "Could not install numpy, maybe that's okay" +python -c 'import numpy' || pip install numpy || echo "Could not install numpy, maybe that's okay" ########################################################################## # --gold => 8-point fft with summary results diff --git a/test/test-regress.sh b/test/test-regress.sh index dd3134c..c9ea9fb 100755 --- a/test/test-regress.sh +++ b/test/test-regress.sh @@ -57,7 +57,7 @@ source $fftgen/bin/setup_genesis.sh # Need numpy for comparison with python sim maybe # FIXME/TODO when we get rid of the python option this is no longer necessary. -pip install numpy || echo "Could not install numpy, maybe that's okay" +python -c 'import numpy' || pip install numpy || echo "Could not install numpy, maybe that's okay" # See if fpu is up to date # TODO/FIXME this (rtl/fpu_snapshot) should really be a submodule, yes? From 1dd2709d463c9958574493fd1a7a0eca542f2781 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 11:04:18 -0700 Subject: [PATCH 02/12] added a README for the test dir --- test/README.txt | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 test/README.txt diff --git a/test/README.txt b/test/README.txt new file mode 100644 index 0000000..f7647ba --- /dev/null +++ b/test/README.txt @@ -0,0 +1,40 @@ +# TO RUN ALL TESTS MAYBE, DO THIS MAYBE +source /nobackup/steveri/garnet_venv/bin/activate +testall.sh |& tee tmp.log | less + + +======================================================================== +NOTES + +ref: /nobackup/steveri/github/fftgen/.github/workflows/CI.yml + +TESTS in CI.yml: test-summary.sh? +- cd bin/simv_analysis; make test +- all it does is it just +-- takes the pre-built log of an fft run +-- runs it through a (perl!) filter to make a readable summary +-- compares the summary to a gold model `exampes/analysis_results.txt` + +------------------------------------------------------------------------ +TESTS in CI.yml: test-pypl.sh --gold8 +- build and test an 8-point fft, compare to cached fftgen results + +TESTS in CI.yml: test-pypl.sh --comp16 +- verify perl and python models get same answer for 16-point FFT + +# TESTS in CI.yml: test-regress.sh -sim verilator --perl +- exhaustive regression test, perl version + +# TESTS in CI.yml: test-regress.sh -sim verilator --python +- exhaustive regression test, python version + + +# OLD i think +# ------------------------------------------------------------------------ +# TESTS in CI.yml: regressions.sh --perl? +# - bin/golden_test.sh --perl -sim verilator > log +# - egrep 'FAIL|ERR' test_results.log +# +# TESTS in CI.yml: regressions.sh --python? +# - bin/golden_test.sh --python -sim verilator > log +# - egrep 'FAIL|ERR' test_results.log From 7c98e024a69bed3507ab4f91e309848c6c4ad38a Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 12:43:08 -0700 Subject: [PATCH 03/12] progress is made, snapshot is tooken --- rtl/fftram.vp | 53 ++++++++++++++++++++++++++++++++++++--------------- 1 file changed, 38 insertions(+), 15 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 94309c7..24a00b6 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -458,37 +458,60 @@ module `mname` // wz signals. If Anyone wants to access a given bank n (op1_bnum==1), // set wz(n) (to zero), unless suppress_wz says not to. - //;# The timing changes according to whether we have a 1port or a 2port SRAM. - //; my ($wz_event, $wz_value); - //; + //;# The timing changes according to whether we have a 1port or a 2port SRAM (note dpump = 2 ports) + //; my ($wz_event, $wz_value, $ass); + + //; # DEFAULT for if n_sram_ports != 1 (see below) + //; $wz_event = "clk_i"; + //; $wz_value = "clk_i"; + //; $ass = "<="; + //; my ($open_paren, $close_paren) = ("(", ")"); # Yeah, this is readable. //; for (my $snum=0; $snum<$nbanks; $snum++) { //; my $sram = sprintf("SRAM%03d", $snum); - //; if ($n_sram_ports == 2) { - //; $wz_event = "clk_i"; - //; $wz_value = "clk_i"; - //; } - //; elsif ($n_sram_ports == 1) { + +//; # //; # Hum notice this if-elsif loop-invariant :( +//; # //; # Oops not quite there's a $snum down there isnt it +//; # //; # Hum also maybe it should be if-else not if-elsif hum +//; # //; if ($n_sram_ports == 2) { +//; # //; $wz_event = "clk_i"; +//; # //; $wz_value = "clk_i"; +//; # //; $ass = "<="; +//; # //; } + + //; if ($n_sram_ports == 1) { //; $wz_event = "posedge clk_i"; //; $wz_value = "suppress_wz_i[$snum]"; + //; $ass = "="; //; } + + + + + //; my $rcb = ""; # Random Code Block + //; my $i; for ($i=0; $i < ($nunits-1); $i++) { + //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; + //; } + //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; + //; $rcb = "${rcb} )) begin\n"; + //; $rcb = "${rcb} ${sram}_wz $ass $wz_value ? 1 : 0;\n"; //; + //; # E.g. rcb= + //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) | + //; # (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 ) + //; # )) begin + //; # SRAM000_wz ? 1 : 0; //; # Yet another terrible hack //; # Some configs work only w blocking assignments and others w non-blocking :( //; # $ass = "="; # ver: 1port 2port ~dpump; vcs 1port 2port dpump //; # $ass = "<="; # ver: ~1port 2port dpump; vcs ~1port 2port dpump -//; my $ass = ($SRAM_TYPE eq "TRUE_1PORT") ? "=" : "<="; +//; # my $ass = ($SRAM_TYPE eq "TRUE_1PORT") ? "=" : "<="; always @ (`$wz_event`) begin if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz `$ass` 1'b1; else if ( fft_started & ( - //; my $i; for ($i=0; $i < ($nunits-1); $i++) { - //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; - //; } - //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; - //; print " )) begin\n"; - //; print " ${sram}_wz $ass $wz_value ? 1 : 0;\n"; + //; print $rcb; //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); From e609e3d17bd5b7b143766eb3072b07385568dd1d Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 13:49:48 -0700 Subject: [PATCH 04/12] progress made, snapshot tooked --- rtl/fftram.vp | 41 ++++++++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 24a00b6..c1ca605 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -459,42 +459,35 @@ module `mname` // set wz(n) (to zero), unless suppress_wz says not to. //;# The timing changes according to whether we have a 1port or a 2port SRAM (note dpump = 2 ports) - //; my ($wz_event, $wz_value, $ass); - //; # DEFAULT for if n_sram_ports != 1 (see below) - //; $wz_event = "clk_i"; - //; $wz_value = "clk_i"; - //; $ass = "<="; - //; my ($open_paren, $close_paren) = ("(", ")"); # Yeah, this is readable. - //; for (my $snum=0; $snum<$nbanks; $snum++) { - //; my $sram = sprintf("SRAM%03d", $snum); -//; # //; # Hum notice this if-elsif loop-invariant :( -//; # //; # Oops not quite there's a $snum down there isnt it -//; # //; # Hum also maybe it should be if-else not if-elsif hum -//; # //; if ($n_sram_ports == 2) { + //; # DEFAULT values for if n_sram_ports != 1 (see below) + //; my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); + //; # //; $wz_event = "clk_i"; //; # //; $wz_value = "clk_i"; //; # //; $ass = "<="; -//; # //; } +//; # //; my ($open_paren, $close_paren) = ("(", ")"); # Yeah, this is readable /s + //; for (my $snum=0; $snum<$nbanks; $snum++) { + //; my $sram = sprintf("SRAM%03d", $snum); + + //; my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); //; if ($n_sram_ports == 1) { //; $wz_event = "posedge clk_i"; //; $wz_value = "suppress_wz_i[$snum]"; //; $ass = "="; + //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); //; } - - - //; my $rcb = ""; # Random Code Block //; my $i; for ($i=0; $i < ($nunits-1); $i++) { //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; //; } //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; //; $rcb = "${rcb} )) begin\n"; - //; $rcb = "${rcb} ${sram}_wz $ass $wz_value ? 1 : 0;\n"; + //; $rcb = "${rcb} $wz_assign;\n"; //; //; # E.g. rcb= //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) | @@ -700,3 +693,17 @@ endmodule // Genesis2 is patent pending. For information regarding the patent please // contact the Stanford Technology Licensing Office. /////////////////////////////////////////////////////////////////////////////// + + + + +//; # //; # Hum notice this if-elsif loop-invariant :( +//; # //; # Oops not quite there's a $snum down there isnt it +//; # //; # Hum also maybe it should be if-else not if-elsif hum +//; # //; if ($n_sram_ports == 2) { +//; # //; $wz_event = "clk_i"; +//; # //; $wz_value = "clk_i"; +//; # //; $ass = "<="; +//; # //; } + + From 98dd2dbf4706806bf7fdc330c74733cde278c685 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 16:43:07 -0700 Subject: [PATCH 05/12] progress made, snapshot did takened --- rtl/fftram.vp | 56 ++++++++++++++++++++++++++++++++++++++------------- 1 file changed, 42 insertions(+), 14 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index c1ca605..5cd916f 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -470,6 +470,25 @@ module `mname` //; # //; $ass = "<="; //; # //; my ($open_paren, $close_paren) = ("(", ")"); # Yeah, this is readable /s + //; # E.g. codeblock1(2, 0) prints this: + //; # " (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" + //; # " (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" + //; # " )) begin" + //; # " SRAM000_wz ? 1 : 0;" + //; + //; sub codeblock1 { + //; my $nunits = shift; # E.g. 0, 1, 2, ... + //; my $snum = shift; # E.g. 0, 1, 2, ... + //; for (my $i=0; $i < $nunits; $i++) { + //; if ($i < $nunits-1) { + //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; + //; } else { + //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; + //; } + //; } + //; print " )) begin\n"; + //; } + //; for (my $snum=0; $snum<$nbanks; $snum++) { //; my $sram = sprintf("SRAM%03d", $snum); @@ -481,19 +500,17 @@ module `mname` //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); //; } - //; my $rcb = ""; # Random Code Block - //; my $i; for ($i=0; $i < ($nunits-1); $i++) { - //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; - //; } - //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; - //; $rcb = "${rcb} )) begin\n"; - //; $rcb = "${rcb} $wz_assign;\n"; - //; - //; # E.g. rcb= - //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) | - //; # (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 ) - //; # )) begin - //; # SRAM000_wz ? 1 : 0; + + +//; # //; my $rcb = ""; # Random Code Block +//; # //; my $i; for ($i=0; $i < ($nunits-1); $i++) { +//; # //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; +//; # //; } +//; # //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; +//; # //; $rcb = "${rcb} )) begin\n"; +//; # //; $rcb = "${rcb} $wz_assign;\n"; + + //; # Yet another terrible hack //; # Some configs work only w blocking assignments and others w non-blocking :( @@ -504,7 +521,18 @@ module `mname` always @ (`$wz_event`) begin if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz `$ass` 1'b1; else if ( fft_started & ( - //; print $rcb; + + //; # print $rcb; + + //; # for (my $snum=0; $snum<$nbanks; $snum++) { + //; # my $sram = sprintf("SRAM%03d", $snum); + //; # my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); + //; codeblock1($nunits, $snum); + //; print(" $wz_assign;\n"); + //; # } + + + //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); From ec6c1ae960dff7ce8d66a576cebf6916b2be4ff0 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 16:53:19 -0700 Subject: [PATCH 06/12] progress=>snapshot --- rtl/fftram.vp | 35 ++++++++--------------------------- 1 file changed, 8 insertions(+), 27 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 5cd916f..e4e9f26 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -465,11 +465,6 @@ module `mname` //; # DEFAULT values for if n_sram_ports != 1 (see below) //; my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); -//; # //; $wz_event = "clk_i"; -//; # //; $wz_value = "clk_i"; -//; # //; $ass = "<="; -//; # //; my ($open_paren, $close_paren) = ("(", ")"); # Yeah, this is readable /s - //; # E.g. codeblock1(2, 0) prints this: //; # " (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" //; # " (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" @@ -486,7 +481,6 @@ module `mname` //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; //; } //; } - //; print " )) begin\n"; //; } //; for (my $snum=0; $snum<$nbanks; $snum++) { @@ -500,18 +494,6 @@ module `mname` //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); //; } - - -//; # //; my $rcb = ""; # Random Code Block -//; # //; my $i; for ($i=0; $i < ($nunits-1); $i++) { -//; # //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; -//; # //; } -//; # //; $rcb = "${rcb} (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; -//; # //; $rcb = "${rcb} )) begin\n"; -//; # //; $rcb = "${rcb} $wz_assign;\n"; - - - //; # Yet another terrible hack //; # Some configs work only w blocking assignments and others w non-blocking :( //; # $ass = "="; # ver: 1port 2port ~dpump; vcs 1port 2port dpump @@ -522,17 +504,16 @@ module `mname` if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz `$ass` 1'b1; else if ( fft_started & ( - //; # print $rcb; + //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" + //; # (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" + //; # )) begin + //; # SRAM000_wz ? 1 : 0; - //; # for (my $snum=0; $snum<$nbanks; $snum++) { - //; # my $sram = sprintf("SRAM%03d", $snum); - //; # my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); //; codeblock1($nunits, $snum); - //; print(" $wz_assign;\n"); - //; # } - - - + )) begin + `$wz_assign`; + + //; # print(" $wz_assign;\n"); //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); From fab710c0e49d53545dbf1c85327508e9b8c57916 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 17:09:42 -0700 Subject: [PATCH 07/12] progress=>snapshot --- rtl/fftram.vp | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index e4e9f26..1dccd39 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -460,29 +460,30 @@ module `mname` //;# The timing changes according to whether we have a 1port or a 2port SRAM (note dpump = 2 ports) - - //; # DEFAULT values for if n_sram_ports != 1 (see below) //; my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); //; # E.g. codeblock1(2, 0) prints this: //; # " (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" //; # " (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" - //; # " )) begin" - //; # " SRAM000_wz ? 1 : 0;" //; //; sub codeblock1 { - //; my $nunits = shift; # E.g. 0, 1, 2, ... - //; my $snum = shift; # E.g. 0, 1, 2, ... - //; for (my $i=0; $i < $nunits; $i++) { - //; if ($i < $nunits-1) { - //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; - //; } else { - //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; - //; } - //; } + //; my ($nunits, $snum) = @_; + +//; # //; for (my $i=0; $i < $nunits-1; $i++) { +//; # //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; +//; # //; } +//; # //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; + + //; my @codeblock; + //; for (my $i=0; $i < $nunits; $i++) { + //; @codeblock[$i] = " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )"; + //; } + //; print join(" |\n", @codeblock); + //; } + //; for (my $snum=0; $snum<$nbanks; $snum++) { //; my $sram = sprintf("SRAM%03d", $snum); From 89a7205c31f9245d6c358a1a1d08bf0fd2be2c9d Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 17:22:10 -0700 Subject: [PATCH 08/12] progress=>snapshot ii --- rtl/fftram.vp | 24 +++++++++--------------- 1 file changed, 9 insertions(+), 15 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 1dccd39..c7baadc 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -461,7 +461,8 @@ module `mname` //;# The timing changes according to whether we have a 1port or a 2port SRAM (note dpump = 2 ports) //; # DEFAULT values for if n_sram_ports != 1 (see below) - //; my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); + //; # my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); + //; my ($wz_event, $wz_value) = ("clk_i", "clk_i"); //; # E.g. codeblock1(2, 0) prints this: //; # " (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" @@ -469,30 +470,23 @@ module `mname` //; //; sub codeblock1 { //; my ($nunits, $snum) = @_; - -//; # //; for (my $i=0; $i < $nunits-1; $i++) { -//; # //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum ) |\n"; -//; # //; } -//; # //; print " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )\n"; - //; my @codeblock; //; for (my $i=0; $i < $nunits; $i++) { //; @codeblock[$i] = " (BFLY${i}_op1_bnum_i == $snum ) | (BFLY${i}_op2_bnum_i == $snum )"; //; } //; print join(" |\n", @codeblock); - //; } - //; for (my $snum=0; $snum<$nbanks; $snum++) { //; my $sram = sprintf("SRAM%03d", $snum); - - //; my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); + //; my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); # async for 2port, dpump + //; my $wz_reset = sprintf("${sram}_wz <= 1'b1"); # async for 2port, dpump //; if ($n_sram_ports == 1) { //; $wz_event = "posedge clk_i"; //; $wz_value = "suppress_wz_i[$snum]"; - //; $ass = "="; - //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); + //; # $ass = "="; + //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); # sync for 2port, dpump + //; $wz_reset = sprintf("${sram}_wz = 1'b1"); # sync for 2port, dpump //; } //; # Yet another terrible hack @@ -502,7 +496,7 @@ module `mname` //; # my $ass = ($SRAM_TYPE eq "TRUE_1PORT") ? "=" : "<="; always @ (`$wz_event`) begin - if (cycle_num == `$nbits_cycle_num`'b0) `${sram}`_wz `$ass` 1'b1; else + if (cycle_num == `$nbits_cycle_num`'b0) `$wz_reset`; else if ( fft_started & ( //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" @@ -534,7 +528,7 @@ module `mname` //; } end else begin - `${sram}`_wz `$ass` 1'b1; + `$wz_reset`; end end //; } From b768cbe3c573c74b4766708b2285873727cd1928 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 26 Jun 2025 18:33:04 -0700 Subject: [PATCH 09/12] progress=>snapshot iii --- rtl/fftram.vp | 31 ++++++++++--------------------- 1 file changed, 10 insertions(+), 21 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index c7baadc..ebbe4a7 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -461,8 +461,6 @@ module `mname` //;# The timing changes according to whether we have a 1port or a 2port SRAM (note dpump = 2 ports) //; # DEFAULT values for if n_sram_ports != 1 (see below) - //; # my ($wz_event, $wz_value, $ass) = ("clk_i", "clk_i", "<="); - //; my ($wz_event, $wz_value) = ("clk_i", "clk_i"); //; # E.g. codeblock1(2, 0) prints this: //; # " (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" @@ -479,37 +477,28 @@ module `mname` //; for (my $snum=0; $snum<$nbanks; $snum++) { //; my $sram = sprintf("SRAM%03d", $snum); - //; my $wz_assign = sprintf("${sram}_wz <= clk_i ? 1 : 0"); # async for 2port, dpump - //; my $wz_reset = sprintf("${sram}_wz <= 1'b1"); # async for 2port, dpump + + //; # async for 2port (inc. dpump) + //; my ($wz_event, $wz_value) = ("clk_i", "clk_i"); + //; my $wz_assign = "${sram}_wz <= $wz_value ? 1 : 0"; + //; my $wz_reset = "${sram}_wz <= 1'b1"; + + //; # sync for 1port //; if ($n_sram_ports == 1) { - //; $wz_event = "posedge clk_i"; - //; $wz_value = "suppress_wz_i[$snum]"; - //; # $ass = "="; - //; $wz_assign = sprintf("${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"); # sync for 2port, dpump - //; $wz_reset = sprintf("${sram}_wz = 1'b1"); # sync for 2port, dpump + //; ($wz_event, $wz_value) = ("posedge clk_i", "suppress_wz_i[$snum]"); + //; $wz_assign = "${sram}_wz = $wz_value ? 1 : 0"; + //; $wz_reset = "${sram}_wz = 1'b1"; //; } -//; # Yet another terrible hack -//; # Some configs work only w blocking assignments and others w non-blocking :( -//; # $ass = "="; # ver: 1port 2port ~dpump; vcs 1port 2port dpump -//; # $ass = "<="; # ver: ~1port 2port dpump; vcs ~1port 2port dpump -//; # my $ass = ($SRAM_TYPE eq "TRUE_1PORT") ? "=" : "<="; - always @ (`$wz_event`) begin if (cycle_num == `$nbits_cycle_num`'b0) `$wz_reset`; else if ( fft_started & ( - //; # (BFLY0_op1_bnum_i == 0 ) | (BFLY0_op2_bnum_i == 0 ) |" //; # (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" - //; # )) begin - //; # SRAM000_wz ? 1 : 0; - //; codeblock1($nunits, $snum); )) begin `$wz_assign`; - //; # print(" $wz_assign;\n"); - //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); From 1704f3b316441d3805b78547c75c174c8efa1f1c Mon Sep 17 00:00:00 2001 From: steveri Date: Fri, 27 Jun 2025 07:52:03 -0700 Subject: [PATCH 10/12] progress=>snapshot iv --- rtl/fftram.vp | 58 ++------------------------------------------------- 1 file changed, 2 insertions(+), 56 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index ebbe4a7..6cf03ce 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -144,10 +144,7 @@ module `mname` logic [`$rbits`] `$sname`_ix; logic [`$op_width-1`:0] `$sname`_rd_data; logic [`$op_width-1`:0] `$sname`_wr_data; logic `$sname`_ez; logic `$sname`_wz; //; } - - //; # no longer optional i guess, everyone needs cycle_num...right? FIXME - //; # if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { - //; if (1 == 1) { + // Trying something new for bypasses: BOTF (bypass on the fly) // (For now) BOTF: must duplicate fftctl's 'cycle_num' signal so we // can conservatively BYPASS ALL FINAL-CYCLE WRITES in a each stage. // FIXME Really shouldn't bypass final-stage writes!!! @@ -156,12 +153,10 @@ module `mname` // Need to count from 0 to [log2(npoints) x (npoints/2) / (nbutts)] // plus at least one beyond that. logic [`$nbits_cycle_num-1`:0] cycle_num; + //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF logic bypass_time; // Bypass_time==1 when cycle_time says it is time to bypass. //; } - //; } else { - // Placeholder for optional BOTF signals, unused in this configuration (cycle_num). - //; } //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { // E.g. SRAM001_active=1 during any cycle that we're accessing SRAM001 (BOTF). @@ -173,20 +168,6 @@ module `mname` // Placeholder for optional BOTF signals, unused in this configuration (SRAM003_active). //; } -//;# //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { -//;# // Trying something new for bypasses: BOTF (bypass on the fly) -//;# //; # logic SRAM000_wants_to_read_then_write; -//;# //; # logic SRAM001_wants_to_read_then_write; -//;# //; # logic SRAM002_wants_to_read_then_write; -//;# //; # ... -//;# //; for (my $i=0; $i<$nbanks; $i++) { -//;# //; my $sname = sprintf("SRAM%03d", $i); # "000", "001", ... "015" etc. -//;# logic `$sname`_wants_to_read_then_write; -//;# //; } -//;# //; } else { -//;# // Placeholder for optional BOTF signals, unused in this configuration. -//;# //; } - //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { // BOTF: At end of each stage, there is possibility of read/write // conflict where one butterfly wants to write to the (single ported) @@ -419,41 +400,6 @@ module `mname` // Placeholder for optional BOTF signals, unused in this configuration. //; } - -//;# unused/old? -//;# //; if ($BYPASS_MECHANISM eq 'old') { -//;# ////////////////////////////////////////////////////////////////////////////////// -//;# // If suppress_wz was set (at posedge clk above), we suppress write to the -//;# // indicated SRAM. Contents originally destined for SRAM now go to bypass_buffer. -//;# -//;# // If I were more paranoid, maybe each case would get its own "@ (negedge clk)"? -//;# always @ (posedge clk_i) begin -//;# //;# -//;# //;# if (suppress_wz[ 0]) bypass_buffer[bufnum_i[ 0]] <= SRAM000_wr_data; -//;# //;# if (suppress_wz[ 1]) bypass_buffer[bufnum_i[ 1]] <= SRAM001_wr_data; -//;# //;# ... -//;# //;# if (suppress_wz[15]) bypass_buffer[bufnum_i[15]] <= SRAM015_wr_data; -//;# -//;# // TODO again, replace ugly repetitive $display w/a task. -//;# // if nunits == 1 this (suppress_wz) is one-hot (or zero) -//;# //; for (my $i = 0; $i < $nbanks; $i++) { -//;# //; my $nn = sprintf("%2d", $i); -//;# //; my $nnn = sprintf("%03d", $i); -//;# //; my $bufnum = ($nunits==1) ? "" : "[bufnum_i[$nn]]"; -//;# //; my $bufnum2 = ($nunits==1) ? "0" : "bufnum_i[$nn]"; -//;# if (suppress_wz_i[`$nn`]) begin -//;# bypass_buffer`$bufnum` <= SRAM`$nnn`_wr_data; -//;# $display("fftram %6d Bypassed SRAM `$i`, wrote (bsr'%08X,bsr'%08X) to bypass_buffer[%1d]", -//;# $time, `ri("SRAM${nnn}_wr_data")`, `$bufnum2`); -//;# end -//;# //; } -//;# end -//;# //; } else { -//;# // LOOK MA NO BYPASS BUFFER mano mano -//;# //; } -//;# unused/old? - // LOOK MA NO BYPASS BUFFER mano mano - ////////////////////////////////////////////////////////////////////////////// // wz signals. If Anyone wants to access a given bank n (op1_bnum==1), // set wz(n) (to zero), unless suppress_wz says not to. From 802595064c65176157e16b7b2a1930f3a2f456c5 Mon Sep 17 00:00:00 2001 From: steveri Date: Fri, 27 Jun 2025 09:32:09 -0700 Subject: [PATCH 11/12] progress=>snapshot v --- rtl/fftram.vp | 87 +++++++++++++++++++-------------------------------- 1 file changed, 33 insertions(+), 54 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 6cf03ce..e9473a0 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -144,39 +144,34 @@ module `mname` logic [`$rbits`] `$sname`_ix; logic [`$op_width-1`:0] `$sname`_rd_data; logic [`$op_width-1`:0] `$sname`_wr_data; logic `$sname`_ez; logic `$sname`_wz; //; } - // Trying something new for bypasses: BOTF (bypass on the fly) - // (For now) BOTF: must duplicate fftctl's 'cycle_num' signal so we - // can conservatively BYPASS ALL FINAL-CYCLE WRITES in a each stage. - // FIXME Really shouldn't bypass final-stage writes!!! - // FIXME Later, can just bring 'cycle_num' (below) in from fftctl as a signal. - // FIXME Or something smarter. - // Need to count from 0 to [log2(npoints) x (npoints/2) / (nbutts)] - // plus at least one beyond that. logic [`$nbits_cycle_num-1`:0] cycle_num; -//; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF + //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF + //; + // Trying something new for bypasses: BOTF (bypass on the fly) + // (For now) BOTF: must duplicate fftctl's 'cycle_num' signal so we + // can conservatively BYPASS ALL FINAL-CYCLE WRITES in a each stage. + // FIXME Really shouldn't bypass final-stage writes!!! + // FIXME Later, can just bring 'cycle_num' (below) in from fftctl as a signal. + // FIXME Or something smarter. + // Need to count from 0 to [log2(npoints) x (npoints/2) / (nbutts)] + // plus at least one beyond that. logic bypass_time; // Bypass_time==1 when cycle_time says it is time to bypass. -//; } - //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { - // E.g. SRAM001_active=1 during any cycle that we're accessing SRAM001 (BOTF). - //; for (my $i=0; $i<$nbanks; $i++) { - //; my $sname = sprintf("SRAM%03d", $i); # "000", "001", ... "015" etc. + // BOTF: E.g. SRAM001_active=1 during any cycle that we're accessing SRAM001 + //; for (my $i=0; $i<$nbanks; $i++) { + //; my $sname = sprintf("SRAM%03d", $i); # "000", "001", ... "015" etc. logic `$sname`_active; - //; } - //; } else { - // Placeholder for optional BOTF signals, unused in this configuration (SRAM003_active). - //; } - - //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { - // BOTF: At end of each stage, there is possibility of read/write - // conflict where one butterfly wants to write to the (single ported) - // SRAM at the same time another one wants to read from the SRAM. - // When this happens, bypass the write data to the 'bypassed_data' buffer. - //; my $nsrams = $nbanks; - //; my $r1 = sprintf("%-6s", ""); - //; my $r2 = sprintf("%-6s", "[$rbits]"); - //; my $r3 = sprintf("%-6s", "[$obits]"); + //; } + //; + // BOTF: At end of each stage, there is possibility of read/write + // conflict where one butterfly wants to write to the (single ported) + // SRAM at the same time another one wants to read from the SRAM. + // When this happens, bypass the write data to the 'bypassed_data' buffer. + //; my $nsrams = $nbanks; + //; my $r1 = sprintf("%-6s", ""); + //; my $r2 = sprintf("%-6s", "[$rbits]"); + //; my $r3 = sprintf("%-6s", "[$obits]"); //; logic `$r1` bypass_valid[0:`$nsrams-1`]; // True (1) iff bypassed_data is valid logic `$r2` bypassed_rnum[0:`$nsrams-1`]; // Use target row number (index) of valid data as an ID. @@ -230,22 +225,6 @@ module `mname` // LOOK MA NO BYPASS BUFFER //; } -//;# //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { -//;# // Initialize BOTF (bypass on the fly) signals -//;# //; # SRAM000_wants_to_read_then_write <= 0; -//;# //; # SRAM001_wants_to_read_then_write <= 0; -//;# //; # SRAM002_wants_to_read_then_write <= 0; -//;# //; # ... -//;# initial begin -//;# //; for (my $i=0; $i<$nbanks; $i++) { -//;# //; my $sname = sprintf("SRAM%03d", $i); # "000", "001", ... "015" etc. -//;# `$sname`_wants_to_read_then_write <= 0; -//;# //; } -//;# end -//;# //; } else { -//;# // Placeholder for initialization of optional BOTF signals, unused in this configuration (sram_wants...). -//;# //; } - //; # FIXME cycle_num no longer optional i guess... //; # if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { //; if (1 == 1) { @@ -255,20 +234,20 @@ module `mname` // Placeholder for initialization of optional BOTF signals, unused in this configuration (cycle_num). //; } - //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { - // Initialize BOTF (bypass on the fly) signals - // bypass_valid: True (1) iff bypassed_data is valid - // bypassed_rnum: Use target row number (index) of valid data as an ID. - // bypassed_data: Valid data lives here instead of 'rnum' in SRAM. - //; # ... - // 'x means "set all bits to x", or so I'm told. + //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF + // Initialize BOTF (bypass on the fly) signals + // bypass_valid: True (1) iff bypassed_data is valid + // bypassed_rnum: Use target row number (index) of valid data as an ID. + // bypassed_data: Valid data lives here instead of 'rnum' in SRAM. + //; # ... + // 'x means "set all bits to x", or so I'm told. initial begin - //; for (my $i=0; $i<$nbanks; $i++) { + //; for (my $i=0; $i<$nbanks; $i++) { bypass_valid[`$i`]=1'b0; bypassed_rnum[`$i`]=`$rwidth`'b0; bypassed_data[`$i`]='x; - //; } + //; } end //; } else { - // Placeholder for initialization of optional BOTF signals, unused in this configuration. + // Placeholder for initialization of optional BOTF signals, unused in this configuration. //; } // END WIRE DECLARATIONS____________________________________________________ From 3f35b86fbc3a05b137c010aeaece3348e0b8e8c4 Mon Sep 17 00:00:00 2001 From: steveri Date: Fri, 27 Jun 2025 09:57:18 -0700 Subject: [PATCH 12/12] final cleanup --- rtl/fftram.vp | 37 ++++++++----------------------------- 1 file changed, 8 insertions(+), 29 deletions(-) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index e9473a0..6e6bee1 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -225,14 +225,7 @@ module `mname` // LOOK MA NO BYPASS BUFFER //; } - //; # FIXME cycle_num no longer optional i guess... - //; # if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { - //; if (1 == 1) { - // Initialize BOTF (bypass on the fly) signals (cycle_num) initial cycle_num = `$nbits_cycle_num`'b0; - //; } else { - // Placeholder for initialization of optional BOTF signals, unused in this configuration (cycle_num). - //; } //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF // Initialize BOTF (bypass on the fly) signals @@ -404,15 +397,15 @@ module `mname` //; my $sram = sprintf("SRAM%03d", $snum); //; # async for 2port (inc. dpump) - //; my ($wz_event, $wz_value) = ("clk_i", "clk_i"); - //; my $wz_assign = "${sram}_wz <= $wz_value ? 1 : 0"; - //; my $wz_reset = "${sram}_wz <= 1'b1"; + //; my $wz_event = "clk_i"; + //; my $wz_set = "${sram}_wz <= clk_i ? 1 : 0"; + //; my $wz_reset = "${sram}_wz <= 1'b1"; //; # sync for 1port //; if ($n_sram_ports == 1) { - //; ($wz_event, $wz_value) = ("posedge clk_i", "suppress_wz_i[$snum]"); - //; $wz_assign = "${sram}_wz = $wz_value ? 1 : 0"; - //; $wz_reset = "${sram}_wz = 1'b1"; + //; $wz_event = "posedge clk_i"; + //; $wz_set = "${sram}_wz = suppress_wz_i[$snum] ? 1 : 0"; + //; $wz_reset = "${sram}_wz = 1'b1"; //; } always @ (`$wz_event`) begin @@ -422,10 +415,10 @@ module `mname` //; # (BFLY1_op1_bnum_i == 0 ) | (BFLY1_op2_bnum_i == 0 )" //; codeblock1($nunits, $snum); )) begin - `$wz_assign`; + `$wz_set`; //; if (($PRECOMPUTED_BYPASS == 0) && ($n_sram_ports == 1)) { # BOTF - // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); + // \$display(\"FLOOF BOTF %1d okay want to write ${sram}\", \$time); if (bypass_time == 1) begin // FIXME really need a task here, no? @@ -611,17 +604,3 @@ endmodule // Genesis2 is patent pending. For information regarding the patent please // contact the Stanford Technology Licensing Office. /////////////////////////////////////////////////////////////////////////////// - - - - -//; # //; # Hum notice this if-elsif loop-invariant :( -//; # //; # Oops not quite there's a $snum down there isnt it -//; # //; # Hum also maybe it should be if-else not if-elsif hum -//; # //; if ($n_sram_ports == 2) { -//; # //; $wz_event = "clk_i"; -//; # //; $wz_value = "clk_i"; -//; # //; $ass = "<="; -//; # //; } - -