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ABOSTMABOSTM
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system(H7) update STM32H7xx HAL Drivers to v1.11.0
Included in STM32CubeH7 FW v1.10.0 Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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+8936
-1885
lines changed

‎system/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 205 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,12 @@ extern "C" {
104104
#if defined(STM32H7)
105105
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
106106
#endif /* STM32H7 */
107+
108+
#if defined(STM32U5)
109+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
110+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
111+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
112+
#endif /* STM32U5 */
107113
/**
108114
* @}
109115
*/
@@ -225,8 +231,11 @@ extern "C" {
225231
/** @defgroup CRC_Aliases CRC API aliases
226232
* @{
227233
*/
234+
#if defined(STM32H5) || defined(STM32C0)
235+
#else
228236
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
229237
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
238+
#endif
230239
/**
231240
* @}
232241
*/
@@ -268,6 +277,11 @@ extern "C" {
268277
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
269278
#endif
270279

280+
#if defined(STM32H5)
281+
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
282+
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
283+
#endif
284+
271285
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
272286
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
273287
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
@@ -410,6 +424,10 @@ extern "C" {
410424
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
411425

412426
#endif /* STM32H7 */
427+
428+
#if defined(STM32U5)
429+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
430+
#endif /* STM32U5 */
413431
/**
414432
* @}
415433
*/
@@ -489,7 +507,7 @@ extern "C" {
489507
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
490508
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
491509
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
492-
#if defined(STM32G0)
510+
#if defined(STM32G0) || defined(STM32C0)
493511
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
494512
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
495513
#else
@@ -558,6 +576,106 @@ extern "C" {
558576
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
559577
#endif /* STM32G4 */
560578

579+
#if defined(STM32H5)
580+
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
581+
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
582+
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
583+
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
584+
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
585+
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
586+
587+
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
588+
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
589+
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
590+
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
591+
592+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
593+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
594+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
595+
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
596+
597+
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
598+
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
599+
600+
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
601+
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
602+
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
603+
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
604+
605+
#define SYSCFG_ETH_MII SBS_ETH_MII
606+
#define SYSCFG_ETH_RMII SBS_ETH_RMII
607+
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
608+
609+
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
610+
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
611+
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
612+
613+
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
614+
615+
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
616+
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
617+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
618+
#define SYSCFG_SAU SBS_SAU
619+
#define SYSCFG_MPU_SEC SBS_MPU_SEC
620+
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
621+
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
622+
#else
623+
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
624+
#endif /* __ARM_FEATURE_CMSE */
625+
626+
#define SYSCFG_CLK SBS_CLK
627+
#define SYSCFG_CLASSB SBS_CLASSB
628+
#define SYSCFG_FPU SBS_FPU
629+
#define SYSCFG_ALL SBS_ALL
630+
631+
#define SYSCFG_SEC SBS_SEC
632+
#define SYSCFG_NSEC SBS_NSEC
633+
634+
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
635+
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
636+
637+
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
638+
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
639+
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
640+
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
641+
642+
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
643+
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
644+
645+
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
646+
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
647+
648+
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
649+
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
650+
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
651+
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
652+
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
653+
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
654+
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
655+
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
656+
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
657+
658+
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
659+
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
660+
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
661+
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
662+
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
663+
664+
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
665+
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
666+
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
667+
668+
#define HAL_SYSCFG_Lock HAL_SBS_Lock
669+
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
670+
671+
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
672+
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
673+
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
674+
#endif /* __ARM_FEATURE_CMSE */
675+
676+
#endif /* STM32H5 */
677+
678+
561679
/**
562680
* @}
563681
*/
@@ -1690,6 +1808,79 @@ extern "C" {
16901808

16911809
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16921810

1811+
#if defined (STM32U5)
1812+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1813+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1814+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1815+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1816+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1817+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1818+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1819+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1820+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1821+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1822+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1823+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1824+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1825+
1826+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1827+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1828+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1829+
1830+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1831+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1832+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1833+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1834+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1835+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1836+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1837+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1838+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1839+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1840+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1841+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1842+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1843+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1844+
1845+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1846+
1847+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1848+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1849+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1850+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1851+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1852+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1853+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1854+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1855+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1856+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1857+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1858+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1859+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1860+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1861+
1862+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1863+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1864+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1865+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1866+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1867+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1868+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1869+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1870+
1871+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1872+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1873+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1874+
1875+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1876+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1877+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1878+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1879+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1880+
1881+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1882+
#endif
1883+
16931884
/**
16941885
* @}
16951886
*/
@@ -3323,7 +3514,10 @@ extern "C" {
33233514
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
33243515
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
33253516

3326-
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
3517+
#if defined(STM32GK)
3518+
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_DISABLE
3519+
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_DISABLE
3520+
#elif defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32V7) || defined(STM32N6)
33273521
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
33283522
#else
33293523
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3458,7 +3652,9 @@ extern "C" {
34583652
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
34593653
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
34603654
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3461-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3655+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3656+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3657+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
34623658
#endif
34633659

34643660
/**
@@ -3477,7 +3673,7 @@ extern "C" {
34773673
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
34783674
* @{
34793675
*/
3480-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3676+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32GK) || defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32V7) || defined (STM32H5) || defined (STM32C0)
34813677
#else
34823678
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
34833679
#endif
@@ -3530,6 +3726,10 @@ extern "C" {
35303726
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
35313727
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
35323728

3729+
#if defined (STM32H5)
3730+
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
3731+
#endif /* STM32H5 */
3732+
35333733
/**
35343734
* @}
35353735
*/
@@ -3541,7 +3741,7 @@ extern "C" {
35413741
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
35423742
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
35433743

3544-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
3744+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
35453745
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
35463746
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
35473747
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE

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