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ABOSTMABOSTM
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system(WB) update STM32WBxx HAL Drivers to v1.11.0
Included in STM32CubeWB FW 1.14.1 Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>
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‎system/Drivers/STM32WBxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h‎

Lines changed: 140 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -37,14 +37,16 @@ extern "C" {
3737
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
3838
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
3939
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
40-
#if defined(STM32U5)
40+
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
4141
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
4242
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
4343
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
4444
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
45+
#if defined(STM32U5)
4546
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
4647
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
4748
#endif /* STM32U5 */
49+
#endif /* STM32U5 || STM32H7 || STM32MP1 */
4850
/**
4951
* @}
5052
*/
@@ -104,6 +106,13 @@ extern "C" {
104106
#if defined(STM32H7)
105107
#define ADC_CHANNEL_VBAT_DIV4 ADC_CHANNEL_VBAT
106108
#endif /* STM32H7 */
109+
110+
#if defined(STM32U5)
111+
#define ADC_SAMPLETIME_5CYCLE ADC_SAMPLETIME_5CYCLES
112+
#define ADC_SAMPLETIME_391CYCLES_5 ADC_SAMPLETIME_391CYCLES
113+
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
114+
#endif /* STM32U5 */
115+
107116
/**
108117
* @}
109118
*/
@@ -225,8 +234,11 @@ extern "C" {
225234
/** @defgroup CRC_Aliases CRC API aliases
226235
* @{
227236
*/
237+
#if defined(STM32C0)
238+
#else
228239
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
229240
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
241+
#endif
230242
/**
231243
* @}
232244
*/
@@ -410,6 +422,10 @@ extern "C" {
410422
#define DAC_TRIGGER_LP2_OUT DAC_TRIGGER_LPTIM2_OUT
411423

412424
#endif /* STM32H7 */
425+
426+
#if defined(STM32U5)
427+
#define GPDMA1_REQUEST_DCMI GPDMA1_REQUEST_DCMI_PSSI
428+
#endif /* STM32U5 */
413429
/**
414430
* @}
415431
*/
@@ -489,7 +505,7 @@ extern "C" {
489505
#define OB_RDP_LEVEL0 OB_RDP_LEVEL_0
490506
#define OB_RDP_LEVEL1 OB_RDP_LEVEL_1
491507
#define OB_RDP_LEVEL2 OB_RDP_LEVEL_2
492-
#if defined(STM32G0)
508+
#if defined(STM32G0) || defined(STM32C0)
493509
#define OB_BOOT_LOCK_DISABLE OB_BOOT_ENTRY_FORCED_NONE
494510
#define OB_BOOT_LOCK_ENABLE OB_BOOT_ENTRY_FORCED_FLASH
495511
#else
@@ -657,6 +673,10 @@ extern "C" {
657673
#if defined(STM32U5)
658674
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
659675
#endif /* STM32U5 */
676+
#if defined(STM32U5)
677+
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
678+
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
679+
#endif /* STM32U5 */
660680
/**
661681
* @}
662682
*/
@@ -904,6 +924,15 @@ extern "C" {
904924
#define LPTIM_TRIGSAMPLETIME_4TRANSITION LPTIM_TRIGSAMPLETIME_4TRANSITIONS
905925
#define LPTIM_TRIGSAMPLETIME_8TRANSITION LPTIM_TRIGSAMPLETIME_8TRANSITIONS
906926

927+
928+
/** @defgroup HAL_LPTIM_Aliased_Defines HAL LPTIM Aliased Defines maintained for legacy purpose
929+
* @{
930+
*/
931+
#define HAL_LPTIM_ReadCompare HAL_LPTIM_ReadCapturedValue
932+
/**
933+
* @}
934+
*/
935+
907936
#if defined(STM32U5)
908937
#define LPTIM_ISR_CC1 LPTIM_ISR_CC1IF
909938
#define LPTIM_ISR_CC2 LPTIM_ISR_CC2IF
@@ -1060,8 +1089,8 @@ extern "C" {
10601089
#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
10611090

10621091
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
1063-
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1064-
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
1092+
#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
1093+
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
10651094
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
10661095

10671096
#define RTC_OUTPUT_REMAP_PC13 RTC_OUTPUT_REMAP_NONE
@@ -1072,15 +1101,22 @@ extern "C" {
10721101
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
10731102
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
10741103

1104+
#if defined(STM32F7)
1105+
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
1106+
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
1107+
#endif /* STM32F7 */
1108+
10751109
#if defined(STM32H7)
10761110
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_X
10771111
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
1112+
#endif /* STM32H7 */
10781113

1114+
#if defined(STM32F7) || defined(STM32H7)
10791115
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
10801116
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
10811117
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
1082-
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMPALL
1083-
#endif /* STM32H7 */
1118+
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
1119+
#endif /* STM32F7 || STM32H7 */
10841120

10851121
/**
10861122
* @}
@@ -1247,6 +1283,10 @@ extern "C" {
12471283
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
12481284
#endif
12491285

1286+
#if defined(STM32U5) || defined(STM32MP2)
1287+
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
1288+
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
1289+
#endif
12501290
/**
12511291
* @}
12521292
*/
@@ -1677,6 +1717,79 @@ extern "C" {
16771717

16781718
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
16791719

1720+
#if defined (STM32U5)
1721+
#define PWR_SRAM1_PAGE1_STOP_RETENTION PWR_SRAM1_PAGE1_STOP
1722+
#define PWR_SRAM1_PAGE2_STOP_RETENTION PWR_SRAM1_PAGE2_STOP
1723+
#define PWR_SRAM1_PAGE3_STOP_RETENTION PWR_SRAM1_PAGE3_STOP
1724+
#define PWR_SRAM1_PAGE4_STOP_RETENTION PWR_SRAM1_PAGE4_STOP
1725+
#define PWR_SRAM1_PAGE5_STOP_RETENTION PWR_SRAM1_PAGE5_STOP
1726+
#define PWR_SRAM1_PAGE6_STOP_RETENTION PWR_SRAM1_PAGE6_STOP
1727+
#define PWR_SRAM1_PAGE7_STOP_RETENTION PWR_SRAM1_PAGE7_STOP
1728+
#define PWR_SRAM1_PAGE8_STOP_RETENTION PWR_SRAM1_PAGE8_STOP
1729+
#define PWR_SRAM1_PAGE9_STOP_RETENTION PWR_SRAM1_PAGE9_STOP
1730+
#define PWR_SRAM1_PAGE10_STOP_RETENTION PWR_SRAM1_PAGE10_STOP
1731+
#define PWR_SRAM1_PAGE11_STOP_RETENTION PWR_SRAM1_PAGE11_STOP
1732+
#define PWR_SRAM1_PAGE12_STOP_RETENTION PWR_SRAM1_PAGE12_STOP
1733+
#define PWR_SRAM1_FULL_STOP_RETENTION PWR_SRAM1_FULL_STOP
1734+
1735+
#define PWR_SRAM2_PAGE1_STOP_RETENTION PWR_SRAM2_PAGE1_STOP
1736+
#define PWR_SRAM2_PAGE2_STOP_RETENTION PWR_SRAM2_PAGE2_STOP
1737+
#define PWR_SRAM2_FULL_STOP_RETENTION PWR_SRAM2_FULL_STOP
1738+
1739+
#define PWR_SRAM3_PAGE1_STOP_RETENTION PWR_SRAM3_PAGE1_STOP
1740+
#define PWR_SRAM3_PAGE2_STOP_RETENTION PWR_SRAM3_PAGE2_STOP
1741+
#define PWR_SRAM3_PAGE3_STOP_RETENTION PWR_SRAM3_PAGE3_STOP
1742+
#define PWR_SRAM3_PAGE4_STOP_RETENTION PWR_SRAM3_PAGE4_STOP
1743+
#define PWR_SRAM3_PAGE5_STOP_RETENTION PWR_SRAM3_PAGE5_STOP
1744+
#define PWR_SRAM3_PAGE6_STOP_RETENTION PWR_SRAM3_PAGE6_STOP
1745+
#define PWR_SRAM3_PAGE7_STOP_RETENTION PWR_SRAM3_PAGE7_STOP
1746+
#define PWR_SRAM3_PAGE8_STOP_RETENTION PWR_SRAM3_PAGE8_STOP
1747+
#define PWR_SRAM3_PAGE9_STOP_RETENTION PWR_SRAM3_PAGE9_STOP
1748+
#define PWR_SRAM3_PAGE10_STOP_RETENTION PWR_SRAM3_PAGE10_STOP
1749+
#define PWR_SRAM3_PAGE11_STOP_RETENTION PWR_SRAM3_PAGE11_STOP
1750+
#define PWR_SRAM3_PAGE12_STOP_RETENTION PWR_SRAM3_PAGE12_STOP
1751+
#define PWR_SRAM3_PAGE13_STOP_RETENTION PWR_SRAM3_PAGE13_STOP
1752+
#define PWR_SRAM3_FULL_STOP_RETENTION PWR_SRAM3_FULL_STOP
1753+
1754+
#define PWR_SRAM4_FULL_STOP_RETENTION PWR_SRAM4_FULL_STOP
1755+
1756+
#define PWR_SRAM5_PAGE1_STOP_RETENTION PWR_SRAM5_PAGE1_STOP
1757+
#define PWR_SRAM5_PAGE2_STOP_RETENTION PWR_SRAM5_PAGE2_STOP
1758+
#define PWR_SRAM5_PAGE3_STOP_RETENTION PWR_SRAM5_PAGE3_STOP
1759+
#define PWR_SRAM5_PAGE4_STOP_RETENTION PWR_SRAM5_PAGE4_STOP
1760+
#define PWR_SRAM5_PAGE5_STOP_RETENTION PWR_SRAM5_PAGE5_STOP
1761+
#define PWR_SRAM5_PAGE6_STOP_RETENTION PWR_SRAM5_PAGE6_STOP
1762+
#define PWR_SRAM5_PAGE7_STOP_RETENTION PWR_SRAM5_PAGE7_STOP
1763+
#define PWR_SRAM5_PAGE8_STOP_RETENTION PWR_SRAM5_PAGE8_STOP
1764+
#define PWR_SRAM5_PAGE9_STOP_RETENTION PWR_SRAM5_PAGE9_STOP
1765+
#define PWR_SRAM5_PAGE10_STOP_RETENTION PWR_SRAM5_PAGE10_STOP
1766+
#define PWR_SRAM5_PAGE11_STOP_RETENTION PWR_SRAM5_PAGE11_STOP
1767+
#define PWR_SRAM5_PAGE12_STOP_RETENTION PWR_SRAM5_PAGE12_STOP
1768+
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
1769+
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
1770+
1771+
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
1772+
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
1773+
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
1774+
#define PWR_DMA2DRAM_FULL_STOP_RETENTION PWR_DMA2DRAM_FULL_STOP
1775+
#define PWR_PERIPHRAM_FULL_STOP_RETENTION PWR_PERIPHRAM_FULL_STOP
1776+
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
1777+
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
1778+
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
1779+
1780+
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
1781+
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
1782+
#define PWR_SRAM2_FULL_STANDBY_RETENTION PWR_SRAM2_FULL_STANDBY
1783+
1784+
#define PWR_SRAM1_FULL_RUN_RETENTION PWR_SRAM1_FULL_RUN
1785+
#define PWR_SRAM2_FULL_RUN_RETENTION PWR_SRAM2_FULL_RUN
1786+
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
1787+
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
1788+
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
1789+
1790+
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
1791+
#endif
1792+
16801793
/**
16811794
* @}
16821795
*/
@@ -3310,7 +3423,7 @@ extern "C" {
33103423
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
33113424
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
33123425

3313-
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL)
3426+
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
33143427
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
33153428
#else
33163429
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
@@ -3423,8 +3536,8 @@ extern "C" {
34233536
#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
34243537
#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
34253538
#if defined(STM32U5)
3426-
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3427-
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
3539+
#define MSIKPLLModeSEL RCC_MSIKPLL_MODE_SEL
3540+
#define MSISPLLModeSEL RCC_MSISPLL_MODE_SEL
34283541
#define __HAL_RCC_AHB21_CLK_DISABLE __HAL_RCC_AHB2_1_CLK_DISABLE
34293542
#define __HAL_RCC_AHB22_CLK_DISABLE __HAL_RCC_AHB2_2_CLK_DISABLE
34303543
#define __HAL_RCC_AHB1_CLK_Disable_Clear __HAL_RCC_AHB1_CLK_ENABLE
@@ -3440,13 +3553,20 @@ extern "C" {
34403553
#define RCC_CLK48CLKSOURCE_PLL2 RCC_ICLK_CLKSOURCE_PLL2
34413554
#define RCC_CLK48CLKSOURCE_PLL1 RCC_ICLK_CLKSOURCE_PLL1
34423555
#define RCC_CLK48CLKSOURCE_MSIK RCC_ICLK_CLKSOURCE_MSIK
3443-
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3444-
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3445-
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3446-
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3447-
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3448-
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3449-
#endif
3556+
#define __HAL_RCC_ADC1_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
3557+
#define __HAL_RCC_ADC1_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
3558+
#define __HAL_RCC_ADC1_IS_CLK_ENABLED __HAL_RCC_ADC12_IS_CLK_ENABLED
3559+
#define __HAL_RCC_ADC1_IS_CLK_DISABLED __HAL_RCC_ADC12_IS_CLK_DISABLED
3560+
#define __HAL_RCC_ADC1_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
3561+
#define __HAL_RCC_ADC1_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
3562+
#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC12_CLK_SLEEP_ENABLE
3563+
#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC12_CLK_SLEEP_DISABLE
3564+
#define __HAL_RCC_GET_CLK48_SOURCE __HAL_RCC_GET_ICLK_SOURCE
3565+
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
3566+
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
3567+
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
3568+
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
3569+
#endif /* STM32U5 */
34503570

34513571
/**
34523572
* @}
@@ -3464,7 +3584,9 @@ extern "C" {
34643584
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
34653585
* @{
34663586
*/
3467-
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5)
3587+
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
3588+
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
3589+
defined (STM32WB_GEN2) || defined (STM32WBA) || defined (STM32C0)
34683590
#else
34693591
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
34703592
#endif
@@ -3528,7 +3650,7 @@ extern "C" {
35283650
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
35293651
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
35303652

3531-
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32L1)
3653+
#if !defined(STM32F1) && !defined(STM32F2) && !defined(STM32F4) && !defined(STM32L1)
35323654
#define eMMC_HIGH_VOLTAGE_RANGE EMMC_HIGH_VOLTAGE_RANGE
35333655
#define eMMC_DUAL_VOLTAGE_RANGE EMMC_DUAL_VOLTAGE_RANGE
35343656
#define eMMC_LOW_VOLTAGE_RANGE EMMC_LOW_VOLTAGE_RANGE

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