system(WB): update the system source file

Signed-off-by: Alexandre Bourdiol <alexandre.bourdiol@st.com>

Author: ABOSTM

system/STM32WBxx/system_stm32wbxx.c

@@ -60,8 +60,8 @@
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics. 
-  * All rights reserved.</center></h2>
+  * Copyright (c) 2019-2021 STMicroelectronics.
+  * All rights reserved.
   *
   * This software component is licensed by ST under Apache License, Version 2.0,
   * the "License"; You may not use this file except in compliance with the 
@@ -142,15 +142,15 @@
 /** @addtogroup STM32WBxx_System_Private_Variables
   * @{
   */
-  /* The SystemCoreClock variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-  uint32_t SystemCoreClock  = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
+/* The SystemCoreClock variable is updated in three ways:
+    1) by calling CMSIS function SystemCoreClockUpdate()
+    2) by calling HAL API function HAL_RCC_GetHCLKFreq()
+    3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
+       Note: If you use this function to configure the system clock; then there
+             is no need to call the 2 first functions listed above, since SystemCoreClock
+             variable is updated automatically.
+*/
+uint32_t SystemCoreClock = 4000000UL ; /*CPU1: M4 on MSI clock after startup (4MHz)*/
 
   const uint32_t AHBPrescTable[16UL] = {1UL, 3UL, 5UL, 1UL, 1UL, 6UL, 10UL, 32UL, 2UL, 4UL, 8UL, 16UL, 64UL, 128UL, 256UL, 512UL};
 
@@ -159,12 +159,12 @@
   const uint32_t MSIRangeTable[16UL] = {100000UL, 200000UL, 400000UL, 800000UL, 1000000UL, 2000000UL, \
                                       4000000UL, 8000000UL, 16000000UL, 24000000UL, 32000000UL, 48000000UL, 0UL, 0UL, 0UL, 0UL}; /* 0UL values are incorrect cases */
 
-#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx)
+#if defined(STM32WB55xx) || defined(STM32WB5Mxx) || defined(STM32WB35xx) || defined (STM32WB15xx) || defined (STM32WB1Mxx)
   const uint32_t SmpsPrescalerTable[4UL][6UL]={{1UL,3UL,2UL,2UL,1UL,2UL}, \
                                         {2UL,6UL,4UL,3UL,2UL,4UL}, \
                                         {4UL,12UL,8UL,6UL,4UL,8UL}, \
                                         {4UL,12UL,8UL,6UL,4UL,8UL}};
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx || STM32WB35xx || STM32WB15xx || STM32WB1Mxx */
 
 /**
   * @}
@@ -192,10 +192,10 @@ void SystemInit(void)
   SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
 
   /* FPU settings ------------------------------------------------------------*/
-  #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
-    SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL)));  /* set CP10 and CP11 Full Access */
-  #endif
-  
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  SCB->CPACR |= ((3UL << (10UL * 2UL)) | (3UL << (11UL * 2UL))); /* set CP10 and CP11 Full Access */
+#endif /* FPU */
+
   /* Reset the RCC clock configuration to the default reset state ------------*/
   /* Set MSION bit */
   RCC->CR |= RCC_CR_MSION;
@@ -204,21 +204,21 @@ void SystemInit(void)
   RCC->CFGR = 0x00070000U;
 
   /* Reset PLLSAI1ON, PLLON, HSECSSON, HSEON, HSION, and MSIPLLON bits */
-  RCC->CR &= 0xFAF6FEFBU;
+  RCC->CR &= (uint32_t)0xFAF6FEFBU;
 
   /*!< Reset LSI1 and LSI2 bits */
-  RCC->CSR &= 0xFFFFFFFAU;
-  
+  RCC->CSR &= (uint32_t)0xFFFFFFFAU;
+
   /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= 0xFFFFFFFEU;
-    
+  RCC->CRRCR &= (uint32_t)0xFFFFFFFEU;
+
   /* Reset PLLCFGR register */
   RCC->PLLCFGR = 0x22041000U;
 
 #if defined(STM32WB55xx) || defined(STM32WB5Mxx)
   /* Reset PLLSAI1CFGR register */
   RCC->PLLSAI1CFGR = 0x22041000U;
-#endif
+#endif /* STM32WB55xx || STM32WB5Mxx */
 
   /* Reset HSEBYP bit */
   RCC->CR &= 0xFFFBFFFFU;
@@ -280,7 +280,7 @@ void SystemInit(void)
   */
 void SystemCoreClockUpdate(void)
 {
-  uint32_t tmp, msirange, pllvco, pllr, pllsource , pllm;
+  uint32_t tmp, msirange, pllvco, pllr, pllsource, pllm;
 
   /* Get MSI Range frequency--------------------------------------------------*/
 
@@ -290,13 +290,13 @@ void SystemCoreClockUpdate(void)
   /* Get SYSCLK source -------------------------------------------------------*/
   switch (RCC->CFGR & RCC_CFGR_SWS)
   {
-    case 0x00:   /* MSI used as system clock source */
+    case 0x00: /* MSI used as system clock source */
       SystemCoreClock = msirange;
       break;
 
-    case 0x04:  /* HSI used as system clock source */
+    case 0x04: /* HSI used as system clock source */
       /* HSI used as system clock source */
-        SystemCoreClock = HSI_VALUE;
+      SystemCoreClock = HSI_VALUE;
       break;
 
     case 0x08:  /* HSE used as system clock source */
@@ -310,36 +310,36 @@ void SystemCoreClockUpdate(void)
       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
       pllm = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLM) >> RCC_PLLCFGR_PLLM_Pos) + 1UL ;
 
-      if(pllsource == 0x02UL) /* HSI used as PLL clock source */
+      if (pllsource == 0x02UL) /* HSI used as PLL clock source */
       {
         pllvco = (HSI_VALUE / pllm);
       }
-      else if(pllsource == 0x03UL) /* HSE used as PLL clock source */
+      else if (pllsource == 0x03UL) /* HSE used as PLL clock source */
       {
         pllvco = (HSE_VALUE / pllm);
       }
       else /* MSI used as PLL clock source */
       {
         pllvco = (msirange / pllm);
       }
-      
+
       pllvco = pllvco * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos) + 1UL);
-      
-      SystemCoreClock = pllvco/pllr;
+
+      SystemCoreClock = pllvco / pllr;
       break;
 
     default:
       SystemCoreClock = msirange;
       break;
   }
-  
+
   /* Compute HCLK clock frequency --------------------------------------------*/
   /* Get HCLK1 prescaler */
   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos)];
+
   /* HCLK clock frequency */
   SystemCoreClock = SystemCoreClock / tmp;
-
 }