Remove references to stages and pipelining

Author: Adel Mamin

peregrine/analysis/tracking_loop.py

@@ -102,12 +102,8 @@ def main():
 
   ms_to_process = int(args.ms_to_process)
 
-  if args.pipelining is not None:
-    tracker_options = {'mode': 'pipelining',
-                       'k': args.pipelining}
-  elif args.short_long_cycles is not None:
-    tracker_options = {'mode': 'short-long-cycles',
-                       'k': args.short_long_cycles}
+  if args.short_long_cycles is not None:
+    tracker_options = {'mode': 'short-long-cycles'}
   else:
     tracker_options = None
 
@@ -120,9 +116,6 @@ def main():
                                  signal=signal,
                                  sample_index=skip_samples)
 
-  if args.l1ca_profile:
-    profile = defaults.l1ca_stage_profiles[args.l1ca_profile]
-
   samples = {L1CA: {'IF': freq_profile['GPS_L1_IF']},
              L2C: {'IF': freq_profile['GPS_L2_IF']},
              'samples_total': -1,
@@ -147,7 +140,6 @@ def main():
   print "Initial carrier Doppler frequency [Hz]: %s" % carr_doppler
   print "Initial code phase [chips]:             %s" % code_phase
   print "Signal:                                 %s" % args.signal
-  print "L1 stage profile:                       %s" % args.l1ca_profile
   print "Tracker options:                        %s" % str(tracker_options)
   print "L2C handover:                           %s" % str(l2c_handover)
   print "======================================================================"

peregrine/run.py

@@ -137,36 +137,15 @@ def populate_peregrine_cmd_line_arguments(parser):
 
   fpgaSim = parser.add_argument_group('FPGA simulation',
                                       'FPGA delay control simulation')
-  fpgaExcl = fpgaSim.add_mutually_exclusive_group(required=False)
-  fpgaExcl.add_argument("--pipelining",
-                        type=float,
-                        nargs='?',
-                        metavar='PIPELINING_K',
-                        help="Use FPGA pipelining simulation. Supply optional "
-                        " coefficient (%f)" % defaults.pipelining_k,
-                        const=defaults.pipelining_k,
-                        default=None)
-
-  fpgaExcl.add_argument("--short-long-cycles",
-                        type=float,
-                        nargs='?',
-                        metavar='PIPELINING_K',
-                        help="Use FPGA short-long cycle simulation. Supply"
-                        " optional pipelining coefficient (0.)",
-                        const=0.,
-                        default=None)
+
+  fpgaSim.add_argument("--short-long-cycles",
+                        help="Use FPGA short-long cycle simulation.",
+                        action="store_true")
 
   signalParam = parser.add_argument_group('Signal tracking',
                                           'Parameters for satellite vehicle'
                                           ' signal')
 
-  signalParam.add_argument('--l1ca-profile',
-                           metavar='PROFILE',
-                           help='L1 C/A stage profile. Controls coherent'
-                                ' integration time and tuning parameters: %s.' %
-                                str(defaults.l1ca_stage_profiles.keys()),
-                           choices=defaults.l1ca_stage_profiles.keys())
-
   return signalParam
 
 
@@ -207,16 +186,8 @@ def main():
   else:
     raise NotImplementedError()
 
-  if args.l1ca_profile:
-    profile = defaults.l1ca_stage_profiles[args.l1ca_profile]
-    stage2_coherent_ms = profile[1]['coherent_ms']
-    stage2_params = profile[1]['loop_filter_params']
-  else:
-    stage2_coherent_ms = None
-    stage2_params = None
-
-  if args.pipelining is not None:
-    tracker_options = {'mode': 'pipelining', 'k': args.pipelining}
+  if args.short_long_cycles is not None:
+    tracker_options = {'mode': 'short-long-cycles'}
   else:
     tracker_options = None
 
@@ -304,8 +275,6 @@ def main():
                                ms_to_track=ms_to_process,
                                sampling_freq=freq_profile[
                                    'sampling_freq'],  # [Hz]
-                               stage2_coherent_ms=stage2_coherent_ms,
-                               stage2_loop_filter_params=stage2_params,
                                tracker_options=tracker_options,
                                output_file=args.file,
                                progress_bar_output=args.progress_bar,

peregrine/tracking.py

@@ -383,8 +383,8 @@ def _set_track_profile(self):
 
     self.coherent_ms = coherent_ms
 
-    logger.info("[PRN: %d (%s)] coherent_ms=%d and PLL bw=%f FLL bw=%f" %
-                (self.prn + 1, self.signal, self.coherent_ms, pll_bw, fll_bw))
+    # logger.info("[PRN: %d (%s)] coherent_ms=%d and PLL bw=%f FLL bw=%f" %
+    #             (self.prn + 1, self.signal, self.coherent_ms, pll_bw, fll_bw))
 
     lock_detect_params_fast = get_lock_detector(pll_bw,
                                               defaults.lock_detect_params_fast)

peregrine/tracking_loop.py

@@ -378,7 +378,6 @@ def retune(self, code_params, carr_params, loop_freq, carr_freq_b1, carr_to_code
     self.phase_c1 = phase_a2 * phase_omega_0
     self.phase_c2 = phase_omega_0 * phase_omega_0
     # self.phase_c1, self.phase_c2 = controlled_root(2, 1 / loop_freq, carr_bw)
-    # print "T = ", 1 / loop_freq, " BW = ", carr_bw
 
     # DLL constants
     code_omega_0 = code_bw / 0.53
@@ -509,7 +508,6 @@ def retune(self, code_params, carr_params, loop_freq, carr_freq_b1, carr_to_code
     self.phase_c1 = phase_a2 * phase_omega_0
     self.phase_c2 = phase_omega_0 * phase_omega_0
     # self.phase_c1, self.phase_c2 = controlled_root(2, 1 / loop_freq, carr_bw)
-    # print "T = ", 1 / loop_freq, " BW = ", carr_bw
 
     # DLL constants
     code_omega_0 = code_bw / 0.53