Upgrade to Chisel 3.6 and Ubuntu 24.04 LTS

Core Upgrades:
- Chisel: 3.4 → 3.6
- Scala: 2.11.12 → 2.12.10
- chisel-iotesters: 1.5 → 2.5
- chiseltest: 0.3 → 0.6
- dsptools: 1.4 → 1.5
- breeze: 0.13.2 → 1.0
- firrtl-diagrammer: 1.3 → 1.6

API Migration:
- Replace chisel3.Driver.emit with ChiselStage().emitChirrtl
- Replace chisel3.Driver.execute with ChiselStage().emitVerilog
- Update type: chisel3.core.UserModule → chisel3.Module
- Remove thunk wrappers: () => module no longer needed

Docker Improvements:
- Ubuntu: 20.04 → 24.04 LTS
- Fix pip installation for Python 3.12
- Remove obsolete python3-distutils package
- Use --break-system-packages for pip in container

Fixes:
- binder/postBuild: Fix shell syntax (separate env vars)
- Notebooks: Update FIRRTL emission in 4.1 and 4.4
- Validate all changes for Chisel 3.6 compatibility

Author: jserv

4.1_firrtl_ast.ipynb

@@ -100,7 +100,7 @@
    },
    "outputs": [],
    "source": [
-    "println(chisel3.Driver.emit(() => new DelayBy2(4)))"
+    "println((new chisel3.stage.ChiselStage).emitChirrtl(new DelayBy2(4)))\n"
    ]
   },
   {
@@ -129,7 +129,7 @@
    },
    "outputs": [],
    "source": [
-    "val firrtlSerialization = chisel3.Driver.emit(() => new DelayBy2(4))\n",
+    "val firrtlSerialization = (new chisel3.stage.ChiselStage).emitChirrtl(new DelayBy2(4))\n",
     "val firrtlAST = firrtl.Parser.parse(firrtlSerialization.split(\"\\n\").toIterator, Parser.GenInfo(\"file.fir\"))\n",
     "\n",
     "println(firrtlAST)"
@@ -343,4 +343,4 @@
  },
  "nbformat": 4,
  "nbformat_minor": 2
-}
+}

4.4_firrtl_add_ops_per_module.ipynb

@@ -257,7 +257,7 @@
    },
    "outputs": [],
    "source": [
-    "val firrtlSerialization = chisel3.Driver.emit(() => new AddMe(8, 4))"
+    "val firrtlSerialization = (new chisel3.stage.ChiselStage).emitChirrtl(new AddMe(8, 4))\n"
    ]
   },
   {
@@ -317,4 +317,4 @@
  },
  "nbformat": 4,
  "nbformat_minor": 2
-}
+}

Dockerfile

@@ -1,5 +1,5 @@
 # First stage : setup the system and environment
-FROM ubuntu:20.04 as base
+FROM ubuntu:24.04 as base
 
 RUN \
     apt-get update && \
@@ -8,15 +8,13 @@ RUN \
         curl \
         graphviz \
         openjdk-8-jre-headless \
-        python3-distutils \
         gcc \
         python3-dev \
         && \
     rm -rf /var/lib/apt/lists/*
 
-RUN curl https://bootstrap.pypa.io/get-pip.py -o get-pip.py
-RUN python3 get-pip.py
-RUN pip3 install jupyter jupyterlab
+RUN apt-get update && apt-get install -y python3-pip && rm -rf /var/lib/apt/lists/*
+RUN pip3 install --no-cache-dir --break-system-packages jupyter jupyterlab
 
 RUN useradd -ms /bin/bash bootcamp
 

binder/postBuild

@@ -1,6 +1,7 @@
 #!/bin/bash
 
-SCALA_VERSION=2.12.10 ALMOND_VERSION=0.9.1
+SCALA_VERSION=2.12.10
+ALMOND_VERSION=0.9.1
 
 # Install coursier
 curl -Lo coursier https://git.io/coursier-cli

source/load-ivy.sc

@@ -4,35 +4,32 @@ interp.repositories() ::: List(
 
 @
 
-interp.configureCompiler(x => x.settings.source.value = scala.tools.nsc.settings.ScalaVersion("2.11.12"))
+interp.configureCompiler(x => x.settings.source.value = scala.tools.nsc.settings.ScalaVersion("2.12.10"))
 
 // Uncomment and change to use proxy
 // System.setProperty("https.proxyHost", "proxy.example.com")
 // System.setProperty("https.proxyPort", "3128")
 
-import $ivy.`edu.berkeley.cs::chisel3:3.4.+`
-import $ivy.`edu.berkeley.cs::chisel-iotesters:1.5.+`
-import $ivy.`edu.berkeley.cs::chiseltest:0.3.+`
-import $ivy.`edu.berkeley.cs::dsptools:1.4.+`
-import $ivy.`org.scalanlp::breeze:0.13.2`
+import $ivy.`edu.berkeley.cs::chisel3:3.6.+`
+import $ivy.`edu.berkeley.cs::chisel-iotesters:2.5.+`
+import $ivy.`edu.berkeley.cs::chiseltest:0.6.+`
+import $ivy.`edu.berkeley.cs::dsptools:1.5.+`
+import $ivy.`org.scalanlp::breeze:1.0`
 import $ivy.`edu.berkeley.cs::rocket-dsptools:1.2.0`
-import $ivy.`edu.berkeley.cs::firrtl-diagrammer:1.3.+`
+import $ivy.`edu.berkeley.cs::firrtl-diagrammer:1.6.+`
 
 import $ivy.`org.scalatest::scalatest:3.2.2`
 
 // Convenience function to invoke Chisel and grab emitted Verilog.
-def getVerilog(dut: => chisel3.core.UserModule): String = {
-  import firrtl._
-  return chisel3.Driver.execute(Array[String](), {() => dut}) match {
-    case s:chisel3.ChiselExecutionSuccess => s.firrtlResultOption match {
-      case Some(f:FirrtlExecutionSuccess) => f.emitted
-    }
-  }
+def getVerilog(dut: => chisel3.Module): String = {
+  import chisel3.stage.ChiselStage
+  (new ChiselStage).emitVerilog(dut)
 }
 
 // Convenience function to invoke Chisel and grab emitted FIRRTL.
-def getFirrtl(dut: => chisel3.core.UserModule): String = {
-  return chisel3.Driver.emit({() => dut})
+def getFirrtl(dut: => chisel3.Module): String = {
+  import chisel3.stage.ChiselStage
+  (new ChiselStage).emitChirrtl(dut)
 }
 
 def compileFIRRTL(