From 25e917c9723388b5341e131fe6a7bf8fbe8bcd3c Mon Sep 17 00:00:00 2001 From: Jim Huang Date: Wed, 13 Nov 2019 06:46:37 +0800 Subject: [PATCH 01/24] Perform consistent indention --- emu-rv32i.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 47b6da4..b449dd5 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1092,12 +1092,6 @@ void execute_instruction() } else { debug_out(">>> BGE\n"); stats[7]++; - } -#endif - cond = ((int32_t) reg[rs1] < (int32_t) reg[rs2]); - break; - case 3: /* bltu/bgeu */ -#ifdef DEBUG_EXTRA if (!(funct3 & 1)) { debug_out(">>> BLTU\n"); stats[8]++; From 275aa51db51479f55e5d37fdd56be56b1bdc71cc Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Fri, 13 Dec 2019 03:07:44 +0800 Subject: [PATCH 02/24] Create the CSRs.h for CSR --- CSRs.h | 91 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 91 insertions(+) create mode 100644 CSRs.h diff --git a/CSRs.h b/CSRs.h new file mode 100644 index 0000000..32daaee --- /dev/null +++ b/CSRs.h @@ -0,0 +1,91 @@ +/* Modified by Nober + 13-DEC-2019 - Define all CSR macro +*/ + +/* +RISCV emulator for the RV32I architecture +based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ +stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test +by Frank Buss, 2018 + +Requires libelf-dev: + +sudo apt-get install libelf-dev + + +Compile it like this: + +gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i + + +It is compatible to Spike for the command line arguments, which means you can run +the compliance test from https://github.com/riscv/riscv-compliance like this: + +make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant + +It is also compatible with qemu32, as it is used for Zephyr. You can compile the +Zephyr examples for qemu like this: + +cd zephyr +source zephyr-env.sh +cd samples/synchronization +mkdir build && cd build +cmake -GNinja -DBOARD=qemu_riscv32 .. +ninja + +After this you can run it with the emulator like this: + +emu-rv32i zephyr/zephyr.elf + + +original copyright: +*/ + + + +/* + * RISCV emulator + * + * Copyright (c) 2016 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include + + +// ====================================================== // +// =================== User Trap Setup ================== // +// ====================================================== // +uint32_t ustatus; /* User status register */ +uint32_t uie; /* User interrupt-enable register */ +uint32_t utvec; /* User trap handler base address */ +// ====================================================== // +// ================= User Trap Handling ================= // +// ====================================================== // +uint32_t uscratch; /* Scratch register for user trap handlers*/ +uint32_t uepc; /* User exception program counter */ +uint32_t ucause; /* User trap cause*/ +uint32_t ubadaddr; /* User bad address */ +uint32_t uip; /* User interrupt pending */ +// ====================================================== // +// ============== User Floating-Point CSRs ============== // +// ====================================================== // +uint32_t fflags; /* Floating-Point Accrued Exceptions*/ +uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ From 5b853e53847088ba39de47f7af16913a452f27d2 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 29 Dec 2019 19:55:09 +0800 Subject: [PATCH 03/24] Add the compressed C.NOP and C.ADDI --- emu-rv32i.c | 94 ++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 11 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index b449dd5..3e9e057 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -160,12 +160,18 @@ int machine_running = TRUE; #define PRV_H 2 #define PRV_M 3 +/* Instruction state*/ +#define CINSN 1 +#define INSN 0 +unsigned char insn_type; + /* CPU state */ uint32_t pc; uint32_t next_pc; uint32_t insn; uint32_t reg[32]; + uint8_t priv = PRV_M; /* see PRV_x */ uint8_t fs; /* MSTATUS_FS value */ uint8_t mxl; /* MXL field in MISA register */ @@ -703,7 +709,7 @@ int raise_interrupt() /* read 32-bit instruction from memory by PC */ -uint32_t get_insn32(uint32_t pc) +uint32_t get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA if (pc && pc < minmemr) @@ -712,10 +718,16 @@ uint32_t get_insn32(uint32_t pc) maxmemr = pc + 3; #endif uint32_t ptr = pc - ram_start; - if (ptr > RAM_SIZE) - return 1; - uint8_t *p = ram + ptr; - return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); + if (ptr > RAM_SIZE) return 1; + uint8_t* p = ram + ptr; +#ifdef RV32C + if((p[0] & 0x03) < 3){ + *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; + return CINSN; + } +#endif + *insn = p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); + return INSN; } /* read 8-bit data from memory */ @@ -1005,10 +1017,22 @@ void execute_instruction() int32_t imm, cond, err; uint32_t addr, val = 0, val2; - opcode = insn & 0x7f; - rd = (insn >> 7) & 0x1f; - rs1 = (insn >> 15) & 0x1f; - rs2 = (insn >> 20) & 0x1f; + uint16_t midpart; + + if(insn_type == INSN){ + opcode = insn & 0x7f; + rd = (insn >> 7) & 0x1f; + rs1 = (insn >> 15) & 0x1f; + rs2 = (insn >> 20) & 0x1f; + } + +#ifdef RV32C + if(insn_type == CINSN){ + opcode = insn & 0x3; + } +#endif + + switch (opcode) { case 0x37: /* lui */ @@ -1836,6 +1860,47 @@ void execute_instruction() break; #endif +#ifdef RV32C + /* Compressed insn */ + case 0: + break; + case 1: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 0: /* C.NOP, C.ADDI */ + if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ + return; + } else { + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; + } + break; + case 1: /* C.JAL, C.ADDIW */ + break; + case 2: /* C.LI */ + break; + case 3: /* C.ADDI16SP, C.LUI */ + break; + case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + break; + case 5: /* C.J */ + break; + case 6: /* C.BEQZ */ + break; + case 7: /* C.BNEZ */ + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0){ + reg[rd] = val; + } + break; + case 2: + break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1878,8 +1943,15 @@ void riscv_cpu_interp_x32() if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { raise_interrupt(); } else { - /* normal instruction execution */ - insn = get_insn32(pc); + /* Compressed or normal */ + insn_type = get_insn32(pc, &insn); +#ifdef RV32C + if(insn_type) + next_pc = pc + 2; +#endif +#ifdef DEBUG_EXTRA + printf("insn : %#x\n", insn); +#endif insn_counter++; debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, From 7a9c40682bdeeb0c29fd6a81295c73cb7773ef51 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 29 Dec 2019 20:17:10 +0800 Subject: [PATCH 04/24] Add the C.JAL and C.ADDIW insn --- emu-rv32i.c | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/emu-rv32i.c b/emu-rv32i.c index 3e9e057..eedb342 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1878,6 +1878,32 @@ void execute_instruction() } break; case 1: /* C.JAL, C.ADDIW */ + switch(XLEN){ + case 32: + imm = (midpart & 0x400) | + ((midpart << 3) & 0x200) | + (midpart & 0x170) | + ((midpart << 2) & 0x40) | + (midpart & 0x20) | + ((midpart << 4) & 0x10) | + ((midpart >> 6) & 0x8) | + ((midpart >> 1) & 0x7); + imm = imm & 0xfffe; + if (rd != 0) + reg[1] = pc + 2; /* Store the link to x1 register */ + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + break; + case 64: + case 128: + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart >> (11 - 5)) | + midpart & 0x1f; + val = reg[rs1] + imm; + break; + } break; case 2: /* C.LI */ break; From dc68602baaa554a54048f776fc0b6cd0cb3b5b84 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 02:58:17 +0800 Subject: [PATCH 05/24] Modified some implementataion detail to support compressed instruction --- debug.txt | 12249 ++++++++++++++++++++++++++++++++++++++++++++++++++ emu-rv32i.c | 267 +- 2 files changed, 12507 insertions(+), 9 deletions(-) create mode 100644 debug.txt diff --git a/debug.txt b/debug.txt new file mode 100644 index 0000000..ac5df94 --- /dev/null +++ b/debug.txt @@ -0,0 +1,12249 @@ +./emu-rv32i work/rv32imc/C-NOP.elf +sym '/tmp/ccoevK6z.o' 0 +sym 'reset_vector' 80000040 +sym 'trap_vector' 80000004 +sym 'write_tohost' 80000036 +sym 'handle_exception' 80000032 +sym 'other_exception' 80000032 +sym 'begin_testcode' 800000f0 +sym 'test_1_res' 80002000 +sym 'end_testcode' 80000122 +sym 'end_signature' 80002020 +sym 'begin_regstate' 80002100 +sym 'begin_signature' 80002000 +sym '_start' 80000000 +sym 'end_regstate' 80002200 +sym '_end' 80002204 +sym 'fromhost' 80001100 +sym 'tohost' 80001000 +begin_signature: 0x80002000 +end_signature: 0x80002020 +start: 0x80000000 +codesize: 0x00002204 (8708) +codesize with offset: 8708 +address 0001a081 +insn_type : CINSN +[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 +>>> C.J +address f1402573 +insn_type : INSN +[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 0297e101 +insn_type : CINSN +[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a +address 00000297 +insn_type : INSN +[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 +>>> AUIPC +address 01228293 +insn_type : INSN +[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x00000000 +csr_write: csr=0x305 val=0x80000058 +address 18005073 +insn_type : INSN +[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x180 -1 +csr_read: csr=0x180 --> 0x00000000 +csr_write: csr=0x180 val=0x00000000 +address 02970001 +insn_type : CINSN +[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 +>>> C.NOP +address 00000297 +insn_type : INSN +[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000058 +csr_write: csr=0x305 val=0x80000070 +address 907352fd +insn_type : CINSN +[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 +>>> C.LI +0000003f, rd: 5 +address 3b029073 +insn_type : INSN +[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3b0 -1 +csr_read: invalid CSR=0x3b0 +csr_write: csr=0x3b0 val=0x0000003f +address 907342fd +insn_type : CINSN +[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 +>>> C.LI +0000001f, rd: 5 +address 3a029073 +insn_type : INSN +[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3a0 -1 +csr_read: invalid CSR=0x3a0 +csr_write: csr=0x3a0 val=0x0000001f +address 00000297 +insn_type : INSN +[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000070 +csr_write: csr=0x305 val=0x80000088 +address 30205073 +insn_type : INSN +[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x302 -1 +csr_read: csr=0x302 --> 0x00000000 +csr_write: csr=0x302 val=0x00000000 +address 30305073 +insn_type : INSN +[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x303 -1 +csr_read: csr=0x303 --> 0x00000000 +csr_write: csr=0x303 val=0x00000000 +address 30405073 +insn_type : INSN +[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x304 -1 +csr_read: csr=0x304 --> 0x00000000 +csr_write: csr=0x304 val=0x00000000 +address 02974181 +insn_type : CINSN +[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 +>>> C.LI +00000000, rd: 3 +address 00000297 +insn_type : INSN +[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 +>>> AUIPC +address f7a28293 +insn_type : INSN +[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000088 +csr_write: csr=0x305 val=0x80000004 +address 057e4505 +insn_type : CINSN +[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 +>>> C.LI +00000001, rd: 10 +address 4763057e +insn_type : CINSN +[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 +address 00054763 +insn_type : INSN +[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 +>>> BLT +address 0ff0000f +insn_type : INSN +[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 80000297 +insn_type : INSN +[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 +>>> AUIPC +address f5828293 +insn_type : INSN +[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 +>>> ADDI +address 00028e63 +insn_type : INSN +[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 +>>> BEQ +address 30005073 +insn_type : INSN +[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x300 -1 +csr_read: csr=0x300 --> 0x00000000 +csr_write: csr=0x300 val=0x00000000 +address 00002537 +insn_type : INSN +[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 +>>> LUI +address 80050513 +insn_type : INSN +[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 +>>> ADDI +address 30052073 +insn_type : INSN +[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 +csr_read: csr=0x300 1 +csr_read: csr=0x300 --> 0x00000000 +>>> CSRRS +csr_write: csr=0x300 val=0x00001800 +address 00000297 +insn_type : INSN +[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 +>>> AUIPC +address 01428293 +insn_type : INSN +[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 +>>> ADDI +address 34129073 +insn_type : INSN +[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x341 -1 +csr_read: csr=0x341 --> 0x00000000 +csr_write: csr=0x341 val=0x800000f0 +address f1402573 +insn_type : INSN +[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 30200073 +insn_type : INSN +[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 +>>> MRET +address 00002117 +insn_type : INSN +[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 +>>> AUIPC +address f1010113 +insn_type : INSN +[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 +>>> ADDI +address 00000013 +insn_type : INSN +[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 +>>> ADDI +address c0020001 +insn_type : CINSN +[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 +>>> C.NOP +address 4201c002 +insn_type : CINSN +[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 +address 02014201 +insn_type : CINSN +[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 +>>> C.LI +00000000, rd: 4 +address c2120201 +insn_type : CINSN +[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 +>>> C.ADDI +address 4401c212 +insn_type : CINSN +[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 +address 04014401 +insn_type : CINSN +[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 +>>> C.LI +00000000, rd: 8 +address c4220401 +insn_type : CINSN +[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 +>>> C.ADDI +address 4481c422 +insn_type : CINSN +[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 +address 04814481 +insn_type : CINSN +[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 +>>> C.LI +00000000, rd: 9 +address c6260481 +insn_type : CINSN +[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 +>>> C.ADDI +address 4581c626 +insn_type : CINSN +[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 +address 05814581 +insn_type : CINSN +[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 +>>> C.LI +00000000, rd: 11 +address c82e0581 +insn_type : CINSN +[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 +>>> C.ADDI +address 000fc82e +insn_type : CINSN +[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 +address 0ff0000f +insn_type : INSN +[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 00000000 +insn_type : CINSN +[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ec]=00000000, mtime: 1db9bc36479, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ee]=00000000, mtime: 1db9bc364c8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f0]=00000000, mtime: 1db9bc36517, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f2]=00000000, mtime: 1db9bc36565, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f4]=00000000, mtime: 1db9bc365b5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f6]=00000000, mtime: 1db9bc36604, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f8]=00000000, mtime: 1db9bc36654, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fa]=00000000, mtime: 1db9bc366a8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fc]=00000000, mtime: 1db9bc366fa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fe]=00000000, mtime: 1db9bc3674b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000200]=00000000, mtime: 1db9bc3679a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000202]=00000000, mtime: 1db9bc367ea, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000204]=00000000, mtime: 1db9bc3683a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000206]=00000000, mtime: 1db9bc3688a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000208]=00000000, mtime: 1db9bc368df, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020a]=00000000, mtime: 1db9bc3692e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020c]=00000000, mtime: 1db9bc3697e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020e]=00000000, mtime: 1db9bc369cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000210]=00000000, mtime: 1db9bc36a1b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000212]=00000000, mtime: 1db9bc36a6a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000214]=00000000, mtime: 1db9bc36ab9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000216]=00000000, mtime: 1db9bc36b0b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000218]=00000000, mtime: 1db9bc36b5d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021a]=00000000, mtime: 1db9bc36baf, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021c]=00000000, mtime: 1db9bc36bff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000021e]=00000000, mtime: 1db9bc36c50, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000220]=00000000, mtime: 1db9bc36ca1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000222]=00000000, mtime: 1db9bc36cf3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000224]=00000000, mtime: 1db9bc36d43, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000226]=00000000, mtime: 1db9bc36d94, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000228]=00000000, mtime: 1db9bc36de4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022a]=00000000, mtime: 1db9bc36e35, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022c]=00000000, mtime: 1db9bc36e85, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000022e]=00000000, mtime: 1db9bc36ed4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000230]=00000000, mtime: 1db9bc36f23, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000232]=00000000, mtime: 1db9bc36f76, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000234]=00000000, mtime: 1db9bc36fc7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000236]=00000000, mtime: 1db9bc3701e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000238]=00000000, mtime: 1db9bc3708c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023a]=00000000, mtime: 1db9bc370db, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023c]=00000000, mtime: 1db9bc3712f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000023e]=00000000, mtime: 1db9bc37181, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000240]=00000000, mtime: 1db9bc371dc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000242]=00000000, mtime: 1db9bc37231, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000244]=00000000, mtime: 1db9bc37283, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000246]=00000000, mtime: 1db9bc372d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000248]=00000000, mtime: 1db9bc37328, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024a]=00000000, mtime: 1db9bc3737b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024c]=00000000, mtime: 1db9bc373cb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000024e]=00000000, mtime: 1db9bc3741d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000250]=00000000, mtime: 1db9bc3746f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000252]=00000000, mtime: 1db9bc374d5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000254]=00000000, mtime: 1db9bc37546, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000256]=00000000, mtime: 1db9bc375be, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000258]=00000000, mtime: 1db9bc37626, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025a]=00000000, mtime: 1db9bc3769b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025c]=00000000, mtime: 1db9bc37705, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000025e]=00000000, mtime: 1db9bc37775, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000260]=00000000, mtime: 1db9bc377f4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000262]=00000000, mtime: 1db9bc3786f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000264]=00000000, mtime: 1db9bc378e8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000266]=00000000, mtime: 1db9bc37959, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000268]=00000000, mtime: 1db9bc379c7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026a]=00000000, mtime: 1db9bc37a3a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026c]=00000000, mtime: 1db9bc37ab7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000026e]=00000000, mtime: 1db9bc37b2c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000270]=00000000, mtime: 1db9bc37b9d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000272]=00000000, mtime: 1db9bc37c11, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000274]=00000000, mtime: 1db9bc37c71, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000276]=00000000, mtime: 1db9bc37cc4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000278]=00000000, mtime: 1db9bc37d13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027a]=00000000, mtime: 1db9bc37d63, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027c]=00000000, mtime: 1db9bc37db2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000027e]=00000000, mtime: 1db9bc37e08, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000280]=00000000, mtime: 1db9bc37e58, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000282]=00000000, mtime: 1db9bc37ea8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000284]=00000000, mtime: 1db9bc37efa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000286]=00000000, mtime: 1db9bc37f4a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000288]=00000000, mtime: 1db9bc37f9a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028a]=00000000, mtime: 1db9bc37fe9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028c]=00000000, mtime: 1db9bc38038, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000028e]=00000000, mtime: 1db9bc3808d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000290]=00000000, mtime: 1db9bc380dc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000292]=00000000, mtime: 1db9bc38130, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000294]=00000000, mtime: 1db9bc381ba, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000296]=00000000, mtime: 1db9bc38210, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000298]=00000000, mtime: 1db9bc38260, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029a]=00000000, mtime: 1db9bc382b2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029c]=00000000, mtime: 1db9bc38302, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000029e]=00000000, mtime: 1db9bc38350, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a0]=00000000, mtime: 1db9bc383a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a2]=00000000, mtime: 1db9bc3841a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a4]=00000000, mtime: 1db9bc38495, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a6]=00000000, mtime: 1db9bc38506, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800002a8]=00000000, mtime: 1db9bc38575, mtimecmp: 0 +address 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00000000 +insn_type : CINSN +[80001f32]=00000000, mtime: 1db9bc6f756, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f34]=00000000, mtime: 1db9bc6f783, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f36]=00000000, mtime: 1db9bc6f7b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f38]=00000000, mtime: 1db9bc6f7dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3a]=00000000, mtime: 1db9bc6f80a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3c]=00000000, mtime: 1db9bc6f836, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3e]=00000000, mtime: 1db9bc6f863, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f40]=00000000, mtime: 1db9bc6f890, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f42]=00000000, mtime: 1db9bc6f8bc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f44]=00000000, mtime: 1db9bc6f8e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f46]=00000000, mtime: 1db9bc6f915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f48]=00000000, mtime: 1db9bc6f942, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4a]=00000000, mtime: 1db9bc6f96e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4c]=00000000, mtime: 1db9bc6f99b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4e]=00000000, mtime: 1db9bc6f9d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f50]=00000000, mtime: 1db9bc6fa07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f52]=00000000, mtime: 1db9bc6fa34, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f54]=00000000, mtime: 1db9bc6fa60, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f56]=00000000, mtime: 1db9bc6fa8c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f58]=00000000, mtime: 1db9bc6fab9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5a]=00000000, mtime: 1db9bc6fae6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5c]=00000000, mtime: 1db9bc6fb13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5e]=00000000, mtime: 1db9bc6fb40, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f60]=00000000, mtime: 1db9bc6fb6c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f62]=00000000, mtime: 1db9bc6fb99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f64]=00000000, mtime: 1db9bc6fbc5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f66]=00000000, mtime: 1db9bc6fbf2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f68]=00000000, mtime: 1db9bc6fc1e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6a]=00000000, mtime: 1db9bc6fc4b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6c]=00000000, mtime: 1db9bc6fc78, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6e]=00000000, mtime: 1db9bc6fca4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f70]=00000000, mtime: 1db9bc6fcd1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f72]=00000000, mtime: 1db9bc6fcfd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f74]=00000000, mtime: 1db9bc6fd2a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f76]=00000000, mtime: 1db9bc6fd56, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f78]=00000000, mtime: 1db9bc6fd83, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7a]=00000000, mtime: 1db9bc6fdaf, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7c]=00000000, mtime: 1db9bc6fddc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7e]=00000000, mtime: 1db9bc6fe08, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f80]=00000000, mtime: 1db9bc6fe35, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f82]=00000000, mtime: 1db9bc6fe61, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f84]=00000000, mtime: 1db9bc6fe8f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f86]=00000000, mtime: 1db9bc6febb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f88]=00000000, mtime: 1db9bc6fee8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8a]=00000000, mtime: 1db9bc6ff14, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8c]=00000000, mtime: 1db9bc6ff41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8e]=00000000, mtime: 1db9bc6ff6d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f90]=00000000, mtime: 1db9bc6ff99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f92]=00000000, mtime: 1db9bc6ffc6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f94]=00000000, mtime: 1db9bc6fff2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f96]=00000000, mtime: 1db9bc7001e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f98]=00000000, mtime: 1db9bc7004c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9a]=00000000, mtime: 1db9bc70078, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9c]=00000000, mtime: 1db9bc700a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9e]=00000000, mtime: 1db9bc700d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa0]=00000000, mtime: 1db9bc700ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa2]=00000000, mtime: 1db9bc7012b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa4]=00000000, mtime: 1db9bc70158, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa6]=00000000, mtime: 1db9bc70184, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa8]=00000000, mtime: 1db9bc701b1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001faa]=00000000, mtime: 1db9bc701dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fac]=00000000, mtime: 1db9bc7021a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fae]=00000000, mtime: 1db9bc70246, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb0]=00000000, mtime: 1db9bc70273, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb2]=00000000, mtime: 1db9bc702a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb4]=00000000, mtime: 1db9bc702cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb6]=00000000, mtime: 1db9bc702f8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb8]=00000000, mtime: 1db9bc70325, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fba]=00000000, mtime: 1db9bc70352, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbc]=00000000, mtime: 1db9bc7037e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbe]=00000000, mtime: 1db9bc703ab, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc0]=00000000, mtime: 1db9bc703d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc2]=00000000, mtime: 1db9bc70408, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc4]=00000000, mtime: 1db9bc7043b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc6]=00000000, mtime: 1db9bc70477, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc8]=00000000, mtime: 1db9bc704bb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fca]=00000000, mtime: 1db9bc704fc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fcc]=00000000, mtime: 1db9bc7053e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fce]=00000000, mtime: 1db9bc70573, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd0]=00000000, mtime: 1db9bc705a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd2]=00000000, mtime: 1db9bc705d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 +address ffff0000 +insn_type : CINSN +[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 +address ffffffff +insn_type : INSN +[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 +raise_exception: illegal instruction 0x2 0xffffffff +done interp faf int=0 mstatus=80 prv=3 + +Registers: +x0 zero: 00000000 +x1 ra: 00000000 +x2 sp: 80002000 +x3 gp: 00000001 +x4 tp: 00000000 +x5 t0: 800000f0 +x6 t1: 00000000 +x7 t2: 00000000 +x8 s0: 00000000 +x9 s1: 00000000 +x10 a0: 00000000 +x11 a1: 00000000 +x12 a2: 00000000 +x13 a3: 00000000 +x14 a4: 00000000 +x15 a5: 00000000 +x16 a6: 00000000 +x17 a7: 00000000 +x18 s2: 00000000 +x19 s3: 00000000 +x20 s4: 00000000 +x21 s5: 00000000 +x22 s6: 00000000 +x23 s7: 00000000 +x24 s8: 00000000 +x25 s9: 00000000 +x26 s10: 00000000 +x27 s11: 00000000 +x28 t3: 00000000 +x29 t4: 00000000 +x30 t5: 00000000 +x31 t6: 00000000 + +Instructions Stat: +LUI = 1 +AUIPC = 7 +BEQ = 1 +BLT = 1 +ADDI = 9 +FENCE = 2 +ECALL = 2 +CSRRW = 7 +CSRRS = 3 +CSRRWI = 5 +LI* = 1 +MRET = 1 + +Five Most Frequent: +1) ADDI = 9 (0.22%) +2) AUIPC = 7 (0.17%) +3) CSRRW = 7 (0.17%) +4) CSRRWI = 5 (0.12%) +5) CSRRS = 3 (0.07%) + +Memory Reading Area 80000000...80002003 +Memory Writing Area NONE + +>>> Execution time: 26116764 ns +>>> Instruction count: 4015 (IPS=153732) +>>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards +>>> Branching T=1 (50.00%) F=1 (50.00%) + diff --git a/emu-rv32i.c b/emu-rv32i.c index eedb342..55d989e 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -634,6 +634,21 @@ void raise_exception(uint32_t cause, uint32_t tval) return; } + switch(cause){ + case CAUSE_MACHINE_ECALL: + printf("Unimplement Machine ecall!\n"); + return; + case CAUSE_USER_ECALL: + printf("Unimplement User ecall!\n"); + return; + case CAUSE_SUPERVISOR_ECALL: + printf("Unimplement Supervisor ecall!\n"); + return; + case CAUSE_HYPERVISOR_ECALL: + printf("Unimplement Hypervisor ecall!\n"); + return; + } + if (priv <= PRV_S) { /* delegate the exception to the supervisor priviledge */ if (cause & CAUSE_INTERRUPT) @@ -709,7 +724,7 @@ int raise_interrupt() /* read 32-bit instruction from memory by PC */ -uint32_t get_insn32(uint32_t pc, uint32_t *insn) +unsigned char get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA if (pc && pc < minmemr) @@ -720,9 +735,12 @@ uint32_t get_insn32(uint32_t pc, uint32_t *insn) uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; +#ifdef DEBUG_OUTPUT + printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); +#endif #ifdef RV32C if((p[0] & 0x03) < 3){ - *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; + *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } #endif @@ -1870,15 +1888,35 @@ void execute_instruction() switch(funct3){ case 0: /* C.NOP, C.ADDI */ if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ +#ifdef DEBUG_EXTRA + dprintf(">>> C.NOP\n"); +#endif return; } else { - rs1 = rd = (midpart >> 5) & 0x1f; +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; } break; case 1: /* C.JAL, C.ADDIW */ +#ifdef DEBUG_EXTRA switch(XLEN){ + case 32: + dprintf(">>> C.JAL\n"); + break; + case 64: + case 128: + dprintf(">>> C.ADDIW\n"); + break; + default: + dprintf(">>> Unknow XLEN\n"); + break; + } +#endif + switch(XLEN) { case 32: imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | @@ -1898,24 +1936,235 @@ void execute_instruction() break; case 64: case 128: - rs1 = rd = (midpart >> 5) & 0x1f; + rs1 = rd = ((midpart >> 5) & 0x1f); imm = (midpart >> (11 - 5)) | - midpart & 0x1f; + (midpart & 0x1f); val = reg[rs1] + imm; break; } break; case 2: /* C.LI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.LI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); + val = imm; + printf("%08x, rd: %d\n", val, rd); break; case 3: /* C.ADDI16SP, C.LUI */ +#ifdef DEBUG_EXTRA + switch(rd){ + case 2: + dprintf(">>> C.ADDI16SP\n"); + break; + default: + dprintf(">>> C.LUI\n"); + } +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + switch(rd){ + case 2: + imm = ((midpart >> 4) & 0x1) | + ((midpart << 1) & 0x2) | + ((midpart) & 0x8) | + ((midpart << 2) & 0xc) | + ((midpart >> 5) & 0x10); + imm = imm << 4; + val = reg[rd] + imm; + break; + default: + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = ((imm << 12) & 0xfffff000); + imm = imm << 14 >> 14; + if(rd != 0) + val = reg[rd] | imm; + break; + } break; case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + switch(((midpart >> 8) & 0x3)){ + case 0: /* C.SRLI C.SRLI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRLI\n"); + break; + case 128: + dprintf(">>> C.SRLI64\n"); + break; + } +#endif + switch(XLEN){ + case 32: + case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | (midpart >> 5 & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val >> imm; + break; + case 1: /* C.SRAI C.SRAI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRAI\n"); + case 128: + dprintf(">>> C.SRAI64\n"); + } +#endif + switch(XLEN){ + case 32: case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val << imm; + break; + case 2: /* C.ANDI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ANDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + val = val & imm; + break; + case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ + rs2 = (midpart & 0x7) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ + case 0: /* C.SUB */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUB\n"); +#endif + val = reg[rd] - reg[rs2]; + break; + case 1: /* C.XOR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.XOR\n"); +#endif + val = reg[rd] ^ reg[rs2]; + break; + case 2: /* C.OR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.OR\n"); +#endif + val = reg[rd] | reg[rs2]; + break; + case 3: /* C.AND */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.AND\n"); +#endif + val = reg[rd] & reg[rs2]; + break; + case 4: /* C.SUBW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUBW\n"); +#endif + val = reg[rd] - reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 5: /* C.ADDW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDW\n"); +#endif + val = reg[rd] + reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 6: + case 7: + /* NOP */ + break; + } + } break; case 5: /* C.J */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.J\n"); +#endif + rd = 0; + imm = ((midpart >> 1) & 0x7) | + ((midpart >> 6) & 0x8) | + ((midpart << 5) & 0x10) | + ((midpart) & 0x20) | + ((midpart << 2) & 0x40) | + ((midpart) & 0x180)| + ((midpart << 3) & 0x200)| + ((midpart) & 0x400); + imm = (imm << 1) << 20 >> 20; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; break; case 6: /* C.BEQZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BEQZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + if(reg[rs1] == 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 3) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } break; case 7: /* C.BNEZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BNEZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + imm = 0; + if(reg[rs1] != 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } +#ifdef DEBUG_EXTRA + printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); +#endif break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1972,11 +2221,11 @@ void riscv_cpu_interp_x32() /* Compressed or normal */ insn_type = get_insn32(pc, &insn); #ifdef RV32C - if(insn_type) + if(insn_type == CINSN) next_pc = pc + 2; #endif #ifdef DEBUG_EXTRA - printf("insn : %#x\n", insn); + printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); #endif insn_counter++; @@ -1985,8 +2234,8 @@ void riscv_cpu_interp_x32() execute_instruction(); } - /* test for misaligned fetches */ - if (next_pc & 3) { + /* test for misaligned fetches , in order to match the compressed instruction. */ + if (next_pc & 0x1) { raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } From 6331c1535ae1fef98b95c35b7d128957b7c74474 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:45:49 +0800 Subject: [PATCH 06/24] Add the new function for signature validation --- Makefile | 1 - debug.txt | 12249 -------------------------------------------------- emu-rv32i.c | 129 +- 3 files changed, 98 insertions(+), 12281 deletions(-) delete mode 100644 debug.txt diff --git a/Makefile b/Makefile index 74f1012..543669f 100644 --- a/Makefile +++ b/Makefile @@ -7,7 +7,6 @@ CFLAGS = -O3 -Wall LDFLAGS = -lelf all: $(BINS) - emu-rv32i: emu-rv32i.c $(CC) $(CFLAGS) -o $@ $< $(LDFLAGS) diff --git a/debug.txt b/debug.txt deleted file mode 100644 index ac5df94..0000000 --- a/debug.txt +++ /dev/null @@ -1,12249 +0,0 @@ -./emu-rv32i work/rv32imc/C-NOP.elf -sym '/tmp/ccoevK6z.o' 0 -sym 'reset_vector' 80000040 -sym 'trap_vector' 80000004 -sym 'write_tohost' 80000036 -sym 'handle_exception' 80000032 -sym 'other_exception' 80000032 -sym 'begin_testcode' 800000f0 -sym 'test_1_res' 80002000 -sym 'end_testcode' 80000122 -sym 'end_signature' 80002020 -sym 'begin_regstate' 80002100 -sym 'begin_signature' 80002000 -sym '_start' 80000000 -sym 'end_regstate' 80002200 -sym '_end' 80002204 -sym 'fromhost' 80001100 -sym 'tohost' 80001000 -begin_signature: 0x80002000 -end_signature: 0x80002020 -start: 0x80000000 -codesize: 0x00002204 (8708) -codesize with offset: 8708 -address 0001a081 -insn_type : CINSN -[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 ->>> C.J -address f1402573 -insn_type : INSN -[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -address 0297e101 -insn_type : CINSN -[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a -address 00000297 -insn_type : INSN -[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 ->>> AUIPC -address 01228293 -insn_type : INSN -[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x00000000 -csr_write: csr=0x305 val=0x80000058 -address 18005073 -insn_type : INSN -[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x180 -1 -csr_read: csr=0x180 --> 0x00000000 -csr_write: csr=0x180 val=0x00000000 -address 02970001 -insn_type : CINSN -[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 ->>> C.NOP -address 00000297 -insn_type : INSN -[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 ->>> AUIPC -address 01828293 -insn_type : INSN -[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000058 -csr_write: csr=0x305 val=0x80000070 -address 907352fd -insn_type : CINSN -[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 ->>> C.LI -0000003f, rd: 5 -address 3b029073 -insn_type : INSN -[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3b0 -1 -csr_read: invalid CSR=0x3b0 -csr_write: csr=0x3b0 val=0x0000003f -address 907342fd -insn_type : CINSN -[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 ->>> C.LI -0000001f, rd: 5 -address 3a029073 -insn_type : INSN -[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3a0 -1 -csr_read: invalid CSR=0x3a0 -csr_write: csr=0x3a0 val=0x0000001f -address 00000297 -insn_type : INSN -[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 ->>> AUIPC -address 01828293 -insn_type : INSN -[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000070 -csr_write: csr=0x305 val=0x80000088 -address 30205073 -insn_type : INSN -[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x302 -1 -csr_read: csr=0x302 --> 0x00000000 -csr_write: csr=0x302 val=0x00000000 -address 30305073 -insn_type : INSN -[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x303 -1 -csr_read: csr=0x303 --> 0x00000000 -csr_write: csr=0x303 val=0x00000000 -address 30405073 -insn_type : INSN -[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x304 -1 -csr_read: csr=0x304 --> 0x00000000 -csr_write: csr=0x304 val=0x00000000 -address 02974181 -insn_type : CINSN -[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 ->>> C.LI -00000000, rd: 3 -address 00000297 -insn_type : INSN -[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 ->>> AUIPC -address f7a28293 -insn_type : INSN -[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 ->>> ADDI -address 30529073 -insn_type : INSN -[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000088 -csr_write: csr=0x305 val=0x80000004 -address 057e4505 -insn_type : CINSN -[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 ->>> C.LI -00000001, rd: 10 -address 4763057e -insn_type : CINSN -[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 -address 00054763 -insn_type : INSN -[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 ->>> BLT -address 0ff0000f -insn_type : INSN -[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 ->>> FENCE -address 00734185 -insn_type : CINSN -[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 ->>> C.LI -00000001, rd: 3 -address 00000073 -insn_type : INSN -[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 ->>> ECALL -syscall: 0001 -Unimplement Machine ecall! -address 80000297 -insn_type : INSN -[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 ->>> AUIPC -address f5828293 -insn_type : INSN -[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 ->>> ADDI -address 00028e63 -insn_type : INSN -[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 ->>> BEQ -address 30005073 -insn_type : INSN -[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x300 -1 -csr_read: csr=0x300 --> 0x00000000 -csr_write: csr=0x300 val=0x00000000 -address 00002537 -insn_type : INSN -[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 ->>> LUI -address 80050513 -insn_type : INSN -[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 ->>> ADDI -address 30052073 -insn_type : INSN -[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 -csr_read: csr=0x300 1 -csr_read: csr=0x300 --> 0x00000000 ->>> CSRRS -csr_write: csr=0x300 val=0x00001800 -address 00000297 -insn_type : INSN -[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 ->>> AUIPC -address 01428293 -insn_type : INSN -[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 ->>> ADDI -address 34129073 -insn_type : INSN -[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x341 -1 -csr_read: csr=0x341 --> 0x00000000 -csr_write: csr=0x341 val=0x800000f0 -address f1402573 -insn_type : INSN -[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -address 30200073 -insn_type : INSN -[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 ->>> MRET -address 00002117 -insn_type : INSN -[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 ->>> AUIPC -address f1010113 -insn_type : INSN -[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 ->>> ADDI -address 00000013 -insn_type : INSN -[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 ->>> ADDI -address c0020001 -insn_type : CINSN -[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 ->>> C.NOP -address 4201c002 -insn_type : CINSN -[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 -address 02014201 -insn_type : CINSN -[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 ->>> C.LI -00000000, rd: 4 -address c2120201 -insn_type : CINSN -[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 ->>> C.ADDI -address 4401c212 -insn_type : CINSN -[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 -address 04014401 -insn_type : CINSN -[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 ->>> C.LI -00000000, rd: 8 -address c4220401 -insn_type : CINSN -[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 ->>> C.ADDI -address 4481c422 -insn_type : CINSN -[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 -address 04814481 -insn_type : CINSN -[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 ->>> C.LI -00000000, rd: 9 -address c6260481 -insn_type : CINSN -[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 ->>> C.ADDI -address 4581c626 -insn_type : CINSN -[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 -address 05814581 -insn_type : CINSN -[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 ->>> C.LI -00000000, rd: 11 -address c82e0581 -insn_type : CINSN -[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 ->>> C.ADDI -address 000fc82e -insn_type : CINSN -[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 -address 0ff0000f -insn_type : INSN -[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 ->>> FENCE -address 00734185 -insn_type : CINSN -[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 ->>> C.LI -00000001, rd: 3 -address 00000073 -insn_type : INSN -[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 ->>> ECALL -syscall: 0001 -Unimplement Machine ecall! -address 00000000 -insn_type : CINSN -[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 -address 00000000 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-insn_type : CINSN -[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 -address ffff0000 -insn_type : CINSN -[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 -address ffffffff -insn_type : INSN -[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 -raise_exception: illegal instruction 0x2 0xffffffff -done interp faf int=0 mstatus=80 prv=3 - -Registers: -x0 zero: 00000000 -x1 ra: 00000000 -x2 sp: 80002000 -x3 gp: 00000001 -x4 tp: 00000000 -x5 t0: 800000f0 -x6 t1: 00000000 -x7 t2: 00000000 -x8 s0: 00000000 -x9 s1: 00000000 -x10 a0: 00000000 -x11 a1: 00000000 -x12 a2: 00000000 -x13 a3: 00000000 -x14 a4: 00000000 -x15 a5: 00000000 -x16 a6: 00000000 -x17 a7: 00000000 -x18 s2: 00000000 -x19 s3: 00000000 -x20 s4: 00000000 -x21 s5: 00000000 -x22 s6: 00000000 -x23 s7: 00000000 -x24 s8: 00000000 -x25 s9: 00000000 -x26 s10: 00000000 -x27 s11: 00000000 -x28 t3: 00000000 -x29 t4: 00000000 -x30 t5: 00000000 -x31 t6: 00000000 - -Instructions Stat: -LUI = 1 -AUIPC = 7 -BEQ = 1 -BLT = 1 -ADDI = 9 -FENCE = 2 -ECALL = 2 -CSRRW = 7 -CSRRS = 3 -CSRRWI = 5 -LI* = 1 -MRET = 1 - -Five Most Frequent: -1) ADDI = 9 (0.22%) -2) AUIPC = 7 (0.17%) -3) CSRRW = 7 (0.17%) -4) CSRRWI = 5 (0.12%) -5) CSRRS = 3 (0.07%) - -Memory Reading Area 80000000...80002003 -Memory Writing Area NONE - ->>> Execution time: 26116764 ns ->>> Instruction count: 4015 (IPS=153732) ->>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards ->>> Branching T=1 (50.00%) F=1 (50.00%) - diff --git a/emu-rv32i.c b/emu-rv32i.c index 55d989e..db6724e 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -18,7 +18,9 @@ #include #include #include - +#include +#include +#include /* uncomment this for an instruction trace and other debug outputs */ // #define DEBUG_OUTPUT // #define DEBUG_EXTRA @@ -1893,14 +1895,14 @@ void execute_instruction() #endif return; } else { + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; #ifdef DEBUG_EXTRA dprintf(">>> C.ADDI\n"); + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); #endif - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - val = reg[rs1] + imm; - } - break; + }break; case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA switch(XLEN){ @@ -1926,9 +1928,8 @@ void execute_instruction() ((midpart << 4) & 0x10) | ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); - imm = imm & 0xfffe; - if (rd != 0) - reg[1] = pc + 2; /* Store the link to x1 register */ + imm = (imm << 1) & 0xfffe; + reg[1] = pc + 2; /* Store the link to x1 register */ next_pc = (int32_t)(pc + imm); if(next_pc > pc) forward_counter++; else backward_counter++; @@ -1950,7 +1951,6 @@ void execute_instruction() rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); val = imm; - printf("%08x, rd: %d\n", val, rd); break; case 3: /* C.ADDI16SP, C.LUI */ #ifdef DEBUG_EXTRA @@ -1962,15 +1962,14 @@ void execute_instruction() dprintf(">>> C.LUI\n"); } #endif - rs1 = rd = ((midpart >> 5) & 0x1f); - switch(rd){ + switch(rd){ /* C.ADDI16SP */ case 2: imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | - ((midpart) & 0x8) | - ((midpart << 2) & 0xc) | - ((midpart >> 5) & 0x10); - imm = imm << 4; + ((midpart >> 1) & 0x4) | + ((midpart << 2) & 0x18) | + ((midpart >> 5) & 0x20); + imm = (imm << 4 )<< (31 - 9) >> (31 - 9); val = reg[rd] + imm; break; default: @@ -2175,6 +2174,25 @@ void execute_instruction() } break; case 2: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 6: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SWSP\n"); +#endif + rs2 = midpart & 0x1f; + imm = ((midpart >> 2) & 0x1e0) | + ((midpart << 4) & 0x600); + imm = (imm >> 3) & 0xff; + addr = reg[2] + imm; + val = reg[rs2]; + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + } break; default: @@ -2256,16 +2274,31 @@ int main(int argc, char **argv) /* automatic STDOUT flushing, no fflush needed */ setvbuf(stdout, NULL, _IONBF, 0); - /* parse command line */ - const char *elf_file = NULL; - const char *signature_file = NULL; - for (int i = 1; i < argc; i++) { - char *arg = argv[i]; - if (arg == strstr(arg, "+signature=")) { - signature_file = arg + 11; - } else if (arg[0] != '-') { - elf_file = arg; + const char* elf_file = NULL; + const char* signature_file = NULL; + const char* output_file = NULL; + int cmd_opt = 0; + struct option opts[] = { + {"elf", 1, NULL, 'e'}, + {"signature", 1, NULL, 's'}, + {"output", 1, NULL, 'o'} + }; + const char* optstring = "e:s:o:"; + while((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1){ + switch(cmd_opt){ + case 'e': + elf_file = optarg; + break; + case 's': + signature_file = optarg; + break; + case 'o': + output_file = optarg; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; } } if (elf_file == NULL) { @@ -2446,18 +2479,52 @@ int main(int argc, char **argv) uint64_t ns2 = get_clock(); /* write signature */ + /* Check signature */ if (signature_file) { - FILE *sf = fopen(signature_file, "w"); + FILE* sf = fopen(signature_file, "r"); + if(sf == NULL){ + printf("Error opening file\n"); + return -1; + } int size = end_signature - begin_signature; - for (int i = 0; i < size / 16; i++) { - for (int j = 0; j < 16; j++) { - fprintf(sf, "%02x", ram[begin_signature + 15 - j - ram_start]); + char temp[50], ans[50]; + uint32_t tb = begin_signature; + int err = 0; + for(int i=0;i %s\n", temp, ans); + err++; + }else{ + printf("%s\n", temp); + } + memset(temp, '\0', 50); + } + if(err == 0){ + printf("%s TEST PASSED\n", elf_file); + }else{ + printf("%s TEST FAILED\n", elf_file); + printf("Number of failed signature : %d\n", err); } fclose(sf); } + if (output_file) { + FILE* of = fopen(output_file, "w"); + int size = end_signature - begin_signature; + for (int i = 0; i < size / 4; i++) { + for (int j = 0; j < 4; j++) { + fprintf(of, "%02x", ram[begin_signature + 3 - j - ram_start]); + } + begin_signature += 4; + fprintf(of, "\n"); + } + fclose(of); + } #ifdef DEBUG_EXTRA dump_regs(); From 5b143f9b73a621cd7ac580572ad441f266c93a88 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:49:01 +0800 Subject: [PATCH 07/24] Modified the gitignore --- .gitignore | 2 ++ 1 file changed, 2 insertions(+) diff --git a/.gitignore b/.gitignore index 4aa3c06..c5adc9d 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,4 @@ emu-rv32i test1 +sig.txt +rom.v From 25705a36b089e76e2a0a43359fb81afa20763e5f Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 18:02:14 +0800 Subject: [PATCH 08/24] Update README.txt Add the method of how to test file --- README.md | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/README.md b/README.md index 723e246..ad7c8bf 100644 --- a/README.md +++ b/README.md @@ -12,9 +12,13 @@ How to compile it: ```shell $ gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i ``` +or +```shell +$ make emu-rv32i +``` -Run RV32I compliance tests. -Assume `emu-rv32i` in `$PATH` environment variable. +Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance +- Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/) ```shell $ git clone https://github.com/riscv/riscv-compliance $ cd riscv-compliance @@ -23,12 +27,7 @@ $ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i va Compiling and running simple code: ```shell -$ riscv32-unknown-elf-gcc -O3 -nostdlib test1.c -o test1 -``` - -or -```shell -$ riscv64-unknown-elf-gcc -march=rv32i -mabi=ilp32 -O3 -nostdlib test1.c -o test1 +$ make test1 ``` then @@ -37,6 +36,13 @@ $ ./emu-rv32i test1 Hello RISC-V! ``` +Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance +``shell +make C-ADDI.log +``` +If there is no accident, it will output the `TEST PASSED` + + RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. ## How to build RISC-V toolchain from scratch From 5036e85845f33bac195a080f7b5dcebfe58179b9 Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 18:05:41 +0800 Subject: [PATCH 09/24] Update README.txt --- README.md | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/README.md b/README.md index ad7c8bf..c0d1243 100644 --- a/README.md +++ b/README.md @@ -36,15 +36,17 @@ $ ./emu-rv32i test1 Hello RISC-V! ``` +- RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. + + Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance -``shell +```shell make C-ADDI.log ``` If there is no accident, it will output the `TEST PASSED` -RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. - +- RV32C instructions can be enabled by commenting `#define RV32C` ## How to build RISC-V toolchain from scratch https://github.com/riscv/riscv-gnu-toolchain From 965e0d871ea705eb59a1b47a35e4d9686a1d8e73 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 18:15:49 +0800 Subject: [PATCH 10/24] Modified the makefile to enable to check the validation --- Makefile | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/Makefile b/Makefile index 543669f..381d946 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,30 @@ BINS = emu-rv32i test1 +TEST_TARGETS = \ + C-ADD.elf \ + C-ADDI.elf \ + C-ADDI4SPN.elf \ + C-AND.elf \ + C-ANDI.elf \ + C-BEQZ.elf \ + C-BNEZ.elf \ + C-J.elf \ + C-JAL.elf \ + C-JALR.elf \ + C-JR.elf \ + C-LI.elf \ + C-LUI.elf \ + C-LW.elf \ + C-LWSP.elf \ + C-MV.elf \ + C-NOP.elf \ + C-OR.elf \ + C-SLLI.elf \ + C-SRAI.elf \ + C-SRLI.elf \ + C-SUB.elf \ + C-SW.elf \ + C-SWSP.elf \ + C-XOR.elf CROSS_COMPILE = riscv-none-embed- RV32I_CFLAGS = -march=rv32i -mabi=ilp32 -O3 -nostdlib From 3ce28805e578cab571e2012bec579be378126570 Mon Sep 17 00:00:00 2001 From: kksweet8845 <37268557+kksweet8845@users.noreply.github.com> Date: Thu, 2 Jan 2020 23:35:35 +0800 Subject: [PATCH 11/24] Update README.md --- README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/README.md b/README.md index c0d1243..748f7eb 100644 --- a/README.md +++ b/README.md @@ -1,4 +1,4 @@ -# RISC-V RV32I[MA] emulator with ELF support +# RISC-V RV32I[MAC] emulator with ELF support This is a RISC-V emulator for the RV32I architecture, based on [TinyEMU](https://bellard.org/tinyemu/) and stripped down for RV32I only. From 0bff3d33f0e609806fcbc7c90cda81b41b7464db Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sat, 11 Jan 2020 16:18:11 +0800 Subject: [PATCH 12/24] Finish the Compressed instruction imp --- .gitignore | 2 + emu-rv32i.c | 658 +++++++++++++++++++++++++++++++++++++++++++++------- 2 files changed, 582 insertions(+), 78 deletions(-) diff --git a/.gitignore b/.gitignore index c5adc9d..91d1c1b 100644 --- a/.gitignore +++ b/.gitignore @@ -2,3 +2,5 @@ emu-rv32i test1 sig.txt rom.v +debug.txt +CSR.h \ No newline at end of file diff --git a/emu-rv32i.c b/emu-rv32i.c index db6724e..b72d218 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -35,87 +35,99 @@ uint32_t minmemr, maxmemr, minmemw, maxmemw; #define STATS_NUM 64 -unsigned int stats[STATS_NUM], top[5], itop[5]; - -char statnames[64][16] = { - "LUI", "AUIPC", "JAL", "JALR", "BEQ", "BNE", "BLT", - "BGE", "BLTU", "BGEU", "LB", "LH", "LW", "LBU", - "LHU", "SB", "SH", "SW", "ADDI", "SLTI", "SLTIU", - "XORI", "ORI", "ANDI", "SLLI", "SRLI", "SRAI", "ADD", - "SUB", "SLL", "SLT", "SLTU", "XOR", "SRL", "SRA", - "OR", "AND", "FENCE", "FENCE.I", "ECALL", "EBREAK", "CSRRW", - "CSRRS", "CSRRC", "CSRRWI", "CSRRSI", "CSRRCI", "LI*", "MUL", - "MULH", "MULHSU", "MULHU", "DIV", "DIVU", "REM", "REMU", - "LR.W", "SC.W", "URET", "SRET", "MRET", "WFI", "SFENCE.VMA", - ""}; +#define C_STATS_NUM 64 + +#ifndef RV32C +unsigned int stats[STATS_NUM], c_stats[C_STATS_NUM],top[5],itop[5]; +char statnames[64][16] = { "LUI","AUIPC","JAL","JALR","BEQ","BNE","BLT","BGE", + "BLTU","BGEU","LB","LH","LW","LBU","LHU","SB","SH","SW","ADDI","SLTI","SLTIU", + "XORI","ORI","ANDI","SLLI","SRLI","SRAI","ADD","SUB","SLL","SLT","SLTU","XOR", + "SRL","SRA","OR","AND","FENCE","FENCE.I","ECALL","EBREAK","CSRRW","CSRRS", + "CSRRC","CSRRWI","CSRRSI","CSRRCI","LI*","MUL","MULH","MULHSU","MULHU","DIV", + "DIVU","REM","REMU","LR.W","SC.W","URET","SRET","MRET","WFI","SFENCE.VMA","" +}; +#endif + +#ifdef RV32C +unsigned int stats[STATS_NUM + C_STATS_NUM],top[5],itop[5]; +char statnames[STATS_NUM + C_STATS_NUM][16] = +{ "LUI","AUIPC","JAL","JALR","BEQ","BNE","BLT","BGE", + "BLTU","BGEU","LB","LH","LW","LBU","LHU","SB","SH","SW","ADDI","SLTI","SLTIU", + "XORI","ORI","ANDI","SLLI","SRLI","SRAI","ADD","SUB","SLL","SLT","SLTU","XOR", + "SRL","SRA","OR","AND","FENCE","FENCE.I","ECALL","EBREAK","CSRRW","CSRRS", + "CSRRC","CSRRWI","CSRRSI","CSRRCI","LI*","MUL","MULH","MULHSU","MULHU","DIV", + "DIVU","REM","REMU","LR.W","SC.W","URET","SRET","MRET","WFI","SFENCE.VMA","", + "ILLINSN", "C.ADDI4SPN", "C.FLD", "C.LQ", "C.LW", + "C.FLW", "C.LD", "Reserved_0", "C.FSD", "C.SQ", "C.SW", "C.FSW", "C.SD", "C.NOP", "C.ADDI", + "C.JAL", "C.ADDIW", "C.LI", "C.ADDI16SP", "C.LUI", "C.SRLI", "C.SRLI64", "C.SRAI", + "C.SRAI64", "C.ANDI", "C.SUB", "C.XOR", "C.OR", "C.AND", "C.SUBW", "C.ADDW", "Reserved_1", + "Reserved_2", "C.J", "C.BEQZ", "C.BNEZ", "C.SLLI", "C.SLLI64", "C.FLDSP", "C.LQSP", + "C.LWSP", "C.FLWSP", "C.LDSP", "C.JR", "C.MV", "C.EBREAK", "C.JALR", "C.ADD", "C.FSDSP", + "C.SQSP", "C.SWSP", "C.FSWSP", "C.SDSP", "", "", "", "", "", "", "", "", "", "", "" +}; +#endif void init_stats(void) { - for (int i = 0; i < STATS_NUM; i++) - stats[i] = 0; - minmemr = minmemw = ~0; - maxmemr = maxmemw = 0; + for(int i=0;i top[0]) { - top[4] = top[3]; - itop[4] = itop[3]; - top[3] = top[2]; - itop[3] = itop[2]; - top[2] = top[1]; - itop[2] = itop[1]; - top[1] = top[0]; - itop[1] = itop[0]; - top[0] = stats[i]; - itop[0] = i; - } else if (stats[i] > top[1]) { - top[4] = top[3]; - itop[4] = itop[3]; - top[3] = top[2]; - itop[3] = itop[2]; - top[2] = top[1]; - itop[2] = itop[1]; - top[1] = stats[i]; - itop[1] = i; - } else if (stats[i] > top[2]) { - top[4] = top[3]; - itop[4] = itop[3]; - top[3] = top[2]; - itop[3] = itop[2]; - top[2] = stats[i]; - itop[2] = i; - } else if (stats[i] > top[3]) { - top[4] = top[3]; - itop[4] = itop[3]; - top[3] = stats[i]; - itop[3] = i; - } else if (stats[i] > top[4]) { - top[4] = stats[i]; - itop[4] = i; - } - if (stats[i]) { - if (i < 63) - printf("%s\t= %u\n", statnames[i], stats[i]); - else - printf("[%i] = %u\n", i, stats[i]); - } - } - printf("\nFive Most Frequent:\n"); - for (int j = 0; j < 5; j++) { - printf("%i) %s\t= %u (%2.2lf%%)\n", j + 1, statnames[itop[j]], top[j], - top[j] * 100.0 / (double) total); - } - printf("\nMemory Reading Area %x...%x\n", minmemr, maxmemr); - if (minmemw + 1) - printf("Memory Writing Area %x...%x\n", minmemw, maxmemw); - else - printf("Memory Writing Area NONE\n"); + printf("\nInstructions Stat:\n"); + top[0] = top[1] = top[2] = top[3] = top[4] = stats[0]; + itop[0] = itop[1] = itop[2] = itop[3] = itop[4] = 0; + for(int i=0;itop[0]) + { + top[4]=top[3];itop[4]=itop[3]; + top[3]=top[2];itop[3]=itop[2]; + top[2]=top[1];itop[2]=itop[1]; + top[1]=top[0];itop[1]=itop[0]; + top[0]=stats[i];itop[0]=i; + } + else if(stats[i]>top[1]) + { + top[4]=top[3];itop[4]=itop[3]; + top[3]=top[2];itop[3]=itop[2]; + top[2]=top[1];itop[2]=itop[1]; + top[1]=stats[i];itop[1]=i; + } + else if(stats[i]>top[2]) + { + top[4]=top[3];itop[4]=itop[3]; + top[3]=top[2];itop[3]=itop[2]; + top[2]=stats[i];itop[2]=i; + } + else if(stats[i]>top[3]) + { + top[4]=top[3];itop[4]=itop[3]; + top[3]=stats[i];itop[3]=i; + } + else if(stats[i]>top[4]) + { + top[4]=stats[i];itop[4]=i; + } + if(stats[i]) + { + if(i> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 0: /* Illegal instruction, C.ADDI4SPN */ + switch(midpart){ + case 0: +#ifdef DEBUG_EXTRA + dprintf(">>> Illegal instruction\n"); + stats[64+0]++; +#endif + break; + default: +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDI4SPN\n"); + stats[64+1]++; +#endif +#ifdef DEBUG_OUTPUT + printf("rd: %d, imm: %d\n", rd, imm); +#endif + rd = (midpart & 0x7) + 8; + rs1 = 2; + imm = (midpart >> 4) & 0x1 | + (midpart >> 2) & 0x2 | + (midpart >> 7) & 0xe | + (midpart >> 1) & 0xf0; + imm = imm << 2; + imm = imm & 0x3ff; + val = reg[rs1] + imm; + break; + } + break; + case 1: /* C.FLD, C.LQ*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLD */ +#ifdef DEBUG_EXTRA + dprintf("C.FLD\n"); + printf("Not support to floating load double"); + stats[64+2]++; +#endif +#ifdef DEBUG_OUTPUT +#endif + rd = 0; + break; + case 128: /* C.LQ*/ +#ifdef DEBUG_EXTRA + dprintf("C.LQ\n"); + printf("Unimp insn\b"); + stats[64+3]++; +#endif +#ifdef DEBUG_OUTPUT +#endif + rd = 0; + break; + } + } + break; + case 2: /* C.LW */ + { +#ifdef DEBUG_EXTRA + dprintf(">>>C.LW\n"); + stats[64+4]++; +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = (midpart & 0x7) + 8; + imm = (midpart >> 4) & 0x1 | + (midpart >> 7) & 0xe | + (midpart << 1) & 0x10; + imm = (imm << 2) & 0x7f; + addr = reg[rs1] + imm; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t)rval; + +#ifdef DEBUG_OUTPUT + printf("rs1 : %d, rd: %d, imm: %d\n", rs1, rd, imm); + printf("addr: %08x\n", addr); +#endif + } + break; + case 3: /* C.FLW C.LD*/ + { + switch(XLEN){ + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FLW\n"); + stats[64+5]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv64c\n"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.LD\n"); + stats[64+6]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv128c\n"); +#endif + break; + } + } + break; + case 4: /* Reserved */ +#ifdef DEBUG_EXTRA + dprintf(">>> Reserved_0\n"); + stats[64+7]++; +#endif + break; + case 5: /* C.FSD */ + { + switch(XLEN){ + case 32: + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSD\n"); + stats[64+8]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SQ\n"); + stats[64+9]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv32imc"); +#endif + break; + default: +#ifdef DEBUG_OUTPUT + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; +#endif + break; + } + } + break; + case 6: + { +#ifdef DEBUG_EXTRA + dprintf(">>> C.SW\n"); + stats[64+10]++; +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rs2 = (midpart & 0x7) + 8; + imm = ((midpart >> 4) & 0x1) | + ((midpart >> 7) & 0xe) | + ((midpart << 1) & 0x10); + imm = (imm << 2) & 0x7f; + addr = reg[rs1] + imm; + val = reg[rs2]; + rd = 0; + printf("addr: %08x\n", addr); + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } +#ifdef DEBUG_OUTPUT + printf("rs1 : %d, rs2: %d, rd: %d, imm: %d\n", rs1, rs2, rd, imm); + printf("addr: %08x\n", addr); +#endif + } + break; + case 7: + { + switch(XLEN){ + case 32: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSW\n"); + stats[64+11]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv32imc"); +#endif + break; + case 64: + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SD\n"); + stats[64+12]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn by rv32imc\n"); +#endif + break; + } + } + break; + default: + { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; + } + if(rd != 0) + reg[rd] = val; break; case 1: funct3 = (insn >> 13) & 0x7; @@ -1892,6 +2109,7 @@ void execute_instruction() if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ #ifdef DEBUG_EXTRA dprintf(">>> C.NOP\n"); + stats[64+13]++; #endif return; } else { @@ -1900,6 +2118,7 @@ void execute_instruction() val = reg[rs1] + imm; #ifdef DEBUG_EXTRA dprintf(">>> C.ADDI\n"); + stats[64+14]++; printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); #endif }break; @@ -1908,10 +2127,12 @@ void execute_instruction() switch(XLEN){ case 32: dprintf(">>> C.JAL\n"); + stats[64+15]++; break; case 64: case 128: dprintf(">>> C.ADDIW\n"); + stats[64+16]++; break; default: dprintf(">>> Unknow XLEN\n"); @@ -1947,6 +2168,7 @@ void execute_instruction() case 2: /* C.LI */ #ifdef DEBUG_EXTRA dprintf(">>> C.LI\n"); + stats[64+17]++; #endif rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); @@ -1957,9 +2179,12 @@ void execute_instruction() switch(rd){ case 2: dprintf(">>> C.ADDI16SP\n"); + stats[64+18]++; break; default: dprintf(">>> C.LUI\n"); + stats[64+19]++; + break; } #endif switch(rd){ /* C.ADDI16SP */ @@ -1989,9 +2214,11 @@ void execute_instruction() case 32: case 64: dprintf(">>> C.SRLI\n"); + stats[64+20]++; break; case 128: dprintf(">>> C.SRLI64\n"); + stats[64+21]++; break; } #endif @@ -2016,8 +2243,12 @@ void execute_instruction() case 32: case 64: dprintf(">>> C.SRAI\n"); + stats[64+22]++; + break; case 128: dprintf(">>> C.SRAI64\n"); + stats[64+23]++; + break; } #endif switch(XLEN){ @@ -2037,6 +2268,7 @@ void execute_instruction() case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA dprintf(">>> C.ANDI\n"); + stats[64+24]++; #endif rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); @@ -2050,30 +2282,36 @@ void execute_instruction() case 0: /* C.SUB */ #ifdef DEBUG_EXTRA dprintf(">>> C.SUB\n"); + stats[64+25]++; #endif val = reg[rd] - reg[rs2]; break; case 1: /* C.XOR */ #ifdef DEBUG_EXTRA dprintf(">>> C.XOR\n"); + stats[64+26]++; #endif val = reg[rd] ^ reg[rs2]; break; case 2: /* C.OR */ #ifdef DEBUG_EXTRA dprintf(">>> C.OR\n"); + stats[64+27]++; #endif val = reg[rd] | reg[rs2]; + //printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); break; case 3: /* C.AND */ #ifdef DEBUG_EXTRA dprintf(">>> C.AND\n"); + stats[64+28]++; #endif val = reg[rd] & reg[rs2]; break; case 4: /* C.SUBW */ #ifdef DEBUG_EXTRA dprintf(">>> C.SUBW\n"); + stats[64+29]++; #endif val = reg[rd] - reg[rs2]; if(XLEN == 128){ @@ -2087,6 +2325,7 @@ void execute_instruction() case 5: /* C.ADDW */ #ifdef DEBUG_EXTRA dprintf(">>> C.ADDW\n"); + stats[64+30]++; #endif val = reg[rd] + reg[rs2]; if(XLEN == 128){ @@ -2098,7 +2337,15 @@ void execute_instruction() } break; case 6: +#ifdef DEBUG_EXTRA + dprintf(">>> Reserved_1\n"); + stats[64+31]++; +#endif case 7: +#ifdef DEBUG_EXTRA + dprintf(">>> Reserved_2\n"); + stats[64+32]++; +#endif /* NOP */ break; } @@ -2107,6 +2354,7 @@ void execute_instruction() case 5: /* C.J */ #ifdef DEBUG_EXTRA dprintf(">>> C.J\n"); + stats[64+33]++; #endif rd = 0; imm = ((midpart >> 1) & 0x7) | @@ -2126,6 +2374,7 @@ void execute_instruction() case 6: /* C.BEQZ */ #ifdef DEBUG_EXTRA dprintf(">>> C.BEQZ\n"); + stats[64+34]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; @@ -2145,6 +2394,7 @@ void execute_instruction() case 7: /* C.BNEZ */ #ifdef DEBUG_EXTRA dprintf(">>> C.BNEZ\n"); + stats[64+35]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; @@ -2161,7 +2411,7 @@ void execute_instruction() else backward_counter++; jump_counter++; } -#ifdef DEBUG_EXTRA +#ifdef DEBUG_OUTPUT printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); #endif break; @@ -2173,20 +2423,240 @@ void execute_instruction() reg[rd] = val; } break; - case 2: + case 2: /* op 2*/ funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; switch(funct3){ - case 6: + case 0: /* C.SLLI, C.SLLI64*/ + { + imm = ((midpart >> 5 & 0x20) | (midpart & 0x1f)); + switch(XLEN){ + case 32: /* C.SLLI*/ + if(((midpart >> 10) & 0x1)){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SLLI\n"); + stats[64+36]++; +#endif + if(imm == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = imm & 0x3f; + break; + case 128: /* C.SLLI64 */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SLLI64\n"); + stats[64+37]++; +#endif + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = 64; + +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn by rv32imc\n"); +#endif + break; + } + if(rd != 0) + val = (uint32_t) reg[rd] << imm; + } + break; + case 1: /* C.FLDSP C.LQSP*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLDSP */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.FLDSP\n");\ + stats[64+38]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported extension by rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.LQSP\n"); + stats[64+39]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("unsupported extension by rv32imc"); +#endif + break; + } + + } + break; + case 2: /* C.LWSP C.FLWSP*/ + { +#ifdef DEBUG_EXTRA + dprintf(">>> C.LWSP\n"); + stats[64+40]++; +#endif + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = ((midpart >> 2) & 0x7) | + ((midpart >> 7) & 0x8) | + ((midpart << 4) & 0x30); + imm = (imm << 2) & 0xff; + rs1 = 2; + addr = reg[rs1] + imm; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t)rval; +#ifdef DEBUG_OUTPUT +#endif + } + break; + case 3: /* C.FLWSP C.LDSP*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLWSP */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.FLWSP\n"); + stats[64+41]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported extension by rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.LDSP\n"); + stats[64+42]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("unsupported extension by rv32imc"); +#endif + break; + } + + } + break; + case 4: /* C.JR C.MV C.EBREAK C.JALR C.ADD */ + { + rd = 0; + rs1 = (midpart >> 5) & 0x1f; + rs2 = (midpart & 0x1f); + switch((midpart >> 10) & 0x1){ + case 0: + if(rs2 == 0){ /* C.JR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.JR\n"); + stats[64+43]++; +#endif + next_pc = reg[rs1]; + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + +#ifdef DEBUG_OUTPUT + printf("rs1: %d, rs2: %d, rd: %d\n", rs1, rs2, rd); +#endif + }else{ /* C.MV */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.MV\n"); + stats[64+44]++; +#endif + rd = rs1; + if(rd + rs1 + rs2 == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val = reg[rs2]; + } + break; + case 1: + if(rs1 == 0 && rs2 == 0){ /* C.EBREAK */ +#ifdef DEBUG_EXTRA + dprintf(">>> EBREAK\n"); + stats[64+45]++; +#endif + raise_exception(CAUSE_BREAKPOINT, 0); + return; + }else if(rs2 == 0 && rs1 != 0){ /* C.JALR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.JALR\n"); + stats[64+46]++; +#endif + rd = 1; + imm = reg[rs1]; + next_pc = reg[rs1]; + val = pc + 2; + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + }else if(rs2 != 0 && rs1 != 0){ /* C.ADD */ + rd = rs1; + val = reg[rs1] + reg[rs2]; + } + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } + break; + case 5: /* C.FSDSP C.SQSP*/ + { + switch(XLEN){ + case 32: + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSDS{\n"); + stats[64+47]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SQSP\n"); + stats[64+48]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + } + } + break; + case 6: /* C.SWSP*/ + { #ifdef DEBUG_EXTRA dprintf(">>> C.SWSP\n"); + stats[64+49]++; #endif + rd = 0; rs2 = midpart & 0x1f; imm = ((midpart >> 2) & 0x1e0) | ((midpart << 4) & 0x600); imm = (imm >> 3) & 0xff; addr = reg[2] + imm; val = reg[rs2]; +#ifdef DEBUG_OUTPUT + printf("rs2: %d, imm: %d, addr: %08x\n", rs2, imm, addr); +#endif if (target_write_u32(addr, val)) { raise_exception(pending_exception, pending_tval); return; @@ -2194,7 +2664,39 @@ void execute_instruction() break; } break; - + case 7: /* C.FSWSP C.SDSP */ + { + switch(XLEN){ + case 32: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSWSP\n"); + stats[64+50]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + case 64: + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SDSP\n"); + stats[64+51]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + } + } + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0) + reg[rd] = val; + break; +#endif default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; From 28fa1d590743b81f60ebeb03ec330e0147714280 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 29 Dec 2019 19:55:09 +0800 Subject: [PATCH 13/24] Add the compressed C.NOP, C.ADDi and modify the get_insn32 function Add the C.JAL and C.ADDIW insn --- emu-rv32i.c | 84 ++++++++++++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 80 insertions(+), 4 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index b72d218..b5833b8 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -749,12 +749,9 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; -#ifdef DEBUG_OUTPUT - printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); -#endif #ifdef RV32C if((p[0] & 0x03) < 3){ - *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); + *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; return CINSN; } #endif @@ -1064,6 +1061,22 @@ void execute_instruction() } #endif + uint16_t midpart; + + if(insn_type == INSN){ + opcode = insn & 0x7f; + rd = (insn >> 7) & 0x1f; + rs1 = (insn >> 15) & 0x1f; + rs2 = (insn >> 20) & 0x1f; + } + +#ifdef RV32C + if(insn_type == CINSN){ + opcode = insn & 0x3; + } +#endif + + switch (opcode) { @@ -1926,6 +1939,69 @@ void execute_instruction() break; } break; + case 1: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 0: /* C.NOP, C.ADDI */ + if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ + return; + } else { + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + val = reg[rs1] + imm; + } + break; + case 1: /* C.JAL, C.ADDIW */ + switch(XLEN){ + case 32: + imm = (midpart & 0x400) | + ((midpart << 3) & 0x200) | + (midpart & 0x170) | + ((midpart << 2) & 0x40) | + (midpart & 0x20) | + ((midpart << 4) & 0x10) | + ((midpart >> 6) & 0x8) | + ((midpart >> 1) & 0x7); + imm = imm & 0xfffe; + if (rd != 0) + reg[1] = pc + 2; /* Store the link to x1 register */ + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + break; + case 64: + case 128: + rs1 = rd = (midpart >> 5) & 0x1f; + imm = (midpart >> (11 - 5)) | + midpart & 0x1f; + val = reg[rs1] + imm; + break; + } + break; + case 2: /* C.LI */ + break; + case 3: /* C.ADDI16SP, C.LUI */ + break; + case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + break; + case 5: /* C.J */ + break; + case 6: /* C.BEQZ */ + break; + case 7: /* C.BNEZ */ + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0){ + reg[rd] = val; + } + break; + case 2: + break; case 1: /* C.FLD, C.LQ*/ { switch(XLEN){ From 79c72f1c91286cbfc047a5df66bcfb90553d1e61 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 02:58:17 +0800 Subject: [PATCH 14/24] Modified some implementataion detail to support compressed instruction --- debug.txt | 12249 ++++++++++++++++++++++++++++++++++++++++++++++++++ emu-rv32i.c | 251 +- 2 files changed, 12487 insertions(+), 13 deletions(-) create mode 100644 debug.txt diff --git a/debug.txt b/debug.txt new file mode 100644 index 0000000..ac5df94 --- /dev/null +++ b/debug.txt @@ -0,0 +1,12249 @@ +./emu-rv32i work/rv32imc/C-NOP.elf +sym '/tmp/ccoevK6z.o' 0 +sym 'reset_vector' 80000040 +sym 'trap_vector' 80000004 +sym 'write_tohost' 80000036 +sym 'handle_exception' 80000032 +sym 'other_exception' 80000032 +sym 'begin_testcode' 800000f0 +sym 'test_1_res' 80002000 +sym 'end_testcode' 80000122 +sym 'end_signature' 80002020 +sym 'begin_regstate' 80002100 +sym 'begin_signature' 80002000 +sym '_start' 80000000 +sym 'end_regstate' 80002200 +sym '_end' 80002204 +sym 'fromhost' 80001100 +sym 'tohost' 80001000 +begin_signature: 0x80002000 +end_signature: 0x80002020 +start: 0x80000000 +codesize: 0x00002204 (8708) +codesize with offset: 8708 +address 0001a081 +insn_type : CINSN +[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 +>>> C.J +address f1402573 +insn_type : INSN +[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 0297e101 +insn_type : CINSN +[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a +address 00000297 +insn_type : INSN +[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 +>>> AUIPC +address 01228293 +insn_type : INSN +[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x00000000 +csr_write: csr=0x305 val=0x80000058 +address 18005073 +insn_type : INSN +[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x180 -1 +csr_read: csr=0x180 --> 0x00000000 +csr_write: csr=0x180 val=0x00000000 +address 02970001 +insn_type : CINSN +[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 +>>> C.NOP +address 00000297 +insn_type : INSN +[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000058 +csr_write: csr=0x305 val=0x80000070 +address 907352fd +insn_type : CINSN +[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 +>>> C.LI +0000003f, rd: 5 +address 3b029073 +insn_type : INSN +[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3b0 -1 +csr_read: invalid CSR=0x3b0 +csr_write: csr=0x3b0 val=0x0000003f +address 907342fd +insn_type : CINSN +[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 +>>> C.LI +0000001f, rd: 5 +address 3a029073 +insn_type : INSN +[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x3a0 -1 +csr_read: invalid CSR=0x3a0 +csr_write: csr=0x3a0 val=0x0000001f +address 00000297 +insn_type : INSN +[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 +>>> AUIPC +address 01828293 +insn_type : INSN +[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000070 +csr_write: csr=0x305 val=0x80000088 +address 30205073 +insn_type : INSN +[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x302 -1 +csr_read: csr=0x302 --> 0x00000000 +csr_write: csr=0x302 val=0x00000000 +address 30305073 +insn_type : INSN +[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x303 -1 +csr_read: csr=0x303 --> 0x00000000 +csr_write: csr=0x303 val=0x00000000 +address 30405073 +insn_type : INSN +[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x304 -1 +csr_read: csr=0x304 --> 0x00000000 +csr_write: csr=0x304 val=0x00000000 +address 02974181 +insn_type : CINSN +[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 +>>> C.LI +00000000, rd: 3 +address 00000297 +insn_type : INSN +[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 +>>> AUIPC +address f7a28293 +insn_type : INSN +[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 +>>> ADDI +address 30529073 +insn_type : INSN +[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x305 -1 +csr_read: csr=0x305 --> 0x80000088 +csr_write: csr=0x305 val=0x80000004 +address 057e4505 +insn_type : CINSN +[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 +>>> C.LI +00000001, rd: 10 +address 4763057e +insn_type : CINSN +[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 +address 00054763 +insn_type : INSN +[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 +>>> BLT +address 0ff0000f +insn_type : INSN +[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 80000297 +insn_type : INSN +[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 +>>> AUIPC +address f5828293 +insn_type : INSN +[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 +>>> ADDI +address 00028e63 +insn_type : INSN +[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 +>>> BEQ +address 30005073 +insn_type : INSN +[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 +>>> CSRRWI +csr_read: csr=0x300 -1 +csr_read: csr=0x300 --> 0x00000000 +csr_write: csr=0x300 val=0x00000000 +address 00002537 +insn_type : INSN +[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 +>>> LUI +address 80050513 +insn_type : INSN +[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 +>>> ADDI +address 30052073 +insn_type : INSN +[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 +csr_read: csr=0x300 1 +csr_read: csr=0x300 --> 0x00000000 +>>> CSRRS +csr_write: csr=0x300 val=0x00001800 +address 00000297 +insn_type : INSN +[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 +>>> AUIPC +address 01428293 +insn_type : INSN +[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 +>>> ADDI +address 34129073 +insn_type : INSN +[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 +>>> CSRRW +csr_read: csr=0x341 -1 +csr_read: csr=0x341 --> 0x00000000 +csr_write: csr=0x341 val=0x800000f0 +address f1402573 +insn_type : INSN +[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 +csr_read: csr=0xf14 0 +csr_read: csr=0xf14 --> 0x00000000 +>>> CSRRS +address 30200073 +insn_type : INSN +[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 +>>> MRET +address 00002117 +insn_type : INSN +[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 +>>> AUIPC +address f1010113 +insn_type : INSN +[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 +>>> ADDI +address 00000013 +insn_type : INSN +[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 +>>> ADDI +address c0020001 +insn_type : CINSN +[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 +>>> C.NOP +address 4201c002 +insn_type : CINSN +[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 +address 02014201 +insn_type : CINSN +[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 +>>> C.LI +00000000, rd: 4 +address c2120201 +insn_type : CINSN +[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 +>>> C.ADDI +address 4401c212 +insn_type : CINSN +[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 +address 04014401 +insn_type : CINSN +[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 +>>> C.LI +00000000, rd: 8 +address c4220401 +insn_type : CINSN +[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 +>>> C.ADDI +address 4481c422 +insn_type : CINSN +[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 +address 04814481 +insn_type : CINSN +[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 +>>> C.LI +00000000, rd: 9 +address c6260481 +insn_type : CINSN +[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 +>>> C.ADDI +address 4581c626 +insn_type : CINSN +[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 +address 05814581 +insn_type : CINSN +[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 +>>> C.LI +00000000, rd: 11 +address c82e0581 +insn_type : CINSN +[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 +>>> C.ADDI +address 000fc82e +insn_type : CINSN +[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 +address 0ff0000f +insn_type : INSN +[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 +>>> FENCE +address 00734185 +insn_type : CINSN +[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 +>>> C.LI +00000001, rd: 3 +address 00000073 +insn_type : INSN +[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 +>>> ECALL +syscall: 0001 +Unimplement Machine ecall! +address 00000000 +insn_type : CINSN +[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ec]=00000000, mtime: 1db9bc36479, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001ee]=00000000, mtime: 1db9bc364c8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f0]=00000000, mtime: 1db9bc36517, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f2]=00000000, mtime: 1db9bc36565, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f4]=00000000, mtime: 1db9bc365b5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f6]=00000000, mtime: 1db9bc36604, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001f8]=00000000, mtime: 1db9bc36654, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fa]=00000000, mtime: 1db9bc366a8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fc]=00000000, mtime: 1db9bc366fa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[800001fe]=00000000, mtime: 1db9bc3674b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000200]=00000000, mtime: 1db9bc3679a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000202]=00000000, mtime: 1db9bc367ea, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000204]=00000000, mtime: 1db9bc3683a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000206]=00000000, mtime: 1db9bc3688a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000208]=00000000, mtime: 1db9bc368df, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020a]=00000000, mtime: 1db9bc3692e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020c]=00000000, mtime: 1db9bc3697e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[8000020e]=00000000, mtime: 1db9bc369cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80000210]=00000000, mtime: 1db9bc36a1b, mtimecmp: 0 +address 00000000 +insn_type : CINSN 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+[80001eb0]=00000000, mtime: 1db9bc6ebde, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eb2]=00000000, mtime: 1db9bc6ec0b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eb4]=00000000, mtime: 1db9bc6ec37, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eb6]=00000000, mtime: 1db9bc6ec64, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eb8]=00000000, mtime: 1db9bc6ec91, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eba]=00000000, mtime: 1db9bc6ecbd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ebc]=00000000, mtime: 1db9bc6ecea, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ebe]=00000000, mtime: 1db9bc6ed16, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ec0]=00000000, mtime: 1db9bc6ed42, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ec2]=00000000, mtime: 1db9bc6ed71, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ec4]=00000000, mtime: 1db9bc6ed9d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ec6]=00000000, mtime: 1db9bc6edca, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ec8]=00000000, mtime: 1db9bc6edf7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eca]=00000000, mtime: 1db9bc6ee24, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ecc]=00000000, mtime: 1db9bc6ee50, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ece]=00000000, mtime: 1db9bc6ee7d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ed0]=00000000, mtime: 1db9bc6eeaa, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ed2]=00000000, mtime: 1db9bc6eed7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ed4]=00000000, mtime: 1db9bc6ef03, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ed6]=00000000, mtime: 1db9bc6ef30, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ed8]=00000000, mtime: 1db9bc6ef5c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eda]=00000000, mtime: 1db9bc6ef89, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001edc]=00000000, mtime: 1db9bc6efb5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ede]=00000000, mtime: 1db9bc6efe2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ee0]=00000000, mtime: 1db9bc6f00f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ee2]=00000000, mtime: 1db9bc6f03b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ee4]=00000000, mtime: 1db9bc6f067, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ee6]=00000000, mtime: 1db9bc6f094, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ee8]=00000000, mtime: 1db9bc6f0c0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eea]=00000000, mtime: 1db9bc6f0ed, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eec]=00000000, mtime: 1db9bc6f119, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001eee]=00000000, mtime: 1db9bc6f146, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ef0]=00000000, mtime: 1db9bc6f173, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ef2]=00000000, mtime: 1db9bc6f1bb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ef4]=00000000, mtime: 1db9bc6f1e7, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ef6]=00000000, mtime: 1db9bc6f214, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ef8]=00000000, mtime: 1db9bc6f240, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001efa]=00000000, mtime: 1db9bc6f26d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001efc]=00000000, mtime: 1db9bc6f29b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001efe]=00000000, mtime: 1db9bc6f2c8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f00]=00000000, mtime: 1db9bc6f2f4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f02]=00000000, mtime: 1db9bc6f321, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f04]=00000000, mtime: 1db9bc6f34d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f06]=00000000, mtime: 1db9bc6f37a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f08]=00000000, mtime: 1db9bc6f3a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f0a]=00000000, mtime: 1db9bc6f3d4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f0c]=00000000, mtime: 1db9bc6f400, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f0e]=00000000, mtime: 1db9bc6f42d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f10]=00000000, mtime: 1db9bc6f459, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f12]=00000000, mtime: 1db9bc6f486, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f14]=00000000, mtime: 1db9bc6f4b2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f16]=00000000, mtime: 1db9bc6f4df, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f18]=00000000, mtime: 1db9bc6f50b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f1a]=00000000, mtime: 1db9bc6f538, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f1c]=00000000, mtime: 1db9bc6f564, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f1e]=00000000, mtime: 1db9bc6f591, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f20]=00000000, mtime: 1db9bc6f5be, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f22]=00000000, mtime: 1db9bc6f5eb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f24]=00000000, mtime: 1db9bc6f618, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f26]=00000000, mtime: 1db9bc6f645, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f28]=00000000, mtime: 1db9bc6f671, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f2a]=00000000, mtime: 1db9bc6f69e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f2c]=00000000, mtime: 1db9bc6f6ca, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f2e]=00000000, mtime: 1db9bc6f6f8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f30]=00000000, mtime: 1db9bc6f725, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f32]=00000000, mtime: 1db9bc6f756, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f34]=00000000, mtime: 1db9bc6f783, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f36]=00000000, mtime: 1db9bc6f7b0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f38]=00000000, mtime: 1db9bc6f7dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3a]=00000000, mtime: 1db9bc6f80a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3c]=00000000, mtime: 1db9bc6f836, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f3e]=00000000, mtime: 1db9bc6f863, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f40]=00000000, mtime: 1db9bc6f890, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f42]=00000000, mtime: 1db9bc6f8bc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f44]=00000000, mtime: 1db9bc6f8e9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f46]=00000000, mtime: 1db9bc6f915, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f48]=00000000, mtime: 1db9bc6f942, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4a]=00000000, mtime: 1db9bc6f96e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4c]=00000000, mtime: 1db9bc6f99b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f4e]=00000000, mtime: 1db9bc6f9d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f50]=00000000, mtime: 1db9bc6fa07, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f52]=00000000, mtime: 1db9bc6fa34, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f54]=00000000, mtime: 1db9bc6fa60, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f56]=00000000, mtime: 1db9bc6fa8c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f58]=00000000, mtime: 1db9bc6fab9, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5a]=00000000, mtime: 1db9bc6fae6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5c]=00000000, mtime: 1db9bc6fb13, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f5e]=00000000, mtime: 1db9bc6fb40, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f60]=00000000, mtime: 1db9bc6fb6c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f62]=00000000, mtime: 1db9bc6fb99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f64]=00000000, mtime: 1db9bc6fbc5, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f66]=00000000, mtime: 1db9bc6fbf2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f68]=00000000, mtime: 1db9bc6fc1e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6a]=00000000, mtime: 1db9bc6fc4b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6c]=00000000, mtime: 1db9bc6fc78, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f6e]=00000000, mtime: 1db9bc6fca4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f70]=00000000, mtime: 1db9bc6fcd1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f72]=00000000, mtime: 1db9bc6fcfd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f74]=00000000, mtime: 1db9bc6fd2a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f76]=00000000, mtime: 1db9bc6fd56, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f78]=00000000, mtime: 1db9bc6fd83, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7a]=00000000, mtime: 1db9bc6fdaf, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7c]=00000000, mtime: 1db9bc6fddc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f7e]=00000000, mtime: 1db9bc6fe08, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f80]=00000000, mtime: 1db9bc6fe35, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f82]=00000000, mtime: 1db9bc6fe61, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f84]=00000000, mtime: 1db9bc6fe8f, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f86]=00000000, mtime: 1db9bc6febb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f88]=00000000, mtime: 1db9bc6fee8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8a]=00000000, mtime: 1db9bc6ff14, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8c]=00000000, mtime: 1db9bc6ff41, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f8e]=00000000, mtime: 1db9bc6ff6d, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f90]=00000000, mtime: 1db9bc6ff99, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f92]=00000000, mtime: 1db9bc6ffc6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f94]=00000000, mtime: 1db9bc6fff2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f96]=00000000, mtime: 1db9bc7001e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f98]=00000000, mtime: 1db9bc7004c, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9a]=00000000, mtime: 1db9bc70078, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9c]=00000000, mtime: 1db9bc700a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001f9e]=00000000, mtime: 1db9bc700d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa0]=00000000, mtime: 1db9bc700ff, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa2]=00000000, mtime: 1db9bc7012b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa4]=00000000, mtime: 1db9bc70158, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa6]=00000000, mtime: 1db9bc70184, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fa8]=00000000, mtime: 1db9bc701b1, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001faa]=00000000, mtime: 1db9bc701dd, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fac]=00000000, mtime: 1db9bc7021a, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fae]=00000000, mtime: 1db9bc70246, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb0]=00000000, mtime: 1db9bc70273, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb2]=00000000, mtime: 1db9bc702a0, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb4]=00000000, mtime: 1db9bc702cc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb6]=00000000, mtime: 1db9bc702f8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fb8]=00000000, mtime: 1db9bc70325, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fba]=00000000, mtime: 1db9bc70352, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbc]=00000000, mtime: 1db9bc7037e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fbe]=00000000, mtime: 1db9bc703ab, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc0]=00000000, mtime: 1db9bc703d8, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc2]=00000000, mtime: 1db9bc70408, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc4]=00000000, mtime: 1db9bc7043b, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc6]=00000000, mtime: 1db9bc70477, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fc8]=00000000, mtime: 1db9bc704bb, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fca]=00000000, mtime: 1db9bc704fc, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fcc]=00000000, mtime: 1db9bc7053e, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fce]=00000000, mtime: 1db9bc70573, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd0]=00000000, mtime: 1db9bc705a2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd2]=00000000, mtime: 1db9bc705d2, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 +address 00000000 +insn_type : CINSN +[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 +address ffff0000 +insn_type : CINSN +[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 +address ffffffff +insn_type : INSN +[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 +raise_exception: illegal instruction 0x2 0xffffffff +done interp faf int=0 mstatus=80 prv=3 + +Registers: +x0 zero: 00000000 +x1 ra: 00000000 +x2 sp: 80002000 +x3 gp: 00000001 +x4 tp: 00000000 +x5 t0: 800000f0 +x6 t1: 00000000 +x7 t2: 00000000 +x8 s0: 00000000 +x9 s1: 00000000 +x10 a0: 00000000 +x11 a1: 00000000 +x12 a2: 00000000 +x13 a3: 00000000 +x14 a4: 00000000 +x15 a5: 00000000 +x16 a6: 00000000 +x17 a7: 00000000 +x18 s2: 00000000 +x19 s3: 00000000 +x20 s4: 00000000 +x21 s5: 00000000 +x22 s6: 00000000 +x23 s7: 00000000 +x24 s8: 00000000 +x25 s9: 00000000 +x26 s10: 00000000 +x27 s11: 00000000 +x28 t3: 00000000 +x29 t4: 00000000 +x30 t5: 00000000 +x31 t6: 00000000 + +Instructions Stat: +LUI = 1 +AUIPC = 7 +BEQ = 1 +BLT = 1 +ADDI = 9 +FENCE = 2 +ECALL = 2 +CSRRW = 7 +CSRRS = 3 +CSRRWI = 5 +LI* = 1 +MRET = 1 + +Five Most Frequent: +1) ADDI = 9 (0.22%) +2) AUIPC = 7 (0.17%) +3) CSRRW = 7 (0.17%) +4) CSRRWI = 5 (0.12%) +5) CSRRS = 3 (0.07%) + +Memory Reading Area 80000000...80002003 +Memory Writing Area NONE + +>>> Execution time: 26116764 ns +>>> Instruction count: 4015 (IPS=153732) +>>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards +>>> Branching T=1 (50.00%) F=1 (50.00%) + diff --git a/emu-rv32i.c b/emu-rv32i.c index b5833b8..9573334 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -749,9 +749,12 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; +#ifdef DEBUG_OUTPUT + printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); +#endif #ifdef RV32C if((p[0] & 0x03) < 3){ - *insn = (p[0] | (p[1] << 8)) & 0x0000ffff; + *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } #endif @@ -1945,15 +1948,35 @@ void execute_instruction() switch(funct3){ case 0: /* C.NOP, C.ADDI */ if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ +#ifdef DEBUG_EXTRA + dprintf(">>> C.NOP\n"); +#endif return; } else { - rs1 = rd = (midpart >> 5) & 0x1f; +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; } break; case 1: /* C.JAL, C.ADDIW */ +#ifdef DEBUG_EXTRA switch(XLEN){ + case 32: + dprintf(">>> C.JAL\n"); + break; + case 64: + case 128: + dprintf(">>> C.ADDIW\n"); + break; + default: + dprintf(">>> Unknow XLEN\n"); + break; + } +#endif + switch(XLEN) { case 32: imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | @@ -1973,24 +1996,235 @@ void execute_instruction() break; case 64: case 128: - rs1 = rd = (midpart >> 5) & 0x1f; + rs1 = rd = ((midpart >> 5) & 0x1f); imm = (midpart >> (11 - 5)) | - midpart & 0x1f; + (midpart & 0x1f); val = reg[rs1] + imm; break; } break; case 2: /* C.LI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.LI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); + val = imm; + printf("%08x, rd: %d\n", val, rd); break; case 3: /* C.ADDI16SP, C.LUI */ +#ifdef DEBUG_EXTRA + switch(rd){ + case 2: + dprintf(">>> C.ADDI16SP\n"); + break; + default: + dprintf(">>> C.LUI\n"); + } +#endif + rs1 = rd = ((midpart >> 5) & 0x1f); + switch(rd){ + case 2: + imm = ((midpart >> 4) & 0x1) | + ((midpart << 1) & 0x2) | + ((midpart) & 0x8) | + ((midpart << 2) & 0xc) | + ((midpart >> 5) & 0x10); + imm = imm << 4; + val = reg[rd] + imm; + break; + default: + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = ((imm << 12) & 0xfffff000); + imm = imm << 14 >> 14; + if(rd != 0) + val = reg[rd] | imm; + break; + } break; case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ + switch(((midpart >> 8) & 0x3)){ + case 0: /* C.SRLI C.SRLI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRLI\n"); + break; + case 128: + dprintf(">>> C.SRLI64\n"); + break; + } +#endif + switch(XLEN){ + case 32: + case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | (midpart >> 5 & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val >> imm; + break; + case 1: /* C.SRAI C.SRAI64 */ +#ifdef DEBUG_EXTRA + switch(XLEN){ + case 32: + case 64: + dprintf(">>> C.SRAI\n"); + case 128: + dprintf(">>> C.SRAI64\n"); + } +#endif + switch(XLEN){ + case 32: case 64: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + break; + case 128: + rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + imm = 64; + val = reg[rs1]; + break; + } + val = val << imm; + break; + case 2: /* C.ANDI */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ANDI\n"); +#endif + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); + val = reg[rs1]; + val = val & imm; + break; + case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ + rs2 = (midpart & 0x7) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ + case 0: /* C.SUB */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUB\n"); +#endif + val = reg[rd] - reg[rs2]; + break; + case 1: /* C.XOR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.XOR\n"); +#endif + val = reg[rd] ^ reg[rs2]; + break; + case 2: /* C.OR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.OR\n"); +#endif + val = reg[rd] | reg[rs2]; + break; + case 3: /* C.AND */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.AND\n"); +#endif + val = reg[rd] & reg[rs2]; + break; + case 4: /* C.SUBW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SUBW\n"); +#endif + val = reg[rd] - reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 5: /* C.ADDW */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDW\n"); +#endif + val = reg[rd] + reg[rs2]; + if(XLEN == 128){ + val = (int32_t) (val << 96) >> 96; + }else if(XLEN == 64){ + val = (int32_t) (val << 32) >> 32; + }else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + } + break; + case 6: + case 7: + /* NOP */ + break; + } + } break; case 5: /* C.J */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.J\n"); +#endif + rd = 0; + imm = ((midpart >> 1) & 0x7) | + ((midpart >> 6) & 0x8) | + ((midpart << 5) & 0x10) | + ((midpart) & 0x20) | + ((midpart << 2) & 0x40) | + ((midpart) & 0x180)| + ((midpart << 3) & 0x200)| + ((midpart) & 0x400); + imm = (imm << 1) << 20 >> 20; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; break; case 6: /* C.BEQZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BEQZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + if(reg[rs1] == 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 3) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } break; case 7: /* C.BNEZ */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.BNEZ\n"); +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = 0; + imm = 0; + if(reg[rs1] != 0){ + imm = ((midpart >> 1) & 0x3) | + ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | + ((midpart << 2) & 0x60) | + ((midpart) & 0x80); + imm = (imm << 1) << 23 >> 23; + next_pc = (int32_t)(pc + imm); + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + } +#ifdef DEBUG_EXTRA + printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); +#endif break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -2027,17 +2261,8 @@ void execute_instruction() rd = 0; break; } - } - break; - case 2: /* C.LW */ { -#ifdef DEBUG_EXTRA - dprintf(">>>C.LW\n"); - stats[64+4]++; #endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = (midpart & 0x7) + 8; - imm = (midpart >> 4) & 0x1 | (midpart >> 7) & 0xe | (midpart << 1) & 0x10; imm = (imm << 2) & 0x7f; From 5483b528c2e965232b525f11d6cb028505d5366d Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 06:56:30 +0800 Subject: [PATCH 15/24] Finish the rv32imc opcode 1 insn --- debug.txt | 12242 ++------------------------------------------------ emu-rv32i.c | 125 +- sig.txt | 8 + 3 files changed, 357 insertions(+), 12018 deletions(-) create mode 100644 sig.txt diff --git a/debug.txt b/debug.txt index ac5df94..5036f60 100644 --- a/debug.txt +++ b/debug.txt @@ -1,5 +1,5 @@ -./emu-rv32i work/rv32imc/C-NOP.elf -sym '/tmp/ccoevK6z.o' 0 +./emu-rv32i work/rv32imc/C-BNEZ.elf +signature=sig.txt +sym '/tmp/cck1QDxQ.o' 0 sym 'reset_vector' 80000040 sym 'trap_vector' 80000004 sym 'write_tohost' 80000036 @@ -7,7 +7,11 @@ sym 'handle_exception' 80000032 sym 'other_exception' 80000032 sym 'begin_testcode' 800000f0 sym 'test_1_res' 80002000 -sym 'end_testcode' 80000122 +sym 'test_2_res' 80002004 +sym 'test_3_res' 80002008 +sym 'test_4_res' 8000200c +sym 'test_5_res' 80002010 +sym 'end_testcode' 80000150 sym 'end_signature' 80002020 sym 'begin_regstate' 80002100 sym 'begin_signature' 80002000 @@ -21,12186 +25,457 @@ end_signature: 0x80002020 start: 0x80000000 codesize: 0x00002204 (8708) codesize with offset: 8708 +Here core dump address 0001a081 insn_type : CINSN -[80000000]=0000a081, mtime: 1db9bc30e4d, mtimecmp: 0 +[80000000]=0000a081, mtime: 1fdbfdbd62f, mtimecmp: 0 >>> C.J +Here core dump address f1402573 insn_type : INSN -[80000040]=f1402573, mtime: 1db9bc30f47, mtimecmp: 0 +[80000040]=f1402573, mtime: 1fdbfdbd747, mtimecmp: 0 csr_read: csr=0xf14 0 csr_read: csr=0xf14 --> 0x00000000 >>> CSRRS +Here core dump address 0297e101 insn_type : CINSN -[80000044]=0000e101, mtime: 1db9bc3103b, mtimecmp: 0 +[80000044]=0000e101, mtime: 1fdbfdbd819, mtimecmp: 0 >>> C.BNEZ -rd : 0, rs1: 10, imm: 0, reg[rs1] : 0, pc: 407b4e99, next_pc: 407b4e9a +rd : 0, rs1: 10, imm: 295583824, reg[rs1] : 0, pc: 0000000e, next_pc: a2dac760 +Here core dump address 00000297 insn_type : INSN -[80000046]=00000297, mtime: 1db9bc3110a, mtimecmp: 0 +[80000046]=00000297, mtime: 1fdbfdbd8ff, mtimecmp: 0 >>> AUIPC +Here core dump address 01228293 insn_type : INSN -[8000004a]=01228293, mtime: 1db9bc311ae, mtimecmp: 0 +[8000004a]=01228293, mtime: 1fdbfdbd99e, mtimecmp: 0 >>> ADDI +Here core dump address 30529073 insn_type : INSN -[8000004e]=30529073, mtime: 1db9bc3124f, mtimecmp: 0 +[8000004e]=30529073, mtime: 1fdbfdbda34, mtimecmp: 0 >>> CSRRW csr_read: csr=0x305 -1 csr_read: csr=0x305 --> 0x00000000 csr_write: csr=0x305 val=0x80000058 +Here core dump address 18005073 insn_type : INSN -[80000052]=18005073, mtime: 1db9bc31368, mtimecmp: 0 +[80000052]=18005073, mtime: 1fdbfdbdb5d, mtimecmp: 0 >>> CSRRWI csr_read: csr=0x180 -1 csr_read: csr=0x180 --> 0x00000000 csr_write: csr=0x180 val=0x00000000 +Here core dump address 02970001 insn_type : CINSN -[80000056]=00000001, mtime: 1db9bc3146e, mtimecmp: 0 +[80000056]=00000001, mtime: 1fdbfdbdc55, mtimecmp: 0 >>> C.NOP +Here core dump address 00000297 insn_type : INSN -[80000058]=00000297, mtime: 1db9bc3150f, mtimecmp: 0 +[80000058]=00000297, mtime: 1fdbfdbdceb, mtimecmp: 0 >>> AUIPC +Here core dump address 01828293 insn_type : INSN -[8000005c]=01828293, mtime: 1db9bc315ae, mtimecmp: 0 +[8000005c]=01828293, mtime: 1fdbfdbdd86, mtimecmp: 0 >>> ADDI +Here core dump address 30529073 insn_type : INSN -[80000060]=30529073, mtime: 1db9bc3164a, mtimecmp: 0 +[80000060]=30529073, mtime: 1fdbfdbde19, mtimecmp: 0 >>> CSRRW csr_read: csr=0x305 -1 csr_read: csr=0x305 --> 0x80000058 csr_write: csr=0x305 val=0x80000070 +Here core dump address 907352fd insn_type : CINSN -[80000064]=000052fd, mtime: 1db9bc31751, mtimecmp: 0 +[80000064]=000052fd, mtime: 1fdbfdbdef9, mtimecmp: 0 >>> C.LI -0000003f, rd: 5 +ffffffff, rd: 5, imm : ffffffff +Here core dump address 3b029073 insn_type : INSN -[80000066]=3b029073, mtime: 1db9bc31814, mtimecmp: 0 +[80000066]=3b029073, mtime: 1fdbfdbdfa8, mtimecmp: 0 >>> CSRRW csr_read: csr=0x3b0 -1 csr_read: invalid CSR=0x3b0 -csr_write: csr=0x3b0 val=0x0000003f +csr_write: csr=0x3b0 val=0xffffffff +Here core dump address 907342fd insn_type : CINSN -[8000006a]=000042fd, mtime: 1db9bc31997, mtimecmp: 0 +[8000006a]=000042fd, mtime: 1fdbfdbe082, mtimecmp: 0 >>> C.LI -0000001f, rd: 5 +0000001f, rd: 5, imm : 0000001f +Here core dump address 3a029073 insn_type : INSN -[8000006c]=3a029073, mtime: 1db9bc31aaf, mtimecmp: 0 +[8000006c]=3a029073, mtime: 1fdbfdbe136, mtimecmp: 0 >>> CSRRW csr_read: csr=0x3a0 -1 csr_read: invalid CSR=0x3a0 csr_write: csr=0x3a0 val=0x0000001f +Here core dump address 00000297 insn_type : INSN -[80000070]=00000297, mtime: 1db9bc31bb5, mtimecmp: 0 +[80000070]=00000297, mtime: 1fdbfdbe213, mtimecmp: 0 >>> AUIPC +Here core dump address 01828293 insn_type : INSN -[80000074]=01828293, mtime: 1db9bc31dd9, mtimecmp: 0 +[80000074]=01828293, mtime: 1fdbfdbe2a7, mtimecmp: 0 >>> ADDI +Here core dump address 30529073 insn_type : INSN -[80000078]=30529073, mtime: 1db9bc31e7c, mtimecmp: 0 +[80000078]=30529073, mtime: 1fdbfdbe33b, mtimecmp: 0 >>> CSRRW csr_read: csr=0x305 -1 csr_read: csr=0x305 --> 0x80000070 csr_write: csr=0x305 val=0x80000088 +Here core dump address 30205073 insn_type : INSN -[8000007c]=30205073, mtime: 1db9bc31f7c, mtimecmp: 0 +[8000007c]=30205073, mtime: 1fdbfdbe417, mtimecmp: 0 >>> CSRRWI csr_read: csr=0x302 -1 csr_read: csr=0x302 --> 0x00000000 csr_write: csr=0x302 val=0x00000000 +Here core dump address 30305073 insn_type : INSN -[80000080]=30305073, mtime: 1db9bc3207e, mtimecmp: 0 +[80000080]=30305073, mtime: 1fdbfdbe5ec, mtimecmp: 0 >>> CSRRWI csr_read: csr=0x303 -1 csr_read: csr=0x303 --> 0x00000000 csr_write: csr=0x303 val=0x00000000 +Here core dump address 30405073 insn_type : INSN -[80000084]=30405073, mtime: 1db9bc321a1, mtimecmp: 0 +[80000084]=30405073, mtime: 1fdbfdbe6c4, mtimecmp: 0 >>> CSRRWI csr_read: csr=0x304 -1 csr_read: csr=0x304 --> 0x00000000 csr_write: csr=0x304 val=0x00000000 +Here core dump address 02974181 insn_type : CINSN -[80000088]=00004181, mtime: 1db9bc3229f, mtimecmp: 0 +[80000088]=00004181, mtime: 1fdbfdbe7c8, mtimecmp: 0 >>> C.LI -00000000, rd: 3 +00000000, rd: 3, imm : 00000000 +Here core dump address 00000297 insn_type : INSN -[8000008a]=00000297, mtime: 1db9bc3235e, mtimecmp: 0 +[8000008a]=00000297, mtime: 1fdbfdbe87f, mtimecmp: 0 >>> AUIPC +Here core dump address f7a28293 insn_type : INSN -[8000008e]=f7a28293, mtime: 1db9bc323fc, mtimecmp: 0 +[8000008e]=f7a28293, mtime: 1fdbfdbe913, mtimecmp: 0 >>> ADDI +Here core dump address 30529073 insn_type : INSN -[80000092]=30529073, mtime: 1db9bc3249f, mtimecmp: 0 +[80000092]=30529073, mtime: 1fdbfdbe9ac, mtimecmp: 0 >>> CSRRW csr_read: csr=0x305 -1 csr_read: csr=0x305 --> 0x80000088 csr_write: csr=0x305 val=0x80000004 +Here core dump address 057e4505 insn_type : CINSN -[80000096]=00004505, mtime: 1db9bc325e5, mtimecmp: 0 +[80000096]=00004505, mtime: 1fdbfdbea83, mtimecmp: 0 >>> C.LI -00000001, rd: 10 +00000001, rd: 10, imm : 00000001 +Here core dump address 4763057e insn_type : CINSN -[80000098]=0000057e, mtime: 1db9bc326a8, mtimecmp: 0 +[80000098]=0000057e, mtime: 1fdbfdbeb35, mtimecmp: 0 +Here core dump address 00054763 insn_type : INSN -[8000009a]=00054763, mtime: 1db9bc3270d, mtimecmp: 0 +[8000009a]=00054763, mtime: 1fdbfdbeba2, mtimecmp: 0 >>> BLT +Here core dump address 0ff0000f insn_type : INSN -[8000009e]=0ff0000f, mtime: 1db9bc327ae, mtimecmp: 0 +[8000009e]=0ff0000f, mtime: 1fdbfdbec38, mtimecmp: 0 >>> FENCE +Here core dump address 00734185 insn_type : CINSN -[800000a2]=00004185, mtime: 1db9bc32853, mtimecmp: 0 +[800000a2]=00004185, mtime: 1fdbfdbeccd, mtimecmp: 0 >>> C.LI -00000001, rd: 3 +00000001, rd: 3, imm : 00000001 +Here core dump address 00000073 insn_type : INSN -[800000a4]=00000073, mtime: 1db9bc32914, mtimecmp: 0 +[800000a4]=00000073, mtime: 1fdbfdbed82, mtimecmp: 0 >>> ECALL syscall: 0001 Unimplement Machine ecall! +Here core dump address 80000297 insn_type : INSN -[800000a8]=80000297, mtime: 1db9bc32a14, mtimecmp: 0 +[800000a8]=80000297, mtime: 1fdbfdbee57, mtimecmp: 0 >>> AUIPC +Here core dump address f5828293 insn_type : INSN -[800000ac]=f5828293, mtime: 1db9bc32ab2, mtimecmp: 0 +[800000ac]=f5828293, mtime: 1fdbfdbeef8, mtimecmp: 0 >>> ADDI +Here core dump address 00028e63 insn_type : INSN -[800000b0]=00028e63, mtime: 1db9bc32b50, mtimecmp: 0 +[800000b0]=00028e63, mtime: 1fdbfdbef8d, mtimecmp: 0 >>> BEQ +Here core dump address 30005073 insn_type : INSN -[800000cc]=30005073, mtime: 1db9bc32bf7, mtimecmp: 0 +[800000cc]=30005073, mtime: 1fdbfdbf024, mtimecmp: 0 >>> CSRRWI csr_read: csr=0x300 -1 csr_read: csr=0x300 --> 0x00000000 csr_write: csr=0x300 val=0x00000000 +Here core dump address 00002537 insn_type : INSN -[800000d0]=00002537, mtime: 1db9bc32cfb, mtimecmp: 0 +[800000d0]=00002537, mtime: 1fdbfdbf103, mtimecmp: 0 >>> LUI +Here core dump address 80050513 insn_type : INSN -[800000d4]=80050513, mtime: 1db9bc32d9c, mtimecmp: 0 +[800000d4]=80050513, mtime: 1fdbfdbf199, mtimecmp: 0 >>> ADDI +Here core dump address 30052073 insn_type : INSN -[800000d8]=30052073, mtime: 1db9bc32e3a, mtimecmp: 0 +[800000d8]=30052073, mtime: 1fdbfdbf231, mtimecmp: 0 csr_read: csr=0x300 1 csr_read: csr=0x300 --> 0x00000000 >>> CSRRS csr_write: csr=0x300 val=0x00001800 +Here core dump address 00000297 insn_type : INSN -[800000dc]=00000297, mtime: 1db9bc32f45, mtimecmp: 0 +[800000dc]=00000297, mtime: 1fdbfdbf30c, mtimecmp: 0 >>> AUIPC +Here core dump address 01428293 insn_type : INSN -[800000e0]=01428293, mtime: 1db9bc32fe3, mtimecmp: 0 +[800000e0]=01428293, mtime: 1fdbfdbf3aa, mtimecmp: 0 >>> ADDI +Here core dump address 34129073 insn_type : INSN -[800000e4]=34129073, mtime: 1db9bc33081, mtimecmp: 0 +[800000e4]=34129073, mtime: 1fdbfdbf43e, mtimecmp: 0 >>> CSRRW csr_read: csr=0x341 -1 csr_read: csr=0x341 --> 0x00000000 csr_write: csr=0x341 val=0x800000f0 +Here core dump address f1402573 insn_type : INSN -[800000e8]=f1402573, mtime: 1db9bc33186, mtimecmp: 0 +[800000e8]=f1402573, mtime: 1fdbfdbf516, mtimecmp: 0 csr_read: csr=0xf14 0 csr_read: csr=0xf14 --> 0x00000000 >>> CSRRS +Here core dump address 30200073 insn_type : INSN -[800000ec]=30200073, mtime: 1db9bc33266, mtimecmp: 0 +[800000ec]=30200073, mtime: 1fdbfdbf5e2, mtimecmp: 0 >>> MRET +Here core dump address 00002117 insn_type : INSN -[800000f0]=00002117, mtime: 1db9bc33304, mtimecmp: 0 +[800000f0]=00002117, mtime: 1fdbfdbf678, mtimecmp: 0 >>> AUIPC +Here core dump address f1010113 insn_type : INSN -[800000f4]=f1010113, mtime: 1db9bc333a2, mtimecmp: 0 +[800000f4]=f1010113, mtime: 1fdbfdbf70b, mtimecmp: 0 >>> ADDI -address 00000013 -insn_type : INSN -[800000f8]=00000013, mtime: 1db9bc3343f, mtimecmp: 0 ->>> ADDI -address c0020001 -insn_type : CINSN -[800000fc]=00000001, mtime: 1db9bc334dd, mtimecmp: 0 ->>> C.NOP -address 4201c002 +Here core dump +address e2914681 insn_type : CINSN -[800000fe]=0000c002, mtime: 1db9bc33584, mtimecmp: 0 -address 02014201 -insn_type : CINSN -[80000100]=00004201, mtime: 1db9bc335e6, mtimecmp: 0 +[800000f8]=00004681, mtime: 1fdbfdbf7a1, mtimecmp: 0 >>> C.LI -00000000, rd: 4 -address c2120201 -insn_type : CINSN -[80000102]=00000201, mtime: 1db9bc336a7, mtimecmp: 0 ->>> C.ADDI -address 4401c212 +00000000, rd: 13, imm : 00000000 +Here core dump +address 4681e291 insn_type : CINSN -[80000104]=0000c212, mtime: 1db9bc33746, mtimecmp: 0 -address 04014401 +[800000fa]=0000e291, mtime: 1fdbfdbf85c, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 13, imm: 295583824, reg[rs1] : 0, pc: 0000000e, next_pc: a2dac760 +Here core dump +address c0364681 insn_type : CINSN -[80000106]=00004401, mtime: 1db9bc337b1, mtimecmp: 0 +[800000fc]=00004681, mtime: 1fdbfdbf919, mtimecmp: 0 >>> C.LI -00000000, rd: 8 -address c4220401 +00000000, rd: 13, imm : 00000000 +Here core dump +address 2117c036 +insn_type : CINSN +[800000fe]=0000c036, mtime: 1fdbfdbf9c4, mtimecmp: 0 +>>> C.SWSP +rs2: 13, imm: 0, reg[rs2]: 0, val: 0 +Here core dump +address 00002117 +insn_type : INSN +[80000100]=00002117, mtime: 1fdbfdbfa74, mtimecmp: 0 +>>> AUIPC +Here core dump +address f0410113 +insn_type : INSN +[80000104]=f0410113, mtime: 1fdbfdbfb09, mtimecmp: 0 +>>> ADDI +Here core dump +address e3114705 insn_type : CINSN -[80000108]=00000401, mtime: 1db9bc3386f, mtimecmp: 0 ->>> C.ADDI -address 4481c422 +[80000108]=00004705, mtime: 1fdbfdbfbd3, mtimecmp: 0 +>>> C.LI +00000001, rd: 14, imm : 00000001 +Here core dump +address 4701e311 insn_type : CINSN -[8000010a]=0000c422, mtime: 1db9bc3390e, mtimecmp: 0 -address 04814481 +[8000010a]=0000e311, mtime: 1fdbfdbfc8a, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 14, imm: 4, reg[rs1] : 1, pc: 0000000e, next_pc: a2dac760 +Here core dump +address 2117c03a +insn_type : CINSN +[8000010e]=0000c03a, mtime: 1fdbfdbfd3b, mtimecmp: 0 +>>> C.SWSP +rs2: 14, imm: 0, reg[rs2]: 1, val: 1 +Here core dump +address 00002117 +insn_type : INSN +[80000110]=00002117, mtime: 1fdbfdbfde7, mtimecmp: 0 +>>> AUIPC +Here core dump +address ef810113 +insn_type : INSN +[80000114]=ef810113, mtime: 1fdbfdbfe7b, mtimecmp: 0 +>>> ADDI +Here core dump +address e39157fd insn_type : CINSN -[8000010c]=00004481, mtime: 1db9bc33970, mtimecmp: 0 +[80000118]=000057fd, mtime: 1fdbfdbff14, mtimecmp: 0 >>> C.LI -00000000, rd: 9 -address c6260481 -insn_type : CINSN -[8000010e]=00000481, mtime: 1db9bc33a2e, mtimecmp: 0 ->>> C.ADDI -address 4581c626 +ffffffff, rd: 15, imm : ffffffff +Here core dump +address 4781e391 insn_type : CINSN -[80000110]=0000c626, mtime: 1db9bc33acc, mtimecmp: 0 -address 05814581 +[8000011a]=0000e391, mtime: 1fdbfdbffc0, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 15, imm: 4, reg[rs1] : -1, pc: 0000000e, next_pc: a2dac760 +Here core dump +address 2117c03e +insn_type : CINSN +[8000011e]=0000c03e, mtime: 1fdbfdc006e, mtimecmp: 0 +>>> C.SWSP +rs2: 15, imm: 0, reg[rs2]: -1, val: -1 +Here core dump +address 00002117 +insn_type : INSN +[80000120]=00002117, mtime: 1fdbfdc011f, mtimecmp: 0 +>>> AUIPC +Here core dump +address eec10113 +insn_type : INSN +[80000124]=eec10113, mtime: 1fdbfdc01b5, mtimecmp: 0 +>>> ADDI +Here core dump +address 00008437 +insn_type : INSN +[80000128]=00008437, mtime: 1fdbfdc0251, mtimecmp: 0 +>>> LUI +Here core dump +address fff40413 +insn_type : INSN +[8000012c]=fff40413, mtime: 1fdbfdc02e9, mtimecmp: 0 +>>> ADDI +Here core dump +address 4401e011 insn_type : CINSN -[80000112]=00004581, mtime: 1db9bc33b2e, mtimecmp: 0 ->>> C.LI -00000000, rd: 11 -address c82e0581 +[80000130]=0000e011, mtime: 1fdbfdc037d, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 8, imm: 4, reg[rs1] : 32767, pc: 0000000e, next_pc: a2dac760 +Here core dump +address 2117c022 +insn_type : CINSN +[80000134]=0000c022, mtime: 1fdbfdc042b, mtimecmp: 0 +>>> C.SWSP +rs2: 8, imm: 0, reg[rs2]: 32767, val: 32767 +Here core dump +address 00002117 +insn_type : INSN +[80000136]=00002117, mtime: 1fdbfdc04e1, mtimecmp: 0 +>>> AUIPC +Here core dump +address eda10113 +insn_type : INSN +[8000013a]=eda10113, mtime: 1fdbfdc0577, mtimecmp: 0 +>>> ADDI +Here core dump +address e09164a1 insn_type : CINSN -[80000114]=00000581, mtime: 1db9bc33bf4, mtimecmp: 0 ->>> C.ADDI -address 000fc82e +[8000013e]=000064a1, mtime: 1fdbfdc060b, mtimecmp: 0 +>>> C.LUI +Here core dump +address 4481e091 insn_type : CINSN -[80000116]=0000c82e, mtime: 1db9bc33c92, mtimecmp: 0 +[80000140]=0000e091, mtime: 1fdbfdc06a2, mtimecmp: 0 +>>> C.BNEZ +rd : 0, rs1: 9, imm: 4, reg[rs1] : 32768, pc: 0000000e, next_pc: a2dac760 +Here core dump +address 000fc026 +insn_type : CINSN +[80000144]=0000c026, mtime: 1fdbfdc0756, mtimecmp: 0 +>>> C.SWSP +rs2: 9, imm: 0, reg[rs2]: 32768, val: 32768 +Here core dump address 0ff0000f insn_type : INSN -[80000118]=0ff0000f, mtime: 1db9bc33cf5, mtimecmp: 0 +[80000146]=0ff0000f, mtime: 1fdbfdc080d, mtimecmp: 0 >>> FENCE +Here core dump address 00734185 insn_type : CINSN -[8000011c]=00004185, mtime: 1db9bc33d94, mtimecmp: 0 +[8000014a]=00004185, mtime: 1fdbfdc08a8, mtimecmp: 0 >>> C.LI -00000001, rd: 3 +00000001, rd: 3, imm : 00000001 +Here core dump address 00000073 insn_type : INSN -[8000011e]=00000073, mtime: 1db9bc33e54, mtimecmp: 0 +[8000014c]=00000073, mtime: 1fdbfdc0960, mtimecmp: 0 >>> ECALL -syscall: 0001 -Unimplement Machine ecall! -address 00000000 -insn_type : CINSN -[80000122]=00000000, mtime: 1db9bc33f7a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000124]=00000000, mtime: 1db9bc33fe0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000126]=00000000, mtime: 1db9bc34044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000128]=00000000, mtime: 1db9bc340a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012a]=00000000, mtime: 1db9bc3410b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012c]=00000000, mtime: 1db9bc3416e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000012e]=00000000, mtime: 1db9bc341d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000130]=00000000, mtime: 1db9bc34234, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000132]=00000000, mtime: 1db9bc34297, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000134]=00000000, mtime: 1db9bc342f9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000136]=00000000, mtime: 1db9bc34362, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000138]=00000000, mtime: 1db9bc343c4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013a]=00000000, mtime: 1db9bc34426, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013c]=00000000, mtime: 1db9bc34488, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000013e]=00000000, mtime: 1db9bc344e9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000140]=00000000, mtime: 1db9bc3454b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000142]=00000000, mtime: 1db9bc345b0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000144]=00000000, mtime: 1db9bc34614, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000146]=00000000, mtime: 1db9bc34676, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000148]=00000000, mtime: 1db9bc346d7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014a]=00000000, mtime: 1db9bc34739, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014c]=00000000, mtime: 1db9bc3479b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000014e]=00000000, mtime: 1db9bc347ff, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000150]=00000000, mtime: 1db9bc34861, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000152]=00000000, mtime: 1db9bc348c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000154]=00000000, mtime: 1db9bc34927, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000156]=00000000, mtime: 1db9bc34990, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000158]=00000000, mtime: 1db9bc349f2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015a]=00000000, mtime: 1db9bc34a54, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015c]=00000000, mtime: 1db9bc34ab5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000015e]=00000000, mtime: 1db9bc34b17, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000160]=00000000, mtime: 1db9bc34b79, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000162]=00000000, mtime: 1db9bc34bdd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000164]=00000000, mtime: 1db9bc34c69, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000166]=00000000, mtime: 1db9bc34cf8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000168]=00000000, mtime: 1db9bc34d7d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016a]=00000000, mtime: 1db9bc34dfb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016c]=00000000, mtime: 1db9bc34e5c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000016e]=00000000, mtime: 1db9bc34ebe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000170]=00000000, mtime: 1db9bc34f20, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000172]=00000000, mtime: 1db9bc34f81, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000174]=00000000, mtime: 1db9bc34fe3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000176]=00000000, mtime: 1db9bc35045, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000178]=00000000, mtime: 1db9bc350a7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017a]=00000000, mtime: 1db9bc35108, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017c]=00000000, mtime: 1db9bc3516a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000017e]=00000000, mtime: 1db9bc351fe, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000180]=00000000, mtime: 1db9bc35261, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000182]=00000000, mtime: 1db9bc352c3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000184]=00000000, mtime: 1db9bc35328, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000186]=00000000, mtime: 1db9bc3538a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000188]=00000000, mtime: 1db9bc353f0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018a]=00000000, mtime: 1db9bc35452, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018c]=00000000, mtime: 1db9bc354b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000018e]=00000000, mtime: 1db9bc355a2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000190]=00000000, mtime: 1db9bc355f5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000192]=00000000, mtime: 1db9bc35645, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000194]=00000000, mtime: 1db9bc35694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000196]=00000000, mtime: 1db9bc356e4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000198]=00000000, mtime: 1db9bc35732, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019a]=00000000, mtime: 1db9bc35781, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019c]=00000000, mtime: 1db9bc357d1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[8000019e]=00000000, mtime: 1db9bc35820, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a0]=00000000, mtime: 1db9bc35876, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a2]=00000000, mtime: 1db9bc358c5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a4]=00000000, mtime: 1db9bc35915, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a6]=00000000, mtime: 1db9bc35964, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001a8]=00000000, mtime: 1db9bc359b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001aa]=00000000, mtime: 1db9bc35a02, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ac]=00000000, mtime: 1db9bc35a51, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ae]=00000000, mtime: 1db9bc35aa3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b0]=00000000, mtime: 1db9bc35af2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b2]=00000000, mtime: 1db9bc35b41, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b4]=00000000, mtime: 1db9bc35b95, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b6]=00000000, mtime: 1db9bc35be6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001b8]=00000000, mtime: 1db9bc35c37, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ba]=00000000, mtime: 1db9bc35c86, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001bc]=00000000, mtime: 1db9bc35cd5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001be]=00000000, mtime: 1db9bc35d25, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c0]=00000000, mtime: 1db9bc35d74, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c2]=00000000, mtime: 1db9bc35dc3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c4]=00000000, mtime: 1db9bc35e13, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c6]=00000000, mtime: 1db9bc35e68, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001c8]=00000000, mtime: 1db9bc35eb8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ca]=00000000, mtime: 1db9bc35f07, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001cc]=00000000, mtime: 1db9bc35f57, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ce]=00000000, mtime: 1db9bc35fa6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d0]=00000000, mtime: 1db9bc35ff5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d2]=00000000, mtime: 1db9bc36044, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d4]=00000000, mtime: 1db9bc36093, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d6]=00000000, mtime: 1db9bc360e6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001d8]=00000000, mtime: 1db9bc36137, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001da]=00000000, mtime: 1db9bc361a0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001dc]=00000000, mtime: 1db9bc361f1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001de]=00000000, mtime: 1db9bc36240, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e0]=00000000, mtime: 1db9bc3628f, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e2]=00000000, mtime: 1db9bc362e2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e4]=00000000, mtime: 1db9bc36331, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e6]=00000000, mtime: 1db9bc36381, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001e8]=00000000, mtime: 1db9bc363d0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ea]=00000000, mtime: 1db9bc36425, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ec]=00000000, mtime: 1db9bc36479, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001ee]=00000000, mtime: 1db9bc364c8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001f0]=00000000, mtime: 1db9bc36517, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001f2]=00000000, mtime: 1db9bc36565, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001f4]=00000000, mtime: 1db9bc365b5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001f6]=00000000, mtime: 1db9bc36604, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001f8]=00000000, mtime: 1db9bc36654, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001fa]=00000000, mtime: 1db9bc366a8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001fc]=00000000, mtime: 1db9bc366fa, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[800001fe]=00000000, mtime: 1db9bc3674b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000200]=00000000, mtime: 1db9bc3679a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000202]=00000000, mtime: 1db9bc367ea, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000204]=00000000, mtime: 1db9bc3683a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80000206]=00000000, mtime: 1db9bc3688a, mtimecmp: 0 -address 00000000 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-insn_type : CINSN -[80001e7a]=00000000, mtime: 1db9bc6e6be, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e7c]=00000000, mtime: 1db9bc6e6ed, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e7e]=00000000, mtime: 1db9bc6e71d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e80]=00000000, mtime: 1db9bc6e753, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e82]=00000000, mtime: 1db9bc6e783, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e84]=00000000, mtime: 1db9bc6e7b3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e86]=00000000, mtime: 1db9bc6e7e2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e88]=00000000, mtime: 1db9bc6e811, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e8a]=00000000, mtime: 1db9bc6e840, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e8c]=00000000, mtime: 1db9bc6e870, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001e8e]=00000000, mtime: 1db9bc6e8a6, mtimecmp: 0 -address 00000000 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-insn_type : CINSN -[80001ea6]=00000000, mtime: 1db9bc6eaff, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ea8]=00000000, mtime: 1db9bc6eb2d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eaa]=00000000, mtime: 1db9bc6eb59, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eac]=00000000, mtime: 1db9bc6eb85, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eae]=00000000, mtime: 1db9bc6ebb2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eb0]=00000000, mtime: 1db9bc6ebde, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eb2]=00000000, mtime: 1db9bc6ec0b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eb4]=00000000, mtime: 1db9bc6ec37, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eb6]=00000000, mtime: 1db9bc6ec64, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eb8]=00000000, mtime: 1db9bc6ec91, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eba]=00000000, mtime: 1db9bc6ecbd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ebc]=00000000, mtime: 1db9bc6ecea, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ebe]=00000000, mtime: 1db9bc6ed16, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ec0]=00000000, mtime: 1db9bc6ed42, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ec2]=00000000, mtime: 1db9bc6ed71, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ec4]=00000000, mtime: 1db9bc6ed9d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ec6]=00000000, mtime: 1db9bc6edca, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ec8]=00000000, mtime: 1db9bc6edf7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eca]=00000000, mtime: 1db9bc6ee24, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ecc]=00000000, mtime: 1db9bc6ee50, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ece]=00000000, mtime: 1db9bc6ee7d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ed0]=00000000, mtime: 1db9bc6eeaa, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ed2]=00000000, mtime: 1db9bc6eed7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ed4]=00000000, mtime: 1db9bc6ef03, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ed6]=00000000, mtime: 1db9bc6ef30, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ed8]=00000000, mtime: 1db9bc6ef5c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eda]=00000000, mtime: 1db9bc6ef89, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001edc]=00000000, mtime: 1db9bc6efb5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ede]=00000000, mtime: 1db9bc6efe2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ee0]=00000000, mtime: 1db9bc6f00f, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ee2]=00000000, mtime: 1db9bc6f03b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ee4]=00000000, mtime: 1db9bc6f067, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ee6]=00000000, mtime: 1db9bc6f094, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ee8]=00000000, mtime: 1db9bc6f0c0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eea]=00000000, mtime: 1db9bc6f0ed, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eec]=00000000, mtime: 1db9bc6f119, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001eee]=00000000, mtime: 1db9bc6f146, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ef0]=00000000, mtime: 1db9bc6f173, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ef2]=00000000, mtime: 1db9bc6f1bb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ef4]=00000000, mtime: 1db9bc6f1e7, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ef6]=00000000, mtime: 1db9bc6f214, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ef8]=00000000, mtime: 1db9bc6f240, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001efa]=00000000, mtime: 1db9bc6f26d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001efc]=00000000, mtime: 1db9bc6f29b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001efe]=00000000, mtime: 1db9bc6f2c8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f00]=00000000, mtime: 1db9bc6f2f4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f02]=00000000, mtime: 1db9bc6f321, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f04]=00000000, mtime: 1db9bc6f34d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f06]=00000000, mtime: 1db9bc6f37a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f08]=00000000, mtime: 1db9bc6f3a6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f0a]=00000000, mtime: 1db9bc6f3d4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f0c]=00000000, mtime: 1db9bc6f400, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f0e]=00000000, mtime: 1db9bc6f42d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f10]=00000000, mtime: 1db9bc6f459, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f12]=00000000, mtime: 1db9bc6f486, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f14]=00000000, mtime: 1db9bc6f4b2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f16]=00000000, mtime: 1db9bc6f4df, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f18]=00000000, mtime: 1db9bc6f50b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f1a]=00000000, mtime: 1db9bc6f538, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f1c]=00000000, mtime: 1db9bc6f564, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f1e]=00000000, mtime: 1db9bc6f591, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f20]=00000000, mtime: 1db9bc6f5be, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f22]=00000000, mtime: 1db9bc6f5eb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f24]=00000000, mtime: 1db9bc6f618, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f26]=00000000, mtime: 1db9bc6f645, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f28]=00000000, mtime: 1db9bc6f671, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f2a]=00000000, mtime: 1db9bc6f69e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f2c]=00000000, mtime: 1db9bc6f6ca, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f2e]=00000000, mtime: 1db9bc6f6f8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f30]=00000000, mtime: 1db9bc6f725, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f32]=00000000, mtime: 1db9bc6f756, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f34]=00000000, mtime: 1db9bc6f783, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f36]=00000000, mtime: 1db9bc6f7b0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f38]=00000000, mtime: 1db9bc6f7dd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f3a]=00000000, mtime: 1db9bc6f80a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f3c]=00000000, mtime: 1db9bc6f836, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f3e]=00000000, mtime: 1db9bc6f863, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f40]=00000000, mtime: 1db9bc6f890, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f42]=00000000, mtime: 1db9bc6f8bc, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f44]=00000000, mtime: 1db9bc6f8e9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f46]=00000000, mtime: 1db9bc6f915, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f48]=00000000, mtime: 1db9bc6f942, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f4a]=00000000, mtime: 1db9bc6f96e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f4c]=00000000, mtime: 1db9bc6f99b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f4e]=00000000, mtime: 1db9bc6f9d8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f50]=00000000, mtime: 1db9bc6fa07, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f52]=00000000, mtime: 1db9bc6fa34, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f54]=00000000, mtime: 1db9bc6fa60, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f56]=00000000, mtime: 1db9bc6fa8c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f58]=00000000, mtime: 1db9bc6fab9, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f5a]=00000000, mtime: 1db9bc6fae6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f5c]=00000000, mtime: 1db9bc6fb13, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f5e]=00000000, mtime: 1db9bc6fb40, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f60]=00000000, mtime: 1db9bc6fb6c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f62]=00000000, mtime: 1db9bc6fb99, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f64]=00000000, mtime: 1db9bc6fbc5, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f66]=00000000, mtime: 1db9bc6fbf2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f68]=00000000, mtime: 1db9bc6fc1e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f6a]=00000000, mtime: 1db9bc6fc4b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f6c]=00000000, mtime: 1db9bc6fc78, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f6e]=00000000, mtime: 1db9bc6fca4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f70]=00000000, mtime: 1db9bc6fcd1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f72]=00000000, mtime: 1db9bc6fcfd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f74]=00000000, mtime: 1db9bc6fd2a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f76]=00000000, mtime: 1db9bc6fd56, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f78]=00000000, mtime: 1db9bc6fd83, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f7a]=00000000, mtime: 1db9bc6fdaf, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f7c]=00000000, mtime: 1db9bc6fddc, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f7e]=00000000, mtime: 1db9bc6fe08, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f80]=00000000, mtime: 1db9bc6fe35, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f82]=00000000, mtime: 1db9bc6fe61, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f84]=00000000, mtime: 1db9bc6fe8f, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f86]=00000000, mtime: 1db9bc6febb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f88]=00000000, mtime: 1db9bc6fee8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f8a]=00000000, mtime: 1db9bc6ff14, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f8c]=00000000, mtime: 1db9bc6ff41, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f8e]=00000000, mtime: 1db9bc6ff6d, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f90]=00000000, mtime: 1db9bc6ff99, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f92]=00000000, mtime: 1db9bc6ffc6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f94]=00000000, mtime: 1db9bc6fff2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f96]=00000000, mtime: 1db9bc7001e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f98]=00000000, mtime: 1db9bc7004c, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f9a]=00000000, mtime: 1db9bc70078, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f9c]=00000000, mtime: 1db9bc700a6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001f9e]=00000000, mtime: 1db9bc700d2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fa0]=00000000, mtime: 1db9bc700ff, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fa2]=00000000, mtime: 1db9bc7012b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fa4]=00000000, mtime: 1db9bc70158, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fa6]=00000000, mtime: 1db9bc70184, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fa8]=00000000, mtime: 1db9bc701b1, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001faa]=00000000, mtime: 1db9bc701dd, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fac]=00000000, mtime: 1db9bc7021a, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fae]=00000000, mtime: 1db9bc70246, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fb0]=00000000, mtime: 1db9bc70273, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fb2]=00000000, mtime: 1db9bc702a0, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fb4]=00000000, mtime: 1db9bc702cc, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fb6]=00000000, mtime: 1db9bc702f8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fb8]=00000000, mtime: 1db9bc70325, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fba]=00000000, mtime: 1db9bc70352, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fbc]=00000000, mtime: 1db9bc7037e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fbe]=00000000, mtime: 1db9bc703ab, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fc0]=00000000, mtime: 1db9bc703d8, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fc2]=00000000, mtime: 1db9bc70408, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fc4]=00000000, mtime: 1db9bc7043b, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fc6]=00000000, mtime: 1db9bc70477, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fc8]=00000000, mtime: 1db9bc704bb, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fca]=00000000, mtime: 1db9bc704fc, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fcc]=00000000, mtime: 1db9bc7053e, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fce]=00000000, mtime: 1db9bc70573, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd0]=00000000, mtime: 1db9bc705a2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd2]=00000000, mtime: 1db9bc705d2, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd4]=00000000, mtime: 1db9bc70605, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd6]=00000000, mtime: 1db9bc70635, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fd8]=00000000, mtime: 1db9bc70665, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fda]=00000000, mtime: 1db9bc70694, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fdc]=00000000, mtime: 1db9bc706c6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fde]=00000000, mtime: 1db9bc706f6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe0]=00000000, mtime: 1db9bc70725, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe2]=00000000, mtime: 1db9bc70755, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe4]=00000000, mtime: 1db9bc70784, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe6]=00000000, mtime: 1db9bc707b4, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fe8]=00000000, mtime: 1db9bc707e3, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fea]=00000000, mtime: 1db9bc70813, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fec]=00000000, mtime: 1db9bc70842, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001fee]=00000000, mtime: 1db9bc70872, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff0]=00000000, mtime: 1db9bc708a6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff2]=00000000, mtime: 1db9bc708d6, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff4]=00000000, mtime: 1db9bc70905, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff6]=00000000, mtime: 1db9bc70935, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ff8]=00000000, mtime: 1db9bc70968, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffa]=00000000, mtime: 1db9bc70998, mtimecmp: 0 -address 00000000 -insn_type : CINSN -[80001ffc]=00000000, mtime: 1db9bc709c7, mtimecmp: 0 -address ffff0000 -insn_type : CINSN -[80001ffe]=00000000, mtime: 1db9bc709f5, mtimecmp: 0 -address ffffffff -insn_type : INSN -[80002000]=ffffffff, mtime: 1db9bc70a22, mtimecmp: 0 -raise_exception: illegal instruction 0x2 0xffffffff -done interp faf int=0 mstatus=80 prv=3 +program end, result: 0000 +done interp 49 int=0 mstatus=80 prv=3 +size : 32 Registers: x0 zero: 00000000 x1 ra: 00000000 -x2 sp: 80002000 +x2 sp: 80002010 x3 gp: 00000001 x4 tp: 00000000 x5 t0: 800000f0 x6 t1: 00000000 x7 t2: 00000000 -x8 s0: 00000000 -x9 s1: 00000000 +x8 s0: 00007fff +x9 s1: 00008000 x10 a0: 00000000 x11 a1: 00000000 x12 a2: 00000000 x13 a3: 00000000 -x14 a4: 00000000 -x15 a5: 00000000 +x14 a4: 00000001 +x15 a5: ffffffff x16 a6: 00000000 x17 a7: 00000000 x18 s2: 00000000 @@ -12219,31 +494,30 @@ x30 t5: 00000000 x31 t6: 00000000 Instructions Stat: -LUI = 1 -AUIPC = 7 +LUI = 2 +AUIPC = 11 BEQ = 1 BLT = 1 -ADDI = 9 +ADDI = 13 FENCE = 2 ECALL = 2 CSRRW = 7 CSRRS = 3 CSRRWI = 5 -LI* = 1 MRET = 1 Five Most Frequent: -1) ADDI = 9 (0.22%) -2) AUIPC = 7 (0.17%) -3) CSRRW = 7 (0.17%) -4) CSRRWI = 5 (0.12%) -5) CSRRS = 3 (0.07%) +1) ADDI = 13 (17.81%) +2) AUIPC = 11 (15.07%) +3) CSRRW = 7 (9.59%) +4) CSRRWI = 5 (6.85%) +5) CSRRS = 3 (4.11%) -Memory Reading Area 80000000...80002003 -Memory Writing Area NONE +Memory Reading Area 80000000...8000014f +Memory Writing Area 80002000...80002013 ->>> Execution time: 26116764 ns ->>> Instruction count: 4015 (IPS=153732) ->>> Jumps: 2 (0.05%) - 2 forwards, 0 backwards +>>> Execution time: 1330762 ns +>>> Instruction count: 73 (IPS=54855) +>>> Jumps: 6 (8.22%) - 6 forwards, 0 backwards >>> Branching T=1 (50.00%) F=1 (50.00%) diff --git a/emu-rv32i.c b/emu-rv32i.c index 9573334..a6aa8b1 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -167,6 +167,7 @@ uint32_t end_signature = 0; /* is set to false to exit the emulator */ int machine_running = TRUE; +unsigned char state = 0; /* privilege levels */ #define PRV_U 0 @@ -750,6 +751,7 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; #ifdef DEBUG_OUTPUT + printf("Here core dump\n"); printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); #endif #ifdef RV32C @@ -1920,10 +1922,7 @@ void execute_instruction() #ifdef DEBUG_EXTRA dprintf(">>> Illegal instruction\n"); stats[64+0]++; -#endif break; - default: -#ifdef DEBUG_EXTRA dprintf(">>> C.ADDI4SPN\n"); stats[64+1]++; #endif @@ -1956,10 +1955,11 @@ void execute_instruction() #ifdef DEBUG_EXTRA dprintf(">>> C.ADDI\n"); #endif - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + rs1 = rd = ((midpart >> 5) & 0x1f); imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; } + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); break; case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA @@ -1978,18 +1978,20 @@ void execute_instruction() #endif switch(XLEN) { case 32: + rd = 0; imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | - (midpart & 0x170) | + (midpart & 0x180) | ((midpart << 2) & 0x40) | (midpart & 0x20) | ((midpart << 4) & 0x10) | ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); - imm = imm & 0xfffe; - if (rd != 0) - reg[1] = pc + 2; /* Store the link to x1 register */ + imm = (imm << 1) & 0xfffe; + printf("%08x\n", imm); + reg[1] = pc + 2; /* Store the link to x1 register */ next_pc = (int32_t)(pc + imm); + printf("next_pc: %08x\n", next_pc); if(next_pc > pc) forward_counter++; else backward_counter++; jump_counter++; @@ -2009,10 +2011,12 @@ void execute_instruction() #endif rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); + imm = imm << 26 >> 26; val = imm; - printf("%08x, rd: %d\n", val, rd); + printf("%08x, rd: %d, imm : %08x\n", val, rd, imm); break; case 3: /* C.ADDI16SP, C.LUI */ + rs1 = rd = ((midpart >> 5) & 0x1f); #ifdef DEBUG_EXTRA switch(rd){ case 2: @@ -2022,23 +2026,34 @@ void execute_instruction() dprintf(">>> C.LUI\n"); } #endif - rs1 = rd = ((midpart >> 5) & 0x1f); switch(rd){ case 2: imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | - ((midpart) & 0x8) | - ((midpart << 2) & 0xc) | - ((midpart >> 5) & 0x10); - imm = imm << 4; + ((midpart >> 1) & 0x4) | + ((midpart << 2) & 0x18) | + ((midpart >> 5) & 0x20); + imm = (imm << 4 )<< (31 - 9) >> (31 - 9); + printf("imm :%d\n", imm); val = reg[rd] + imm; break; default: imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - imm = ((imm << 12) & 0xfffff000); - imm = imm << 14 >> 14; - if(rd != 0) - val = reg[rd] | imm; + imm = (imm << 12); + if(imm == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0 && rd != 2){ + val = (reg[rd] & ~0x0003f000) | imm; + val = val & 0xfffff000; + val = (int32_t) val << (31 - 17) >> (31 - 17); + + } + else{ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } break; } break; @@ -2058,13 +2073,21 @@ void execute_instruction() #endif switch(XLEN){ case 32: + if((midpart >> 10 & 0x1)){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | (midpart >> 5 & 0x10); + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | (midpart >> 5 & 0x20); + if(imm == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } val = reg[rs1]; break; case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = 64; val = reg[rs1]; break; @@ -2077,30 +2100,44 @@ void execute_instruction() case 32: case 64: dprintf(">>> C.SRAI\n"); + break; case 128: dprintf(">>> C.SRAI64\n"); + break; } #endif switch(XLEN){ - case 32: case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); + case 32: + if((midpart >> 10 & 0x1)){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + case 64: + rs1 = rd = ((midpart >> 5) & 0x7) + 8; + imm = (midpart & 0x1f) | (midpart >> 5 & 0x20); + if(imm == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } val = reg[rs1]; + printf("imm : %08x\n", imm); + printf("val : %08x\n", val); break; case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; + rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = 64; val = reg[rs1]; break; } - val = val << imm; + val = (int32_t) val >> imm; break; case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA dprintf(">>> C.ANDI\n"); #endif rs1 = rd = ((midpart >> 5) & 0x7) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = imm << (31 - 5) >> (31 - 5); val = reg[rs1]; val = val & imm; break; @@ -2125,6 +2162,7 @@ void execute_instruction() dprintf(">>> C.OR\n"); #endif val = reg[rd] | reg[rs2]; + printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); break; case 3: /* C.AND */ #ifdef DEBUG_EXTRA @@ -2172,7 +2210,7 @@ void execute_instruction() rd = 0; imm = ((midpart >> 1) & 0x7) | ((midpart >> 6) & 0x8) | - ((midpart << 5) & 0x10) | + ((midpart << 4) & 0x10) | ((midpart) & 0x20) | ((midpart << 2) & 0x40) | ((midpart) & 0x180)| @@ -2192,11 +2230,11 @@ void execute_instruction() rd = 0; if(reg[rs1] == 0){ imm = ((midpart >> 1) & 0x3) | - ((midpart >> 3) & 0xc) | + ((midpart >> 6) & 0xc) | ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; + ((midpart >> 3) & 0x80); + imm = (imm << 1) << (31 - 8) >> (31 - 8); next_pc = (int32_t)(pc + imm); if(next_pc > pc) forward_counter++; else backward_counter++; @@ -2209,14 +2247,13 @@ void execute_instruction() #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; - imm = 0; if(reg[rs1] != 0){ imm = ((midpart >> 1) & 0x3) | ((midpart >> 6) & 0xc) | ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; + ((midpart >> 3) & 0x80); + imm = (imm << 1) << (31 - 8) >> (31 - 8); next_pc = (int32_t)(pc + imm); if(next_pc > pc) forward_counter++; else backward_counter++; @@ -2235,6 +2272,26 @@ void execute_instruction() } break; case 2: + funct3 = (insn >> 13) & 0x7; + midpart = (insn >> 2) & 0x07ff; + switch(funct3){ + case 6: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SWSP\n"); +#endif + rs2 = midpart & 0x1f; + imm = ((midpart >> 2) & 0x1e0) | + ((midpart << 4) & 0x600); + imm = (imm >> 3) & 0xff; + addr = reg[2] + imm; + val = reg[rs2]; + printf("rs2: %d, imm: %d, reg[rs2]: %d, val: %d\n", rs2, imm, reg[rs2], val); + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } + break; + } break; case 1: /* C.FLD, C.LQ*/ { diff --git a/sig.txt b/sig.txt new file mode 100644 index 0000000..906fac6 --- /dev/null +++ b/sig.txt @@ -0,0 +1,8 @@ +00000000 +00000001 +ffffffff +00007fff +00008000 +00000000 +00000000 +00000000 From 4232314ac3d27cf336fe894c6c105d6f398b7b65 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:45:49 +0800 Subject: [PATCH 16/24] Add the new function for signature validation --- debug.txt | 523 ---------------------------------------------------- emu-rv32i.c | 32 ++-- sig.txt | 20 ++ 3 files changed, 37 insertions(+), 538 deletions(-) delete mode 100644 debug.txt diff --git a/debug.txt b/debug.txt deleted file mode 100644 index 5036f60..0000000 --- a/debug.txt +++ /dev/null @@ -1,523 +0,0 @@ -./emu-rv32i work/rv32imc/C-BNEZ.elf +signature=sig.txt -sym '/tmp/cck1QDxQ.o' 0 -sym 'reset_vector' 80000040 -sym 'trap_vector' 80000004 -sym 'write_tohost' 80000036 -sym 'handle_exception' 80000032 -sym 'other_exception' 80000032 -sym 'begin_testcode' 800000f0 -sym 'test_1_res' 80002000 -sym 'test_2_res' 80002004 -sym 'test_3_res' 80002008 -sym 'test_4_res' 8000200c -sym 'test_5_res' 80002010 -sym 'end_testcode' 80000150 -sym 'end_signature' 80002020 -sym 'begin_regstate' 80002100 -sym 'begin_signature' 80002000 -sym '_start' 80000000 -sym 'end_regstate' 80002200 -sym '_end' 80002204 -sym 'fromhost' 80001100 -sym 'tohost' 80001000 -begin_signature: 0x80002000 -end_signature: 0x80002020 -start: 0x80000000 -codesize: 0x00002204 (8708) -codesize with offset: 8708 -Here core dump -address 0001a081 -insn_type : CINSN -[80000000]=0000a081, mtime: 1fdbfdbd62f, mtimecmp: 0 ->>> C.J -Here core dump -address f1402573 -insn_type : INSN -[80000040]=f1402573, mtime: 1fdbfdbd747, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -Here core dump -address 0297e101 -insn_type : CINSN -[80000044]=0000e101, mtime: 1fdbfdbd819, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 10, imm: 295583824, reg[rs1] : 0, pc: 0000000e, next_pc: a2dac760 -Here core dump -address 00000297 -insn_type : INSN -[80000046]=00000297, mtime: 1fdbfdbd8ff, mtimecmp: 0 ->>> AUIPC -Here core dump -address 01228293 -insn_type : INSN -[8000004a]=01228293, mtime: 1fdbfdbd99e, mtimecmp: 0 ->>> ADDI -Here core dump -address 30529073 -insn_type : INSN -[8000004e]=30529073, mtime: 1fdbfdbda34, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x00000000 -csr_write: csr=0x305 val=0x80000058 -Here core dump -address 18005073 -insn_type : INSN -[80000052]=18005073, mtime: 1fdbfdbdb5d, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x180 -1 -csr_read: csr=0x180 --> 0x00000000 -csr_write: csr=0x180 val=0x00000000 -Here core dump -address 02970001 -insn_type : CINSN -[80000056]=00000001, mtime: 1fdbfdbdc55, mtimecmp: 0 ->>> C.NOP -Here core dump -address 00000297 -insn_type : INSN -[80000058]=00000297, mtime: 1fdbfdbdceb, mtimecmp: 0 ->>> AUIPC -Here core dump -address 01828293 -insn_type : INSN -[8000005c]=01828293, mtime: 1fdbfdbdd86, mtimecmp: 0 ->>> ADDI -Here core dump -address 30529073 -insn_type : INSN -[80000060]=30529073, mtime: 1fdbfdbde19, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000058 -csr_write: csr=0x305 val=0x80000070 -Here core dump -address 907352fd -insn_type : CINSN -[80000064]=000052fd, mtime: 1fdbfdbdef9, mtimecmp: 0 ->>> C.LI -ffffffff, rd: 5, imm : ffffffff -Here core dump -address 3b029073 -insn_type : INSN -[80000066]=3b029073, mtime: 1fdbfdbdfa8, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3b0 -1 -csr_read: invalid CSR=0x3b0 -csr_write: csr=0x3b0 val=0xffffffff -Here core dump -address 907342fd -insn_type : CINSN -[8000006a]=000042fd, mtime: 1fdbfdbe082, mtimecmp: 0 ->>> C.LI -0000001f, rd: 5, imm : 0000001f -Here core dump -address 3a029073 -insn_type : INSN -[8000006c]=3a029073, mtime: 1fdbfdbe136, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x3a0 -1 -csr_read: invalid CSR=0x3a0 -csr_write: csr=0x3a0 val=0x0000001f -Here core dump -address 00000297 -insn_type : INSN -[80000070]=00000297, mtime: 1fdbfdbe213, mtimecmp: 0 ->>> AUIPC -Here core dump -address 01828293 -insn_type : INSN -[80000074]=01828293, mtime: 1fdbfdbe2a7, mtimecmp: 0 ->>> ADDI -Here core dump -address 30529073 -insn_type : INSN -[80000078]=30529073, mtime: 1fdbfdbe33b, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000070 -csr_write: csr=0x305 val=0x80000088 -Here core dump -address 30205073 -insn_type : INSN -[8000007c]=30205073, mtime: 1fdbfdbe417, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x302 -1 -csr_read: csr=0x302 --> 0x00000000 -csr_write: csr=0x302 val=0x00000000 -Here core dump -address 30305073 -insn_type : INSN -[80000080]=30305073, mtime: 1fdbfdbe5ec, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x303 -1 -csr_read: csr=0x303 --> 0x00000000 -csr_write: csr=0x303 val=0x00000000 -Here core dump -address 30405073 -insn_type : INSN -[80000084]=30405073, mtime: 1fdbfdbe6c4, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x304 -1 -csr_read: csr=0x304 --> 0x00000000 -csr_write: csr=0x304 val=0x00000000 -Here core dump -address 02974181 -insn_type : CINSN -[80000088]=00004181, mtime: 1fdbfdbe7c8, mtimecmp: 0 ->>> C.LI -00000000, rd: 3, imm : 00000000 -Here core dump -address 00000297 -insn_type : INSN -[8000008a]=00000297, mtime: 1fdbfdbe87f, mtimecmp: 0 ->>> AUIPC -Here core dump -address f7a28293 -insn_type : INSN -[8000008e]=f7a28293, mtime: 1fdbfdbe913, mtimecmp: 0 ->>> ADDI -Here core dump -address 30529073 -insn_type : INSN -[80000092]=30529073, mtime: 1fdbfdbe9ac, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x305 -1 -csr_read: csr=0x305 --> 0x80000088 -csr_write: csr=0x305 val=0x80000004 -Here core dump -address 057e4505 -insn_type : CINSN -[80000096]=00004505, mtime: 1fdbfdbea83, mtimecmp: 0 ->>> C.LI -00000001, rd: 10, imm : 00000001 -Here core dump -address 4763057e -insn_type : CINSN -[80000098]=0000057e, mtime: 1fdbfdbeb35, mtimecmp: 0 -Here core dump -address 00054763 -insn_type : INSN -[8000009a]=00054763, mtime: 1fdbfdbeba2, mtimecmp: 0 ->>> BLT -Here core dump -address 0ff0000f -insn_type : INSN -[8000009e]=0ff0000f, mtime: 1fdbfdbec38, mtimecmp: 0 ->>> FENCE -Here core dump -address 00734185 -insn_type : CINSN -[800000a2]=00004185, mtime: 1fdbfdbeccd, mtimecmp: 0 ->>> C.LI -00000001, rd: 3, imm : 00000001 -Here core dump -address 00000073 -insn_type : INSN -[800000a4]=00000073, mtime: 1fdbfdbed82, mtimecmp: 0 ->>> ECALL -syscall: 0001 -Unimplement Machine ecall! -Here core dump -address 80000297 -insn_type : INSN -[800000a8]=80000297, mtime: 1fdbfdbee57, mtimecmp: 0 ->>> AUIPC -Here core dump -address f5828293 -insn_type : INSN -[800000ac]=f5828293, mtime: 1fdbfdbeef8, mtimecmp: 0 ->>> ADDI -Here core dump -address 00028e63 -insn_type : INSN -[800000b0]=00028e63, mtime: 1fdbfdbef8d, mtimecmp: 0 ->>> BEQ -Here core dump -address 30005073 -insn_type : INSN -[800000cc]=30005073, mtime: 1fdbfdbf024, mtimecmp: 0 ->>> CSRRWI -csr_read: csr=0x300 -1 -csr_read: csr=0x300 --> 0x00000000 -csr_write: csr=0x300 val=0x00000000 -Here core dump -address 00002537 -insn_type : INSN -[800000d0]=00002537, mtime: 1fdbfdbf103, mtimecmp: 0 ->>> LUI -Here core dump -address 80050513 -insn_type : INSN -[800000d4]=80050513, mtime: 1fdbfdbf199, mtimecmp: 0 ->>> ADDI -Here core dump -address 30052073 -insn_type : INSN -[800000d8]=30052073, mtime: 1fdbfdbf231, mtimecmp: 0 -csr_read: csr=0x300 1 -csr_read: csr=0x300 --> 0x00000000 ->>> CSRRS -csr_write: csr=0x300 val=0x00001800 -Here core dump -address 00000297 -insn_type : INSN -[800000dc]=00000297, mtime: 1fdbfdbf30c, mtimecmp: 0 ->>> AUIPC -Here core dump -address 01428293 -insn_type : INSN -[800000e0]=01428293, mtime: 1fdbfdbf3aa, mtimecmp: 0 ->>> ADDI -Here core dump -address 34129073 -insn_type : INSN -[800000e4]=34129073, mtime: 1fdbfdbf43e, mtimecmp: 0 ->>> CSRRW -csr_read: csr=0x341 -1 -csr_read: csr=0x341 --> 0x00000000 -csr_write: csr=0x341 val=0x800000f0 -Here core dump -address f1402573 -insn_type : INSN -[800000e8]=f1402573, mtime: 1fdbfdbf516, mtimecmp: 0 -csr_read: csr=0xf14 0 -csr_read: csr=0xf14 --> 0x00000000 ->>> CSRRS -Here core dump -address 30200073 -insn_type : INSN -[800000ec]=30200073, mtime: 1fdbfdbf5e2, mtimecmp: 0 ->>> MRET -Here core dump -address 00002117 -insn_type : INSN -[800000f0]=00002117, mtime: 1fdbfdbf678, mtimecmp: 0 ->>> AUIPC -Here core dump -address f1010113 -insn_type : INSN -[800000f4]=f1010113, mtime: 1fdbfdbf70b, mtimecmp: 0 ->>> ADDI -Here core dump -address e2914681 -insn_type : CINSN -[800000f8]=00004681, mtime: 1fdbfdbf7a1, mtimecmp: 0 ->>> C.LI -00000000, rd: 13, imm : 00000000 -Here core dump -address 4681e291 -insn_type : CINSN -[800000fa]=0000e291, mtime: 1fdbfdbf85c, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 13, imm: 295583824, reg[rs1] : 0, pc: 0000000e, next_pc: a2dac760 -Here core dump -address c0364681 -insn_type : CINSN -[800000fc]=00004681, mtime: 1fdbfdbf919, mtimecmp: 0 ->>> C.LI -00000000, rd: 13, imm : 00000000 -Here core dump -address 2117c036 -insn_type : CINSN -[800000fe]=0000c036, mtime: 1fdbfdbf9c4, mtimecmp: 0 ->>> C.SWSP -rs2: 13, imm: 0, reg[rs2]: 0, val: 0 -Here core dump -address 00002117 -insn_type : INSN -[80000100]=00002117, mtime: 1fdbfdbfa74, mtimecmp: 0 ->>> AUIPC -Here core dump -address f0410113 -insn_type : INSN -[80000104]=f0410113, mtime: 1fdbfdbfb09, mtimecmp: 0 ->>> ADDI -Here core dump -address e3114705 -insn_type : CINSN -[80000108]=00004705, mtime: 1fdbfdbfbd3, mtimecmp: 0 ->>> C.LI -00000001, rd: 14, imm : 00000001 -Here core dump -address 4701e311 -insn_type : CINSN -[8000010a]=0000e311, mtime: 1fdbfdbfc8a, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 14, imm: 4, reg[rs1] : 1, pc: 0000000e, next_pc: a2dac760 -Here core dump -address 2117c03a -insn_type : CINSN -[8000010e]=0000c03a, mtime: 1fdbfdbfd3b, mtimecmp: 0 ->>> C.SWSP -rs2: 14, imm: 0, reg[rs2]: 1, val: 1 -Here core dump -address 00002117 -insn_type : INSN -[80000110]=00002117, mtime: 1fdbfdbfde7, mtimecmp: 0 ->>> AUIPC -Here core dump -address ef810113 -insn_type : INSN -[80000114]=ef810113, mtime: 1fdbfdbfe7b, mtimecmp: 0 ->>> ADDI -Here core dump -address e39157fd -insn_type : CINSN -[80000118]=000057fd, mtime: 1fdbfdbff14, mtimecmp: 0 ->>> C.LI -ffffffff, rd: 15, imm : ffffffff -Here core dump -address 4781e391 -insn_type : CINSN -[8000011a]=0000e391, mtime: 1fdbfdbffc0, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 15, imm: 4, reg[rs1] : -1, pc: 0000000e, next_pc: a2dac760 -Here core dump -address 2117c03e -insn_type : CINSN -[8000011e]=0000c03e, mtime: 1fdbfdc006e, mtimecmp: 0 ->>> C.SWSP -rs2: 15, imm: 0, reg[rs2]: -1, val: -1 -Here core dump -address 00002117 -insn_type : INSN -[80000120]=00002117, mtime: 1fdbfdc011f, mtimecmp: 0 ->>> AUIPC -Here core dump -address eec10113 -insn_type : INSN -[80000124]=eec10113, mtime: 1fdbfdc01b5, mtimecmp: 0 ->>> ADDI -Here core dump -address 00008437 -insn_type : INSN -[80000128]=00008437, mtime: 1fdbfdc0251, mtimecmp: 0 ->>> LUI -Here core dump -address fff40413 -insn_type : INSN -[8000012c]=fff40413, mtime: 1fdbfdc02e9, mtimecmp: 0 ->>> ADDI -Here core dump -address 4401e011 -insn_type : CINSN -[80000130]=0000e011, mtime: 1fdbfdc037d, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 8, imm: 4, reg[rs1] : 32767, pc: 0000000e, next_pc: a2dac760 -Here core dump -address 2117c022 -insn_type : CINSN -[80000134]=0000c022, mtime: 1fdbfdc042b, mtimecmp: 0 ->>> C.SWSP -rs2: 8, imm: 0, reg[rs2]: 32767, val: 32767 -Here core dump -address 00002117 -insn_type : INSN -[80000136]=00002117, mtime: 1fdbfdc04e1, mtimecmp: 0 ->>> AUIPC -Here core dump -address eda10113 -insn_type : INSN -[8000013a]=eda10113, mtime: 1fdbfdc0577, mtimecmp: 0 ->>> ADDI -Here core dump -address e09164a1 -insn_type : CINSN -[8000013e]=000064a1, mtime: 1fdbfdc060b, mtimecmp: 0 ->>> C.LUI -Here core dump -address 4481e091 -insn_type : CINSN -[80000140]=0000e091, mtime: 1fdbfdc06a2, mtimecmp: 0 ->>> C.BNEZ -rd : 0, rs1: 9, imm: 4, reg[rs1] : 32768, pc: 0000000e, next_pc: a2dac760 -Here core dump -address 000fc026 -insn_type : CINSN -[80000144]=0000c026, mtime: 1fdbfdc0756, mtimecmp: 0 ->>> C.SWSP -rs2: 9, imm: 0, reg[rs2]: 32768, val: 32768 -Here core dump -address 0ff0000f -insn_type : INSN -[80000146]=0ff0000f, mtime: 1fdbfdc080d, mtimecmp: 0 ->>> FENCE -Here core dump -address 00734185 -insn_type : CINSN -[8000014a]=00004185, mtime: 1fdbfdc08a8, mtimecmp: 0 ->>> C.LI -00000001, rd: 3, imm : 00000001 -Here core dump -address 00000073 -insn_type : INSN -[8000014c]=00000073, mtime: 1fdbfdc0960, mtimecmp: 0 ->>> ECALL -program end, result: 0000 -done interp 49 int=0 mstatus=80 prv=3 -size : 32 - -Registers: -x0 zero: 00000000 -x1 ra: 00000000 -x2 sp: 80002010 -x3 gp: 00000001 -x4 tp: 00000000 -x5 t0: 800000f0 -x6 t1: 00000000 -x7 t2: 00000000 -x8 s0: 00007fff -x9 s1: 00008000 -x10 a0: 00000000 -x11 a1: 00000000 -x12 a2: 00000000 -x13 a3: 00000000 -x14 a4: 00000001 -x15 a5: ffffffff -x16 a6: 00000000 -x17 a7: 00000000 -x18 s2: 00000000 -x19 s3: 00000000 -x20 s4: 00000000 -x21 s5: 00000000 -x22 s6: 00000000 -x23 s7: 00000000 -x24 s8: 00000000 -x25 s9: 00000000 -x26 s10: 00000000 -x27 s11: 00000000 -x28 t3: 00000000 -x29 t4: 00000000 -x30 t5: 00000000 -x31 t6: 00000000 - -Instructions Stat: -LUI = 2 -AUIPC = 11 -BEQ = 1 -BLT = 1 -ADDI = 13 -FENCE = 2 -ECALL = 2 -CSRRW = 7 -CSRRS = 3 -CSRRWI = 5 -MRET = 1 - -Five Most Frequent: -1) ADDI = 13 (17.81%) -2) AUIPC = 11 (15.07%) -3) CSRRW = 7 (9.59%) -4) CSRRWI = 5 (6.85%) -5) CSRRS = 3 (4.11%) - -Memory Reading Area 80000000...8000014f -Memory Writing Area 80002000...80002013 - ->>> Execution time: 1330762 ns ->>> Instruction count: 73 (IPS=54855) ->>> Jumps: 6 (8.22%) - 6 forwards, 0 backwards ->>> Branching T=1 (50.00%) F=1 (50.00%) - diff --git a/emu-rv32i.c b/emu-rv32i.c index a6aa8b1..c8a9110 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -21,9 +21,20 @@ #include #include #include +<<<<<<< HEAD /* uncomment this for an instruction trace and other debug outputs */ // #define DEBUG_OUTPUT // #define DEBUG_EXTRA +======= + +/* uncomment this for an instruction trace and other debug outputs */ +#if 0 +#define DEBUG_OUTPUT +#endif +#if 0 +#define DEBUG_EXTRA +#endif +>>>>>>> Add the new function for signature validation #define STRICT_RV32I #define FALSE (0) @@ -751,7 +762,6 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) if (ptr > RAM_SIZE) return 1; uint8_t* p = ram + ptr; #ifdef DEBUG_OUTPUT - printf("Here core dump\n"); printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); #endif #ifdef RV32C @@ -1952,15 +1962,14 @@ void execute_instruction() #endif return; } else { -#ifdef DEBUG_EXTRA - dprintf(">>> C.ADDI\n"); -#endif rs1 = rd = ((midpart >> 5) & 0x1f); imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; - } - printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); - break; +#ifdef DEBUG_EXTRA + dprintf(">>> C.ADDI\n"); + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); +#endif + }break; case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA switch(XLEN){ @@ -1988,10 +1997,8 @@ void execute_instruction() ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); imm = (imm << 1) & 0xfffe; - printf("%08x\n", imm); reg[1] = pc + 2; /* Store the link to x1 register */ next_pc = (int32_t)(pc + imm); - printf("next_pc: %08x\n", next_pc); if(next_pc > pc) forward_counter++; else backward_counter++; jump_counter++; @@ -2013,7 +2020,6 @@ void execute_instruction() imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); imm = imm << 26 >> 26; val = imm; - printf("%08x, rd: %d, imm : %08x\n", val, rd, imm); break; case 3: /* C.ADDI16SP, C.LUI */ rs1 = rd = ((midpart >> 5) & 0x1f); @@ -2026,7 +2032,7 @@ void execute_instruction() dprintf(">>> C.LUI\n"); } #endif - switch(rd){ + switch(rd){ /* C.ADDI16SP */ case 2: imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | @@ -2034,7 +2040,6 @@ void execute_instruction() ((midpart << 2) & 0x18) | ((midpart >> 5) & 0x20); imm = (imm << 4 )<< (31 - 9) >> (31 - 9); - printf("imm :%d\n", imm); val = reg[rd] + imm; break; default: @@ -2120,8 +2125,6 @@ void execute_instruction() return; } val = reg[rs1]; - printf("imm : %08x\n", imm); - printf("val : %08x\n", val); break; case 128: rs1 = rd = ((midpart >> 5) & 0x7) + 8; @@ -2285,7 +2288,6 @@ void execute_instruction() imm = (imm >> 3) & 0xff; addr = reg[2] + imm; val = reg[rs2]; - printf("rs2: %d, imm: %d, reg[rs2]: %d, val: %d\n", rs2, imm, reg[rs2], val); if (target_write_u32(addr, val)) { raise_exception(pending_exception, pending_tval); return; diff --git a/sig.txt b/sig.txt index 906fac6..fc6ef5f 100644 --- a/sig.txt +++ b/sig.txt @@ -1,8 +1,28 @@ 00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000001 +00000001 +00000001 +00000000 +00000000 00000001 ffffffff 00007fff 00008000 00000000 +00000001 +00007fff +00007fff +00000000 +00000000 +00000000 +00008000 +00000000 +00008000 +00000000 00000000 00000000 From fcd3ebfc70d0525795ef5027939915afa56e4765 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Thu, 2 Jan 2020 17:49:01 +0800 Subject: [PATCH 17/24] Modified the gitignore Delete the unnecessary file --- .gitignore | 2 +- emu-rv32i.c | 11 ----------- sig.txt | 28 ---------------------------- 3 files changed, 1 insertion(+), 40 deletions(-) delete mode 100644 sig.txt diff --git a/.gitignore b/.gitignore index 91d1c1b..64dda3f 100644 --- a/.gitignore +++ b/.gitignore @@ -3,4 +3,4 @@ test1 sig.txt rom.v debug.txt -CSR.h \ No newline at end of file +CSR.h diff --git a/emu-rv32i.c b/emu-rv32i.c index c8a9110..0857893 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -21,20 +21,9 @@ #include #include #include -<<<<<<< HEAD /* uncomment this for an instruction trace and other debug outputs */ // #define DEBUG_OUTPUT // #define DEBUG_EXTRA -======= - -/* uncomment this for an instruction trace and other debug outputs */ -#if 0 -#define DEBUG_OUTPUT -#endif -#if 0 -#define DEBUG_EXTRA -#endif ->>>>>>> Add the new function for signature validation #define STRICT_RV32I #define FALSE (0) diff --git a/sig.txt b/sig.txt deleted file mode 100644 index fc6ef5f..0000000 --- a/sig.txt +++ /dev/null @@ -1,28 +0,0 @@ -00000000 -00000000 -00000000 -00000000 -00000000 -00000000 -00000001 -00000001 -00000001 -00000000 -00000000 -00000001 -ffffffff -00007fff -00008000 -00000000 -00000001 -00007fff -00007fff -00000000 -00000000 -00000000 -00008000 -00000000 -00008000 -00000000 -00000000 -00000000 From 6f8c58367e53cc8f5d99bb83de9852af045a6de9 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sat, 11 Jan 2020 16:18:11 +0800 Subject: [PATCH 18/24] Finish the Compressed instruction imp --- emu-rv32i.c | 353 ++++++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 344 insertions(+), 9 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 0857893..9be8d8d 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1940,6 +1940,41 @@ void execute_instruction() break; } break; + case 7: + { + switch(XLEN){ + case 32: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSW\n"); + stats[64+11]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unimp insn for rv32imc"); +#endif + break; + case 64: + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SD\n"); + stats[64+12]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn by rv32imc\n"); +#endif + break; + } + } + break; + default: + { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + break; + } + if(rd != 0) + reg[rd] = val; + break; case 1: funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; @@ -1948,6 +1983,7 @@ void execute_instruction() if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ #ifdef DEBUG_EXTRA dprintf(">>> C.NOP\n"); + stats[64+13]++; #endif return; } else { @@ -1956,6 +1992,7 @@ void execute_instruction() val = reg[rs1] + imm; #ifdef DEBUG_EXTRA dprintf(">>> C.ADDI\n"); + stats[64+14]++; printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); #endif }break; @@ -1964,10 +2001,12 @@ void execute_instruction() switch(XLEN){ case 32: dprintf(">>> C.JAL\n"); + stats[64+15]++; break; case 64: case 128: dprintf(">>> C.ADDIW\n"); + stats[64+16]++; break; default: dprintf(">>> Unknow XLEN\n"); @@ -2004,6 +2043,7 @@ void execute_instruction() case 2: /* C.LI */ #ifdef DEBUG_EXTRA dprintf(">>> C.LI\n"); + stats[64+17]++; #endif rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); @@ -2016,9 +2056,12 @@ void execute_instruction() switch(rd){ case 2: dprintf(">>> C.ADDI16SP\n"); + stats[64+18]++; break; default: dprintf(">>> C.LUI\n"); + stats[64+19]++; + break; } #endif switch(rd){ /* C.ADDI16SP */ @@ -2059,9 +2102,11 @@ void execute_instruction() case 32: case 64: dprintf(">>> C.SRLI\n"); + stats[64+20]++; break; case 128: dprintf(">>> C.SRLI64\n"); + stats[64+21]++; break; } #endif @@ -2094,9 +2139,11 @@ void execute_instruction() case 32: case 64: dprintf(">>> C.SRAI\n"); + stats[64+22]++; break; case 128: dprintf(">>> C.SRAI64\n"); + stats[64+23]++; break; } #endif @@ -2126,6 +2173,7 @@ void execute_instruction() case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA dprintf(">>> C.ANDI\n"); + stats[64+24]++; #endif rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); @@ -2140,31 +2188,36 @@ void execute_instruction() case 0: /* C.SUB */ #ifdef DEBUG_EXTRA dprintf(">>> C.SUB\n"); + stats[64+25]++; #endif val = reg[rd] - reg[rs2]; break; case 1: /* C.XOR */ #ifdef DEBUG_EXTRA dprintf(">>> C.XOR\n"); + stats[64+26]++; #endif val = reg[rd] ^ reg[rs2]; break; case 2: /* C.OR */ #ifdef DEBUG_EXTRA dprintf(">>> C.OR\n"); + stats[64+27]++; #endif val = reg[rd] | reg[rs2]; - printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); + //printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); break; case 3: /* C.AND */ #ifdef DEBUG_EXTRA dprintf(">>> C.AND\n"); + stats[64+28]++; #endif val = reg[rd] & reg[rs2]; break; case 4: /* C.SUBW */ #ifdef DEBUG_EXTRA dprintf(">>> C.SUBW\n"); + stats[64+29]++; #endif val = reg[rd] - reg[rs2]; if(XLEN == 128){ @@ -2178,6 +2231,7 @@ void execute_instruction() case 5: /* C.ADDW */ #ifdef DEBUG_EXTRA dprintf(">>> C.ADDW\n"); + stats[64+30]++; #endif val = reg[rd] + reg[rs2]; if(XLEN == 128){ @@ -2189,7 +2243,15 @@ void execute_instruction() } break; case 6: +#ifdef DEBUG_EXTRA + dprintf(">>> Reserved_1\n"); + stats[64+31]++; +#endif case 7: +#ifdef DEBUG_EXTRA + dprintf(">>> Reserved_2\n"); + stats[64+32]++; +#endif /* NOP */ break; } @@ -2198,6 +2260,7 @@ void execute_instruction() case 5: /* C.J */ #ifdef DEBUG_EXTRA dprintf(">>> C.J\n"); + stats[64+33]++; #endif rd = 0; imm = ((midpart >> 1) & 0x7) | @@ -2217,6 +2280,7 @@ void execute_instruction() case 6: /* C.BEQZ */ #ifdef DEBUG_EXTRA dprintf(">>> C.BEQZ\n"); + stats[64+34]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; @@ -2236,6 +2300,7 @@ void execute_instruction() case 7: /* C.BNEZ */ #ifdef DEBUG_EXTRA dprintf(">>> C.BNEZ\n"); + stats[64+35]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; @@ -2251,7 +2316,7 @@ void execute_instruction() else backward_counter++; jump_counter++; } -#ifdef DEBUG_EXTRA +#ifdef DEBUG_OUTPUT printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); #endif break; @@ -2263,20 +2328,240 @@ void execute_instruction() reg[rd] = val; } break; - case 2: + case 2: /* op 2*/ funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; switch(funct3){ - case 6: + case 0: /* C.SLLI, C.SLLI64*/ + { + imm = ((midpart >> 5 & 0x20) | (midpart & 0x1f)); + switch(XLEN){ + case 32: /* C.SLLI*/ + if(((midpart >> 10) & 0x1)){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SLLI\n"); + stats[64+36]++; +#endif + if(imm == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = imm & 0x3f; + break; + case 128: /* C.SLLI64 */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.SLLI64\n"); + stats[64+37]++; +#endif + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = 64; + +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn by rv32imc\n"); +#endif + break; + } + if(rd != 0) + val = (uint32_t) reg[rd] << imm; + } + break; + case 1: /* C.FLDSP C.LQSP*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLDSP */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.FLDSP\n");\ + stats[64+38]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported extension by rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.LQSP\n"); + stats[64+39]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("unsupported extension by rv32imc"); +#endif + break; + } + + } + break; + case 2: /* C.LWSP C.FLWSP*/ + { +#ifdef DEBUG_EXTRA + dprintf(">>> C.LWSP\n"); + stats[64+40]++; +#endif + rd = ((midpart >> 5) & 0x1f); + if(rd == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = ((midpart >> 2) & 0x7) | + ((midpart >> 7) & 0x8) | + ((midpart << 4) & 0x30); + imm = (imm << 2) & 0xff; + rs1 = 2; + addr = reg[rs1] + imm; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t)rval; +#ifdef DEBUG_OUTPUT +#endif + } + break; + case 3: /* C.FLWSP C.LDSP*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLWSP */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.FLWSP\n"); + stats[64+41]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported extension by rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.LDSP\n"); + stats[64+42]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("unsupported extension by rv32imc"); +#endif + break; + } + + } + break; + case 4: /* C.JR C.MV C.EBREAK C.JALR C.ADD */ + { + rd = 0; + rs1 = (midpart >> 5) & 0x1f; + rs2 = (midpart & 0x1f); + switch((midpart >> 10) & 0x1){ + case 0: + if(rs2 == 0){ /* C.JR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.JR\n"); + stats[64+43]++; +#endif + next_pc = reg[rs1]; + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + +#ifdef DEBUG_OUTPUT + printf("rs1: %d, rs2: %d, rd: %d\n", rs1, rs2, rd); +#endif + }else{ /* C.MV */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.MV\n"); + stats[64+44]++; +#endif + rd = rs1; + if(rd + rs1 + rs2 == 0){ + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + val = reg[rs2]; + } + break; + case 1: + if(rs1 == 0 && rs2 == 0){ /* C.EBREAK */ +#ifdef DEBUG_EXTRA + dprintf(">>> EBREAK\n"); + stats[64+45]++; +#endif + raise_exception(CAUSE_BREAKPOINT, 0); + return; + }else if(rs2 == 0 && rs1 != 0){ /* C.JALR */ +#ifdef DEBUG_EXTRA + dprintf(">>> C.JALR\n"); + stats[64+46]++; +#endif + rd = 1; + imm = reg[rs1]; + next_pc = reg[rs1]; + val = pc + 2; + if(next_pc > pc) forward_counter++; + else backward_counter++; + jump_counter++; + }else if(rs2 != 0 && rs1 != 0){ /* C.ADD */ + rd = rs1; + val = reg[rs1] + reg[rs2]; + } + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + } + break; + case 5: /* C.FSDSP C.SQSP*/ + { + switch(XLEN){ + case 32: + case 64: +#ifdef DEBUG_EXTRA + dprintf(">>> C.FSDS{\n"); + stats[64+47]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SQSP\n"); + stats[64+48]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + } + } + break; + case 6: /* C.SWSP*/ + { #ifdef DEBUG_EXTRA dprintf(">>> C.SWSP\n"); + stats[64+49]++; #endif + rd = 0; rs2 = midpart & 0x1f; imm = ((midpart >> 2) & 0x1e0) | ((midpart << 4) & 0x600); imm = (imm >> 3) & 0xff; addr = reg[2] + imm; val = reg[rs2]; +#ifdef DEBUG_OUTPUT + printf("rs2: %d, imm: %d, addr: %08x\n", rs2, imm, addr); +#endif if (target_write_u32(addr, val)) { raise_exception(pending_exception, pending_tval); return; @@ -2284,15 +2569,65 @@ void execute_instruction() break; } break; - case 1: /* C.FLD, C.LQ*/ + case 7: /* C.FSWSP C.SDSP */ { switch(XLEN){ case 32: - case 64: /* C.FLD */ #ifdef DEBUG_EXTRA - dprintf("C.FLD\n"); - printf("Not support to floating load double"); - stats[64+2]++; + dprintf(">>> C.FSWSP\n"); + stats[64+50]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + case 64: + case 128: +#ifdef DEBUG_EXTRA + dprintf(">>> C.SDSP\n"); + stats[64+51]++; +#endif +#ifdef DEBUG_OUTPUT + dprintf("Unsupported insn of rv32imc\n"); +#endif + break; + } + } + break; + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + if(rd != 0) + reg[rd] = val; + break; +#endif + default: + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } +} + +/* returns realtime in nanoseconds */ +int64_t get_clock() +{ + struct timespec ts; + clock_gettime(CLOCK_MONOTONIC, &ts); + return ts.tv_sec * 1000000000LL + ts.tv_nsec; +} + + +void riscv_cpu_interp_x32() +{ + /* we use a single execution loop to keep a simple control flow for emscripten */ + while (machine_running) { +#if 1 + /* update timer, assuming 10 MHz clock (100 ns period) for the mtime counter */ + mtime = get_clock() / 100ll; + + /* for reproducible debug runs, you can use a fixed fixed increment per instruction */ +#else + mtime += 10; #endif #ifdef DEBUG_OUTPUT #endif From 743ad851dc641cffc64468e1a6022a2369e4b0c4 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sat, 11 Jan 2020 20:25:21 +0800 Subject: [PATCH 19/24] Fix unknow problem of merging from previous commit --- emu-rv32i.c | 868 +++++++++++++++++++++++++++------------------------- 1 file changed, 448 insertions(+), 420 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 9be8d8d..c0626ac 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1,21 +1,73 @@ +/* Modified by Shaos + 24-DEC-2018 - Find top 5 instructions in DEBUG_EXTRA mode + 20-DEC-2018 - More statistical points + 22-NOV-2018 - Added saving HEX file with copy of the code in DEBUG_OUTPUT mode + 21-NOV-2018 - Some statistics added in DEBUG_EXTRA mode + 20-NOV-2018 - By default RV32M and RV32A extensions are disabled (STRICT_RV32I) + 18-NOV-2018 - Slghtly modified for pure C + Source code taken from https://gist.github.com/FrankBuss/c974e59826d33e21d7cad54491ab50e8 +*/ + +/* +RISCV emulator for the RV32I architecture +based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ +stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test +by Frank Buss, 2018 +Requires libelf-dev: +sudo apt-get install libelf-dev +Compile it like this: +gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i +It is compatible to Spike for the command line arguments, which means you can run +the compliance test from https://github.com/riscv/riscv-compliance like this: +make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant +It is also compatible with qemu32, as it is used for Zephyr. You can compile the +Zephyr examples for qemu like this: +cd zephyr +source zephyr-env.sh +cd samples/synchronization +mkdir build && cd build +cmake -GNinja -DBOARD=qemu_riscv32 .. +ninja +After this you can run it with the emulator like this: +emu-rv32i zephyr/zephyr.elf +original copyright: +*/ + /* - * A minimalist RISC-V emulator for the RV32I architecture. + * RISCV emulator + * + * Copyright (c) 2016 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: * - * rv32emu is freely redistributable under the MIT License. See the file - * "LICENSE" for information on usage and redistribution of this file. + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. */ #define XLEN 32 +#include +#include +#include #include -#include -#include -#include #include #include +#include #include -#include -#include +#include #include #include #include @@ -31,7 +83,7 @@ #ifdef DEBUG_EXTRA -uint32_t minmemr, maxmemr, minmemw, maxmemw; +uint32_t minmemr,maxmemr,minmemw,maxmemw; #define STATS_NUM 64 @@ -133,9 +185,9 @@ void print_stats(uint64_t total) #endif #ifdef DEBUG_OUTPUT -#define debug_out(...) printf(__VA_ARGS__) +#define dprintf(s) printf(s) #else -#define debug_out(...) +#define dprintf(s) #endif /* memory mapped registers */ @@ -154,9 +206,6 @@ uint64_t mtimecmp; /* virtual start address for index 0 in the ram array */ uint32_t ram_start; -/* program entry point */ -uint32_t start; - /* last byte of the memory initialized and temporary value */ uint32_t ram_last = 0; uint32_t ram_curr = 0; @@ -188,11 +237,10 @@ uint32_t reg[32]; uint8_t priv = PRV_M; /* see PRV_x */ -uint8_t fs; /* MSTATUS_FS value */ -uint8_t mxl; /* MXL field in MISA register */ +uint8_t fs; /* MSTATUS_FS value */ +uint8_t mxl; /* MXL field in MISA register */ -uint64_t jump_counter = 0, backward_counter = 0, forward_counter = 0, - true_counter = 0, false_counter = 0; +uint64_t jump_counter=0,backward_counter=0,forward_counter=0,true_counter=0,false_counter=0; uint64_t insn_counter = 0; int pending_exception; /* used during MMU exception handling */ @@ -223,33 +271,33 @@ uint32_t scounteren; uint32_t load_res; /* for atomic LR/SC */ /* exception causes */ -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_INTERRUPT ((uint32_t) 1 << 31) +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_INTERRUPT ((uint32_t)1 << 31) /* misa CSR */ -#define MCPUID_SUPER (1 << ('S' - 'A')) -#define MCPUID_USER (1 << ('U' - 'A')) -#define MCPUID_I (1 << ('I' - 'A')) -#define MCPUID_M (1 << ('M' - 'A')) -#define MCPUID_A (1 << ('A' - 'A')) -#define MCPUID_F (1 << ('F' - 'A')) -#define MCPUID_D (1 << ('D' - 'A')) -#define MCPUID_Q (1 << ('Q' - 'A')) -#define MCPUID_C (1 << ('C' - 'A')) +#define MCPUID_SUPER (1 << ('S' - 'A')) +#define MCPUID_USER (1 << ('U' - 'A')) +#define MCPUID_I (1 << ('I' - 'A')) +#define MCPUID_M (1 << ('M' - 'A')) +#define MCPUID_A (1 << ('A' - 'A')) +#define MCPUID_F (1 << ('F' - 'A')) +#define MCPUID_D (1 << ('D' - 'A')) +#define MCPUID_Q (1 << ('Q' - 'A')) +#define MCPUID_C (1 << ('C' - 'A')) #define MIP_USIP (1 << 0) #define MIP_SSIP (1 << 1) @@ -289,8 +337,8 @@ uint32_t load_res; /* for atomic LR/SC */ #define MSTATUS_MPRV (1 << 17) #define MSTATUS_SUM (1 << 18) #define MSTATUS_MXR (1 << 19) -#define MSTATUS_UXL_MASK ((uint64_t) 3 << MSTATUS_UXL_SHIFT) -#define MSTATUS_SXL_MASK ((uint64_t) 3 << MSTATUS_SXL_SHIFT) +#define MSTATUS_UXL_MASK ((uint64_t)3 << MSTATUS_UXL_SHIFT) +#define MSTATUS_SXL_MASK ((uint64_t)3 << MSTATUS_SXL_SHIFT) static inline int ctz32(uint32_t val) { @@ -327,16 +375,19 @@ static inline int ctz32(uint32_t val) #endif } -#define SSTATUS_MASK0 \ - (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_UPIE | MSTATUS_SPIE | MSTATUS_SPP | \ - MSTATUS_FS | MSTATUS_XS | MSTATUS_SUM | MSTATUS_MXR) +#define SSTATUS_MASK0 (MSTATUS_UIE | MSTATUS_SIE | \ + MSTATUS_UPIE | MSTATUS_SPIE | \ + MSTATUS_SPP | \ + MSTATUS_FS | MSTATUS_XS | \ + MSTATUS_SUM | MSTATUS_MXR) #define SSTATUS_MASK SSTATUS_MASK0 -#define MSTATUS_MASK \ - (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_MIE | MSTATUS_UPIE | MSTATUS_SPIE | \ - MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_MPP | MSTATUS_FS | MSTATUS_MPRV | \ - MSTATUS_SUM | MSTATUS_MXR) +#define MSTATUS_MASK (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_MIE | \ + MSTATUS_UPIE | MSTATUS_SPIE | MSTATUS_MPIE | \ + MSTATUS_SPP | MSTATUS_MPP | \ + MSTATUS_FS | \ + MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR) /* cycle and insn counters */ #define COUNTEREN_MASK ((1 << 0) | (1 << 2)) @@ -348,10 +399,10 @@ uint32_t get_mstatus(uint32_t mask) int sd; val = mstatus | (fs << MSTATUS_FS_SHIFT); val &= mask; - sd = - ((val & MSTATUS_FS) == MSTATUS_FS) | ((val & MSTATUS_XS) == MSTATUS_XS); + sd = ((val & MSTATUS_FS) == MSTATUS_FS) | + ((val & MSTATUS_XS) == MSTATUS_XS); if (sd) - val |= (uint32_t) 1 << (XLEN - 1); + val |= (uint32_t)1 << (XLEN - 1); return val; } @@ -367,14 +418,17 @@ void invalid_csr(uint32_t *pval, uint32_t csr) { /* the 'time' counter is usually emulated */ if (csr != 0xc01 && csr != 0xc81) { - debug_out("csr_read: invalid CSR=0x%x\n", csr); +#ifdef DEBUG_OUTPUT + printf("csr_read: invalid CSR=0x%x\n", csr); +#endif } *pval = 0; } /* return -1 if invalid CSR. 0 if OK. 'will_write' indicate that the csr will be written after (used for CSR access check) */ -int csr_read(uint32_t *pval, uint32_t csr, int will_write) +int csr_read(uint32_t *pval, uint32_t csr, + int will_write) { uint32_t val; @@ -387,7 +441,7 @@ int csr_read(uint32_t *pval, uint32_t csr, int will_write) if (priv < ((csr >> 8) & 3)) return -1; /* not enough priviledge */ - switch (csr) { + switch(csr) { case 0xc00: /* cycle */ case 0xc02: /* instret */ { @@ -403,8 +457,8 @@ int csr_read(uint32_t *pval, uint32_t csr, int will_write) } } } - val = (int64_t) insn_counter; - break; + val = (int64_t)insn_counter; + break; case 0xc80: /* cycleh */ case 0xc82: /* instreth */ { @@ -420,8 +474,8 @@ int csr_read(uint32_t *pval, uint32_t csr, int will_write) } } } - val = insn_counter >> 32; - break; + val = insn_counter >> 32; + break; case 0x100: val = get_mstatus(SSTATUS_MASK); @@ -454,11 +508,11 @@ int csr_read(uint32_t *pval, uint32_t csr, int will_write) val = satp; break; case 0x300: - val = get_mstatus((uint32_t) -1); + val = get_mstatus((uint32_t)-1); break; case 0x301: val = misa; - val |= (uint32_t) mxl << (XLEN - 2); + val |= (uint32_t)mxl << (XLEN - 2); break; case 0x302: val = medeleg; @@ -492,7 +546,7 @@ int csr_read(uint32_t *pval, uint32_t csr, int will_write) break; case 0xb00: /* mcycle */ case 0xb02: /* minstret */ - val = (int64_t) insn_counter; + val = (int64_t)insn_counter; break; case 0xb80: /* mcycleh */ case 0xb82: /* minstreth */ @@ -523,7 +577,7 @@ int csr_write(uint32_t csr, uint32_t val) #ifdef DEBUG_EXTRA printf("csr_write: csr=0x%03x val=0x%08x\n", csr, val); #endif - switch (csr) { + switch(csr) { case 0x100: /* sstatus */ set_mstatus((mstatus & ~SSTATUS_MASK) | (val & SSTATUS_MASK)); break; @@ -554,11 +608,12 @@ int csr_write(uint32_t csr, uint32_t val) mip = (mip & ~mask) | (val & mask); break; case 0x180: /* no ASID implemented */ - { - int new_mode; - new_mode = (val >> 31) & 1; - satp = (val & (((uint32_t) 1 << 22) - 1)) | (new_mode << 31); - } + { + int new_mode; + new_mode = (val >> 31) & 1; + satp = (val & (((uint32_t)1 << 22) - 1)) | + (new_mode << 31); + } return 2; case 0x300: @@ -613,7 +668,8 @@ void handle_sret() spp = (mstatus >> MSTATUS_SPP_SHIFT) & 1; /* set the IE state to previous IE state */ spie = (mstatus >> MSTATUS_SPIE_SHIFT) & 1; - mstatus = (mstatus & ~(1 << spp)) | (spie << spp); + mstatus = (mstatus & ~(1 << spp)) | + (spie << spp); /* set SPIE to 1 */ mstatus |= MSTATUS_SPIE; /* set SPP to U */ @@ -628,7 +684,8 @@ void handle_mret() mpp = (mstatus >> MSTATUS_MPP_SHIFT) & 3; /* set the IE state to previous IE state */ mpie = (mstatus >> MSTATUS_MPIE_SHIFT) & 1; - mstatus = (mstatus & ~(1 << mpp)) | (mpie << mpp); + mstatus = (mstatus & ~(1 << mpp)) | + (mpie << mpp); /* set MPIE to 1 */ mstatus |= MSTATUS_MPIE; /* set MPP to U */ @@ -643,8 +700,9 @@ void raise_exception(uint32_t cause, uint32_t tval) /* exit for Zephyr applications */ if (cause == CAUSE_ILLEGAL_INSTRUCTION) { - debug_out("raise_exception: illegal instruction 0x%x 0x%x\n", cause, - tval); +#ifdef DEBUG_OUTPUT + printf("raise_exception: illegal instruction 0x%x 0x%x\n", cause, tval); +#endif machine_running = FALSE; return; } @@ -680,7 +738,8 @@ void raise_exception(uint32_t cause, uint32_t tval) stval = tval; mstatus = (mstatus & ~MSTATUS_SPIE) | (((mstatus >> priv) & 1) << MSTATUS_SPIE_SHIFT); - mstatus = (mstatus & ~MSTATUS_SPP) | (priv << MSTATUS_SPP_SHIFT); + mstatus = (mstatus & ~MSTATUS_SPP) | + (priv << MSTATUS_SPP_SHIFT); mstatus &= ~MSTATUS_SIE; priv = PRV_S; next_pc = stvec; @@ -690,7 +749,8 @@ void raise_exception(uint32_t cause, uint32_t tval) mtval = tval; mstatus = (mstatus & ~MSTATUS_MPIE) | (((mstatus >> priv) & 1) << MSTATUS_MPIE_SHIFT); - mstatus = (mstatus & ~MSTATUS_MPP) | (priv << MSTATUS_MPP_SHIFT); + mstatus = (mstatus & ~MSTATUS_MPP) | + (priv << MSTATUS_MPP_SHIFT); mstatus &= ~MSTATUS_MIE; priv = PRV_M; next_pc = mtvec; @@ -706,7 +766,7 @@ uint32_t get_pending_irq_mask() return 0; enabled_ints = 0; - switch (priv) { + switch(priv) { case PRV_M: if (mstatus & MSTATUS_MIE) enabled_ints = ~mideleg; @@ -742,10 +802,8 @@ int raise_interrupt() unsigned char get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA - if (pc && pc < minmemr) - minmemr = pc; - if (pc + 3 > maxmemr) - maxmemr = pc + 3; + if(pc && pc < minmemr) minmemr = pc; + if(pc+3 > maxmemr) maxmemr = pc+3; #endif uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) return 1; @@ -768,10 +826,8 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) int target_read_u8(uint8_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemr) - minmemr = addr; - if (addr > maxmemr) - maxmemr = addr; + if((addr>>28)!=4 && addr < minmemr) minmemr = addr; + if(addr > maxmemr) maxmemr = addr; #endif addr -= ram_start; if (addr > RAM_SIZE) { @@ -780,7 +836,7 @@ int target_read_u8(uint8_t *pval, uint32_t addr) addr + ram_start); return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; *pval = p[0]; } return 0; @@ -791,10 +847,8 @@ int target_read_u8(uint8_t *pval, uint32_t addr) int target_read_u16(uint16_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemr) - minmemr = addr; - if (addr + 1 > maxmemr) - maxmemr = addr + 1; + if((addr>>28)!=4 && addr < minmemr) minmemr = addr; + if(addr+1 > maxmemr) maxmemr = addr+1; #endif if (addr & 1) { pending_exception = CAUSE_MISALIGNED_LOAD; @@ -802,13 +856,12 @@ int target_read_u16(uint16_t *pval, uint32_t addr) return 1; } addr -= ram_start; - if (addr > RAM_SIZE) { + if (addr > RAM_SIZE) { *pval = 0; - printf("illegal read 16, PC: 0x%08x, address: 0x%08x\n", pc, - addr + ram_start); + printf("illegal read 16, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; *pval = p[0] | (p[1] << 8); } return 0; @@ -819,10 +872,8 @@ int target_read_u16(uint16_t *pval, uint32_t addr) int target_read_u32(uint32_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemr) - minmemr = addr; - if (addr + 3 > maxmemr) - maxmemr = addr + 3; + if((addr>>28)!=4 && addr < minmemr) minmemr = addr; + if(addr+3 > maxmemr) maxmemr = addr+3; #endif if (addr & 3) { pending_exception = CAUSE_MISALIGNED_LOAD; @@ -832,20 +883,19 @@ int target_read_u32(uint32_t *pval, uint32_t addr) if (addr == MTIMECMP_ADDR) { *pval = (uint32_t) mtimecmp; } else if (addr == MTIMECMP_ADDR + 4) { - *pval = (uint32_t)(mtimecmp >> 32); + *pval = (uint32_t) (mtimecmp >> 32); } else if (addr == MTIME_ADDR) { *pval = (uint32_t) mtime; } else if (addr == MTIME_ADDR + 4) { - *pval = (uint32_t)(mtime >> 32); + *pval = (uint32_t) (mtime >> 32); } else { addr -= ram_start; if (addr > RAM_SIZE) { *pval = 0; - printf("illegal read 32, PC: 0x%08x, address: 0x%08x\n", pc, - addr + ram_start); + printf("illegal read 32, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; *pval = p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); } } @@ -857,10 +907,8 @@ int target_read_u32(uint32_t *pval, uint32_t addr) int target_write_u8(uint32_t addr, uint8_t val) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemw) - minmemw = addr; - if (addr > maxmemw) - maxmemw = addr; + if((addr>>28)!=4 && addr < minmemw) minmemw = addr; + if(addr > maxmemw) maxmemw = addr; #endif if (addr == UART_TX_ADDR) { /* test for UART output, compatible with QEMU */ @@ -868,11 +916,10 @@ int target_write_u8(uint32_t addr, uint8_t val) } else { addr -= ram_start; if (addr > RAM_SIZE - 1) { - printf("illegal write 8, PC: 0x%08x, address: 0x%08x\n", pc, - addr + ram_start); + printf("illegal write 8, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; p[0] = val & 0xff; } } @@ -884,10 +931,8 @@ int target_write_u8(uint32_t addr, uint8_t val) int target_write_u16(uint32_t addr, uint16_t val) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemw) - minmemw = addr; - if (addr + 1 > maxmemw) - maxmemw = addr + 1; + if((addr>>28)!=4 && addr < minmemw) minmemw = addr; + if(addr+1 > maxmemw) maxmemw = addr+1; #endif if (addr & 1) { pending_exception = CAUSE_MISALIGNED_STORE; @@ -896,11 +941,10 @@ int target_write_u16(uint32_t addr, uint16_t val) } addr -= ram_start; if (addr > RAM_SIZE - 2) { - printf("illegal write 16, PC: 0x%08x, address: 0x%08x\n", pc, - addr + ram_start); + printf("illegal write 16, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; p[0] = val & 0xff; p[1] = (val >> 8) & 0xff; } @@ -912,10 +956,8 @@ int target_write_u16(uint32_t addr, uint16_t val) int target_write_u32(uint32_t addr, uint32_t val) { #ifdef DEBUG_EXTRA - if ((addr >> 28) != 4 && addr < minmemw) - minmemw = addr; - if (addr + 3 > maxmemw) - maxmemw = addr + 3; + if((addr>>28)!=4 && addr < minmemw) minmemw = addr; + if(addr+3 > maxmemw) maxmemw = addr+3; #endif if (addr & 3) { pending_exception = CAUSE_MISALIGNED_STORE; @@ -926,16 +968,14 @@ int target_write_u32(uint32_t addr, uint32_t val) mtimecmp = (mtimecmp & 0xffffffff00000000ll) | val; mip &= ~MIP_MTIP; } else if (addr == MTIMECMP_ADDR + 4) { - mtimecmp = (mtimecmp & 0xffffffffll) | (((uint64_t) val) << 32); + mtimecmp = (mtimecmp & 0xffffffffll) | (((uint64_t)val) << 32); mip &= ~MIP_MTIP; } else { addr -= ram_start; - if (addr > RAM_SIZE - 4) { - printf("illegal write 32, PC: 0x%08x, address: 0x%08x\n", pc, - addr + ram_start); + if (addr > RAM_SIZE - 4) { return 1; } else { - uint8_t *p = ram + addr; + uint8_t* p = ram + addr; p[0] = val & 0xff; p[1] = (val >> 8) & 0xff; p[2] = (val >> 16) & 0xff; @@ -951,7 +991,7 @@ int32_t div32(int32_t a, int32_t b) { if (b == 0) { return -1; - } else if (a == ((int32_t) 1 << (XLEN - 1)) && b == -1) { + } else if (a == ((int32_t)1 << (XLEN - 1)) && b == -1) { return a; } else { return a / b; @@ -962,41 +1002,44 @@ uint32_t divu32(uint32_t a, uint32_t b) { if (b == 0) { return -1; + } else { + return a / b; } - return a / b; } int32_t rem32(int32_t a, int32_t b) { if (b == 0) { return a; - } else if (a == ((int32_t) 1 << (XLEN - 1)) && b == -1) { + } else if (a == ((int32_t)1 << (XLEN - 1)) && b == -1) { return 0; + } else { + return a % b; } - return a % b; } uint32_t remu32(uint32_t a, uint32_t b) { if (b == 0) { return a; + } else { + return a % b; } - return a % b; } static uint32_t mulh32(int32_t a, int32_t b) { - return ((int64_t) a * (int64_t) b) >> 32; + return ((int64_t)a * (int64_t)b) >> 32; } static uint32_t mulhsu32(int32_t a, uint32_t b) { - return ((int64_t) a * (int64_t) b) >> 32; + return ((int64_t)a * (int64_t)b) >> 32; } static uint32_t mulhu32(uint32_t a, uint32_t b) { - return ((int64_t) a * (int64_t) b) >> 32; + return ((int64_t)a * (int64_t)b) >> 32; } #endif @@ -1048,7 +1091,7 @@ void execute_instruction() { uint32_t opcode, rd, rs1, rs2, funct3; int32_t imm, cond, err; - uint32_t addr, val = 0, val2; + uint32_t addr, val=0, val2; uint16_t midpart; @@ -1083,11 +1126,12 @@ void execute_instruction() - switch (opcode) { + switch(opcode) { + case 0x37: /* lui */ #ifdef DEBUG_EXTRA - debug_out(">>> LUI\n"); + dprintf(">>> LUI\n"); stats[0]++; #endif if (rd != 0) @@ -1097,7 +1141,7 @@ void execute_instruction() case 0x17: /* auipc */ #ifdef DEBUG_EXTRA - debug_out(">>> AUIPC\n"); + dprintf(">>> AUIPC\n"); stats[1]++; #endif if (rd != 0) @@ -1107,52 +1151,50 @@ void execute_instruction() case 0x6f: /* jal */ #ifdef DEBUG_EXTRA - debug_out(">>> JAL\n"); + dprintf(">>> JAL\n"); stats[2]++; #endif - imm = ((insn >> (31 - 20)) & (1 << 20)) | ((insn >> (21 - 1)) & 0x7fe) | - ((insn >> (20 - 11)) & (1 << 11)) | (insn & 0xff000); + imm = ((insn >> (31 - 20)) & (1 << 20)) | + ((insn >> (21 - 1)) & 0x7fe) | + ((insn >> (20 - 11)) & (1 << 11)) | + (insn & 0xff000); imm = (imm << 11) >> 11; if (rd != 0) reg[rd] = pc + 4; next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; + if(next_pc > pc) forward_counter++; + else backward_counter++; jump_counter++; break; case 0x67: /* jalr */ #ifdef DEBUG_EXTRA - debug_out(">>> JALR\n"); + dprintf(">>> JALR\n"); stats[3]++; #endif - imm = (int32_t) insn >> 20; + imm = (int32_t)insn >> 20; val = pc + 4; next_pc = (int32_t)(reg[rs1] + imm) & ~1; if (rd != 0) reg[rd] = val; - if (next_pc > pc) - forward_counter++; - else - backward_counter++; + if(next_pc > pc) forward_counter++; + else backward_counter++; jump_counter++; break; case 0x63: /* BRANCH */ funct3 = (insn >> 12) & 7; - switch (funct3 >> 1) { + switch(funct3 >> 1) { case 0: /* beq/bne */ #ifdef DEBUG_EXTRA - if (!(funct3 & 1)) { - debug_out(">>> BEQ\n"); - stats[4]++; - } else { - debug_out(">>> BNE\n"); - stats[5]++; + if(!(funct3 & 1)) { + dprintf(">>> BEQ\n"); + stats[4]++; + } else { + dprintf(">>> BNE\n"); + stats[5]++; } #endif cond = (reg[rs1] == reg[rs2]); @@ -1182,31 +1224,30 @@ void execute_instruction() cond ^= (funct3 & 1); if (cond) { imm = ((insn >> (31 - 12)) & (1 << 12)) | - ((insn >> (25 - 5)) & 0x7e0) | ((insn >> (8 - 1)) & 0x1e) | + ((insn >> (25 - 5)) & 0x7e0) | + ((insn >> (8 - 1)) & 0x1e) | ((insn << (11 - 7)) & (1 << 11)); imm = (imm << 19) >> 19; next_pc = (int32_t)(pc + imm); - if (next_pc > pc) - forward_counter++; - else - backward_counter++; + if(next_pc > pc) forward_counter++; + else backward_counter++; jump_counter++; true_counter++; break; - } else - false_counter++; + } else false_counter++; break; case 0x03: /* LOAD */ funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; + imm = (int32_t)insn >> 20; addr = reg[rs1] + imm; - switch (funct3) { + switch(funct3) { + case 0: /* lb */ { #ifdef DEBUG_EXTRA - debug_out(">>> LB\n"); + dprintf(">>> LB\n"); stats[10]++; #endif uint8_t rval; @@ -1214,13 +1255,14 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int8_t) rval; - } break; + val = (int8_t)rval; + } + break; case 1: /* lh */ { #ifdef DEBUG_EXTRA - debug_out(">>> LH\n"); + dprintf(">>> LH\n"); stats[11]++; #endif uint16_t rval; @@ -1228,13 +1270,14 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int16_t) rval; - } break; + val = (int16_t)rval; + } + break; case 2: /* lw */ { #ifdef DEBUG_EXTRA - debug_out(">>> LW\n"); + dprintf(">>> LW\n"); stats[12]++; #endif uint32_t rval; @@ -1242,13 +1285,14 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int32_t) rval; - } break; + val = (int32_t)rval; + } + break; case 4: /* lbu */ { #ifdef DEBUG_EXTRA - debug_out(">>> LBU\n"); + dprintf(">>> LBU\n"); stats[13]++; #endif uint8_t rval; @@ -1257,12 +1301,13 @@ void execute_instruction() return; } val = rval; - } break; + } + break; case 5: /* lhu */ { #ifdef DEBUG_EXTRA - debug_out(">>> LHU\n"); + dprintf(">>> LHU\n"); stats[14]++; #endif uint16_t rval; @@ -1271,7 +1316,8 @@ void execute_instruction() return; } val = rval; - } break; + } + break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1288,10 +1334,11 @@ void execute_instruction() imm = (imm << 20) >> 20; addr = reg[rs1] + imm; val = reg[rs2]; - switch (funct3) { + switch(funct3) { + case 0: /* sb */ #ifdef DEBUG_EXTRA - debug_out(">>> SB\n"); + dprintf(">>> SB\n"); stats[15]++; #endif if (target_write_u8(addr, val)) { @@ -1302,7 +1349,7 @@ void execute_instruction() case 1: /* sh */ #ifdef DEBUG_EXTRA - debug_out(">>> SH\n"); + dprintf(">>> SH\n"); stats[16]++; #endif if (target_write_u16(addr, val)) { @@ -1313,7 +1360,7 @@ void execute_instruction() case 2: /* sw */ #ifdef DEBUG_EXTRA - debug_out(">>> SW\n"); + dprintf(">>> SW\n"); stats[17]++; #endif if (target_write_u32(addr, val)) { @@ -1331,20 +1378,19 @@ void execute_instruction() case 0x13: /* OP-IMM */ funct3 = (insn >> 12) & 7; - imm = (int32_t) insn >> 20; - switch (funct3) { + imm = (int32_t)insn >> 20; + switch(funct3) { case 0: /* addi */ #ifdef DEBUG_EXTRA - debug_out(">>> ADDI\n"); + dprintf(">>> ADDI\n"); stats[18]++; - if (rs1 == 0) - stats[47]++; /* li */ + if(rs1==0) stats[47]++; /* li */ #endif val = (int32_t)(reg[rs1] + imm); break; case 1: /* slli */ #ifdef DEBUG_EXTRA - debug_out(">>> SLLI\n"); + dprintf(">>> SLLI\n"); stats[24]++; #endif if ((imm & ~(XLEN - 1)) != 0) { @@ -1355,21 +1401,21 @@ void execute_instruction() break; case 2: /* slti */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTI\n"); + dprintf(">>> SLTI\n"); stats[19]++; #endif - val = (int32_t) reg[rs1] < (int32_t) imm; + val = (int32_t)reg[rs1] < (int32_t)imm; break; case 3: /* sltiu */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTIU\n"); + dprintf(">>> SLTIU\n"); stats[20]++; #endif - val = reg[rs1] < (uint32_t) imm; + val = reg[rs1] < (uint32_t)imm; break; case 4: /* xori */ #ifdef DEBUG_EXTRA - debug_out(">>> XORI\n"); + dprintf(">>> XORI\n"); stats[21]++; #endif val = reg[rs1] ^ imm; @@ -1379,30 +1425,33 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if (imm & 0x400) { + if (imm & 0x400) + { #ifdef DEBUG_EXTRA - debug_out(">>> SRAI\n"); + dprintf(">>> SRAI\n"); stats[26]++; #endif - val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); - } else { + val = (int32_t)reg[rs1] >> (imm & (XLEN - 1)); + } + else + { #ifdef DEBUG_EXTRA - debug_out(">>> SRLI\n"); + dprintf(">>> SRLI\n"); stats[25]++; #endif - val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); + val = (int32_t)((uint32_t)reg[rs1] >> (imm & (XLEN - 1))); } break; case 6: /* ori */ #ifdef DEBUG_EXTRA - debug_out(">>> ORI\n"); + dprintf(">>> ORI\n"); stats[22]++; #endif val = reg[rs1] | imm; break; case 7: /* andi */ #ifdef DEBUG_EXTRA - debug_out(">>> ANDI\n"); + dprintf(">>> ANDI\n"); stats[23]++; #endif val = reg[rs1] & imm; @@ -1420,68 +1469,69 @@ void execute_instruction() #ifndef STRICT_RV32I if (imm == 1) { funct3 = (insn >> 12) & 7; - switch (funct3) { + switch(funct3) { case 0: /* mul */ #ifdef DEBUG_EXTRA - debug_out(">>> MUL\n"); + dprintf(">>> MUL\n"); stats[48]++; #endif - val = (int32_t)((int32_t) val * (int32_t) val2); + val = (int32_t)((int32_t)val * (int32_t)val2); break; case 1: /* mulh */ #ifdef DEBUG_EXTRA - debug_out(">>> MULH\n"); + dprintf(">>> MULH\n"); stats[49]++; #endif - val = (int32_t) mulh32(val, val2); + val = (int32_t)mulh32(val, val2); break; - case 2: /* mulhsu */ + case 2:/* mulhsu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHSU\n"); + dprintf(">>> MULHSU\n"); stats[50]++; #endif - val = (int32_t) mulhsu32(val, val2); + val = (int32_t)mulhsu32(val, val2); break; - case 3: /* mulhu */ + case 3:/* mulhu */ #ifdef DEBUG_EXTRA - debug_out(">>> MULHU\n"); + dprintf(">>> MULHU\n"); stats[51]++; #endif - val = (int32_t) mulhu32(val, val2); + val = (int32_t)mulhu32(val, val2); break; - case 4: /* div */ + case 4:/* div */ #ifdef DEBUG_EXTRA - debug_out(">>> DIV\n"); + dprintf(">>> DIV\n"); stats[52]++; #endif val = div32(val, val2); break; - case 5: /* divu */ + case 5:/* divu */ #ifdef DEBUG_EXTRA - debug_out(">>> DIVU\n"); + dprintf(">>> DIVU\n"); stats[53]++; #endif - val = (int32_t) divu32(val, val2); + val = (int32_t)divu32(val, val2); break; - case 6: /* rem */ + case 6:/* rem */ #ifdef DEBUG_EXTRA - debug_out(">>> REM\n"); + dprintf(">>> REM\n"); stats[54]++; #endif val = rem32(val, val2); break; - case 7: /* remu */ + case 7:/* remu */ #ifdef DEBUG_EXTRA - debug_out(">>> REMU\n"); + dprintf(">>> REMU\n"); stats[55]++; #endif - val = (int32_t) remu32(val, val2); + val = (int32_t)remu32(val, val2); break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } else + } + else #endif { if (imm & ~0x20) { @@ -1489,73 +1539,73 @@ void execute_instruction() return; } funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); - switch (funct3) { + switch(funct3) { case 0: /* add */ #ifdef DEBUG_EXTRA - debug_out(">>> ADD\n"); + dprintf(">>> ADD\n"); stats[27]++; #endif val = (int32_t)(val + val2); break; case 0 | 8: /* sub */ #ifdef DEBUG_EXTRA - debug_out(">>> SUB\n"); + dprintf(">>> SUB\n"); stats[28]++; #endif val = (int32_t)(val - val2); break; case 1: /* sll */ #ifdef DEBUG_EXTRA - debug_out(">>> SLL\n"); + dprintf(">>> SLL\n"); stats[29]++; #endif val = (int32_t)(val << (val2 & (XLEN - 1))); break; case 2: /* slt */ #ifdef DEBUG_EXTRA - debug_out(">>> SLT\n"); + dprintf(">>> SLT\n"); stats[30]++; #endif - val = (int32_t) val < (int32_t) val2; + val = (int32_t)val < (int32_t)val2; break; case 3: /* sltu */ #ifdef DEBUG_EXTRA - debug_out(">>> SLTU\n"); + dprintf(">>> SLTU\n"); stats[31]++; #endif val = val < val2; break; case 4: /* xor */ #ifdef DEBUG_EXTRA - debug_out(">>> XOR\n"); + dprintf(">>> XOR\n"); stats[32]++; #endif val = val ^ val2; break; case 5: /* srl */ #ifdef DEBUG_EXTRA - debug_out(">>> SRL\n"); + dprintf(">>> SRL\n"); stats[33]++; #endif - val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); + val = (int32_t)((uint32_t)val >> (val2 & (XLEN - 1))); break; case 5 | 8: /* sra */ #ifdef DEBUG_EXTRA - debug_out(">>> SRA\n"); + dprintf(">>> SRA\n"); stats[34]++; #endif - val = (int32_t) val >> (val2 & (XLEN - 1)); + val = (int32_t)val >> (val2 & (XLEN - 1)); break; case 6: /* or */ #ifdef DEBUG_EXTRA - debug_out(">>> OR\n"); + dprintf(">>> OR\n"); stats[35]++; #endif val = val | val2; break; case 7: /* and */ #ifdef DEBUG_EXTRA - debug_out(">>> AND\n"); + dprintf(">>> AND\n"); stats[36]++; #endif val = val & val2; @@ -1578,22 +1628,26 @@ void execute_instruction() else val = reg[rs1]; funct3 &= 3; - switch (funct3) { + switch(funct3) { + case 1: /* csrrw & csrrwi */ #ifdef DEBUG_EXTRA - if ((insn >> 12) & 4) { - debug_out(">>> CSRRWI\n"); - stats[44]++; - } else { - debug_out(">>> CSRRW\n"); - stats[41]++; + if ((insn >> 12) & 4) + { + dprintf(">>> CSRRWI\n"); + stats[44]++; + } + else + { + dprintf(">>> CSRRW\n"); + stats[41]++; } #endif if (csr_read(&val2, imm, TRUE)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - val2 = (int32_t) val2; + val2 = (int32_t)val2; err = csr_write(imm, val); if (err < 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1612,31 +1666,24 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - val2 = (int32_t) val2; + val2 = (int32_t)val2; #ifdef DEBUG_EXTRA - switch ((insn >> 12) & 7) { - case 2: - debug_out(">>> CSRRS\n"); - stats[42]++; - break; - case 3: - debug_out(">>> CSRRC\n"); - stats[43]++; - break; - case 6: - debug_out(">>> CSRRSI\n"); - stats[45]++; - break; - case 7: - debug_out(">>> CSRRCI\n"); - stats[46]++; - break; + switch((insn >> 12) & 7) + { + case 2: dprintf(">>> CSRRS\n"); stats[42]++; break; + case 3: dprintf(">>> CSRRC\n"); stats[43]++; break; + case 6: dprintf(">>> CSRRSI\n"); stats[45]++; break; + case 7: dprintf(">>> CSRRCI\n"); stats[46]++; break; } #endif - if (rs1 != 0) { - if (funct3 == 2) { + if (rs1 != 0) + { + if (funct3 == 2) + { val = val2 | val; - } else { + } + else + { val = val2 & ~val; } err = csr_write(imm, val); @@ -1644,7 +1691,9 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } else { + } + else + { err = 0; } if (rd != 0) @@ -1652,10 +1701,10 @@ void execute_instruction() break; case 0: - switch (imm) { + switch(imm) { case 0x000: /* ecall */ #ifdef DEBUG_EXTRA - debug_out(">>> ECALL\n"); + dprintf(">>> ECALL\n"); stats[39]++; #endif if (insn & 0x000fff80) { @@ -1669,17 +1718,20 @@ void execute_instruction() */ if (begin_signature) { if (reg[3] & 1) { - debug_out("program end, result: %04x\n", reg[3] >> 1); +#ifdef DEBUG_OUTPUT + printf("program end, result: %04x\n", reg[3] >> 1); +#endif machine_running = FALSE; return; } else { - debug_out("syscall: %04x\n", reg[3]); +#ifdef DEBUG_OUTPUT + printf("syscall: %04x\n", reg[3]); +#endif raise_exception(CAUSE_USER_ECALL + priv, 0); } } else { - /* on real hardware, an exception is raised, the I-ECALL-01 - * compliance test tests this as well */ + /* on real hardware, an exception is raised, the I-ECALL-01 compliance test tests this as well */ raise_exception(CAUSE_USER_ECALL + priv, 0); return; } @@ -1687,7 +1739,7 @@ void execute_instruction() case 0x001: /* ebreak */ #ifdef DEBUG_EXTRA - debug_out(">>> EBREAK\n"); + dprintf(">>> EBREAK\n"); stats[40]++; #endif if (insn & 0x000fff80) { @@ -1700,7 +1752,7 @@ void execute_instruction() case 0x102: /* sret */ { #ifdef DEBUG_EXTRA - debug_out(">>> SRET\n"); + dprintf(">>> SRET\n"); stats[59]++; #endif if ((insn & 0x000fff80) || (priv < PRV_S)) { @@ -1709,11 +1761,12 @@ void execute_instruction() } handle_sret(); return; - } break; + } + break; case 0x105: /* wfi */ #ifdef DEBUG_EXTRA - debug_out(">>> WFI\n"); + dprintf(">>> WFI\n"); stats[61]++; #endif /* wait for interrupt: it is allowed to execute it as nop */ @@ -1722,7 +1775,7 @@ void execute_instruction() case 0x302: /* mret */ { #ifdef DEBUG_EXTRA - debug_out(">>> MRET\n"); + dprintf(">>> MRET\n"); stats[60]++; #endif if ((insn & 0x000fff80) || (priv < PRV_M)) { @@ -1731,12 +1784,13 @@ void execute_instruction() } handle_mret(); return; - } break; + } + break; default: if ((imm >> 5) == 0x09) { #ifdef DEBUG_EXTRA - debug_out(">>> SFENCE.VMA\n"); + dprintf(">>> SFENCE.VMA\n"); stats[62]++; #endif /* sfence.vma */ @@ -1761,10 +1815,11 @@ void execute_instruction() case 0x0f: /* MISC-MEM */ funct3 = (insn >> 12) & 7; - switch (funct3) { + switch(funct3) { + case 0: /* fence */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE\n"); + dprintf(">>> FENCE\n"); stats[37]++; #endif if (insn & 0xf00fff80) { @@ -1775,7 +1830,7 @@ void execute_instruction() case 1: /* fence.i */ #ifdef DEBUG_EXTRA - debug_out(">>> FENCE.I\n"); + dprintf(">>> FENCE.I\n"); stats[38]++; #endif if (insn != 0x0000100f) { @@ -1795,16 +1850,18 @@ void execute_instruction() case 0x2f: /* AMO */ funct3 = (insn >> 12) & 7; - switch (funct3) { - case 2: { + switch(funct3) { + case 2: + { uint32_t rval; addr = reg[rs1]; funct3 = insn >> 27; - switch (funct3) { + switch(funct3) { + case 2: /* lr.w */ #ifdef DEBUG_EXTRA - debug_out(">>> LR.W\n"); + dprintf(">>> LR.W\n"); stats[56]++; #endif if (rs2 != 0) { @@ -1815,13 +1872,13 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int32_t) rval; + val = (int32_t)rval; load_res = addr; break; case 3: /* sc.w */ #ifdef DEBUG_EXTRA - debug_out(">>> SC.W\n"); + dprintf(">>> SC.W\n"); stats[57]++; #endif if (load_res == addr) { @@ -1835,27 +1892,27 @@ void execute_instruction() } break; - case 1: /* amiswap.w */ - case 0: /* amoadd.w */ - case 4: /* amoxor.w */ - case 0xc: /* amoand.w */ - case 0x8: /* amoor.w */ + case 1: /* amiswap.w */ + case 0: /* amoadd.w */ + case 4: /* amoxor.w */ + case 0xc: /* amoand.w */ + case 0x8: /* amoor.w */ case 0x10: /* amomin.w */ case 0x14: /* amomax.w */ case 0x18: /* amominu.w */ case 0x1c: /* amomaxu.w */ #ifdef DEBUG_EXTRA - debug_out(">>> AM...\n"); + dprintf(">>> AM...\n"); stats[63]++; #endif if (target_read_u32(&rval, addr)) { raise_exception(pending_exception, pending_tval); return; } - val = (int32_t) rval; + val = (int32_t)rval; val2 = reg[rs2]; - switch (funct3) { + switch(funct3) { case 1: /* amiswap.w */ break; case 0: /* amoadd.w */ @@ -1871,20 +1928,20 @@ void execute_instruction() val2 = (int32_t)(val | val2); break; case 0x10: /* amomin.w */ - if ((int32_t) val < (int32_t) val2) - val2 = (int32_t) val; + if ((int32_t)val < (int32_t)val2) + val2 = (int32_t)val; break; case 0x14: /* amomax.w */ - if ((int32_t) val > (int32_t) val2) - val2 = (int32_t) val; + if ((int32_t)val > (int32_t)val2) + val2 = (int32_t)val; break; case 0x18: /* amominu.w */ - if ((uint32_t) val < (uint32_t) val2) - val2 = (int32_t) val; + if ((uint32_t)val < (uint32_t)val2) + val2 = (int32_t)val; break; case 0x1c: /* amomaxu.w */ - if ((uint32_t) val > (uint32_t) val2) - val2 = (int32_t) val; + if ((uint32_t)val > (uint32_t)val2) + val2 = (int32_t)val; break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1899,7 +1956,8 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } break; + } + break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; @@ -2662,6 +2720,7 @@ void riscv_cpu_interp_x32() printf("addr: %08x\n", addr); #endif } +<<<<<<< HEAD break; case 3: /* C.FLW C.LD*/ { @@ -2671,18 +2730,17 @@ void riscv_cpu_interp_x32() dprintf(">>> C.FLW\n"); stats[64+5]++; #endif -#ifdef DEBUG_OUTPUT dprintf("Unimp insn for rv64c\n"); -#endif - break; - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.LD\n"); - stats[64+6]++; -#endif +======= + + /* update current PC */ + pc = next_pc; + } + #ifdef DEBUG_OUTPUT - dprintf("Unimp insn for rv128c\n"); -#endif + printf("done interp %lx int=%x mstatus=%lx prv=%d\n", + (uint64_t)insn_counter, mip & mie, (uint64_t)mstatus, + priv); break; } } @@ -3492,8 +3550,7 @@ int main(int argc, char **argv) return 1; } - for (uint32_t u = 0; u < RAM_SIZE; u++) - ram[u] = 0; + for(uint32_t u=0;u= ram_start) { for (size_t i = 0; i < shdr.sh_size; i++) { ram_curr = shdr.sh_addr + i - ram_start; - if (ram_curr >= RAM_SIZE) { - debug_out( - "memory pointer outside of range 0x%08x (section " - "at address 0x%08x)\n", - ram_curr, (uint32_t) shdr.sh_addr); + if(ram_curr >= RAM_SIZE) + { +#ifdef DEBUG_OUTPUT + printf("memory pointer outside of range 0x%08x (section at address 0x%08x)\n", ram_curr, (uint32_t) shdr.sh_addr); +#endif /* break; */ - } else { - ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; - if (ram_curr > ram_last) - ram_last = ram_curr; + } + else + { + ram[ram_curr] = ((uint8_t *)data->d_buf)[i]; + if(ram_curr > ram_last) ram_last = ram_curr; } } } else { - debug_out("ignoring section at address 0x%08x\n", - (uint32_t) shdr.sh_addr); +#ifdef DEBUG_OUTPUT + printf("ignoring section at address 0x%08x\n", (uint32_t) shdr.sh_addr); +#endif } } } @@ -3601,56 +3641,54 @@ int main(int argc, char **argv) close(fd); #ifdef DEBUG_OUTPUT - printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); + printf("codesize: 0x%08x (%i)\n", ram_last+1, ram_last+1); strcpy(hex_file, elf_file); - po = strrchr(hex_file, '.'); - if (po != NULL) - *po = 0; - strcat(hex_file, ".mem"); - fo = fopen(hex_file, "wt"); - if (fo != NULL) { - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, "%02X ", ram[u]); - if ((u & 15) == 15) - fprintf(fo, "\n"); - } - fprintf(fo, "\n"); - fclose(fo); + po = strrchr(hex_file,'.'); + if(po!=NULL) *po = 0; + strcat(hex_file,".mem"); + fo = fopen(hex_file,"wt"); + if(fo!=NULL) + { + for(uint32_t u=0;u<=ram_last;u++) + { + fprintf(fo,"%02X ",ram[u]); + if((u&15)==15) fprintf(fo,"\n"); + } + fprintf(fo,"\n"); + fclose(fo); } #if 1 - fo = fopen("rom.v", "wt"); - if (fo != NULL) { - fprintf(fo, "module rom(addr,data);\n"); - uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; - printf("codesize with offset: %i\n", romsz); - if (romsz >= 32768) - fprintf(fo, "input [15:0] addr;\n"); - else if (romsz >= 16384) - fprintf(fo, "input [14:0] addr;\n"); - else if (romsz >= 8192) - fprintf(fo, "input [13:0] addr;\n"); - else if (romsz >= 4096) - fprintf(fo, "input [12:0] addr;\n"); - else if (romsz >= 2048) - fprintf(fo, "input [11:0] addr;\n"); - else if (romsz >= 1024) - fprintf(fo, "input [10:0] addr;\n"); - else if (romsz >= 512) - fprintf(fo, "input [9:0] addr;\n"); - else if (romsz >= 256) - fprintf(fo, "input [8:0] addr;\n"); - else - fprintf(fo, "input [7:0] addr;\n"); - fprintf(fo, - "output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); - for (uint32_t u = 0; u <= ram_last; u++) { - fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, - ram[u]); - } - fprintf(fo, - " default: data = 8'h01; // invalid instruction\n " - "endcase\nend\nendmodule\n"); - fclose(fo); + fo = fopen("rom.v","wt"); + if(fo!=NULL) + { + fprintf(fo,"module rom(addr,data);\n"); + uint32_t romsz = (ram_start&0xFFFF) + ram_last + 1; + printf("codesize with offset: %i\n",romsz); + if(romsz >= 32768) + fprintf(fo,"input [15:0] addr;\n"); + else if(romsz >= 16384) + fprintf(fo,"input [14:0] addr;\n"); + else if(romsz >= 8192) + fprintf(fo,"input [13:0] addr;\n"); + else if(romsz >= 4096) + fprintf(fo,"input [12:0] addr;\n"); + else if(romsz >= 2048) + fprintf(fo,"input [11:0] addr;\n"); + else if(romsz >= 1024) + fprintf(fo,"input [10:0] addr;\n"); + else if(romsz >= 512) + fprintf(fo,"input [9:0] addr;\n"); + else if(romsz >= 256) + fprintf(fo,"input [8:0] addr;\n"); + else + fprintf(fo,"input [7:0] addr;\n"); + fprintf(fo,"output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); + for(uint32_t u=0;u<=ram_last;u++) + { + fprintf(fo," %i : data = 8'h%02X;\n",(ram_start&0xFFFF)+u,ram[u]); + } + fprintf(fo," default: data = 8'h01; // invalid instruction\n endcase\nend\nendmodule\n"); + fclose(fo); } #endif #endif @@ -3719,21 +3757,11 @@ int main(int argc, char **argv) #if 1 printf("\n"); - printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); - printf(">>> Instruction count: %llu (IPS=%llu)\n", - (long long unsigned) insn_counter, - (long long) insn_counter * 1000000000LL / (ns2 - ns1)); - printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", - (long long unsigned) jump_counter, - jump_counter * 100.0 / insn_counter, - (long long unsigned) forward_counter, - (long long unsigned) backward_counter); - printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", - (long long unsigned) true_counter, - true_counter * 100.0 / (true_counter + false_counter), - (long long unsigned) false_counter, - false_counter * 100.0 / (true_counter + false_counter)); + printf(">>> Execution time: %llu ns\n",(long long unsigned)ns2-ns1); + printf(">>> Instruction count: %llu (IPS=%llu)\n",(long long unsigned)insn_counter,(long long)insn_counter*1000000000LL/(ns2-ns1)); + printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n",(long long unsigned)jump_counter,jump_counter*100.0/insn_counter,(long long unsigned)forward_counter,(long long unsigned)backward_counter); + printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n",(long long unsigned)true_counter,true_counter*100.0/(true_counter+false_counter),(long long unsigned)false_counter,false_counter*100.0/(true_counter+false_counter)); printf("\n"); #endif return 0; -} +} \ No newline at end of file From 3440e94016c6be0cadff914214a3f50d20c1b598 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sat, 11 Jan 2020 20:27:22 +0800 Subject: [PATCH 20/24] Remove missing debugging info --- emu-rv32i.c | 1 - 1 file changed, 1 deletion(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index c0626ac..9ca412a 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -2797,7 +2797,6 @@ void riscv_cpu_interp_x32() addr = reg[rs1] + imm; val = reg[rs2]; rd = 0; - printf("addr: %08x\n", addr); if (target_write_u32(addr, val)) { raise_exception(pending_exception, pending_tval); return; From 83f34134c641721455b1be3f192c1db4da68ca65 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sat, 11 Jan 2020 23:31:37 +0800 Subject: [PATCH 21/24] Modified the README.md about testing the test-cases --- README.md | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/README.md b/README.md index 748f7eb..fa56e40 100644 --- a/README.md +++ b/README.md @@ -17,13 +17,23 @@ or $ make emu-rv32i ``` -Passed RV32I compliance tests from https://github.com/riscv/riscv-compliance +Passed RV32IC compliance tests from https://github.com/riscv/riscv-compliance - Must install the [risc-v toolchain](https://xpack.github.io/riscv-none-embed-gcc/) + +- Run RV32I compliance tests. +Assume `emu-rv32i` in `$PATH` environment variable. ```shell $ git clone https://github.com/riscv/riscv-compliance $ cd riscv-compliance $ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32i TARGET_SIM=emu-rv32i variant ``` +- Run RV32IMC compliance tests. +Assume `emu-rv32i` in `$PATH` environment variable. +```shell +$ git clone https://github.com/riscv/riscv-compliance +$ cd riscv-compliance +$ make RISCV_PREFIX=riscv-none-embed- RISCV_DEVICE=rv32imc TARGET_SIM=emu-rv32i variant +``` Compiling and running simple code: ```shell @@ -38,15 +48,7 @@ Hello RISC-V! - RV32M and RV32A instructions may be enabled by commenting `#define STRICT_RV32I`. - -Passed RV32C compliance tests from https://github.com/riscv/riscv-compliance -```shell -make C-ADDI.log -``` -If there is no accident, it will output the `TEST PASSED` - - -- RV32C instructions can be enabled by commenting `#define RV32C` +- RV32C instructions can be enabled by uncommenting `#define RV32C` ## How to build RISC-V toolchain from scratch https://github.com/riscv/riscv-gnu-toolchain From 6672f8d93a460b03d9a1e02e86cbecaeaa90cfe0 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Sun, 12 Jan 2020 04:01:45 +0800 Subject: [PATCH 22/24] Make emu-rv32i be compatible to sysprog21 --- Makefile | 2 +- emu-rv32i.c | 280 +++++++++++++++++++++++++++++++++++++++------------- 2 files changed, 213 insertions(+), 69 deletions(-) diff --git a/Makefile b/Makefile index 381d946..f5fd166 100644 --- a/Makefile +++ b/Makefile @@ -40,7 +40,7 @@ test1: test1.c $(CROSS_COMPILE)gcc $(RV32I_CFLAGS) -o $@ $< check: $(BINS) - ./emu-rv32i test1 + ./emu-rv32i --elf test1 clean: $(RM) $(BINS) diff --git a/emu-rv32i.c b/emu-rv32i.c index 9ca412a..c65b6e2 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -74,8 +74,8 @@ original copyright: #include #include /* uncomment this for an instruction trace and other debug outputs */ -// #define DEBUG_OUTPUT -// #define DEBUG_EXTRA +#define DEBUG_OUTPUT +#define DEBUG_EXTRA #define STRICT_RV32I #define FALSE (0) @@ -206,6 +206,9 @@ uint64_t mtimecmp; /* virtual start address for index 0 in the ram array */ uint32_t ram_start; +/* Program entry point */ +uint32_t start; + /* last byte of the memory initialized and temporary value */ uint32_t ram_last = 0; uint32_t ram_curr = 0; @@ -806,13 +809,19 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) if(pc+3 > maxmemr) maxmemr = pc+3; #endif uint32_t ptr = pc - ram_start; - if (ptr > RAM_SIZE) return 1; + if (ptr > RAM_SIZE) { + *insn = 0; + return 1; + } uint8_t* p = ram + ptr; -#ifdef DEBUG_OUTPUT - printf("address %08x\n", p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24)); -#endif #ifdef RV32C - if((p[0] & 0x03) < 3){ + uint8_t hb, lb; + uint16_t temp; + hb = p[1]; + lb = p[0]; + temp = (hb << 8) | lb; + printf("%04x\n", temp); + if( temp != 0 && (lb & 0x03) < 3){ *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } @@ -1977,7 +1986,7 @@ void execute_instruction() switch(midpart){ case 0: #ifdef DEBUG_EXTRA - dprintf(">>> Illegal instruction\n"); + debug_out(">>> Illegal instruction\n"); stats[64+0]++; break; dprintf(">>> C.ADDI4SPN\n"); @@ -1998,26 +2007,165 @@ void execute_instruction() break; } break; + case 1: /* C.FLD, C.LQ*/ + { + switch(XLEN){ + case 32: + case 64: /* C.FLD */ +#ifdef DEBUG_EXTRA + debug_out("C.FLD\n"); + printf("Not support to floating load double"); + stats[64+2]++; +#endif +#ifdef DEBUG_OUTPUT +#endif + rd = 0; + break; + case 128: /* C.LQ*/ +#ifdef DEBUG_EXTRA + debug_out("C.LQ\n"); + printf("Unimp insn\b"); + stats[64+3]++; +#endif +#ifdef DEBUG_OUTPUT +#endif + rd = 0; + break; + } + } + break; + case 2: /* C.LW */ + { +#ifdef DEBUG_EXTRA + debug_out(">>>C.LW\n"); + stats[64+4]++; +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rd = (midpart & 0x7) + 8; + imm = (midpart >> 4) & 0x1 | + (midpart >> 7) & 0xe | + (midpart << 1) & 0x10; + imm = (imm << 2) & 0x7f; + addr = reg[rs1] + imm; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t)rval; + +#ifdef DEBUG_OUTPUT + printf("rs1 : %d, rd: %d, imm: %d\n", rs1, rd, imm); + printf("addr: %08x\n", addr); +#endif + } + break; + case 3: /* C.FLW C.LD*/ + { + switch(XLEN){ + case 64: +#ifdef DEBUG_EXTRA + debug_out(">>> C.FLW\n"); + stats[64+5]++; +#endif +#ifdef DEBUG_OUTPUT + debug_out("Unimp insn for rv64c\n"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + debug_out(">>> C.LD\n"); + stats[64+6]++; +#endif +#ifdef DEBUG_OUTPUT + debug_out("Unimp insn for rv128c\n"); +#endif + break; + } + } + break; + case 4: /* Reserved */ +#ifdef DEBUG_EXTRA + debug_out(">>> Reserved_0\n"); + stats[64+7]++; +#endif + break; + case 5: /* C.FSD */ + { + switch(XLEN){ + case 32: + case 64: +#ifdef DEBUG_EXTRA + debug_out(">>> C.FSD\n"); + stats[64+8]++; +#endif +#ifdef DEBUG_OUTPUT + debug_out("Unimp insn for rv32imc"); +#endif + break; + case 128: +#ifdef DEBUG_EXTRA + debug_out(">>> C.SQ\n"); + stats[64+9]++; +#endif +#ifdef DEBUG_OUTPUT + debug_out("Unimp insn for rv32imc"); +#endif + break; + default: +#ifdef DEBUG_OUTPUT + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; +#endif + break; + } + } + break; + case 6: + { +#ifdef DEBUG_EXTRA + debug_out(">>> C.SW\n"); + stats[64+10]++; +#endif + rs1 = ((midpart >> 5) & 0x7) + 8; + rs2 = (midpart & 0x7) + 8; + imm = ((midpart >> 4) & 0x1) | + ((midpart >> 7) & 0xe) | + ((midpart << 1) & 0x10); + imm = (imm << 2) & 0x7f; + addr = reg[rs1] + imm; + val = reg[rs2]; + rd = 0; + if (target_write_u32(addr, val)) { + raise_exception(pending_exception, pending_tval); + return; + } +#ifdef DEBUG_OUTPUT + printf("rs1 : %d, rs2: %d, rd: %d, imm: %d\n", rs1, rs2, rd, imm); + printf("addr: %08x\n", addr); +#endif + } + break; case 7: { switch(XLEN){ case 32: #ifdef DEBUG_EXTRA - dprintf(">>> C.FSW\n"); + debug_out(">>> C.FSW\n"); stats[64+11]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unimp insn for rv32imc"); + debug_out("Unimp insn for rv32imc"); #endif break; case 64: case 128: #ifdef DEBUG_EXTRA - dprintf(">>> C.SD\n"); + debug_out(">>> C.SD\n"); stats[64+12]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn by rv32imc\n"); + debug_out("Unsupported insn by rv32imc\n"); #endif break; } @@ -2040,7 +2188,7 @@ void execute_instruction() case 0: /* C.NOP, C.ADDI */ if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ #ifdef DEBUG_EXTRA - dprintf(">>> C.NOP\n"); + debug_out(">>> C.NOP\n"); stats[64+13]++; #endif return; @@ -2049,7 +2197,7 @@ void execute_instruction() imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; #ifdef DEBUG_EXTRA - dprintf(">>> C.ADDI\n"); + debug_out(">>> C.ADDI\n"); stats[64+14]++; printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); #endif @@ -2058,16 +2206,16 @@ void execute_instruction() #ifdef DEBUG_EXTRA switch(XLEN){ case 32: - dprintf(">>> C.JAL\n"); + debug_out(">>> C.JAL\n"); stats[64+15]++; break; case 64: case 128: - dprintf(">>> C.ADDIW\n"); + debug_out(">>> C.ADDIW\n"); stats[64+16]++; break; default: - dprintf(">>> Unknow XLEN\n"); + debug_out(">>> Unknow XLEN\n"); break; } #endif @@ -2100,7 +2248,7 @@ void execute_instruction() break; case 2: /* C.LI */ #ifdef DEBUG_EXTRA - dprintf(">>> C.LI\n"); + debug_out(">>> C.LI\n"); stats[64+17]++; #endif rs1 = rd = ((midpart >> 5) & 0x1f); @@ -2113,11 +2261,11 @@ void execute_instruction() #ifdef DEBUG_EXTRA switch(rd){ case 2: - dprintf(">>> C.ADDI16SP\n"); + debug_out(">>> C.ADDI16SP\n"); stats[64+18]++; break; default: - dprintf(">>> C.LUI\n"); + debug_out(">>> C.LUI\n"); stats[64+19]++; break; } @@ -2159,11 +2307,11 @@ void execute_instruction() switch(XLEN){ case 32: case 64: - dprintf(">>> C.SRLI\n"); + debug_out(">>> C.SRLI\n"); stats[64+20]++; break; case 128: - dprintf(">>> C.SRLI64\n"); + debug_out(">>> C.SRLI64\n"); stats[64+21]++; break; } @@ -2196,11 +2344,11 @@ void execute_instruction() switch(XLEN){ case 32: case 64: - dprintf(">>> C.SRAI\n"); + debug_out(">>> C.SRAI\n"); stats[64+22]++; break; case 128: - dprintf(">>> C.SRAI64\n"); + debug_out(">>> C.SRAI64\n"); stats[64+23]++; break; } @@ -2230,7 +2378,7 @@ void execute_instruction() break; case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA - dprintf(">>> C.ANDI\n"); + debug_out(">>> C.ANDI\n"); stats[64+24]++; #endif rs1 = rd = ((midpart >> 5) & 0x7) + 8; @@ -2245,21 +2393,21 @@ void execute_instruction() switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ case 0: /* C.SUB */ #ifdef DEBUG_EXTRA - dprintf(">>> C.SUB\n"); + debug_out(">>> C.SUB\n"); stats[64+25]++; #endif val = reg[rd] - reg[rs2]; break; case 1: /* C.XOR */ #ifdef DEBUG_EXTRA - dprintf(">>> C.XOR\n"); + debug_out(">>> C.XOR\n"); stats[64+26]++; #endif val = reg[rd] ^ reg[rs2]; break; case 2: /* C.OR */ #ifdef DEBUG_EXTRA - dprintf(">>> C.OR\n"); + debug_out(">>> C.OR\n"); stats[64+27]++; #endif val = reg[rd] | reg[rs2]; @@ -2267,14 +2415,14 @@ void execute_instruction() break; case 3: /* C.AND */ #ifdef DEBUG_EXTRA - dprintf(">>> C.AND\n"); + debug_out(">>> C.AND\n"); stats[64+28]++; #endif val = reg[rd] & reg[rs2]; break; case 4: /* C.SUBW */ #ifdef DEBUG_EXTRA - dprintf(">>> C.SUBW\n"); + debug_out(">>> C.SUBW\n"); stats[64+29]++; #endif val = reg[rd] - reg[rs2]; @@ -2288,7 +2436,7 @@ void execute_instruction() break; case 5: /* C.ADDW */ #ifdef DEBUG_EXTRA - dprintf(">>> C.ADDW\n"); + debug_out(">>> C.ADDW\n"); stats[64+30]++; #endif val = reg[rd] + reg[rs2]; @@ -2302,12 +2450,12 @@ void execute_instruction() break; case 6: #ifdef DEBUG_EXTRA - dprintf(">>> Reserved_1\n"); + debug_out(">>> Reserved_1\n"); stats[64+31]++; #endif case 7: #ifdef DEBUG_EXTRA - dprintf(">>> Reserved_2\n"); + debug_out(">>> Reserved_2\n"); stats[64+32]++; #endif /* NOP */ @@ -2317,7 +2465,7 @@ void execute_instruction() break; case 5: /* C.J */ #ifdef DEBUG_EXTRA - dprintf(">>> C.J\n"); + debug_out(">>> C.J\n"); stats[64+33]++; #endif rd = 0; @@ -2337,7 +2485,7 @@ void execute_instruction() break; case 6: /* C.BEQZ */ #ifdef DEBUG_EXTRA - dprintf(">>> C.BEQZ\n"); + debug_out(">>> C.BEQZ\n"); stats[64+34]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; @@ -2357,7 +2505,7 @@ void execute_instruction() break; case 7: /* C.BNEZ */ #ifdef DEBUG_EXTRA - dprintf(">>> C.BNEZ\n"); + debug_out(">>> C.BNEZ\n"); stats[64+35]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; @@ -2401,7 +2549,7 @@ void execute_instruction() } case 64: #ifdef DEBUG_EXTRA - dprintf(">>> C.SLLI\n"); + debug_out(">>> C.SLLI\n"); stats[64+36]++; #endif if(imm == 0){ @@ -2417,7 +2565,7 @@ void execute_instruction() break; case 128: /* C.SLLI64 */ #ifdef DEBUG_EXTRA - dprintf(">>> C.SLLI64\n"); + debug_out(">>> C.SLLI64\n"); stats[64+37]++; #endif rd = ((midpart >> 5) & 0x1f); @@ -2428,7 +2576,7 @@ void execute_instruction() imm = 64; #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn by rv32imc\n"); + debug_out("Unsupported insn by rv32imc\n"); #endif break; } @@ -2442,20 +2590,20 @@ void execute_instruction() case 32: case 64: /* C.FLDSP */ #ifdef DEBUG_EXTRA - dprintf(">>> C.FLDSP\n");\ + debug_out(">>> C.FLDSP\n");\ stats[64+38]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported extension by rv32imc"); + debug_out("Unsupported extension by rv32imc"); #endif break; case 128: #ifdef DEBUG_EXTRA - dprintf(">>> C.LQSP\n"); + debug_out(">>> C.LQSP\n"); stats[64+39]++; #endif #ifdef DEBUG_OUTPUT - dprintf("unsupported extension by rv32imc"); + debug_out("unsupported extension by rv32imc"); #endif break; } @@ -2465,7 +2613,7 @@ void execute_instruction() case 2: /* C.LWSP C.FLWSP*/ { #ifdef DEBUG_EXTRA - dprintf(">>> C.LWSP\n"); + debug_out(">>> C.LWSP\n"); stats[64+40]++; #endif rd = ((midpart >> 5) & 0x1f); @@ -2495,20 +2643,20 @@ void execute_instruction() case 32: case 64: /* C.FLWSP */ #ifdef DEBUG_EXTRA - dprintf(">>> C.FLWSP\n"); + debug_out(">>> C.FLWSP\n"); stats[64+41]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported extension by rv32imc"); + debug_out("Unsupported extension by rv32imc"); #endif break; case 128: #ifdef DEBUG_EXTRA - dprintf(">>> C.LDSP\n"); + debug_out(">>> C.LDSP\n"); stats[64+42]++; #endif #ifdef DEBUG_OUTPUT - dprintf("unsupported extension by rv32imc"); + debug_out("unsupported extension by rv32imc"); #endif break; } @@ -2524,7 +2672,7 @@ void execute_instruction() case 0: if(rs2 == 0){ /* C.JR */ #ifdef DEBUG_EXTRA - dprintf(">>> C.JR\n"); + debug_out(">>> C.JR\n"); stats[64+43]++; #endif next_pc = reg[rs1]; @@ -2537,7 +2685,7 @@ void execute_instruction() #endif }else{ /* C.MV */ #ifdef DEBUG_EXTRA - dprintf(">>> C.MV\n"); + debug_out(">>> C.MV\n"); stats[64+44]++; #endif rd = rs1; @@ -2551,14 +2699,14 @@ void execute_instruction() case 1: if(rs1 == 0 && rs2 == 0){ /* C.EBREAK */ #ifdef DEBUG_EXTRA - dprintf(">>> EBREAK\n"); + debug_out(">>> EBREAK\n"); stats[64+45]++; #endif raise_exception(CAUSE_BREAKPOINT, 0); return; }else if(rs2 == 0 && rs1 != 0){ /* C.JALR */ #ifdef DEBUG_EXTRA - dprintf(">>> C.JALR\n"); + debug_out(">>> C.JALR\n"); stats[64+46]++; #endif rd = 1; @@ -2585,20 +2733,20 @@ void execute_instruction() case 32: case 64: #ifdef DEBUG_EXTRA - dprintf(">>> C.FSDS{\n"); + debug_out(">>> C.FSDS{\n"); stats[64+47]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); + debug_out("Unsupported insn of rv32imc\n"); #endif break; case 128: #ifdef DEBUG_EXTRA - dprintf(">>> C.SQSP\n"); + debug_out(">>> C.SQSP\n"); stats[64+48]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); + debug_out("Unsupported insn of rv32imc\n"); #endif break; } @@ -2607,7 +2755,7 @@ void execute_instruction() case 6: /* C.SWSP*/ { #ifdef DEBUG_EXTRA - dprintf(">>> C.SWSP\n"); + debug_out(">>> C.SWSP\n"); stats[64+49]++; #endif rd = 0; @@ -2632,21 +2780,21 @@ void execute_instruction() switch(XLEN){ case 32: #ifdef DEBUG_EXTRA - dprintf(">>> C.FSWSP\n"); + debug_out(">>> C.FSWSP\n"); stats[64+50]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); + debug_out("Unsupported insn of rv32imc\n"); #endif break; case 64: case 128: #ifdef DEBUG_EXTRA - dprintf(">>> C.SDSP\n"); + debug_out(">>> C.SDSP\n"); stats[64+51]++; #endif #ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); + debug_out("Unsupported insn of rv32imc\n"); #endif break; } @@ -3587,12 +3735,12 @@ int main(int argc, char **argv) /* for compliance test */ if (strcmp(name, "_start") == 0) { - ram_start = sym.st_value; + start = sym.st_value; } /* for zephyr */ if (strcmp(name, "__reset") == 0) { - ram_start = sym.st_value; + start = sym.st_value; } if (strcmp(name, "__irq_wrapper") == 0) { mtvec = sym.st_value; @@ -3600,13 +3748,9 @@ int main(int argc, char **argv) } } } -#ifdef DEBUG_OUTPUT - printf("begin_signature: 0x%08x\n", begin_signature); - printf("end_signature: 0x%08x\n", end_signature); - printf("start: 0x%08x\n", ram_start); -#endif /* scan for program */ + scn = NULL; while ((scn = elf_nextscn(elf, scn)) != NULL) { gelf_getshdr(scn, &shdr); if (shdr.sh_type == SHT_PROGBITS) { From 75a75dcf5d6bbfe1435539b41bec443b27aafffc Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Mon, 20 Jan 2020 21:53:45 +0800 Subject: [PATCH 23/24] Rework to a better style --- .gitignore | 3 + CSRs.h | 174 ++++++----- emu-rv32i.c | 842 ++++++++++++++++++++++++++-------------------------- test1.c | 4 +- 4 files changed, 525 insertions(+), 498 deletions(-) diff --git a/.gitignore b/.gitignore index 64dda3f..e9dd2da 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,6 @@ sig.txt rom.v debug.txt CSR.h +# ignore generated files +work +*.mem diff --git a/CSRs.h b/CSRs.h index 32daaee..4c9f99b 100644 --- a/CSRs.h +++ b/CSRs.h @@ -1,91 +1,109 @@ -/* Modified by Nober - 13-DEC-2019 - Define all CSR macro -*/ - -/* -RISCV emulator for the RV32I architecture -based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ -stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test -by Frank Buss, 2018 - -Requires libelf-dev: - -sudo apt-get install libelf-dev - - -Compile it like this: - -gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i - - -It is compatible to Spike for the command line arguments, which means you can run -the compliance test from https://github.com/riscv/riscv-compliance like this: - -make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant - -It is also compatible with qemu32, as it is used for Zephyr. You can compile the -Zephyr examples for qemu like this: - -cd zephyr -source zephyr-env.sh -cd samples/synchronization -mkdir build && cd build -cmake -GNinja -DBOARD=qemu_riscv32 .. -ninja - -After this you can run it with the emulator like this: - -emu-rv32i zephyr/zephyr.elf - +#include -original copyright: -*/ +// ====================================================== // +// =================== User Trap Setup ================== // +// ====================================================== // +uint32_t ustatus; /* User status register */ +uint32_t uie; /* User interrupt-enable register */ +uint32_t utvec; /* User trap handler base address */ +// ====================================================== // +// ================= User Trap Handling ================= // +// ====================================================== // +uint32_t uscratch; /* Scratch register for user trap handlers*/ +uint32_t uepc; /* User exception program counter */ +uint32_t ucause; /* User trap cause*/ +uint32_t ubadaddr; /* User bad address */ +uint32_t uip; /* User interrupt pending */ +// ====================================================== // +// ============== User Floating-Point CSRs ============== // +// ====================================================== // +uint32_t fflags; /* Floating-Point Accrued Exceptions*/ +uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ +uint32_t fcsr; /* Floating-Point Control and Status Register (frm + fflags )*/ +// ====================================================== // +// ================ User Counter / TImers =============== // +// ====================================================== // +uint32_t cycle; /* Cycle counter for RDCYCLE instruction */ +uint32_t time; /* Timer for RDTIME instruction */ +uint32_t instret; /* Instructions-retired counter for RDINSTRET instructions*/ +uint32_t cycleh; /* Upper 32 bits of cycle, RV32I only. */ +uint32_t timeh; /* Upper 32 bits of time, RV32I only. */ +// ====================================================== // +// ================ Supervior Trap Setup ================ // +// ====================================================== // +uint32_t sstatus; /* Supervisor status register */ +uint32_t sedeleg; /* Supervisor exception delegation register */ +uint32_t sideleg; /* Supervisor interrupt delegation register */ +uint32_t sie; /* Supervisor interrupt-enable register*/ +uint32_t stvec; /* Supervisor trap handler base address */ +// ====================================================== // +// ============== Supervisor Trap Handling ============== // +// ====================================================== // +uint32_t sscratch; /* Scratch register for supervisor trap handlers */ +uint32_t sepc; /* Supervisor exception program counter */ +uint32_t scause; /* Supervisor trap cause */ +uint32_t sbadaddr; /* Supervisor bad address */ +uint32_t sip; /* Supervisor interrupt pending */ +// ====================================================== // +// ======== Supervisor Protection and Translation ======= // +// ====================================================== // +uint32_t sptbr; /* Page-table base register */ -/* - * RISCV emulator - * - * Copyright (c) 2016 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. - */ -#include +// ====================================================== // +// ================ Hypervisor Trap Setup =============== // +// ====================================================== // +uint32_t hstatus; /* Hypervisor status register */ +uint32_t hedeleg; /* Hypervisor exception delegation register */ +uint32_t hideleg; /* Hyperbisor interrupt delegation register */ +uint32_t hie; /* Hypervisor interrupt-enable register */ +uint32_t htvec; /* Hypervisor trap handler base address */ +// ====================================================== // +// ============== Hypervisor Trap Handling ============== // +// ====================================================== // +uint32_t hscratch; /* Scratch register for hypervisor trap handlers */ +uint32_t hepc; /* Hypervisor exception program counter */ +uint32_t hcause; /* Hypervisor trap cause */ +uint32_t hbadaddr; /* Hypervisor bad address */ +uint32_t hip; /* Hypervisor interrupt pending */ +// ====================================================== // +// ======== Hypervisor Protection and Translation ======= // +// ====================================================== // +// uint32_t TBD; /* TBD */ // ====================================================== // -// =================== User Trap Setup ================== // +// ============ Machine Information Register ============ // // ====================================================== // -uint32_t ustatus; /* User status register */ -uint32_t uie; /* User interrupt-enable register */ -uint32_t utvec; /* User trap handler base address */ +uint32_t mvendorid; /* Vendor ID*/ +uint32_t marchid; /* Architecture ID */ +uint32_t mimpid; /* Implementation ID */ +uint32_t mhartid; /* Hardware thread ID */ // ====================================================== // -// ================= User Trap Handling ================= // +// ================= Machine Trap Setup ================= // // ====================================================== // -uint32_t uscratch; /* Scratch register for user trap handlers*/ -uint32_t uepc; /* User exception program counter */ -uint32_t ucause; /* User trap cause*/ -uint32_t ubadaddr; /* User bad address */ -uint32_t uip; /* User interrupt pending */ +uint32_t mstatus; /* Machine status register */ +uint32_t misa; /* ISA and extensions */ +uint32_t medeleg; /* Machine exception delegation register */ +uint32_t mideleg; /* Machine interrupt delegation register */ +uint32_t mie; /* Machine interrupt-enable register */ +uint32_t mtvec; /* Machine trap-handler base address */ // ====================================================== // -// ============== User Floating-Point CSRs ============== // +// ================ Machine Trap Handling =============== // +// ====================================================== // +uint32_t mscratch; /* Scratch register for machine trap handlers */ +uint32_t mepc; /* Machine exception program counter */ +uint32_t mcause; /* Machine trap cause */ +uint32_t mbadaddr; /* Machine bad address */ +uint32_t mip; /* Machine interrupt pending */ +// ====================================================== // +// ========= Machine Protextion and Translation ========= // // ====================================================== // -uint32_t fflags; /* Floating-Point Accrued Exceptions*/ -uint32_t frm; /* Floating-Point Dynamic Rounding Mode*/ +uint32_t mbase; /* Base regsiter */ +uint32_t mbound; /* Bound register */ +uint32_t mibase; /* Instruction base register */ +uint32_t mibound; /* Instruction bound register */ +uint32_t mdbase; /* Data base register */ +uint32_t mdbound; /* Data bound register */ diff --git a/emu-rv32i.c b/emu-rv32i.c index c65b6e2..4e574c8 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1,38 +1,3 @@ -/* Modified by Shaos - 24-DEC-2018 - Find top 5 instructions in DEBUG_EXTRA mode - 20-DEC-2018 - More statistical points - 22-NOV-2018 - Added saving HEX file with copy of the code in DEBUG_OUTPUT mode - 21-NOV-2018 - Some statistics added in DEBUG_EXTRA mode - 20-NOV-2018 - By default RV32M and RV32A extensions are disabled (STRICT_RV32I) - 18-NOV-2018 - Slghtly modified for pure C - Source code taken from https://gist.github.com/FrankBuss/c974e59826d33e21d7cad54491ab50e8 -*/ - -/* -RISCV emulator for the RV32I architecture -based on TinyEMU by Fabrice Bellard, see https://bellard.org/tinyemu/ -stripped down for RV32I only, all "gotos" removed, and fixed some bugs for the compliance test -by Frank Buss, 2018 -Requires libelf-dev: -sudo apt-get install libelf-dev -Compile it like this: -gcc -O3 -Wall -lelf emu-rv32i.c -o emu-rv32i -It is compatible to Spike for the command line arguments, which means you can run -the compliance test from https://github.com/riscv/riscv-compliance like this: -make RISCV_TARGET=spike RISCV_DEVICE=rv32i TARGET_SIM=/full/path/emulator variant -It is also compatible with qemu32, as it is used for Zephyr. You can compile the -Zephyr examples for qemu like this: -cd zephyr -source zephyr-env.sh -cd samples/synchronization -mkdir build && cd build -cmake -GNinja -DBOARD=qemu_riscv32 .. -ninja -After this you can run it with the emulator like this: -emu-rv32i zephyr/zephyr.elf -original copyright: -*/ - /* * RISCV emulator * @@ -63,6 +28,10 @@ original copyright: #include #include #include +#include +#include +#include +#include #include #include #include @@ -72,11 +41,10 @@ original copyright: #include #include #include -#include -/* uncomment this for an instruction trace and other debug outputs */ -#define DEBUG_OUTPUT -#define DEBUG_EXTRA +// #define DEBUG_OUTPUT + +/* added by Shaos: */ #define STRICT_RV32I #define FALSE (0) #define TRUE (-1) @@ -85,101 +53,106 @@ original copyright: uint32_t minmemr,maxmemr,minmemw,maxmemw; -#define STATS_NUM 64 - +#if defined(RV32C) #define C_STATS_NUM 64 - -#ifndef RV32C -unsigned int stats[STATS_NUM], c_stats[C_STATS_NUM],top[5],itop[5]; -char statnames[64][16] = { "LUI","AUIPC","JAL","JALR","BEQ","BNE","BLT","BGE", - "BLTU","BGEU","LB","LH","LW","LBU","LHU","SB","SH","SW","ADDI","SLTI","SLTIU", - "XORI","ORI","ANDI","SLLI","SRLI","SRAI","ADD","SUB","SLL","SLT","SLTU","XOR", - "SRL","SRA","OR","AND","FENCE","FENCE.I","ECALL","EBREAK","CSRRW","CSRRS", - "CSRRC","CSRRWI","CSRRSI","CSRRCI","LI*","MUL","MULH","MULHSU","MULHU","DIV", - "DIVU","REM","REMU","LR.W","SC.W","URET","SRET","MRET","WFI","SFENCE.VMA","" -}; +#else +#define C_STATS_NUM 0 + +unsigned int stats[STATS_NUM + C_STATS_NUM], top[5], itop[5]; +char statnames[STATS_NUM + C_STATS_NUM][16] = { + "LUI", "AUIPC", "JAL", "JALR", "BEQ", "BNE", + "BLT", "BGE", "BLTU", "BGEU", "LB", "LH", + "LW", "LBU", "LHU", "SB", "SH", "SW", + "ADDI", "SLTI", "SLTIU", "XORI", "ORI", "ANDI", + "SLLI", "SRLI", "SRAI", "ADD", "SUB", "SLL", + "SLT", "SLTU", "XOR", "SRL", "SRA", "OR", + "AND", "FENCE", "FENCE.I", "ECALL", "EBREAK", "CSRRW", + "CSRRS", "CSRRC", "CSRRWI", "CSRRSI", "CSRRCI", "LI*", + "MUL", "MULH", "MULHSU", "MULHU", "DIV", "DIVU", + "REM", "REMU", "LR.W", "SC.W", "URET", "SRET", + "MRET", "WFI", "SFENCE.VMA", "", +#if defined(RV32C) + "ILLINSN", "C.ADDI4SPN", "C.FLD", "C.LQ", "C.LW", "C.FLW", + "C.LD", "Reserved_0", "C.FSD", "C.SQ", "C.SW", "C.FSW", + "C.SD", "C.NOP", "C.ADDI", "C.JAL", "C.ADDIW", "C.LI", + "C.ADDI16SP", "C.LUI", "C.SRLI", "C.SRLI64", "C.SRAI", "C.SRAI64", + "C.ANDI", "C.SUB", "C.XOR", "C.OR", "C.AND", "C.SUBW", + "C.ADDW", "Reserved_1", "Reserved_2", "C.J", "C.BEQZ", "C.BNEZ", + "C.SLLI", "C.SLLI64", "C.FLDSP", "C.LQSP", "C.LWSP", "C.FLWSP", + "C.LDSP", "C.JR", "C.MV", "C.EBREAK", "C.JALR", "C.ADD", + "C.FSDSP", "C.SQSP", "C.SWSP", "C.FSWSP", "C.SDSP", "", + "", "", "", "", "", "", + "", "", "", "" #endif - -#ifdef RV32C -unsigned int stats[STATS_NUM + C_STATS_NUM],top[5],itop[5]; -char statnames[STATS_NUM + C_STATS_NUM][16] = -{ "LUI","AUIPC","JAL","JALR","BEQ","BNE","BLT","BGE", - "BLTU","BGEU","LB","LH","LW","LBU","LHU","SB","SH","SW","ADDI","SLTI","SLTIU", - "XORI","ORI","ANDI","SLLI","SRLI","SRAI","ADD","SUB","SLL","SLT","SLTU","XOR", - "SRL","SRA","OR","AND","FENCE","FENCE.I","ECALL","EBREAK","CSRRW","CSRRS", - "CSRRC","CSRRWI","CSRRSI","CSRRCI","LI*","MUL","MULH","MULHSU","MULHU","DIV", - "DIVU","REM","REMU","LR.W","SC.W","URET","SRET","MRET","WFI","SFENCE.VMA","", - "ILLINSN", "C.ADDI4SPN", "C.FLD", "C.LQ", "C.LW", - "C.FLW", "C.LD", "Reserved_0", "C.FSD", "C.SQ", "C.SW", "C.FSW", "C.SD", "C.NOP", "C.ADDI", - "C.JAL", "C.ADDIW", "C.LI", "C.ADDI16SP", "C.LUI", "C.SRLI", "C.SRLI64", "C.SRAI", - "C.SRAI64", "C.ANDI", "C.SUB", "C.XOR", "C.OR", "C.AND", "C.SUBW", "C.ADDW", "Reserved_1", - "Reserved_2", "C.J", "C.BEQZ", "C.BNEZ", "C.SLLI", "C.SLLI64", "C.FLDSP", "C.LQSP", - "C.LWSP", "C.FLWSP", "C.LDSP", "C.JR", "C.MV", "C.EBREAK", "C.JALR", "C.ADD", "C.FSDSP", - "C.SQSP", "C.SWSP", "C.FSWSP", "C.SDSP", "", "", "", "", "", "", "", "", "", "", "" }; -#endif void init_stats(void) { - for(int i=0;itop[0]) - { - top[4]=top[3];itop[4]=itop[3]; - top[3]=top[2];itop[3]=itop[2]; - top[2]=top[1];itop[2]=itop[1]; - top[1]=top[0];itop[1]=itop[0]; - top[0]=stats[i];itop[0]=i; - } - else if(stats[i]>top[1]) - { - top[4]=top[3];itop[4]=itop[3]; - top[3]=top[2];itop[3]=itop[2]; - top[2]=top[1];itop[2]=itop[1]; - top[1]=stats[i];itop[1]=i; - } - else if(stats[i]>top[2]) - { - top[4]=top[3];itop[4]=itop[3]; - top[3]=top[2];itop[3]=itop[2]; - top[2]=stats[i];itop[2]=i; - } - else if(stats[i]>top[3]) - { - top[4]=top[3];itop[4]=itop[3]; - top[3]=stats[i];itop[3]=i; - } - else if(stats[i]>top[4]) - { - top[4]=stats[i];itop[4]=i; - } - if(stats[i]) - { - if(i top[0]) { + top[4] = top[3]; + itop[4] = itop[3]; + top[3] = top[2]; + itop[3] = itop[2]; + top[2] = top[1]; + itop[2] = itop[1]; + top[1] = top[0]; + itop[1] = itop[0]; + top[0] = stats[i]; + itop[0] = i; + } else if (stats[i] > top[1]) { + top[4] = top[3]; + itop[4] = itop[3]; + top[3] = top[2]; + itop[3] = itop[2]; + top[2] = top[1]; + itop[2] = itop[1]; + top[1] = stats[i]; + itop[1] = i; + } else if (stats[i] > top[2]) { + top[4] = top[3]; + itop[4] = itop[3]; + top[3] = top[2]; + itop[3] = itop[2]; + top[2] = stats[i]; + itop[2] = i; + } else if (stats[i] > top[3]) { + top[4] = top[3]; + itop[4] = itop[3]; + top[3] = stats[i]; + itop[3] = i; + } else if (stats[i] > top[4]) { + top[4] = stats[i]; + itop[4] = i; + } + if (stats[i]) { + if (i < STATS_NUM + C_STATS_NUM - 11) + printf("%s\t= %u\n", statnames[i], stats[i]); + else + printf("[%i] = %u\n", i, stats[i]); + } + } + printf("\nFive Most Frequent:\n"); + for (int j = 0; j < 5; j++) { + printf("%i) %s\t= %u (%2.2lf%%)\n", j + 1, statnames[itop[j]], top[j], + top[j] * 100.0 / (double) total); + } + printf("\nMemory Reading Area %x...%x\n", minmemr, maxmemr); + if (minmemw + 1) + printf("Memory Writing Area %x...%x\n", minmemw, maxmemw); + else + printf("Memory Writing Area NONE\n"); } #endif @@ -710,7 +683,7 @@ void raise_exception(uint32_t cause, uint32_t tval) return; } - switch(cause){ + switch (cause) { case CAUSE_MACHINE_ECALL: printf("Unimplement Machine ecall!\n"); return; @@ -813,15 +786,15 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) *insn = 0; return 1; } - uint8_t* p = ram + ptr; + uint8_t *p = ram + ptr; #ifdef RV32C uint8_t hb, lb; - uint16_t temp; + uint16_t temp; hb = p[1]; lb = p[0]; temp = (hb << 8) | lb; printf("%04x\n", temp); - if( temp != 0 && (lb & 0x03) < 3){ + if (temp != 0 && (lb & 0x03) < 3) { *insn = (p[0] | ((p[1] << 8) & 0x0000ffff)); return CINSN; } @@ -1119,7 +1092,7 @@ void execute_instruction() uint16_t midpart; - if(insn_type == INSN){ + if (insn_type == INSN) { opcode = insn & 0x7f; rd = (insn >> 7) & 0x1f; rs1 = (insn >> 15) & 0x1f; @@ -1127,7 +1100,7 @@ void execute_instruction() } #ifdef RV32C - if(insn_type == CINSN){ + if (insn_type == CINSN) { opcode = insn & 0x3; } #endif @@ -1981,69 +1954,69 @@ void execute_instruction() case 0: funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; - switch(funct3){ + switch (funct3) { case 0: /* Illegal instruction, C.ADDI4SPN */ - switch(midpart){ + switch (midpart) { case 0: #ifdef DEBUG_EXTRA debug_out(">>> Illegal instruction\n"); - stats[64+0]++; - break; - dprintf(">>> C.ADDI4SPN\n"); - stats[64+1]++; + stats[64 + 0]++; +#endif + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + default: +#ifdef DEBUG_EXTRA + debug_out(">>> C.ADDI4SPN\n"); + stats[64 + 1]++; #endif #ifdef DEBUG_OUTPUT printf("rd: %d, imm: %d\n", rd, imm); #endif rd = (midpart & 0x7) + 8; rs1 = 2; - imm = (midpart >> 4) & 0x1 | - (midpart >> 2) & 0x2 | - (midpart >> 7) & 0xe | - (midpart >> 1) & 0xf0; + imm = (midpart >> 4) & 0x1 | (midpart >> 2) & 0x2 | + (midpart >> 7) & 0xe | (midpart >> 1) & 0xf0; imm = imm << 2; imm = imm & 0x3ff; val = reg[rs1] + imm; break; } - break; + break; case 1: /* C.FLD, C.LQ*/ { - switch(XLEN){ + switch (XLEN) { case 32: case 64: /* C.FLD */ #ifdef DEBUG_EXTRA debug_out("C.FLD\n"); printf("Not support to floating load double"); - stats[64+2]++; + stats[64 + 2]++; #endif #ifdef DEBUG_OUTPUT #endif rd = 0; - break; + break; case 128: /* C.LQ*/ #ifdef DEBUG_EXTRA debug_out("C.LQ\n"); printf("Unimp insn\b"); - stats[64+3]++; + stats[64 + 3]++; #endif #ifdef DEBUG_OUTPUT #endif rd = 0; - break; + break; } - } - break; + } break; case 2: /* C.LW */ { #ifdef DEBUG_EXTRA - debug_out(">>>C.LW\n"); - stats[64+4]++; + debug_out(">>>C.LW\n"); + stats[64 + 4]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; - rd = (midpart & 0x7) + 8; - imm = (midpart >> 4) & 0x1 | - (midpart >> 7) & 0xe | + rd = (midpart & 0x7) + 8; + imm = (midpart >> 4) & 0x1 | (midpart >> 7) & 0xe | (midpart << 1) & 0x10; imm = (imm << 2) & 0x7f; addr = reg[rs1] + imm; @@ -2052,85 +2025,80 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int32_t)rval; + val = (int32_t) rval; #ifdef DEBUG_OUTPUT printf("rs1 : %d, rd: %d, imm: %d\n", rs1, rd, imm); printf("addr: %08x\n", addr); #endif - } - break; + } break; case 3: /* C.FLW C.LD*/ { - switch(XLEN){ + switch (XLEN) { case 64: #ifdef DEBUG_EXTRA - debug_out(">>> C.FLW\n"); - stats[64+5]++; + debug_out(">>> C.FLW\n"); + stats[64 + 5]++; #endif #ifdef DEBUG_OUTPUT - debug_out("Unimp insn for rv64c\n"); + debug_out("Unimp insn for rv64c\n"); #endif - break; + break; case 128: #ifdef DEBUG_EXTRA - debug_out(">>> C.LD\n"); - stats[64+6]++; + debug_out(">>> C.LD\n"); + stats[64 + 6]++; #endif #ifdef DEBUG_OUTPUT - debug_out("Unimp insn for rv128c\n"); + debug_out("Unimp insn for rv128c\n"); #endif - break; + break; } - } - break; + } break; case 4: /* Reserved */ #ifdef DEBUG_EXTRA debug_out(">>> Reserved_0\n"); - stats[64+7]++; + stats[64 + 7]++; #endif - break; + break; case 5: /* C.FSD */ { - switch(XLEN){ + switch (XLEN) { case 32: case 64: #ifdef DEBUG_EXTRA debug_out(">>> C.FSD\n"); - stats[64+8]++; + stats[64 + 8]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unimp insn for rv32imc"); #endif - break; + break; case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.SQ\n"); - stats[64+9]++; + stats[64 + 9]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unimp insn for rv32imc"); #endif - break; + break; default: #ifdef DEBUG_OUTPUT raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; #endif - break; + break; } - } - break; - case 6: - { + } break; + case 6: { #ifdef DEBUG_EXTRA debug_out(">>> C.SW\n"); - stats[64+10]++; + stats[64 + 10]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rs2 = (midpart & 0x7) + 8; - imm = ((midpart >> 4) & 0x1) | - ((midpart >> 7) & 0xe) | + imm = ((midpart >> 4) & 0x1) | ((midpart >> 7) & 0xe) | ((midpart << 1) & 0x10); imm = (imm << 2) & 0x7f; addr = reg[rs1] + imm; @@ -2144,104 +2112,98 @@ void execute_instruction() printf("rs1 : %d, rs2: %d, rd: %d, imm: %d\n", rs1, rs2, rd, imm); printf("addr: %08x\n", addr); #endif - } - break; - case 7: - { - switch(XLEN){ + } break; + case 7: { + switch (XLEN) { case 32: #ifdef DEBUG_EXTRA debug_out(">>> C.FSW\n"); - stats[64+11]++; + stats[64 + 11]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unimp insn for rv32imc"); #endif - break; + break; case 64: case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.SD\n"); - stats[64+12]++; + stats[64 + 12]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported insn by rv32imc\n"); #endif - break; + break; } - } - break; - default: - { + } break; + default: { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; + } break; } - break; - } - if(rd != 0) + if (rd != 0) reg[rd] = val; break; case 1: funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; - switch(funct3){ - case 0: /* C.NOP, C.ADDI */ - if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ + switch (funct3) { + case 0: /* C.NOP, C.ADDI */ + if (((midpart >> 5) & 0x1f) == 0) { /* C.NOP*/ #ifdef DEBUG_EXTRA debug_out(">>> C.NOP\n"); - stats[64+13]++; + stats[64 + 13]++; #endif return; } else { rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); + imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); val = reg[rs1] + imm; #ifdef DEBUG_EXTRA debug_out(">>> C.ADDI\n"); - stats[64+14]++; - printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); + stats[64 + 14]++; + printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, + rs1, imm, reg[rd], val); #endif - }break; + } + break; case 1: /* C.JAL, C.ADDIW */ #ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: - debug_out(">>> C.JAL\n"); - stats[64+15]++; - break; - case 64: - case 128: - debug_out(">>> C.ADDIW\n"); - stats[64+16]++; - break; - default: - debug_out(">>> Unknow XLEN\n"); - break; + switch (XLEN) { + case 32: + debug_out(">>> C.JAL\n"); + stats[64 + 15]++; + break; + case 64: + case 128: + debug_out(">>> C.ADDIW\n"); + stats[64 + 16]++; + break; + default: + debug_out(">>> Unknow XLEN\n"); + break; } #endif - switch(XLEN) { + switch (XLEN) { case 32: rd = 0; - imm = (midpart & 0x400) | - ((midpart << 3) & 0x200) | - (midpart & 0x180) | - ((midpart << 2) & 0x40) | - (midpart & 0x20) | - ((midpart << 4) & 0x10) | - ((midpart >> 6) & 0x8) | - ((midpart >> 1) & 0x7); + imm = (midpart & 0x400) | ((midpart << 3) & 0x200) | + (midpart & 0x180) | ((midpart << 2) & 0x40) | + (midpart & 0x20) | ((midpart << 4) & 0x10) | + ((midpart >> 6) & 0x8) | ((midpart >> 1) & 0x7); imm = (imm << 1) & 0xfffe; reg[1] = pc + 2; /* Store the link to x1 register */ next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; break; case 64: case 128: rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart >> (11 - 5)) | - (midpart & 0x1f); + imm = (midpart >> (11 - 5)) | (midpart & 0x1f); val = reg[rs1] + imm; break; } @@ -2249,7 +2211,7 @@ void execute_instruction() case 2: /* C.LI */ #ifdef DEBUG_EXTRA debug_out(">>> C.LI\n"); - stats[64+17]++; + stats[64 + 17]++; #endif rs1 = rd = ((midpart >> 5) & 0x1f); imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); @@ -2259,73 +2221,71 @@ void execute_instruction() case 3: /* C.ADDI16SP, C.LUI */ rs1 = rd = ((midpart >> 5) & 0x1f); #ifdef DEBUG_EXTRA - switch(rd){ + switch (rd) { case 2: debug_out(">>> C.ADDI16SP\n"); - stats[64+18]++; + stats[64 + 18]++; break; default: debug_out(">>> C.LUI\n"); - stats[64+19]++; + stats[64 + 19]++; break; } #endif - switch(rd){ /* C.ADDI16SP */ + switch (rd) { /* C.ADDI16SP */ case 2: - imm = ((midpart >> 4) & 0x1) | - ((midpart << 1) & 0x2) | - ((midpart >> 1) & 0x4) | - ((midpart << 2) & 0x18) | + imm = ((midpart >> 4) & 0x1) | ((midpart << 1) & 0x2) | + ((midpart >> 1) & 0x4) | ((midpart << 2) & 0x18) | ((midpart >> 5) & 0x20); - imm = (imm << 4 )<< (31 - 9) >> (31 - 9); + imm = (imm << 4) << (31 - 9) >> (31 - 9); val = reg[rd] + imm; break; default: imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); imm = (imm << 12); - if(imm == 0){ + if (imm == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if(rd != 0 && rd != 2){ + if (rd != 0 && rd != 2) { val = (reg[rd] & ~0x0003f000) | imm; val = val & 0xfffff000; val = (int32_t) val << (31 - 17) >> (31 - 17); - } - else{ + } else { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } break; } break; - case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ - switch(((midpart >> 8) & 0x3)){ + case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, + C.OR, C.AND, C.SUBW, C.ADDW*/ + switch (((midpart >> 8) & 0x3)) { case 0: /* C.SRLI C.SRLI64 */ #ifdef DEBUG_EXTRA - switch(XLEN){ + switch (XLEN) { case 32: case 64: debug_out(">>> C.SRLI\n"); - stats[64+20]++; + stats[64 + 20]++; break; case 128: debug_out(">>> C.SRLI64\n"); - stats[64+21]++; + stats[64 + 21]++; break; } #endif - switch(XLEN){ + switch (XLEN) { case 32: - if((midpart >> 10 & 0x1)){ + if ((midpart >> 10 & 0x1)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } case 64: rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = (midpart & 0x1f) | (midpart >> 5 & 0x20); - if(imm == 0){ + if (imm == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } @@ -2341,28 +2301,28 @@ void execute_instruction() break; case 1: /* C.SRAI C.SRAI64 */ #ifdef DEBUG_EXTRA - switch(XLEN){ + switch (XLEN) { case 32: case 64: debug_out(">>> C.SRAI\n"); - stats[64+22]++; + stats[64 + 22]++; break; case 128: debug_out(">>> C.SRAI64\n"); - stats[64+23]++; + stats[64 + 23]++; break; } #endif - switch(XLEN){ + switch (XLEN) { case 32: - if((midpart >> 10 & 0x1)){ + if ((midpart >> 10 & 0x1)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } case 64: rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = (midpart & 0x1f) | (midpart >> 5 & 0x20); - if(imm == 0){ + if (imm == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } @@ -2379,7 +2339,7 @@ void execute_instruction() case 2: /* C.ANDI */ #ifdef DEBUG_EXTRA debug_out(">>> C.ANDI\n"); - stats[64+24]++; + stats[64 + 24]++; #endif rs1 = rd = ((midpart >> 5) & 0x7) + 8; imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); @@ -2390,73 +2350,74 @@ void execute_instruction() case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ rs2 = (midpart & 0x7) + 8; rs1 = rd = ((midpart >> 5) & 0x7) + 8; - switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ + switch (((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4)) { case 0: /* C.SUB */ #ifdef DEBUG_EXTRA debug_out(">>> C.SUB\n"); - stats[64+25]++; + stats[64 + 25]++; #endif val = reg[rd] - reg[rs2]; break; case 1: /* C.XOR */ #ifdef DEBUG_EXTRA debug_out(">>> C.XOR\n"); - stats[64+26]++; + stats[64 + 26]++; #endif val = reg[rd] ^ reg[rs2]; break; case 2: /* C.OR */ #ifdef DEBUG_EXTRA debug_out(">>> C.OR\n"); - stats[64+27]++; + stats[64 + 27]++; #endif val = reg[rd] | reg[rs2]; - //printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); + // printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], + // reg[rs2]); break; case 3: /* C.AND */ #ifdef DEBUG_EXTRA debug_out(">>> C.AND\n"); - stats[64+28]++; + stats[64 + 28]++; #endif val = reg[rd] & reg[rs2]; break; case 4: /* C.SUBW */ #ifdef DEBUG_EXTRA debug_out(">>> C.SUBW\n"); - stats[64+29]++; + stats[64 + 29]++; #endif val = reg[rd] - reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ + if (XLEN == 128) { + val = (int32_t)(val << 96) >> 96; + } else if (XLEN == 64) { + val = (int32_t)(val << 32) >> 32; + } else { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); } break; case 5: /* C.ADDW */ #ifdef DEBUG_EXTRA debug_out(">>> C.ADDW\n"); - stats[64+30]++; + stats[64 + 30]++; #endif val = reg[rd] + reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ + if (XLEN == 128) { + val = (int32_t)(val << 96) >> 96; + } else if (XLEN == 64) { + val = (int32_t)(val << 32) >> 32; + } else { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); } break; case 6: #ifdef DEBUG_EXTRA debug_out(">>> Reserved_1\n"); - stats[64+31]++; + stats[64 + 31]++; #endif case 7: #ifdef DEBUG_EXTRA debug_out(">>> Reserved_2\n"); - stats[64+32]++; + stats[64 + 32]++; #endif /* NOP */ break; @@ -2466,110 +2427,111 @@ void execute_instruction() case 5: /* C.J */ #ifdef DEBUG_EXTRA debug_out(">>> C.J\n"); - stats[64+33]++; + stats[64 + 33]++; #endif rd = 0; - imm = ((midpart >> 1) & 0x7) | - ((midpart >> 6) & 0x8) | - ((midpart << 4) & 0x10) | - ((midpart) & 0x20) | - ((midpart << 2) & 0x40) | - ((midpart) & 0x180)| - ((midpart << 3) & 0x200)| - ((midpart) & 0x400); + imm = ((midpart >> 1) & 0x7) | ((midpart >> 6) & 0x8) | + ((midpart << 4) & 0x10) | ((midpart) &0x20) | + ((midpart << 2) & 0x40) | ((midpart) &0x180) | + ((midpart << 3) & 0x200) | ((midpart) &0x400); imm = (imm << 1) << 20 >> 20; next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; break; case 6: /* C.BEQZ */ #ifdef DEBUG_EXTRA debug_out(">>> C.BEQZ\n"); - stats[64+34]++; + stats[64 + 34]++; #endif rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; - if(reg[rs1] == 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 6) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | + if (reg[rs1] == 0) { + imm = ((midpart >> 1) & 0x3) | ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | ((midpart >> 3) & 0x80); imm = (imm << 1) << (31 - 8) >> (31 - 8); next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; } break; case 7: /* C.BNEZ */ #ifdef DEBUG_EXTRA debug_out(">>> C.BNEZ\n"); - stats[64+35]++; + stats[64 + 35]++; #endif - rs1 = ((midpart >> 5) & 0x7) + 8; + rs1 = ((midpart >> 5) & 0x7) + 8; rd = 0; - if(reg[rs1] != 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 6) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | + if (reg[rs1] != 0) { + imm = ((midpart >> 1) & 0x3) | ((midpart >> 6) & 0xc) | + ((midpart << 4) & 0x10) | ((midpart << 2) & 0x60) | ((midpart >> 3) & 0x80); imm = (imm << 1) << (31 - 8) >> (31 - 8); next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; } #ifdef DEBUG_OUTPUT - printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); + printf( + "rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: " + "%08x\n", + rd, rs1, imm, reg[rs1]); #endif break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if(rd != 0){ + if (rd != 0) { reg[rd] = val; } break; case 2: /* op 2*/ funct3 = (insn >> 13) & 0x7; midpart = (insn >> 2) & 0x07ff; - switch(funct3){ + switch (funct3) { case 0: /* C.SLLI, C.SLLI64*/ { imm = ((midpart >> 5 & 0x20) | (midpart & 0x1f)); - switch(XLEN){ + switch (XLEN) { case 32: /* C.SLLI*/ - if(((midpart >> 10) & 0x1)){ + if (((midpart >> 10) & 0x1)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } case 64: #ifdef DEBUG_EXTRA debug_out(">>> C.SLLI\n"); - stats[64+36]++; + stats[64 + 36]++; #endif - if(imm == 0){ + if (imm == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ + if (rd == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } imm = imm & 0x3f; - break; + break; case 128: /* C.SLLI64 */ #ifdef DEBUG_EXTRA debug_out(">>> C.SLLI64\n"); - stats[64+37]++; + stats[64 + 37]++; #endif rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ + if (rd == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } @@ -2578,190 +2540,186 @@ void execute_instruction() #ifdef DEBUG_OUTPUT debug_out("Unsupported insn by rv32imc\n"); #endif - break; + break; } - if(rd != 0) + if (rd != 0) val = (uint32_t) reg[rd] << imm; - } - break; + } break; case 1: /* C.FLDSP C.LQSP*/ { - switch(XLEN){ + switch (XLEN) { case 32: case 64: /* C.FLDSP */ #ifdef DEBUG_EXTRA - debug_out(">>> C.FLDSP\n");\ - stats[64+38]++; + debug_out(">>> C.FLDSP\n"); + stats[64 + 38]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported extension by rv32imc"); #endif - break; + break; case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.LQSP\n"); - stats[64+39]++; + stats[64 + 39]++; #endif #ifdef DEBUG_OUTPUT debug_out("unsupported extension by rv32imc"); #endif - break; + break; } - } - break; + } break; case 2: /* C.LWSP C.FLWSP*/ { #ifdef DEBUG_EXTRA - debug_out(">>> C.LWSP\n"); - stats[64+40]++; + debug_out(">>> C.LWSP\n"); + stats[64 + 40]++; #endif - rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - imm = ((midpart >> 2) & 0x7) | - ((midpart >> 7) & 0x8) | - ((midpart << 4) & 0x30); - imm = (imm << 2) & 0xff; - rs1 = 2; - addr = reg[rs1] + imm; - uint32_t rval; - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t)rval; + rd = ((midpart >> 5) & 0x1f); + if (rd == 0) { + raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); + return; + } + imm = ((midpart >> 2) & 0x7) | ((midpart >> 7) & 0x8) | + ((midpart << 4) & 0x30); + imm = (imm << 2) & 0xff; + rs1 = 2; + addr = reg[rs1] + imm; + uint32_t rval; + if (target_read_u32(&rval, addr)) { + raise_exception(pending_exception, pending_tval); + return; + } + val = (int32_t) rval; #ifdef DEBUG_OUTPUT #endif - } - break; + } break; case 3: /* C.FLWSP C.LDSP*/ { - switch(XLEN){ + switch (XLEN) { case 32: case 64: /* C.FLWSP */ #ifdef DEBUG_EXTRA debug_out(">>> C.FLWSP\n"); - stats[64+41]++; + stats[64 + 41]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported extension by rv32imc"); #endif - break; + break; case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.LDSP\n"); - stats[64+42]++; + stats[64 + 42]++; #endif #ifdef DEBUG_OUTPUT debug_out("unsupported extension by rv32imc"); #endif - break; + break; } - } - break; + } break; case 4: /* C.JR C.MV C.EBREAK C.JALR C.ADD */ { rd = 0; rs1 = (midpart >> 5) & 0x1f; rs2 = (midpart & 0x1f); - switch((midpart >> 10) & 0x1){ + switch ((midpart >> 10) & 0x1) { case 0: - if(rs2 == 0){ /* C.JR */ + if (rs2 == 0) { /* C.JR */ #ifdef DEBUG_EXTRA debug_out(">>> C.JR\n"); - stats[64+43]++; + stats[64 + 43]++; #endif next_pc = reg[rs1]; - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; #ifdef DEBUG_OUTPUT printf("rs1: %d, rs2: %d, rd: %d\n", rs1, rs2, rd); #endif - }else{ /* C.MV */ + } else { /* C.MV */ #ifdef DEBUG_EXTRA debug_out(">>> C.MV\n"); - stats[64+44]++; + stats[64 + 44]++; #endif rd = rs1; - if(rd + rs1 + rs2 == 0){ + if (rd + rs1 + rs2 == 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } val = reg[rs2]; } - break; + break; case 1: - if(rs1 == 0 && rs2 == 0){ /* C.EBREAK */ + if (rs1 == 0 && rs2 == 0) { /* C.EBREAK */ #ifdef DEBUG_EXTRA debug_out(">>> EBREAK\n"); - stats[64+45]++; + stats[64 + 45]++; #endif raise_exception(CAUSE_BREAKPOINT, 0); return; - }else if(rs2 == 0 && rs1 != 0){ /* C.JALR */ + } else if (rs2 == 0 && rs1 != 0) { /* C.JALR */ #ifdef DEBUG_EXTRA debug_out(">>> C.JALR\n"); - stats[64+46]++; + stats[64 + 46]++; #endif rd = 1; imm = reg[rs1]; next_pc = reg[rs1]; val = pc + 2; - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; - }else if(rs2 != 0 && rs1 != 0){ /* C.ADD */ + } else if (rs2 != 0 && rs1 != 0) { /* C.ADD */ rd = rs1; val = reg[rs1] + reg[rs2]; } - break; + break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } - break; + } break; case 5: /* C.FSDSP C.SQSP*/ { - switch(XLEN){ + switch (XLEN) { case 32: case 64: #ifdef DEBUG_EXTRA debug_out(">>> C.FSDS{\n"); - stats[64+47]++; + stats[64 + 47]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported insn of rv32imc\n"); #endif - break; + break; case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.SQSP\n"); - stats[64+48]++; + stats[64 + 48]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported insn of rv32imc\n"); #endif - break; + break; } - } - break; + } break; case 6: /* C.SWSP*/ { #ifdef DEBUG_EXTRA debug_out(">>> C.SWSP\n"); - stats[64+49]++; + stats[64 + 49]++; #endif rd = 0; rs2 = midpart & 0x1f; - imm = ((midpart >> 2) & 0x1e0) | - ((midpart << 4) & 0x600); + imm = ((midpart >> 2) & 0x1e0) | ((midpart << 4) & 0x600); imm = (imm >> 3) & 0xff; addr = reg[2] + imm; val = reg[rs2]; @@ -2773,38 +2731,36 @@ void execute_instruction() return; } break; - } - break; + } break; case 7: /* C.FSWSP C.SDSP */ { - switch(XLEN){ + switch (XLEN) { case 32: #ifdef DEBUG_EXTRA debug_out(">>> C.FSWSP\n"); - stats[64+50]++; + stats[64 + 50]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported insn of rv32imc\n"); #endif - break; + break; case 64: case 128: #ifdef DEBUG_EXTRA debug_out(">>> C.SDSP\n"); - stats[64+51]++; + stats[64 + 51]++; #endif #ifdef DEBUG_OUTPUT debug_out("Unsupported insn of rv32imc\n"); #endif - break; + break; } - } - break; + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if(rd != 0) + if (rd != 0) reg[rd] = val; break; #endif @@ -2835,15 +2791,28 @@ void riscv_cpu_interp_x32() #else mtime += 10; #endif -#ifdef DEBUG_OUTPUT + /* default value for next PC is next instruction, can be changed by + * branches or exceptions */ + next_pc = pc + 4; + + /* test for timer interrupt */ + if (mtimecmp <= mtime) { + mip |= MIP_MTIP; + } + if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { + raise_interrupt(); + } else { + /* Compressed or normal */ + insn_type = get_insn32(pc, &insn); +#ifdef RV32C + if (insn_type == CINSN) + next_pc = pc + 2; #endif rd = 0; break; case 128: /* C.LQ*/ #ifdef DEBUG_EXTRA - dprintf("C.LQ\n"); - printf("Unimp insn\b"); - stats[64+3]++; + printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); #endif #ifdef DEBUG_OUTPUT #endif @@ -2863,10 +2832,10 @@ void riscv_cpu_interp_x32() } val = (int32_t)rval; -#ifdef DEBUG_OUTPUT - printf("rs1 : %d, rd: %d, imm: %d\n", rs1, rd, imm); - printf("addr: %08x\n", addr); -#endif + /* test for misaligned fetches , in order to match the compressed + * instruction. */ + if (next_pc & 0x1) { + raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } <<<<<<< HEAD break; @@ -2886,11 +2855,43 @@ void riscv_cpu_interp_x32() } #ifdef DEBUG_OUTPUT +<<<<<<< HEAD printf("done interp %lx int=%x mstatus=%lx prv=%d\n", (uint64_t)insn_counter, mip & mie, (uint64_t)mstatus, priv); break; } +======= + FILE *fo; + char *po, hex_file[100]; +#endif + + /* automatic STDOUT flushing, no fflush needed */ + setvbuf(stdout, NULL, _IONBF, 0); + /* parse command line */ + const char *elf_file = NULL; + const char *signature_file = NULL; + const char *output_file = NULL; + int cmd_opt = 0; + struct option opts[] = {{"elf", 1, NULL, 'e'}, + {"signature", 1, NULL, 's'}, + {"output", 1, NULL, 'o'}}; + const char *optstring = "e:s:o:"; + while ((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1) { + switch (cmd_opt) { + case 'e': + elf_file = optarg; + break; + case 's': + signature_file = optarg; + break; + case 'o': + output_file = optarg; + break; + default: + printf("Unknow argument: %s\n", optarg); + break; +>>>>>>> Rework to a better style } break; case 4: /* Reserved */ @@ -3726,6 +3727,10 @@ int main(int argc, char **argv) GElf_Sym sym; gelf_getsym(data, i, &sym); char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); +#ifdef DEBUG_EXTRA + if (*name) + printf("sym '%s' %lx\n", name, sym.st_value); +#endif if (strcmp(name, "begin_signature") == 0) { begin_signature = sym.st_value; } @@ -3848,8 +3853,8 @@ int main(int argc, char **argv) /* write signature */ /* Check signature */ if (signature_file) { - FILE* sf = fopen(signature_file, "r"); - if(sf == NULL){ + FILE *sf = fopen(signature_file, "r"); + if (sf == NULL) { printf("Error opening file\n"); return -1; } @@ -3857,31 +3862,32 @@ int main(int argc, char **argv) char temp[50], ans[50]; uint32_t tb = begin_signature; int err = 0; - for(int i=0;i %s\n", temp, ans); err++; - }else{ + } else { printf("%s\n", temp); } memset(temp, '\0', 50); } - if(err == 0){ + if (err == 0) { printf("%s TEST PASSED\n", elf_file); - }else{ + } else { printf("%s TEST FAILED\n", elf_file); printf("Number of failed signature : %d\n", err); } fclose(sf); } if (output_file) { - FILE* of = fopen(output_file, "w"); + FILE *of = fopen(output_file, "w"); int size = end_signature - begin_signature; for (int i = 0; i < size / 4; i++) { for (int j = 0; j < 4; j++) { diff --git a/test1.c b/test1.c index 99ed3ea..7df402e 100644 --- a/test1.c +++ b/test1.c @@ -3,8 +3,8 @@ */ void _start() { - volatile char* tx = (volatile char*) 0x40002000; - const char* hello = "Hello RISC-V!\n"; + volatile char *tx = (volatile char *) 0x40002000; + const char *hello = "Hello RISC-V!\n"; while (*hello) { *tx = *hello; hello++; From ce9f3308a11fe79f215219fbf428eead0a77aa25 Mon Sep 17 00:00:00 2001 From: "f74064054@mail.ncku.edu.tw" Date: Mon, 20 Jan 2020 22:30:54 +0800 Subject: [PATCH 24/24] Rework to a final version of emu-rv32i.c --- emu-rv32i.c | 1781 ++++++++++++++------------------------------------- 1 file changed, 479 insertions(+), 1302 deletions(-) diff --git a/emu-rv32i.c b/emu-rv32i.c index 4e574c8..968e26d 100644 --- a/emu-rv32i.c +++ b/emu-rv32i.c @@ -1,32 +1,12 @@ /* - * RISCV emulator + * A minimalist RISC-V emulator for the RV32I architecture. * - * Copyright (c) 2016 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. + * rv32emu is freely redistributable under the MIT License. See the file + * "LICENSE" for information on usage and redistribution of this file. */ #define XLEN 32 -#include -#include -#include #include #include #include @@ -34,14 +14,15 @@ #include #include #include -#include #include -#include +#include +#include #include #include -#include -#include + +/* uncomment this for an instruction trace and other debug outputs */ // #define DEBUG_OUTPUT +// #define DEBUG_EXTRA /* added by Shaos: */ @@ -51,12 +32,15 @@ #ifdef DEBUG_EXTRA -uint32_t minmemr,maxmemr,minmemw,maxmemw; +uint32_t minmemr, maxmemr, minmemw, maxmemw; + +#define STATS_NUM 64 #if defined(RV32C) #define C_STATS_NUM 64 #else #define C_STATS_NUM 0 +#endif unsigned int stats[STATS_NUM + C_STATS_NUM], top[5], itop[5]; char statnames[STATS_NUM + C_STATS_NUM][16] = { @@ -158,9 +142,9 @@ void print_stats(uint64_t total) #endif #ifdef DEBUG_OUTPUT -#define dprintf(s) printf(s) +#define debug_out(...) printf(__VA_ARGS__) #else -#define dprintf(s) +#define debug_out(...) #endif /* memory mapped registers */ @@ -213,10 +197,11 @@ uint32_t reg[32]; uint8_t priv = PRV_M; /* see PRV_x */ -uint8_t fs; /* MSTATUS_FS value */ -uint8_t mxl; /* MXL field in MISA register */ +uint8_t fs; /* MSTATUS_FS value */ +uint8_t mxl; /* MXL field in MISA register */ -uint64_t jump_counter=0,backward_counter=0,forward_counter=0,true_counter=0,false_counter=0; +uint64_t jump_counter = 0, backward_counter = 0, forward_counter = 0, + true_counter = 0, false_counter = 0; uint64_t insn_counter = 0; int pending_exception; /* used during MMU exception handling */ @@ -247,33 +232,33 @@ uint32_t scounteren; uint32_t load_res; /* for atomic LR/SC */ /* exception causes */ -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 +#define CAUSE_MISALIGNED_FETCH 0x0 +#define CAUSE_FAULT_FETCH 0x1 #define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_FETCH_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_PAGE_FAULT 0xf -#define CAUSE_INTERRUPT ((uint32_t)1 << 31) +#define CAUSE_BREAKPOINT 0x3 +#define CAUSE_MISALIGNED_LOAD 0x4 +#define CAUSE_FAULT_LOAD 0x5 +#define CAUSE_MISALIGNED_STORE 0x6 +#define CAUSE_FAULT_STORE 0x7 +#define CAUSE_USER_ECALL 0x8 +#define CAUSE_SUPERVISOR_ECALL 0x9 +#define CAUSE_HYPERVISOR_ECALL 0xa +#define CAUSE_MACHINE_ECALL 0xb +#define CAUSE_FETCH_PAGE_FAULT 0xc +#define CAUSE_LOAD_PAGE_FAULT 0xd +#define CAUSE_STORE_PAGE_FAULT 0xf +#define CAUSE_INTERRUPT ((uint32_t) 1 << 31) /* misa CSR */ -#define MCPUID_SUPER (1 << ('S' - 'A')) -#define MCPUID_USER (1 << ('U' - 'A')) -#define MCPUID_I (1 << ('I' - 'A')) -#define MCPUID_M (1 << ('M' - 'A')) -#define MCPUID_A (1 << ('A' - 'A')) -#define MCPUID_F (1 << ('F' - 'A')) -#define MCPUID_D (1 << ('D' - 'A')) -#define MCPUID_Q (1 << ('Q' - 'A')) -#define MCPUID_C (1 << ('C' - 'A')) +#define MCPUID_SUPER (1 << ('S' - 'A')) +#define MCPUID_USER (1 << ('U' - 'A')) +#define MCPUID_I (1 << ('I' - 'A')) +#define MCPUID_M (1 << ('M' - 'A')) +#define MCPUID_A (1 << ('A' - 'A')) +#define MCPUID_F (1 << ('F' - 'A')) +#define MCPUID_D (1 << ('D' - 'A')) +#define MCPUID_Q (1 << ('Q' - 'A')) +#define MCPUID_C (1 << ('C' - 'A')) #define MIP_USIP (1 << 0) #define MIP_SSIP (1 << 1) @@ -313,8 +298,8 @@ uint32_t load_res; /* for atomic LR/SC */ #define MSTATUS_MPRV (1 << 17) #define MSTATUS_SUM (1 << 18) #define MSTATUS_MXR (1 << 19) -#define MSTATUS_UXL_MASK ((uint64_t)3 << MSTATUS_UXL_SHIFT) -#define MSTATUS_SXL_MASK ((uint64_t)3 << MSTATUS_SXL_SHIFT) +#define MSTATUS_UXL_MASK ((uint64_t) 3 << MSTATUS_UXL_SHIFT) +#define MSTATUS_SXL_MASK ((uint64_t) 3 << MSTATUS_SXL_SHIFT) static inline int ctz32(uint32_t val) { @@ -351,19 +336,16 @@ static inline int ctz32(uint32_t val) #endif } -#define SSTATUS_MASK0 (MSTATUS_UIE | MSTATUS_SIE | \ - MSTATUS_UPIE | MSTATUS_SPIE | \ - MSTATUS_SPP | \ - MSTATUS_FS | MSTATUS_XS | \ - MSTATUS_SUM | MSTATUS_MXR) +#define SSTATUS_MASK0 \ + (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_UPIE | MSTATUS_SPIE | MSTATUS_SPP | \ + MSTATUS_FS | MSTATUS_XS | MSTATUS_SUM | MSTATUS_MXR) #define SSTATUS_MASK SSTATUS_MASK0 -#define MSTATUS_MASK (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_MIE | \ - MSTATUS_UPIE | MSTATUS_SPIE | MSTATUS_MPIE | \ - MSTATUS_SPP | MSTATUS_MPP | \ - MSTATUS_FS | \ - MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MXR) +#define MSTATUS_MASK \ + (MSTATUS_UIE | MSTATUS_SIE | MSTATUS_MIE | MSTATUS_UPIE | MSTATUS_SPIE | \ + MSTATUS_MPIE | MSTATUS_SPP | MSTATUS_MPP | MSTATUS_FS | MSTATUS_MPRV | \ + MSTATUS_SUM | MSTATUS_MXR) /* cycle and insn counters */ #define COUNTEREN_MASK ((1 << 0) | (1 << 2)) @@ -375,10 +357,10 @@ uint32_t get_mstatus(uint32_t mask) int sd; val = mstatus | (fs << MSTATUS_FS_SHIFT); val &= mask; - sd = ((val & MSTATUS_FS) == MSTATUS_FS) | - ((val & MSTATUS_XS) == MSTATUS_XS); + sd = + ((val & MSTATUS_FS) == MSTATUS_FS) | ((val & MSTATUS_XS) == MSTATUS_XS); if (sd) - val |= (uint32_t)1 << (XLEN - 1); + val |= (uint32_t) 1 << (XLEN - 1); return val; } @@ -394,17 +376,14 @@ void invalid_csr(uint32_t *pval, uint32_t csr) { /* the 'time' counter is usually emulated */ if (csr != 0xc01 && csr != 0xc81) { -#ifdef DEBUG_OUTPUT - printf("csr_read: invalid CSR=0x%x\n", csr); -#endif + debug_out("csr_read: invalid CSR=0x%x\n", csr); } *pval = 0; } /* return -1 if invalid CSR. 0 if OK. 'will_write' indicate that the csr will be written after (used for CSR access check) */ -int csr_read(uint32_t *pval, uint32_t csr, - int will_write) +int csr_read(uint32_t *pval, uint32_t csr, int will_write) { uint32_t val; @@ -417,7 +396,7 @@ int csr_read(uint32_t *pval, uint32_t csr, if (priv < ((csr >> 8) & 3)) return -1; /* not enough priviledge */ - switch(csr) { + switch (csr) { case 0xc00: /* cycle */ case 0xc02: /* instret */ { @@ -433,8 +412,8 @@ int csr_read(uint32_t *pval, uint32_t csr, } } } - val = (int64_t)insn_counter; - break; + val = (int64_t) insn_counter; + break; case 0xc80: /* cycleh */ case 0xc82: /* instreth */ { @@ -450,8 +429,8 @@ int csr_read(uint32_t *pval, uint32_t csr, } } } - val = insn_counter >> 32; - break; + val = insn_counter >> 32; + break; case 0x100: val = get_mstatus(SSTATUS_MASK); @@ -484,11 +463,11 @@ int csr_read(uint32_t *pval, uint32_t csr, val = satp; break; case 0x300: - val = get_mstatus((uint32_t)-1); + val = get_mstatus((uint32_t) -1); break; case 0x301: val = misa; - val |= (uint32_t)mxl << (XLEN - 2); + val |= (uint32_t) mxl << (XLEN - 2); break; case 0x302: val = medeleg; @@ -522,7 +501,7 @@ int csr_read(uint32_t *pval, uint32_t csr, break; case 0xb00: /* mcycle */ case 0xb02: /* minstret */ - val = (int64_t)insn_counter; + val = (int64_t) insn_counter; break; case 0xb80: /* mcycleh */ case 0xb82: /* minstreth */ @@ -553,7 +532,7 @@ int csr_write(uint32_t csr, uint32_t val) #ifdef DEBUG_EXTRA printf("csr_write: csr=0x%03x val=0x%08x\n", csr, val); #endif - switch(csr) { + switch (csr) { case 0x100: /* sstatus */ set_mstatus((mstatus & ~SSTATUS_MASK) | (val & SSTATUS_MASK)); break; @@ -584,12 +563,11 @@ int csr_write(uint32_t csr, uint32_t val) mip = (mip & ~mask) | (val & mask); break; case 0x180: /* no ASID implemented */ - { - int new_mode; - new_mode = (val >> 31) & 1; - satp = (val & (((uint32_t)1 << 22) - 1)) | - (new_mode << 31); - } + { + int new_mode; + new_mode = (val >> 31) & 1; + satp = (val & (((uint32_t) 1 << 22) - 1)) | (new_mode << 31); + } return 2; case 0x300: @@ -644,8 +622,7 @@ void handle_sret() spp = (mstatus >> MSTATUS_SPP_SHIFT) & 1; /* set the IE state to previous IE state */ spie = (mstatus >> MSTATUS_SPIE_SHIFT) & 1; - mstatus = (mstatus & ~(1 << spp)) | - (spie << spp); + mstatus = (mstatus & ~(1 << spp)) | (spie << spp); /* set SPIE to 1 */ mstatus |= MSTATUS_SPIE; /* set SPP to U */ @@ -660,8 +637,7 @@ void handle_mret() mpp = (mstatus >> MSTATUS_MPP_SHIFT) & 3; /* set the IE state to previous IE state */ mpie = (mstatus >> MSTATUS_MPIE_SHIFT) & 1; - mstatus = (mstatus & ~(1 << mpp)) | - (mpie << mpp); + mstatus = (mstatus & ~(1 << mpp)) | (mpie << mpp); /* set MPIE to 1 */ mstatus |= MSTATUS_MPIE; /* set MPP to U */ @@ -676,9 +652,8 @@ void raise_exception(uint32_t cause, uint32_t tval) /* exit for Zephyr applications */ if (cause == CAUSE_ILLEGAL_INSTRUCTION) { -#ifdef DEBUG_OUTPUT - printf("raise_exception: illegal instruction 0x%x 0x%x\n", cause, tval); -#endif + debug_out("raise_exception: illegal instruction 0x%x 0x%x\n", cause, + tval); machine_running = FALSE; return; } @@ -714,8 +689,7 @@ void raise_exception(uint32_t cause, uint32_t tval) stval = tval; mstatus = (mstatus & ~MSTATUS_SPIE) | (((mstatus >> priv) & 1) << MSTATUS_SPIE_SHIFT); - mstatus = (mstatus & ~MSTATUS_SPP) | - (priv << MSTATUS_SPP_SHIFT); + mstatus = (mstatus & ~MSTATUS_SPP) | (priv << MSTATUS_SPP_SHIFT); mstatus &= ~MSTATUS_SIE; priv = PRV_S; next_pc = stvec; @@ -725,8 +699,7 @@ void raise_exception(uint32_t cause, uint32_t tval) mtval = tval; mstatus = (mstatus & ~MSTATUS_MPIE) | (((mstatus >> priv) & 1) << MSTATUS_MPIE_SHIFT); - mstatus = (mstatus & ~MSTATUS_MPP) | - (priv << MSTATUS_MPP_SHIFT); + mstatus = (mstatus & ~MSTATUS_MPP) | (priv << MSTATUS_MPP_SHIFT); mstatus &= ~MSTATUS_MIE; priv = PRV_M; next_pc = mtvec; @@ -742,7 +715,7 @@ uint32_t get_pending_irq_mask() return 0; enabled_ints = 0; - switch(priv) { + switch (priv) { case PRV_M: if (mstatus & MSTATUS_MIE) enabled_ints = ~mideleg; @@ -778,8 +751,10 @@ int raise_interrupt() unsigned char get_insn32(uint32_t pc, uint32_t *insn) { #ifdef DEBUG_EXTRA - if(pc && pc < minmemr) minmemr = pc; - if(pc+3 > maxmemr) maxmemr = pc+3; + if (pc && pc < minmemr) + minmemr = pc; + if (pc + 3 > maxmemr) + maxmemr = pc + 3; #endif uint32_t ptr = pc - ram_start; if (ptr > RAM_SIZE) { @@ -808,8 +783,10 @@ unsigned char get_insn32(uint32_t pc, uint32_t *insn) int target_read_u8(uint8_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemr) minmemr = addr; - if(addr > maxmemr) maxmemr = addr; + if ((addr >> 28) != 4 && addr < minmemr) + minmemr = addr; + if (addr > maxmemr) + maxmemr = addr; #endif addr -= ram_start; if (addr > RAM_SIZE) { @@ -818,7 +795,7 @@ int target_read_u8(uint8_t *pval, uint32_t addr) addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; *pval = p[0]; } return 0; @@ -829,8 +806,10 @@ int target_read_u8(uint8_t *pval, uint32_t addr) int target_read_u16(uint16_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemr) minmemr = addr; - if(addr+1 > maxmemr) maxmemr = addr+1; + if ((addr >> 28) != 4 && addr < minmemr) + minmemr = addr; + if (addr + 1 > maxmemr) + maxmemr = addr + 1; #endif if (addr & 1) { pending_exception = CAUSE_MISALIGNED_LOAD; @@ -838,12 +817,13 @@ int target_read_u16(uint16_t *pval, uint32_t addr) return 1; } addr -= ram_start; - if (addr > RAM_SIZE) { + if (addr > RAM_SIZE) { *pval = 0; - printf("illegal read 16, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); + printf("illegal read 16, PC: 0x%08x, address: 0x%08x\n", pc, + addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; *pval = p[0] | (p[1] << 8); } return 0; @@ -854,8 +834,10 @@ int target_read_u16(uint16_t *pval, uint32_t addr) int target_read_u32(uint32_t *pval, uint32_t addr) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemr) minmemr = addr; - if(addr+3 > maxmemr) maxmemr = addr+3; + if ((addr >> 28) != 4 && addr < minmemr) + minmemr = addr; + if (addr + 3 > maxmemr) + maxmemr = addr + 3; #endif if (addr & 3) { pending_exception = CAUSE_MISALIGNED_LOAD; @@ -865,19 +847,20 @@ int target_read_u32(uint32_t *pval, uint32_t addr) if (addr == MTIMECMP_ADDR) { *pval = (uint32_t) mtimecmp; } else if (addr == MTIMECMP_ADDR + 4) { - *pval = (uint32_t) (mtimecmp >> 32); + *pval = (uint32_t)(mtimecmp >> 32); } else if (addr == MTIME_ADDR) { *pval = (uint32_t) mtime; } else if (addr == MTIME_ADDR + 4) { - *pval = (uint32_t) (mtime >> 32); + *pval = (uint32_t)(mtime >> 32); } else { addr -= ram_start; if (addr > RAM_SIZE) { *pval = 0; - printf("illegal read 32, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); + printf("illegal read 32, PC: 0x%08x, address: 0x%08x\n", pc, + addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; *pval = p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24); } } @@ -889,8 +872,10 @@ int target_read_u32(uint32_t *pval, uint32_t addr) int target_write_u8(uint32_t addr, uint8_t val) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemw) minmemw = addr; - if(addr > maxmemw) maxmemw = addr; + if ((addr >> 28) != 4 && addr < minmemw) + minmemw = addr; + if (addr > maxmemw) + maxmemw = addr; #endif if (addr == UART_TX_ADDR) { /* test for UART output, compatible with QEMU */ @@ -898,10 +883,11 @@ int target_write_u8(uint32_t addr, uint8_t val) } else { addr -= ram_start; if (addr > RAM_SIZE - 1) { - printf("illegal write 8, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); + printf("illegal write 8, PC: 0x%08x, address: 0x%08x\n", pc, + addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; p[0] = val & 0xff; } } @@ -913,8 +899,10 @@ int target_write_u8(uint32_t addr, uint8_t val) int target_write_u16(uint32_t addr, uint16_t val) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemw) minmemw = addr; - if(addr+1 > maxmemw) maxmemw = addr+1; + if ((addr >> 28) != 4 && addr < minmemw) + minmemw = addr; + if (addr + 1 > maxmemw) + maxmemw = addr + 1; #endif if (addr & 1) { pending_exception = CAUSE_MISALIGNED_STORE; @@ -923,10 +911,11 @@ int target_write_u16(uint32_t addr, uint16_t val) } addr -= ram_start; if (addr > RAM_SIZE - 2) { - printf("illegal write 16, PC: 0x%08x, address: 0x%08x\n", pc, addr + ram_start); + printf("illegal write 16, PC: 0x%08x, address: 0x%08x\n", pc, + addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; p[0] = val & 0xff; p[1] = (val >> 8) & 0xff; } @@ -938,8 +927,10 @@ int target_write_u16(uint32_t addr, uint16_t val) int target_write_u32(uint32_t addr, uint32_t val) { #ifdef DEBUG_EXTRA - if((addr>>28)!=4 && addr < minmemw) minmemw = addr; - if(addr+3 > maxmemw) maxmemw = addr+3; + if ((addr >> 28) != 4 && addr < minmemw) + minmemw = addr; + if (addr + 3 > maxmemw) + maxmemw = addr + 3; #endif if (addr & 3) { pending_exception = CAUSE_MISALIGNED_STORE; @@ -950,14 +941,16 @@ int target_write_u32(uint32_t addr, uint32_t val) mtimecmp = (mtimecmp & 0xffffffff00000000ll) | val; mip &= ~MIP_MTIP; } else if (addr == MTIMECMP_ADDR + 4) { - mtimecmp = (mtimecmp & 0xffffffffll) | (((uint64_t)val) << 32); + mtimecmp = (mtimecmp & 0xffffffffll) | (((uint64_t) val) << 32); mip &= ~MIP_MTIP; } else { addr -= ram_start; - if (addr > RAM_SIZE - 4) { + if (addr > RAM_SIZE - 4) { + printf("illegal write 32, PC: 0x%08x, address: 0x%08x\n", pc, + addr + ram_start); return 1; } else { - uint8_t* p = ram + addr; + uint8_t *p = ram + addr; p[0] = val & 0xff; p[1] = (val >> 8) & 0xff; p[2] = (val >> 16) & 0xff; @@ -973,7 +966,7 @@ int32_t div32(int32_t a, int32_t b) { if (b == 0) { return -1; - } else if (a == ((int32_t)1 << (XLEN - 1)) && b == -1) { + } else if (a == ((int32_t) 1 << (XLEN - 1)) && b == -1) { return a; } else { return a / b; @@ -984,44 +977,41 @@ uint32_t divu32(uint32_t a, uint32_t b) { if (b == 0) { return -1; - } else { - return a / b; } + return a / b; } int32_t rem32(int32_t a, int32_t b) { if (b == 0) { return a; - } else if (a == ((int32_t)1 << (XLEN - 1)) && b == -1) { + } else if (a == ((int32_t) 1 << (XLEN - 1)) && b == -1) { return 0; - } else { - return a % b; } + return a % b; } uint32_t remu32(uint32_t a, uint32_t b) { if (b == 0) { return a; - } else { - return a % b; } + return a % b; } static uint32_t mulh32(int32_t a, int32_t b) { - return ((int64_t)a * (int64_t)b) >> 32; + return ((int64_t) a * (int64_t) b) >> 32; } static uint32_t mulhsu32(int32_t a, uint32_t b) { - return ((int64_t)a * (int64_t)b) >> 32; + return ((int64_t) a * (int64_t) b) >> 32; } static uint32_t mulhu32(uint32_t a, uint32_t b) { - return ((int64_t)a * (int64_t)b) >> 32; + return ((int64_t) a * (int64_t) b) >> 32; } #endif @@ -1073,22 +1063,7 @@ void execute_instruction() { uint32_t opcode, rd, rs1, rs2, funct3; int32_t imm, cond, err; - uint32_t addr, val=0, val2; - - uint16_t midpart; - - if(insn_type == INSN){ - opcode = insn & 0x7f; - rd = (insn >> 7) & 0x1f; - rs1 = (insn >> 15) & 0x1f; - rs2 = (insn >> 20) & 0x1f; - } - -#ifdef RV32C - if(insn_type == CINSN){ - opcode = insn & 0x3; - } -#endif + uint32_t addr, val = 0, val2; uint16_t midpart; @@ -1107,13 +1082,11 @@ void execute_instruction() - - switch(opcode) { - + switch (opcode) { case 0x37: /* lui */ #ifdef DEBUG_EXTRA - dprintf(">>> LUI\n"); + debug_out(">>> LUI\n"); stats[0]++; #endif if (rd != 0) @@ -1123,7 +1096,7 @@ void execute_instruction() case 0x17: /* auipc */ #ifdef DEBUG_EXTRA - dprintf(">>> AUIPC\n"); + debug_out(">>> AUIPC\n"); stats[1]++; #endif if (rd != 0) @@ -1133,50 +1106,52 @@ void execute_instruction() case 0x6f: /* jal */ #ifdef DEBUG_EXTRA - dprintf(">>> JAL\n"); + debug_out(">>> JAL\n"); stats[2]++; #endif - imm = ((insn >> (31 - 20)) & (1 << 20)) | - ((insn >> (21 - 1)) & 0x7fe) | - ((insn >> (20 - 11)) & (1 << 11)) | - (insn & 0xff000); + imm = ((insn >> (31 - 20)) & (1 << 20)) | ((insn >> (21 - 1)) & 0x7fe) | + ((insn >> (20 - 11)) & (1 << 11)) | (insn & 0xff000); imm = (imm << 11) >> 11; if (rd != 0) reg[rd] = pc + 4; next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; break; case 0x67: /* jalr */ #ifdef DEBUG_EXTRA - dprintf(">>> JALR\n"); + debug_out(">>> JALR\n"); stats[3]++; #endif - imm = (int32_t)insn >> 20; + imm = (int32_t) insn >> 20; val = pc + 4; next_pc = (int32_t)(reg[rs1] + imm) & ~1; if (rd != 0) reg[rd] = val; - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; break; case 0x63: /* BRANCH */ funct3 = (insn >> 12) & 7; - switch(funct3 >> 1) { + switch (funct3 >> 1) { case 0: /* beq/bne */ #ifdef DEBUG_EXTRA - if(!(funct3 & 1)) { - dprintf(">>> BEQ\n"); - stats[4]++; - } else { - dprintf(">>> BNE\n"); - stats[5]++; + if (!(funct3 & 1)) { + debug_out(">>> BEQ\n"); + stats[4]++; + } else { + debug_out(">>> BNE\n"); + stats[5]++; } #endif cond = (reg[rs1] == reg[rs2]); @@ -1189,6 +1164,12 @@ void execute_instruction() } else { debug_out(">>> BGE\n"); stats[7]++; + } +#endif + cond = ((int32_t) reg[rs1] < (int32_t) reg[rs2]); + break; + case 3: /* bltu/bgeu */ +#ifdef DEBUG_EXTRA if (!(funct3 & 1)) { debug_out(">>> BLTU\n"); stats[8]++; @@ -1206,30 +1187,31 @@ void execute_instruction() cond ^= (funct3 & 1); if (cond) { imm = ((insn >> (31 - 12)) & (1 << 12)) | - ((insn >> (25 - 5)) & 0x7e0) | - ((insn >> (8 - 1)) & 0x1e) | + ((insn >> (25 - 5)) & 0x7e0) | ((insn >> (8 - 1)) & 0x1e) | ((insn << (11 - 7)) & (1 << 11)); imm = (imm << 19) >> 19; next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; + if (next_pc > pc) + forward_counter++; + else + backward_counter++; jump_counter++; true_counter++; break; - } else false_counter++; + } else + false_counter++; break; case 0x03: /* LOAD */ funct3 = (insn >> 12) & 7; - imm = (int32_t)insn >> 20; + imm = (int32_t) insn >> 20; addr = reg[rs1] + imm; - switch(funct3) { - + switch (funct3) { case 0: /* lb */ { #ifdef DEBUG_EXTRA - dprintf(">>> LB\n"); + debug_out(">>> LB\n"); stats[10]++; #endif uint8_t rval; @@ -1237,14 +1219,13 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int8_t)rval; - } - break; + val = (int8_t) rval; + } break; case 1: /* lh */ { #ifdef DEBUG_EXTRA - dprintf(">>> LH\n"); + debug_out(">>> LH\n"); stats[11]++; #endif uint16_t rval; @@ -1252,14 +1233,13 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int16_t)rval; - } - break; + val = (int16_t) rval; + } break; case 2: /* lw */ { #ifdef DEBUG_EXTRA - dprintf(">>> LW\n"); + debug_out(">>> LW\n"); stats[12]++; #endif uint32_t rval; @@ -1267,14 +1247,13 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int32_t)rval; - } - break; + val = (int32_t) rval; + } break; case 4: /* lbu */ { #ifdef DEBUG_EXTRA - dprintf(">>> LBU\n"); + debug_out(">>> LBU\n"); stats[13]++; #endif uint8_t rval; @@ -1283,13 +1262,12 @@ void execute_instruction() return; } val = rval; - } - break; + } break; case 5: /* lhu */ { #ifdef DEBUG_EXTRA - dprintf(">>> LHU\n"); + debug_out(">>> LHU\n"); stats[14]++; #endif uint16_t rval; @@ -1298,8 +1276,7 @@ void execute_instruction() return; } val = rval; - } - break; + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1316,11 +1293,10 @@ void execute_instruction() imm = (imm << 20) >> 20; addr = reg[rs1] + imm; val = reg[rs2]; - switch(funct3) { - + switch (funct3) { case 0: /* sb */ #ifdef DEBUG_EXTRA - dprintf(">>> SB\n"); + debug_out(">>> SB\n"); stats[15]++; #endif if (target_write_u8(addr, val)) { @@ -1331,7 +1307,7 @@ void execute_instruction() case 1: /* sh */ #ifdef DEBUG_EXTRA - dprintf(">>> SH\n"); + debug_out(">>> SH\n"); stats[16]++; #endif if (target_write_u16(addr, val)) { @@ -1342,7 +1318,7 @@ void execute_instruction() case 2: /* sw */ #ifdef DEBUG_EXTRA - dprintf(">>> SW\n"); + debug_out(">>> SW\n"); stats[17]++; #endif if (target_write_u32(addr, val)) { @@ -1360,19 +1336,20 @@ void execute_instruction() case 0x13: /* OP-IMM */ funct3 = (insn >> 12) & 7; - imm = (int32_t)insn >> 20; - switch(funct3) { + imm = (int32_t) insn >> 20; + switch (funct3) { case 0: /* addi */ #ifdef DEBUG_EXTRA - dprintf(">>> ADDI\n"); + debug_out(">>> ADDI\n"); stats[18]++; - if(rs1==0) stats[47]++; /* li */ + if (rs1 == 0) + stats[47]++; /* li */ #endif val = (int32_t)(reg[rs1] + imm); break; case 1: /* slli */ #ifdef DEBUG_EXTRA - dprintf(">>> SLLI\n"); + debug_out(">>> SLLI\n"); stats[24]++; #endif if ((imm & ~(XLEN - 1)) != 0) { @@ -1383,21 +1360,21 @@ void execute_instruction() break; case 2: /* slti */ #ifdef DEBUG_EXTRA - dprintf(">>> SLTI\n"); + debug_out(">>> SLTI\n"); stats[19]++; #endif - val = (int32_t)reg[rs1] < (int32_t)imm; + val = (int32_t) reg[rs1] < (int32_t) imm; break; case 3: /* sltiu */ #ifdef DEBUG_EXTRA - dprintf(">>> SLTIU\n"); + debug_out(">>> SLTIU\n"); stats[20]++; #endif - val = reg[rs1] < (uint32_t)imm; + val = reg[rs1] < (uint32_t) imm; break; case 4: /* xori */ #ifdef DEBUG_EXTRA - dprintf(">>> XORI\n"); + debug_out(">>> XORI\n"); stats[21]++; #endif val = reg[rs1] ^ imm; @@ -1407,33 +1384,30 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - if (imm & 0x400) - { + if (imm & 0x400) { #ifdef DEBUG_EXTRA - dprintf(">>> SRAI\n"); + debug_out(">>> SRAI\n"); stats[26]++; #endif - val = (int32_t)reg[rs1] >> (imm & (XLEN - 1)); - } - else - { + val = (int32_t) reg[rs1] >> (imm & (XLEN - 1)); + } else { #ifdef DEBUG_EXTRA - dprintf(">>> SRLI\n"); + debug_out(">>> SRLI\n"); stats[25]++; #endif - val = (int32_t)((uint32_t)reg[rs1] >> (imm & (XLEN - 1))); + val = (int32_t)((uint32_t) reg[rs1] >> (imm & (XLEN - 1))); } break; case 6: /* ori */ #ifdef DEBUG_EXTRA - dprintf(">>> ORI\n"); + debug_out(">>> ORI\n"); stats[22]++; #endif val = reg[rs1] | imm; break; case 7: /* andi */ #ifdef DEBUG_EXTRA - dprintf(">>> ANDI\n"); + debug_out(">>> ANDI\n"); stats[23]++; #endif val = reg[rs1] & imm; @@ -1451,69 +1425,68 @@ void execute_instruction() #ifndef STRICT_RV32I if (imm == 1) { funct3 = (insn >> 12) & 7; - switch(funct3) { + switch (funct3) { case 0: /* mul */ #ifdef DEBUG_EXTRA - dprintf(">>> MUL\n"); + debug_out(">>> MUL\n"); stats[48]++; #endif - val = (int32_t)((int32_t)val * (int32_t)val2); + val = (int32_t)((int32_t) val * (int32_t) val2); break; case 1: /* mulh */ #ifdef DEBUG_EXTRA - dprintf(">>> MULH\n"); + debug_out(">>> MULH\n"); stats[49]++; #endif - val = (int32_t)mulh32(val, val2); + val = (int32_t) mulh32(val, val2); break; - case 2:/* mulhsu */ + case 2: /* mulhsu */ #ifdef DEBUG_EXTRA - dprintf(">>> MULHSU\n"); + debug_out(">>> MULHSU\n"); stats[50]++; #endif - val = (int32_t)mulhsu32(val, val2); + val = (int32_t) mulhsu32(val, val2); break; - case 3:/* mulhu */ + case 3: /* mulhu */ #ifdef DEBUG_EXTRA - dprintf(">>> MULHU\n"); + debug_out(">>> MULHU\n"); stats[51]++; #endif - val = (int32_t)mulhu32(val, val2); + val = (int32_t) mulhu32(val, val2); break; - case 4:/* div */ + case 4: /* div */ #ifdef DEBUG_EXTRA - dprintf(">>> DIV\n"); + debug_out(">>> DIV\n"); stats[52]++; #endif val = div32(val, val2); break; - case 5:/* divu */ + case 5: /* divu */ #ifdef DEBUG_EXTRA - dprintf(">>> DIVU\n"); + debug_out(">>> DIVU\n"); stats[53]++; #endif - val = (int32_t)divu32(val, val2); + val = (int32_t) divu32(val, val2); break; - case 6:/* rem */ + case 6: /* rem */ #ifdef DEBUG_EXTRA - dprintf(">>> REM\n"); + debug_out(">>> REM\n"); stats[54]++; #endif val = rem32(val, val2); break; - case 7:/* remu */ + case 7: /* remu */ #ifdef DEBUG_EXTRA - dprintf(">>> REMU\n"); + debug_out(">>> REMU\n"); stats[55]++; #endif - val = (int32_t)remu32(val, val2); + val = (int32_t) remu32(val, val2); break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } - else + } else #endif { if (imm & ~0x20) { @@ -1521,73 +1494,73 @@ void execute_instruction() return; } funct3 = ((insn >> 12) & 7) | ((insn >> (30 - 3)) & (1 << 3)); - switch(funct3) { + switch (funct3) { case 0: /* add */ #ifdef DEBUG_EXTRA - dprintf(">>> ADD\n"); + debug_out(">>> ADD\n"); stats[27]++; #endif val = (int32_t)(val + val2); break; case 0 | 8: /* sub */ #ifdef DEBUG_EXTRA - dprintf(">>> SUB\n"); + debug_out(">>> SUB\n"); stats[28]++; #endif val = (int32_t)(val - val2); break; case 1: /* sll */ #ifdef DEBUG_EXTRA - dprintf(">>> SLL\n"); + debug_out(">>> SLL\n"); stats[29]++; #endif val = (int32_t)(val << (val2 & (XLEN - 1))); break; case 2: /* slt */ #ifdef DEBUG_EXTRA - dprintf(">>> SLT\n"); + debug_out(">>> SLT\n"); stats[30]++; #endif - val = (int32_t)val < (int32_t)val2; + val = (int32_t) val < (int32_t) val2; break; case 3: /* sltu */ #ifdef DEBUG_EXTRA - dprintf(">>> SLTU\n"); + debug_out(">>> SLTU\n"); stats[31]++; #endif val = val < val2; break; case 4: /* xor */ #ifdef DEBUG_EXTRA - dprintf(">>> XOR\n"); + debug_out(">>> XOR\n"); stats[32]++; #endif val = val ^ val2; break; case 5: /* srl */ #ifdef DEBUG_EXTRA - dprintf(">>> SRL\n"); + debug_out(">>> SRL\n"); stats[33]++; #endif - val = (int32_t)((uint32_t)val >> (val2 & (XLEN - 1))); + val = (int32_t)((uint32_t) val >> (val2 & (XLEN - 1))); break; case 5 | 8: /* sra */ #ifdef DEBUG_EXTRA - dprintf(">>> SRA\n"); + debug_out(">>> SRA\n"); stats[34]++; #endif - val = (int32_t)val >> (val2 & (XLEN - 1)); + val = (int32_t) val >> (val2 & (XLEN - 1)); break; case 6: /* or */ #ifdef DEBUG_EXTRA - dprintf(">>> OR\n"); + debug_out(">>> OR\n"); stats[35]++; #endif val = val | val2; break; case 7: /* and */ #ifdef DEBUG_EXTRA - dprintf(">>> AND\n"); + debug_out(">>> AND\n"); stats[36]++; #endif val = val & val2; @@ -1610,26 +1583,22 @@ void execute_instruction() else val = reg[rs1]; funct3 &= 3; - switch(funct3) { - + switch (funct3) { case 1: /* csrrw & csrrwi */ #ifdef DEBUG_EXTRA - if ((insn >> 12) & 4) - { - dprintf(">>> CSRRWI\n"); - stats[44]++; - } - else - { - dprintf(">>> CSRRW\n"); - stats[41]++; + if ((insn >> 12) & 4) { + debug_out(">>> CSRRWI\n"); + stats[44]++; + } else { + debug_out(">>> CSRRW\n"); + stats[41]++; } #endif if (csr_read(&val2, imm, TRUE)) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - val2 = (int32_t)val2; + val2 = (int32_t) val2; err = csr_write(imm, val); if (err < 0) { raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1648,24 +1617,31 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - val2 = (int32_t)val2; + val2 = (int32_t) val2; #ifdef DEBUG_EXTRA - switch((insn >> 12) & 7) - { - case 2: dprintf(">>> CSRRS\n"); stats[42]++; break; - case 3: dprintf(">>> CSRRC\n"); stats[43]++; break; - case 6: dprintf(">>> CSRRSI\n"); stats[45]++; break; - case 7: dprintf(">>> CSRRCI\n"); stats[46]++; break; + switch ((insn >> 12) & 7) { + case 2: + debug_out(">>> CSRRS\n"); + stats[42]++; + break; + case 3: + debug_out(">>> CSRRC\n"); + stats[43]++; + break; + case 6: + debug_out(">>> CSRRSI\n"); + stats[45]++; + break; + case 7: + debug_out(">>> CSRRCI\n"); + stats[46]++; + break; } #endif - if (rs1 != 0) - { - if (funct3 == 2) - { + if (rs1 != 0) { + if (funct3 == 2) { val = val2 | val; - } - else - { + } else { val = val2 & ~val; } err = csr_write(imm, val); @@ -1673,9 +1649,7 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } - else - { + } else { err = 0; } if (rd != 0) @@ -1683,10 +1657,10 @@ void execute_instruction() break; case 0: - switch(imm) { + switch (imm) { case 0x000: /* ecall */ #ifdef DEBUG_EXTRA - dprintf(">>> ECALL\n"); + debug_out(">>> ECALL\n"); stats[39]++; #endif if (insn & 0x000fff80) { @@ -1700,20 +1674,17 @@ void execute_instruction() */ if (begin_signature) { if (reg[3] & 1) { -#ifdef DEBUG_OUTPUT - printf("program end, result: %04x\n", reg[3] >> 1); -#endif + debug_out("program end, result: %04x\n", reg[3] >> 1); machine_running = FALSE; return; } else { -#ifdef DEBUG_OUTPUT - printf("syscall: %04x\n", reg[3]); -#endif + debug_out("syscall: %04x\n", reg[3]); raise_exception(CAUSE_USER_ECALL + priv, 0); } } else { - /* on real hardware, an exception is raised, the I-ECALL-01 compliance test tests this as well */ + /* on real hardware, an exception is raised, the I-ECALL-01 + * compliance test tests this as well */ raise_exception(CAUSE_USER_ECALL + priv, 0); return; } @@ -1721,7 +1692,7 @@ void execute_instruction() case 0x001: /* ebreak */ #ifdef DEBUG_EXTRA - dprintf(">>> EBREAK\n"); + debug_out(">>> EBREAK\n"); stats[40]++; #endif if (insn & 0x000fff80) { @@ -1734,7 +1705,7 @@ void execute_instruction() case 0x102: /* sret */ { #ifdef DEBUG_EXTRA - dprintf(">>> SRET\n"); + debug_out(">>> SRET\n"); stats[59]++; #endif if ((insn & 0x000fff80) || (priv < PRV_S)) { @@ -1743,12 +1714,11 @@ void execute_instruction() } handle_sret(); return; - } - break; + } break; case 0x105: /* wfi */ #ifdef DEBUG_EXTRA - dprintf(">>> WFI\n"); + debug_out(">>> WFI\n"); stats[61]++; #endif /* wait for interrupt: it is allowed to execute it as nop */ @@ -1757,7 +1727,7 @@ void execute_instruction() case 0x302: /* mret */ { #ifdef DEBUG_EXTRA - dprintf(">>> MRET\n"); + debug_out(">>> MRET\n"); stats[60]++; #endif if ((insn & 0x000fff80) || (priv < PRV_M)) { @@ -1766,13 +1736,12 @@ void execute_instruction() } handle_mret(); return; - } - break; + } break; default: if ((imm >> 5) == 0x09) { #ifdef DEBUG_EXTRA - dprintf(">>> SFENCE.VMA\n"); + debug_out(">>> SFENCE.VMA\n"); stats[62]++; #endif /* sfence.vma */ @@ -1797,11 +1766,10 @@ void execute_instruction() case 0x0f: /* MISC-MEM */ funct3 = (insn >> 12) & 7; - switch(funct3) { - + switch (funct3) { case 0: /* fence */ #ifdef DEBUG_EXTRA - dprintf(">>> FENCE\n"); + debug_out(">>> FENCE\n"); stats[37]++; #endif if (insn & 0xf00fff80) { @@ -1812,7 +1780,7 @@ void execute_instruction() case 1: /* fence.i */ #ifdef DEBUG_EXTRA - dprintf(">>> FENCE.I\n"); + debug_out(">>> FENCE.I\n"); stats[38]++; #endif if (insn != 0x0000100f) { @@ -1832,18 +1800,16 @@ void execute_instruction() case 0x2f: /* AMO */ funct3 = (insn >> 12) & 7; - switch(funct3) { - case 2: - { + switch (funct3) { + case 2: { uint32_t rval; addr = reg[rs1]; funct3 = insn >> 27; - switch(funct3) { - + switch (funct3) { case 2: /* lr.w */ #ifdef DEBUG_EXTRA - dprintf(">>> LR.W\n"); + debug_out(">>> LR.W\n"); stats[56]++; #endif if (rs2 != 0) { @@ -1854,13 +1820,13 @@ void execute_instruction() raise_exception(pending_exception, pending_tval); return; } - val = (int32_t)rval; + val = (int32_t) rval; load_res = addr; break; case 3: /* sc.w */ #ifdef DEBUG_EXTRA - dprintf(">>> SC.W\n"); + debug_out(">>> SC.W\n"); stats[57]++; #endif if (load_res == addr) { @@ -1874,27 +1840,27 @@ void execute_instruction() } break; - case 1: /* amiswap.w */ - case 0: /* amoadd.w */ - case 4: /* amoxor.w */ - case 0xc: /* amoand.w */ - case 0x8: /* amoor.w */ + case 1: /* amiswap.w */ + case 0: /* amoadd.w */ + case 4: /* amoxor.w */ + case 0xc: /* amoand.w */ + case 0x8: /* amoor.w */ case 0x10: /* amomin.w */ case 0x14: /* amomax.w */ case 0x18: /* amominu.w */ case 0x1c: /* amomaxu.w */ #ifdef DEBUG_EXTRA - dprintf(">>> AM...\n"); + debug_out(">>> AM...\n"); stats[63]++; #endif if (target_read_u32(&rval, addr)) { raise_exception(pending_exception, pending_tval); return; } - val = (int32_t)rval; + val = (int32_t) rval; val2 = reg[rs2]; - switch(funct3) { + switch (funct3) { case 1: /* amiswap.w */ break; case 0: /* amoadd.w */ @@ -1910,20 +1876,20 @@ void execute_instruction() val2 = (int32_t)(val | val2); break; case 0x10: /* amomin.w */ - if ((int32_t)val < (int32_t)val2) - val2 = (int32_t)val; + if ((int32_t) val < (int32_t) val2) + val2 = (int32_t) val; break; case 0x14: /* amomax.w */ - if ((int32_t)val > (int32_t)val2) - val2 = (int32_t)val; + if ((int32_t) val > (int32_t) val2) + val2 = (int32_t) val; break; case 0x18: /* amominu.w */ - if ((uint32_t)val < (uint32_t)val2) - val2 = (int32_t)val; + if ((uint32_t) val < (uint32_t) val2) + val2 = (int32_t) val; break; case 0x1c: /* amomaxu.w */ - if ((uint32_t)val > (uint32_t)val2) - val2 = (int32_t)val; + if ((uint32_t) val > (uint32_t) val2) + val2 = (int32_t) val; break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); @@ -1938,8 +1904,7 @@ void execute_instruction() raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; } - } - break; + } break; default: raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); return; @@ -2781,13 +2746,16 @@ int64_t get_clock() void riscv_cpu_interp_x32() { - /* we use a single execution loop to keep a simple control flow for emscripten */ + /* we use a single execution loop to keep a simple control flow for + * emscripten */ while (machine_running) { #if 1 - /* update timer, assuming 10 MHz clock (100 ns period) for the mtime counter */ + /* update timer, assuming 10 MHz clock (100 ns period) for the mtime + * counter */ mtime = get_clock() / 100ll; - /* for reproducible debug runs, you can use a fixed fixed increment per instruction */ + /* for reproducible debug runs, you can use a fixed fixed increment per + * instruction */ #else mtime += 10; #endif @@ -2808,60 +2776,33 @@ void riscv_cpu_interp_x32() if (insn_type == CINSN) next_pc = pc + 2; #endif - rd = 0; - break; - case 128: /* C.LQ*/ #ifdef DEBUG_EXTRA printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); #endif -#ifdef DEBUG_OUTPUT -#endif - rd = 0; - break; - } - { -#endif - (midpart >> 7) & 0xe | - (midpart << 1) & 0x10; - imm = (imm << 2) & 0x7f; - addr = reg[rs1] + imm; - uint32_t rval; - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t)rval; + insn_counter++; + + debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, + mtime, mtimecmp); + execute_instruction(); + } /* test for misaligned fetches , in order to match the compressed * instruction. */ if (next_pc & 0x1) { raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); } -<<<<<<< HEAD - break; - case 3: /* C.FLW C.LD*/ - { - switch(XLEN){ - case 64: -#ifdef DEBUG_EXTRA - dprintf(">>> C.FLW\n"); - stats[64+5]++; -#endif - dprintf("Unimp insn for rv64c\n"); -======= /* update current PC */ pc = next_pc; } + debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", + (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); +} + +int main(int argc, char **argv) +{ #ifdef DEBUG_OUTPUT -<<<<<<< HEAD - printf("done interp %lx int=%x mstatus=%lx prv=%d\n", - (uint64_t)insn_counter, mip & mie, (uint64_t)mstatus, - priv); - break; - } -======= FILE *fo; char *po, hex_file[100]; #endif @@ -2891,895 +2832,118 @@ void riscv_cpu_interp_x32() default: printf("Unknow argument: %s\n", optarg); break; ->>>>>>> Rework to a better style } - break; - case 4: /* Reserved */ -#ifdef DEBUG_EXTRA - dprintf(">>> Reserved_0\n"); - stats[64+7]++; -#endif - break; - case 5: /* C.FSD */ - { - switch(XLEN){ - case 32: - case 64: + } + if (elf_file == NULL) { + printf("missing ELF file\n"); + return 1; + } + + for (uint32_t u = 0; u < RAM_SIZE; u++) + ram[u] = 0; + + #ifdef DEBUG_EXTRA - dprintf(">>> C.FSD\n"); - stats[64+8]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unimp insn for rv32imc"); + init_stats(); #endif - break; - case 128: + + + /* open ELF file */ + elf_version(EV_CURRENT); + int fd = open(elf_file, O_RDONLY); + if (fd == -1) { + printf("can't open file %s\n", elf_file); + return 1; + } + Elf *elf = elf_begin(fd, ELF_C_READ, NULL); + + /* scan for symbol table */ + Elf_Scn *scn = NULL; + GElf_Shdr shdr; + while ((scn = elf_nextscn(elf, scn)) != NULL) { + gelf_getshdr(scn, &shdr); + if (shdr.sh_type == SHT_SYMTAB) { + Elf_Data *data = elf_getdata(scn, NULL); + int count = shdr.sh_size / shdr.sh_entsize; + for (int i = 0; i < count; i++) { + GElf_Sym sym; + gelf_getsym(data, i, &sym); + char *name = elf_strptr(elf, shdr.sh_link, sym.st_name); #ifdef DEBUG_EXTRA - dprintf(">>> C.SQ\n"); - stats[64+9]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unimp insn for rv32imc"); -#endif - break; - default: -#ifdef DEBUG_OUTPUT - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; + if (*name) + printf("sym '%s' %lx\n", name, sym.st_value); #endif - break; + if (strcmp(name, "begin_signature") == 0) { + begin_signature = sym.st_value; + } + if (strcmp(name, "end_signature") == 0) { + end_signature = sym.st_value; + } + + /* for compliance test */ + if (strcmp(name, "_start") == 0) { + start = sym.st_value; + } + + /* for zephyr */ + if (strcmp(name, "__reset") == 0) { + start = sym.st_value; + } + if (strcmp(name, "__irq_wrapper") == 0) { + mtvec = sym.st_value; + } } } - break; - case 6: - { -#ifdef DEBUG_EXTRA - dprintf(">>> C.SW\n"); - stats[64+10]++; -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rs2 = (midpart & 0x7) + 8; - imm = ((midpart >> 4) & 0x1) | - ((midpart >> 7) & 0xe) | - ((midpart << 1) & 0x10); - imm = (imm << 2) & 0x7f; - addr = reg[rs1] + imm; - val = reg[rs2]; - rd = 0; - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } -#ifdef DEBUG_OUTPUT - printf("rs1 : %d, rs2: %d, rd: %d, imm: %d\n", rs1, rs2, rd, imm); - printf("addr: %08x\n", addr); -#endif - } - break; - case 7: - { - switch(XLEN){ - case 32: -#ifdef DEBUG_EXTRA - dprintf(">>> C.FSW\n"); - stats[64+11]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unimp insn for rv32imc"); -#endif - break; - case 64: - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SD\n"); - stats[64+12]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn by rv32imc\n"); -#endif - break; - } - } - break; - default: - { - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - break; - } - if(rd != 0) - reg[rd] = val; - break; - case 1: - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch(funct3){ - case 0: /* C.NOP, C.ADDI */ - if( ((midpart >> 5) & 0x1f) == 0){ /* C.NOP*/ -#ifdef DEBUG_EXTRA - dprintf(">>> C.NOP\n"); - stats[64+13]++; -#endif - return; - } else { - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - val = reg[rs1] + imm; -#ifdef DEBUG_EXTRA - dprintf(">>> C.ADDI\n"); - stats[64+14]++; - printf("rd: %d, rs1: %d, imm: %d, reg[rd]: %d, val: %d\n", rd, rs1, imm, reg[rd], val); -#endif - }break; - case 1: /* C.JAL, C.ADDIW */ -#ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: - dprintf(">>> C.JAL\n"); - stats[64+15]++; - break; - case 64: - case 128: - dprintf(">>> C.ADDIW\n"); - stats[64+16]++; - break; - default: - dprintf(">>> Unknow XLEN\n"); - break; - } -#endif - switch(XLEN) { - case 32: - imm = (midpart & 0x400) | - ((midpart << 3) & 0x200) | - (midpart & 0x170) | - ((midpart << 2) & 0x40) | - (midpart & 0x20) | - ((midpart << 4) & 0x10) | - ((midpart >> 6) & 0x8) | - ((midpart >> 1) & 0x7); - imm = (imm << 1) & 0xfffe; - reg[1] = pc + 2; /* Store the link to x1 register */ - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - break; - case 64: - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = (midpart >> (11 - 5)) | - (midpart & 0x1f); - val = reg[rs1] + imm; - break; - } - break; - case 2: /* C.LI */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.LI\n"); - stats[64+17]++; -#endif - rs1 = rd = ((midpart >> 5) & 0x1f); - imm = ((midpart >> 5) & 0x20) | (midpart & 0x1f); - val = imm; - break; - case 3: /* C.ADDI16SP, C.LUI */ -#ifdef DEBUG_EXTRA - switch(rd){ - case 2: - dprintf(">>> C.ADDI16SP\n"); - stats[64+18]++; - break; - default: - dprintf(">>> C.LUI\n"); - stats[64+19]++; - break; - } -#endif - switch(rd){ /* C.ADDI16SP */ - case 2: - imm = ((midpart >> 4) & 0x1) | - ((midpart << 1) & 0x2) | - ((midpart >> 1) & 0x4) | - ((midpart << 2) & 0x18) | - ((midpart >> 5) & 0x20); - imm = (imm << 4 )<< (31 - 9) >> (31 - 9); - val = reg[rd] + imm; - break; - default: - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x20); - imm = ((imm << 12) & 0xfffff000); - imm = imm << 14 >> 14; - if(rd != 0) - val = reg[rd] | imm; - break; - } - break; - case 4: /* C.SRLI, C.SRLI64, C.SRAI, C.SRAI64, C.ANDI, C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW*/ - switch(((midpart >> 8) & 0x3)){ - case 0: /* C.SRLI C.SRLI64 */ -#ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: - case 64: - dprintf(">>> C.SRLI\n"); - stats[64+20]++; - break; - case 128: - dprintf(">>> C.SRLI64\n"); - stats[64+21]++; - break; - } -#endif - switch(XLEN){ - case 32: - case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | (midpart >> 5 & 0x10); - val = reg[rs1]; - break; - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; - break; - } - val = val >> imm; - break; - case 1: /* C.SRAI C.SRAI64 */ -#ifdef DEBUG_EXTRA - switch(XLEN){ - case 32: - case 64: - dprintf(">>> C.SRAI\n"); - stats[64+22]++; - break; - case 128: - dprintf(">>> C.SRAI64\n"); - stats[64+23]++; - break; - } -#endif - switch(XLEN){ - case 32: case 64: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = (midpart & 0xf) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - break; - case 128: - rs1 = rd = ((midpart >> 5) & 0x1f) + 8; - imm = 64; - val = reg[rs1]; - break; - } - val = val << imm; - break; - case 2: /* C.ANDI */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.ANDI\n"); - stats[64+24]++; -#endif - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - imm = (midpart & 0x1f) | ((midpart >> 5) & 0x10); - val = reg[rs1]; - val = val & imm; - break; - case 3: /* C.SUB, C.XOR, C.OR, C.AND, C.SUBW, C.ADDW */ - rs2 = (midpart & 0x7) + 8; - rs1 = rd = ((midpart >> 5) & 0x7) + 8; - switch(((midpart >> 3) & 0x3) | ((midpart >> 8) & 0x4) ){ - case 0: /* C.SUB */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SUB\n"); - stats[64+25]++; -#endif - val = reg[rd] - reg[rs2]; - break; - case 1: /* C.XOR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.XOR\n"); - stats[64+26]++; -#endif - val = reg[rd] ^ reg[rs2]; - break; - case 2: /* C.OR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.OR\n"); - stats[64+27]++; -#endif - val = reg[rd] | reg[rs2]; - //printf("reg[rd]: %08x, reg[rs2]: %08x\n", reg[rd], reg[rs2]); - break; - case 3: /* C.AND */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.AND\n"); - stats[64+28]++; -#endif - val = reg[rd] & reg[rs2]; - break; - case 4: /* C.SUBW */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SUBW\n"); - stats[64+29]++; -#endif - val = reg[rd] - reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - } - break; - case 5: /* C.ADDW */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.ADDW\n"); - stats[64+30]++; -#endif - val = reg[rd] + reg[rs2]; - if(XLEN == 128){ - val = (int32_t) (val << 96) >> 96; - }else if(XLEN == 64){ - val = (int32_t) (val << 32) >> 32; - }else{ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - } - break; - case 6: -#ifdef DEBUG_EXTRA - dprintf(">>> Reserved_1\n"); - stats[64+31]++; -#endif - case 7: -#ifdef DEBUG_EXTRA - dprintf(">>> Reserved_2\n"); - stats[64+32]++; -#endif - /* NOP */ - break; - } - } - break; - case 5: /* C.J */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.J\n"); - stats[64+33]++; -#endif - rd = 0; - imm = ((midpart >> 1) & 0x7) | - ((midpart >> 6) & 0x8) | - ((midpart << 5) & 0x10) | - ((midpart) & 0x20) | - ((midpart << 2) & 0x40) | - ((midpart) & 0x180)| - ((midpart << 3) & 0x200)| - ((midpart) & 0x400); - imm = (imm << 1) << 20 >> 20; - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - break; - case 6: /* C.BEQZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BEQZ\n"); - stats[64+34]++; -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - if(reg[rs1] == 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 3) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - } - break; - case 7: /* C.BNEZ */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.BNEZ\n"); - stats[64+35]++; -#endif - rs1 = ((midpart >> 5) & 0x7) + 8; - rd = 0; - imm = 0; - if(reg[rs1] != 0){ - imm = ((midpart >> 1) & 0x3) | - ((midpart >> 6) & 0xc) | - ((midpart << 4) & 0x10) | - ((midpart << 2) & 0x60) | - ((midpart) & 0x80); - imm = (imm << 1) << 23 >> 23; - next_pc = (int32_t)(pc + imm); - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - } -#ifdef DEBUG_OUTPUT - printf("rd : %d, rs1: %d, imm: %d, reg[rs1] : %d, pc: %08x, next_pc: %08x\n", rd, rs1, imm, reg[rs1]); -#endif - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if(rd != 0){ - reg[rd] = val; - } - break; - case 2: /* op 2*/ - funct3 = (insn >> 13) & 0x7; - midpart = (insn >> 2) & 0x07ff; - switch(funct3){ - case 0: /* C.SLLI, C.SLLI64*/ - { - imm = ((midpart >> 5 & 0x20) | (midpart & 0x1f)); - switch(XLEN){ - case 32: /* C.SLLI*/ - if(((midpart >> 10) & 0x1)){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - case 64: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SLLI\n"); - stats[64+36]++; -#endif - if(imm == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - imm = imm & 0x3f; - break; - case 128: /* C.SLLI64 */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.SLLI64\n"); - stats[64+37]++; -#endif - rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - imm = 64; - -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn by rv32imc\n"); -#endif - break; - } - if(rd != 0) - val = (uint32_t) reg[rd] << imm; - } - break; - case 1: /* C.FLDSP C.LQSP*/ - { - switch(XLEN){ - case 32: - case 64: /* C.FLDSP */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.FLDSP\n");\ - stats[64+38]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported extension by rv32imc"); -#endif - break; - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.LQSP\n"); - stats[64+39]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("unsupported extension by rv32imc"); -#endif - break; - } - - } - break; - case 2: /* C.LWSP C.FLWSP*/ - { -#ifdef DEBUG_EXTRA - dprintf(">>> C.LWSP\n"); - stats[64+40]++; -#endif - rd = ((midpart >> 5) & 0x1f); - if(rd == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - imm = ((midpart >> 2) & 0x7) | - ((midpart >> 7) & 0x8) | - ((midpart << 4) & 0x30); - imm = (imm << 2) & 0xff; - rs1 = 2; - addr = reg[rs1] + imm; - uint32_t rval; - if (target_read_u32(&rval, addr)) { - raise_exception(pending_exception, pending_tval); - return; - } - val = (int32_t)rval; -#ifdef DEBUG_OUTPUT -#endif - } - break; - case 3: /* C.FLWSP C.LDSP*/ - { - switch(XLEN){ - case 32: - case 64: /* C.FLWSP */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.FLWSP\n"); - stats[64+41]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported extension by rv32imc"); -#endif - break; - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.LDSP\n"); - stats[64+42]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("unsupported extension by rv32imc"); -#endif - break; - } - - } - break; - case 4: /* C.JR C.MV C.EBREAK C.JALR C.ADD */ - { - rd = 0; - rs1 = (midpart >> 5) & 0x1f; - rs2 = (midpart & 0x1f); - switch((midpart >> 10) & 0x1){ - case 0: - if(rs2 == 0){ /* C.JR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.JR\n"); - stats[64+43]++; -#endif - next_pc = reg[rs1]; - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - -#ifdef DEBUG_OUTPUT - printf("rs1: %d, rs2: %d, rd: %d\n", rs1, rs2, rd); -#endif - }else{ /* C.MV */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.MV\n"); - stats[64+44]++; -#endif - rd = rs1; - if(rd + rs1 + rs2 == 0){ - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - val = reg[rs2]; - } - break; - case 1: - if(rs1 == 0 && rs2 == 0){ /* C.EBREAK */ -#ifdef DEBUG_EXTRA - dprintf(">>> EBREAK\n"); - stats[64+45]++; -#endif - raise_exception(CAUSE_BREAKPOINT, 0); - return; - }else if(rs2 == 0 && rs1 != 0){ /* C.JALR */ -#ifdef DEBUG_EXTRA - dprintf(">>> C.JALR\n"); - stats[64+46]++; -#endif - rd = 1; - imm = reg[rs1]; - next_pc = reg[rs1]; - val = pc + 2; - if(next_pc > pc) forward_counter++; - else backward_counter++; - jump_counter++; - }else if(rs2 != 0 && rs1 != 0){ /* C.ADD */ - rd = rs1; - val = reg[rs1] + reg[rs2]; - } - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - } - break; - case 5: /* C.FSDSP C.SQSP*/ - { - switch(XLEN){ - case 32: - case 64: -#ifdef DEBUG_EXTRA - dprintf(">>> C.FSDS{\n"); - stats[64+47]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); -#endif - break; - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SQSP\n"); - stats[64+48]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); -#endif - break; - } - } - break; - case 6: /* C.SWSP*/ - { -#ifdef DEBUG_EXTRA - dprintf(">>> C.SWSP\n"); - stats[64+49]++; -#endif - rd = 0; - rs2 = midpart & 0x1f; - imm = ((midpart >> 2) & 0x1e0) | - ((midpart << 4) & 0x600); - imm = (imm >> 3) & 0xff; - addr = reg[2] + imm; - val = reg[rs2]; -#ifdef DEBUG_OUTPUT - printf("rs2: %d, imm: %d, addr: %08x\n", rs2, imm, addr); -#endif - if (target_write_u32(addr, val)) { - raise_exception(pending_exception, pending_tval); - return; - } - break; - } - break; - case 7: /* C.FSWSP C.SDSP */ - { - switch(XLEN){ - case 32: -#ifdef DEBUG_EXTRA - dprintf(">>> C.FSWSP\n"); - stats[64+50]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); -#endif - break; - case 64: - case 128: -#ifdef DEBUG_EXTRA - dprintf(">>> C.SDSP\n"); - stats[64+51]++; -#endif -#ifdef DEBUG_OUTPUT - dprintf("Unsupported insn of rv32imc\n"); -#endif - break; - } - } - break; - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } - if(rd != 0) - reg[rd] = val; - break; -#endif - default: - raise_exception(CAUSE_ILLEGAL_INSTRUCTION, insn); - return; - } -} - -/* returns realtime in nanoseconds */ -int64_t get_clock() -{ - struct timespec ts; - clock_gettime(CLOCK_MONOTONIC, &ts); - return ts.tv_sec * 1000000000LL + ts.tv_nsec; -} - - -void riscv_cpu_interp_x32() -{ - /* we use a single execution loop to keep a simple control flow for - * emscripten */ - while (machine_running) { -#if 1 - /* update timer, assuming 10 MHz clock (100 ns period) for the mtime - * counter */ - mtime = get_clock() / 100ll; - - /* for reproducible debug runs, you can use a fixed fixed increment per - * instruction */ -#else - mtime += 10; -#endif - /* default value for next PC is next instruction, can be changed by - * branches or exceptions */ - next_pc = pc + 4; - - /* test for timer interrupt */ - if (mtimecmp <= mtime) { - mip |= MIP_MTIP; - } - if ((mip & mie) != 0 && (mstatus & MSTATUS_MIE)) { - raise_interrupt(); - } else { - /* Compressed or normal */ - insn_type = get_insn32(pc, &insn); -#ifdef RV32C - if(insn_type == CINSN) - next_pc = pc + 2; -#endif -#ifdef DEBUG_EXTRA - printf("insn_type : %s\n", insn_type == CINSN ? "CINSN" : "INSN"); -#endif - insn_counter++; - - debug_out("[%08x]=%08x, mtime: %lx, mtimecmp: %lx\n", pc, insn, - mtime, mtimecmp); - execute_instruction(); - } - - /* test for misaligned fetches , in order to match the compressed instruction. */ - if (next_pc & 0x1) { - raise_exception(CAUSE_MISALIGNED_FETCH, next_pc); - } - - /* update current PC */ - pc = next_pc; - } - - debug_out("done interp %lx int=%x mstatus=%lx prv=%d\n", - (uint64_t) insn_counter, mip & mie, (uint64_t) mstatus, priv); -} - -int main(int argc, char **argv) -{ -#ifdef DEBUG_OUTPUT - FILE *fo; - char *po, hex_file[100]; -#endif - - /* automatic STDOUT flushing, no fflush needed */ - setvbuf(stdout, NULL, _IONBF, 0); - /* parse command line */ - const char* elf_file = NULL; - const char* signature_file = NULL; - const char* output_file = NULL; - int cmd_opt = 0; - struct option opts[] = { - {"elf", 1, NULL, 'e'}, - {"signature", 1, NULL, 's'}, - {"output", 1, NULL, 'o'} - }; - const char* optstring = "e:s:o:"; - while((cmd_opt = getopt_long(argc, argv, optstring, opts, NULL)) != -1){ - switch(cmd_opt){ - case 'e': - elf_file = optarg; - break; - case 's': - signature_file = optarg; - break; - case 'o': - output_file = optarg; - break; - default: - printf("Unknow argument: %s\n", optarg); - break; - } - } - if (elf_file == NULL) { - printf("missing ELF file\n"); - return 1; - } - - for(uint32_t u=0;u= ram_start) { for (size_t i = 0; i < shdr.sh_size; i++) { ram_curr = shdr.sh_addr + i - ram_start; - if(ram_curr >= RAM_SIZE) - { -#ifdef DEBUG_OUTPUT - printf("memory pointer outside of range 0x%08x (section at address 0x%08x)\n", ram_curr, (uint32_t) shdr.sh_addr); -#endif + if (ram_curr >= RAM_SIZE) { + debug_out( + "memory pointer outside of range 0x%08x (section " + "at address 0x%08x)\n", + ram_curr, (uint32_t) shdr.sh_addr); /* break; */ - } - else - { - ram[ram_curr] = ((uint8_t *)data->d_buf)[i]; - if(ram_curr > ram_last) ram_last = ram_curr; + } else { + ram[ram_curr] = ((uint8_t *) data->d_buf)[i]; + if (ram_curr > ram_last) + ram_last = ram_curr; } } } else { -#ifdef DEBUG_OUTPUT - printf("ignoring section at address 0x%08x\n", (uint32_t) shdr.sh_addr); -#endif + debug_out("ignoring section at address 0x%08x\n", + (uint32_t) shdr.sh_addr); } } } @@ -3789,54 +2953,56 @@ int main(int argc, char **argv) close(fd); #ifdef DEBUG_OUTPUT - printf("codesize: 0x%08x (%i)\n", ram_last+1, ram_last+1); + printf("codesize: 0x%08x (%i)\n", ram_last + 1, ram_last + 1); strcpy(hex_file, elf_file); - po = strrchr(hex_file,'.'); - if(po!=NULL) *po = 0; - strcat(hex_file,".mem"); - fo = fopen(hex_file,"wt"); - if(fo!=NULL) - { - for(uint32_t u=0;u<=ram_last;u++) - { - fprintf(fo,"%02X ",ram[u]); - if((u&15)==15) fprintf(fo,"\n"); - } - fprintf(fo,"\n"); - fclose(fo); + po = strrchr(hex_file, '.'); + if (po != NULL) + *po = 0; + strcat(hex_file, ".mem"); + fo = fopen(hex_file, "wt"); + if (fo != NULL) { + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, "%02X ", ram[u]); + if ((u & 15) == 15) + fprintf(fo, "\n"); + } + fprintf(fo, "\n"); + fclose(fo); } #if 1 - fo = fopen("rom.v","wt"); - if(fo!=NULL) - { - fprintf(fo,"module rom(addr,data);\n"); - uint32_t romsz = (ram_start&0xFFFF) + ram_last + 1; - printf("codesize with offset: %i\n",romsz); - if(romsz >= 32768) - fprintf(fo,"input [15:0] addr;\n"); - else if(romsz >= 16384) - fprintf(fo,"input [14:0] addr;\n"); - else if(romsz >= 8192) - fprintf(fo,"input [13:0] addr;\n"); - else if(romsz >= 4096) - fprintf(fo,"input [12:0] addr;\n"); - else if(romsz >= 2048) - fprintf(fo,"input [11:0] addr;\n"); - else if(romsz >= 1024) - fprintf(fo,"input [10:0] addr;\n"); - else if(romsz >= 512) - fprintf(fo,"input [9:0] addr;\n"); - else if(romsz >= 256) - fprintf(fo,"input [8:0] addr;\n"); - else - fprintf(fo,"input [7:0] addr;\n"); - fprintf(fo,"output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); - for(uint32_t u=0;u<=ram_last;u++) - { - fprintf(fo," %i : data = 8'h%02X;\n",(ram_start&0xFFFF)+u,ram[u]); - } - fprintf(fo," default: data = 8'h01; // invalid instruction\n endcase\nend\nendmodule\n"); - fclose(fo); + fo = fopen("rom.v", "wt"); + if (fo != NULL) { + fprintf(fo, "module rom(addr,data);\n"); + uint32_t romsz = (ram_start & 0xFFFF) + ram_last + 1; + printf("codesize with offset: %i\n", romsz); + if (romsz >= 32768) + fprintf(fo, "input [15:0] addr;\n"); + else if (romsz >= 16384) + fprintf(fo, "input [14:0] addr;\n"); + else if (romsz >= 8192) + fprintf(fo, "input [13:0] addr;\n"); + else if (romsz >= 4096) + fprintf(fo, "input [12:0] addr;\n"); + else if (romsz >= 2048) + fprintf(fo, "input [11:0] addr;\n"); + else if (romsz >= 1024) + fprintf(fo, "input [10:0] addr;\n"); + else if (romsz >= 512) + fprintf(fo, "input [9:0] addr;\n"); + else if (romsz >= 256) + fprintf(fo, "input [8:0] addr;\n"); + else + fprintf(fo, "input [7:0] addr;\n"); + fprintf(fo, + "output reg [7:0] data;\nalways @(addr) begin\n case(addr)\n"); + for (uint32_t u = 0; u <= ram_last; u++) { + fprintf(fo, " %i : data = 8'h%02X;\n", (ram_start & 0xFFFF) + u, + ram[u]); + } + fprintf(fo, + " default: data = 8'h01; // invalid instruction\n " + "endcase\nend\nendmodule\n"); + fclose(fo); } #endif #endif @@ -3844,7 +3010,8 @@ int main(int argc, char **argv) uint64_t ns1 = get_clock(); /* run program in emulator */ - pc = start; + pc = ram_start; + /* Initialize the address of stack pointer*/ reg[2] = ram_start + RAM_SIZE; riscv_cpu_interp_x32(); @@ -3906,10 +3073,20 @@ int main(int argc, char **argv) #if 1 printf("\n"); - printf(">>> Execution time: %llu ns\n",(long long unsigned)ns2-ns1); - printf(">>> Instruction count: %llu (IPS=%llu)\n",(long long unsigned)insn_counter,(long long)insn_counter*1000000000LL/(ns2-ns1)); - printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n",(long long unsigned)jump_counter,jump_counter*100.0/insn_counter,(long long unsigned)forward_counter,(long long unsigned)backward_counter); - printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n",(long long unsigned)true_counter,true_counter*100.0/(true_counter+false_counter),(long long unsigned)false_counter,false_counter*100.0/(true_counter+false_counter)); + printf(">>> Execution time: %llu ns\n", (long long unsigned) ns2 - ns1); + printf(">>> Instruction count: %llu (IPS=%llu)\n", + (long long unsigned) insn_counter, + (long long) insn_counter * 1000000000LL / (ns2 - ns1)); + printf(">>> Jumps: %llu (%2.2lf%%) - %llu forwards, %llu backwards\n", + (long long unsigned) jump_counter, + jump_counter * 100.0 / insn_counter, + (long long unsigned) forward_counter, + (long long unsigned) backward_counter); + printf(">>> Branching T=%llu (%2.2lf%%) F=%llu (%2.2lf%%)\n", + (long long unsigned) true_counter, + true_counter * 100.0 / (true_counter + false_counter), + (long long unsigned) false_counter, + false_counter * 100.0 / (true_counter + false_counter)); printf("\n"); #endif return 0;