ptl: increase the number of L2 page tables

With userspace enabled we easily use up the currently configured for
ACE 3.0 by Zephyr 64 L2 page tables when running tests with multiple
pipelines on multiple cores with userspace enabled. Double the number
to cover current test cases.

Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>

Author: lyakh

app/boards/intel_adsp_ace30_ptl.conf

@@ -53,6 +53,7 @@ CONFIG_DMA_DW_LLI_POOL_SIZE=50
 CONFIG_MEMORY_WIN_2_SIZE=12288
 CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y
 CONFIG_MM_DRV_INTEL_VIRTUAL_REGION_COUNT=2
+CONFIG_XTENSA_MMU_NUM_L2_TABLES=128
 CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000
 
 # Zephyr / power settings