icarus-verilog

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Here are 83 public repositories matching this topic...

olofk / edalize

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An abstraction library for interfacing EDA tools

Updated Sep 23, 2025
Python

dpretet / async_fifo

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A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

asic fpga async verification verilog synthesis icarus-verilog fifo cdc hdl verilog-hdl fifo-queue fifo-cache verilator asic-design cross-clock-domain

Updated Sep 16, 2025
Verilog

mshr-h / vscode-verilog-hdl-support

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HDL support for VS Code

ctags vscode verilog vivado systemverilog icarus-verilog modelsim hacktoberfest verilog-hdl iverilog bluespec-systemverilog verilator language-server-client systemverilog-support svls

Updated Oct 6, 2025
TypeScript

stnolting / neorv32-verilog

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♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

asic fpga verilog icarus-verilog ghdl neorv32

Updated Oct 6, 2025
VHDL

scarv / xcrypto

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XCrypto: a cryptographic ISE for RISC-V

open-source cryptography cpu crypto hardware riscv verilog research-project mit-license ise icarus-verilog hardware-acceleration formal-verification yosys instruction-set-architecture risc-v xcrypto

Updated Jan 5, 2023
Verilog

unixb0y / SystemVerilogSHA256

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SHA256 in (System-) Verilog / Open Source FPGA Miner

fpga bitcoin mining verilog sha256 systemverilog icarus-verilog

Updated Mar 10, 2018
SystemVerilog

dpretet / svut

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SVUT is a simple framework to create Verilog/SystemVerilog unit tests. Just focus on your tests!

python flow simulator tdd simulation foss verilog testcase tdd-utilities mit-license systemverilog icarus-verilog gtkwave verification-methodologies vcd verilator surfer svut

Updated Oct 22, 2024
Python

sgherbst / svreal

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Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

simulation verilog vcs synthesis vivado systemverilog fixed-point floating-point icarus-verilog iverilog icarus verilator xrun synthesizable xcelium irun ncsim

Updated Jan 13, 2021
SystemVerilog

albertxie / iverilog-tutorial

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Quickstart guide on Icarus Verilog.

verilog signal icarus-verilog gtkwave csc258

Updated Jun 18, 2020
Verilog

yasnakateb / PipelinedARM

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💎 A 32-bit ARM Processor Implementation in Verilog HDL

arm cpu verilog icarus-verilog verilog-hdl iverilog arm-processor arm-pipeline

Updated Mar 21, 2022
Verilog

sifferman / fusesoc_template

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Example of how to get started with olofk/fusesoc.

vivado icestorm icarus-verilog yosys fusesoc tinyfpga-bx nexys-a7 nextpnr-ice40

Updated Jul 25, 2021
Python

aditeyabaral / DDCO-Lab-UE18CS207

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A repository containing the source codes for the Digital Design and Computer Organization Laboratory course (UE18CS2) at PES University.

verilog logic-programming icarus-verilog digital-design computer-organization verilog-code

Updated Apr 17, 2020
Verilog

Elphel / vdt-plugin

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mirror of https://git.elphel.com/Elphel/vdt-plugin

eclipse ide eclipse-plugin verilog vivado icarus-verilog gtkwave quartus cocotb

Updated Nov 29, 2017
Java

esynr3z / pyhdlsim

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Example of Python and PyTest powered workflow for a HDL simulation

python asic fpga pytest rtl verilog icarus-verilog hdl modelsim system-verilog vivado-simulator

Updated Jan 17, 2021
Python

addisonElliott / SCIC

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Project of Addison Elliott and Dan Ashbaugh to create IC layout of 32-bit custom CPU used in teaching digital design at SIUE.

asic cpu digital simulation tcl rtl verilog synthesis icarus-verilog gate cadence

Updated Nov 29, 2018
Verilog

yasnakateb / NoCRouter

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🎞️ NoC router in Verilog with FIFO

router verilog icarus-verilog verilog-hdl iverilog

Updated Sep 1, 2022
Verilog

yasnakateb / PipelinedMIPS

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🔮 A 16-bit MIPS Processor Implementation in Verilog HDL

cpu pipeline mips verilog icarus-verilog verilog-hdl iverilog mips-processor mips-pipeline

Updated Aug 30, 2020
Verilog

TheOneKevin / icarusext

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iverilog extension for Visual Studio Code to satisfy the needs for an easy testbench runner. Includes builtin GTKWave support.

verilog vscode-extension icarus-verilog gtkwave verilog-testbenches

Updated Mar 4, 2023
TypeScript

SymbiFlow / XilinxUnisimLibrary

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Apache 2.0 licensed copy of the Xilinx Unisim library.

simulation xilinx vivado icarus-verilog icarus verilator

Updated Jul 22, 2020
Verilog

varkenvarken / robin

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SoC design targeted at the IceBreaker board

cpu processor verilog robin icestorm alu icarus-verilog soc yosys icestick icebreaker next-npr

Updated Mar 21, 2020
Assembly

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icarus-verilog

Here are 83 public repositories matching this topic...

olofk / edalize

dpretet / async_fifo

mshr-h / vscode-verilog-hdl-support

stnolting / neorv32-verilog

scarv / xcrypto

unixb0y / SystemVerilogSHA256

dpretet / svut

sgherbst / svreal

albertxie / iverilog-tutorial

yasnakateb / PipelinedARM

sifferman / fusesoc_template

aditeyabaral / DDCO-Lab-UE18CS207

Elphel / vdt-plugin

esynr3z / pyhdlsim

addisonElliott / SCIC

yasnakateb / NoCRouter

yasnakateb / PipelinedMIPS

TheOneKevin / icarusext

SymbiFlow / XilinxUnisimLibrary

varkenvarken / robin

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