Add all the Design Rule Checks for JLCPCB

[seveibar]

• JLCPCB Constraints: https://jlcpcb.com/capabilities/pcb-capabilities

• Drill Diameter Min/Max

• Pad Hole-to-Hole Spacing

• Edit this issue to add more!

Video explanation: https://drive.google.com/file/d/1jHbS8c4RvO7QbV5tgeG4wWfQVHfaKsl-/view?usp=drive_link

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Here's the list of KiCad rules with added descriptions:

• bus_definition_conflict - Detects conflicts in bus definitions, where the same bus name is defined differently in different parts of the schematic.

• bus_entry_needed - Identifies instances where a bus entry symbol is required but missing, typically when connecting a wire to a bus.

• bus_to_bus_conflict - Checks for conflicts between bus connections, such as mismatched bus widths or incompatible member nets.

• bus_to_net_conflict - Identifies conflicts between bus and individual net connections, like connecting a single wire to a multi-wire bus.

• conflicting_netclasses - Detects when a net is assigned to multiple, conflicting net classes.

• different_unit_footprint - Checks for inconsistencies in footprint assignments across different units of the same component.

• different_unit_net - Identifies cases where corresponding pins of different units of the same component are connected to different nets.

• duplicate_reference - Detects duplicate reference designators in the schematic, which should be unique for each component.

• duplicate_sheet_names - Checks for duplicate sheet names in a multi-sheet schematic, which can cause confusion and errors.

• endpoint_off_grid - Identifies wire or component endpoints that are not aligned to the schematic grid, potentially causing connection issues.

• extra_units - Detects when there are extra, unused units of multi-unit components in the schematic.

• global_label_dangling - Checks for global labels that are not connected to any nets or components.

• hier_label_mismatch - Identifies mismatches between hierarchical labels across different levels of the schematic hierarchy.

• label_dangling - Detects local labels that are not connected to any nets or components.

• lib_symbol_issues - Checks for various issues with library symbols, such as missing or incorrect properties.

• missing_bidi_pin - Identifies components that are missing expected bidirectional pins according to their symbol definition.

• missing_input_pin - Detects components that are missing expected input pins according to their symbol definition.

• missing_power_pin - Checks for components that are missing expected power pins according to their symbol definition.

• missing_unit - Identifies cases where a required unit of a multi-unit component is missing from the schematic.

• multiple_net_names - Detects when a single net has been assigned multiple names, which can lead to confusion and errors.

• net_not_bus_member - Checks for nets that are connected to a bus but not properly defined as members of that bus.

• no_connect_connected - Identifies no-connect symbols that are incorrectly connected to nets or components.

• no_connect_dangling - Detects no-connect symbols that are not properly attached to component pins.

• pin_not_connected - Checks for component pins that are not connected to any nets, which may indicate missing connections.

• pin_not_driven - Identifies input pins that are not driven by any output, which may indicate incomplete circuitry.

• pin_to_pin - Detects direct pin-to-pin connections without a wire, which can be error-prone and less visible.

• power_pin_not_driven - Checks for power pins that are not connected to appropriate power nets.

• similar_labels - Identifies labels with similar names, which could indicate potential typos or naming inconsistencies.

• simulation_model_issue - Detects issues with simulation models assigned to components, such as missing or incompatible models.

• unannotated - Checks for components that have not been annotated with unique reference designators.

• unit_value_mismatch - Identifies inconsistencies in unit values across different instances of the same component.

• unresolved_variable - Detects use of unresolved variables in component properties or other schematic elements.

• wire_dangling - Checks for wires that are not properly connected at both ends, potentially indicating incomplete connections.

[homie-gg]

Here are some pull requests that might be helpful reference for this task:

• fix pcb prop being required for constraints, add edgeToEdge, centerToCenter and other constraint properties to clarify application
• allow holes to be constrained, add typechecking on CI, implement ydist constraint solving, fix edgeToEdge constraint offset issue