From 09b28ce600174fab4ef399a0b3356ab83d3b3849 Mon Sep 17 00:00:00 2001 From: ShiboSoftwareDev Date: Sun, 8 Mar 2026 12:40:34 +0200 Subject: [PATCH 1/3] Add source_component_pins_underspecified_error Check --- README.md | 3 +- index.ts | 1 + ...ll-pins-in-component-are-underspecified.ts | 74 +++++++++++++++ lib/run-all-checks.ts | 6 +- package.json | 2 +- ...ns-in-component-are-underspecified.test.ts | 95 +++++++++++++++++++ tests/lib/run-all-checks.test.ts | 8 ++ tests/lib/user-circuit-netlist.test.tsx | 24 ++++- 8 files changed, 208 insertions(+), 5 deletions(-) create mode 100644 lib/check-all-pins-in-component-are-underspecified.ts create mode 100644 tests/lib/check-all-pins-in-component-are-underspecified.test.ts diff --git a/README.md b/README.md index b63b21f..d465ce6 100644 --- a/README.md +++ b/README.md @@ -10,6 +10,7 @@ and output an array of arrays for any issues found. | Function | Description | | --- | --- | | [`checkConnectorAccessibleOrientation`](./lib/check-connector-accessible-orientation.ts) | Returns `pcb_accessibility_error` for connectors whose orientation makes them inaccessible. | +| [`checkAllPinsInComponentAreUnderspecified`](./lib/check-all-pins-in-component-are-underspecified.ts) | Returns `source_component_pins_underspecified_error` when every pin on a component lacks pin attributes. | | [`checkDifferentNetViaSpacing`](./lib/check-different-net-via-spacing.ts) | Returns `pcb_via_clearance_error` if vias on different nets are too close together. | | [`checkEachPcbPortConnectedToPcbTraces`](./lib/check-each-pcb-port-connected-to-pcb-trace.ts) | Returns `pcb_trace_error` if any `source_port` is not connected to its corresponding PCB traces. | | [`checkEachPcbTraceNonOverlapping`](./lib/check-each-pcb-trace-non-overlapping/check-each-pcb-trace-non-overlapping.ts) | Returns `pcb_trace_error` when `pcb_trace` segments overlap incompatible geometry on the same layer. | @@ -27,7 +28,7 @@ and output an array of arrays for any issues found. | Function | Description | | --- | --- | | [`runAllPlacementChecks`](./lib/run-all-checks.ts) | Runs all placement checks (`checkViasOffBoard`, `checkPcbComponentsOutOfBoard`, `checkPcbComponentOverlap`, and `checkConnectorAccessibleOrientation`). | -| [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs all netlist checks (`checkPinMustBeConnected`). | +| [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs all netlist checks (`checkPinMustBeConnected` and `checkAllPinsInComponentAreUnderspecified`). | | [`runAllRoutingChecks`](./lib/run-all-checks.ts) | Runs all routing checks currently enabled (`checkEachPcbPortConnectedToPcbTraces`, `checkSourceTracesHavePcbTraces`, `checkEachPcbTraceNonOverlapping`, same/different net via spacing, and `checkPcbTracesOutOfBoard`). | | [`runAllChecks`](./lib/run-all-checks.ts) | Runs all placement, netlist, and routing checks and returns a combined list of errors. | diff --git a/index.ts b/index.ts index cd67a83..e6f8f1d 100644 --- a/index.ts +++ b/index.ts @@ -9,6 +9,7 @@ export { checkSourceTracesHavePcbTraces } from "./lib/check-source-traces-have-p export { checkPcbTracesOutOfBoard } from "./lib/check-trace-out-of-board/checkTraceOutOfBoard" export { checkPcbComponentOverlap } from "./lib/check-pcb-components-overlap/checkPcbComponentOverlap" export { checkPinMustBeConnected } from "./lib/check-pin-must-be-connected" +export { checkAllPinsInComponentAreUnderspecified } from "./lib/check-all-pins-in-component-are-underspecified" export { runAllChecks, runAllNetlistChecks, diff --git a/lib/check-all-pins-in-component-are-underspecified.ts b/lib/check-all-pins-in-component-are-underspecified.ts new file mode 100644 index 0000000..e9409ad --- /dev/null +++ b/lib/check-all-pins-in-component-are-underspecified.ts @@ -0,0 +1,74 @@ +import { cju } from "@tscircuit/circuit-json-util" +import type { + AnyCircuitElement, + SourcePinAttributes, + SourcePort, +} from "circuit-json" +import { source_pin_attributes } from "circuit-json" + +type SourceComponent = Extract + +type SourceComponentPinsUnderspecifiedError = { + type: "source_component_pins_underspecified_error" + source_component_pins_underspecified_error_id: string + error_type: "source_component_pins_underspecified_error" + message: string + source_component_id: string + source_port_ids: string[] + subcircuit_id?: string +} + +const PIN_ATTRIBUTE_KEYS = Object.keys( + source_pin_attributes.shape, +) as (keyof SourcePinAttributes)[] + +function hasAnyPinAttribute(port: SourcePort): boolean { + return PIN_ATTRIBUTE_KEYS.some((key) => port[key] !== undefined) +} + +/** + * Check that each component with ports has at least one pin attribute + * specified across its ports. Returns an error when all pins are + * underspecified (no SourcePinAttributes fields set on any port). + */ +export function checkAllPinsInComponentAreUnderspecified( + circuitJson: AnyCircuitElement[], +): SourceComponentPinsUnderspecifiedError[] { + const errors: SourceComponentPinsUnderspecifiedError[] = [] + const db = cju(circuitJson) + + const sourceComponents = db.source_component.list() as SourceComponent[] + const sourcePorts = db.source_port.list() as SourcePort[] + + const portsByComponent = new Map() + for (const port of sourcePorts) { + if (!port.source_component_id) continue + const existing = portsByComponent.get(port.source_component_id) ?? [] + existing.push(port) + portsByComponent.set(port.source_component_id, existing) + } + + for (const component of sourceComponents) { + const componentPorts = + portsByComponent.get(component.source_component_id) ?? [] + if (componentPorts.length === 0) continue + + const hasAnySpecifiedAttributes = componentPorts.some((port) => + hasAnyPinAttribute(port), + ) + + if (hasAnySpecifiedAttributes) continue + + errors.push({ + type: "source_component_pins_underspecified_error", + source_component_pins_underspecified_error_id: `source_component_pins_underspecified_error_${component.source_component_id}`, + error_type: "source_component_pins_underspecified_error", + message: `All pins on ${component.name} are underspecified (no pinAttributes set)`, + source_component_id: component.source_component_id, + source_port_ids: componentPorts.map((port) => port.source_port_id), + subcircuit_id: componentPorts[0]?.subcircuit_id, + }) + } + + return errors +} diff --git a/lib/run-all-checks.ts b/lib/run-all-checks.ts index b73bd1f..7e2898b 100644 --- a/lib/run-all-checks.ts +++ b/lib/run-all-checks.ts @@ -1,4 +1,5 @@ import type { AnyCircuitElement } from "circuit-json" +import { checkAllPinsInComponentAreUnderspecified } from "./check-all-pins-in-component-are-underspecified" import { checkDifferentNetViaSpacing } from "./check-different-net-via-spacing" import { checkEachPcbPortConnectedToPcbTraces } from "./check-each-pcb-port-connected-to-pcb-trace" import { checkEachPcbTraceNonOverlapping } from "./check-each-pcb-trace-non-overlapping/check-each-pcb-trace-non-overlapping" @@ -22,7 +23,10 @@ export async function runAllPlacementChecks(circuitJson: AnyCircuitElement[]) { } export async function runAllNetlistChecks(circuitJson: AnyCircuitElement[]) { - return [...checkPinMustBeConnected(circuitJson)] + return [ + ...checkPinMustBeConnected(circuitJson), + ...checkAllPinsInComponentAreUnderspecified(circuitJson), + ] } export async function runAllRoutingChecks(circuitJson: AnyCircuitElement[]) { diff --git a/package.json b/package.json index 298efce..5564fa7 100644 --- a/package.json +++ b/package.json @@ -19,7 +19,7 @@ "@types/debug": "^4.1.12", "bun-match-svg": "^0.0.11", "circuit-to-svg": "^0.0.333", - "circuit-json": "^0.0.391", + "circuit-json": "^0.0.392", "debug": "^4.3.5", "tscircuit": "^0.0.1439", "zod": "^3.23.8", diff --git a/tests/lib/check-all-pins-in-component-are-underspecified.test.ts b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts new file mode 100644 index 0000000..42c2430 --- /dev/null +++ b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts @@ -0,0 +1,95 @@ +import { describe, expect, test } from "bun:test" +import type { AnyCircuitElement } from "circuit-json" +import { checkAllPinsInComponentAreUnderspecified } from "lib/check-all-pins-in-component-are-underspecified" + +describe("checkAllPinsInComponentAreUnderspecified", () => { + test("returns an error when all ports on a component are missing pinAttributes", () => { + const circuitJson: AnyCircuitElement[] = [ + { + type: "source_component", + source_component_id: "component_1", + name: "U1", + ftype: "simple_chip", + }, + { + type: "source_port", + source_port_id: "port_1", + source_component_id: "component_1", + name: "IO1", + }, + { + type: "source_port", + source_port_id: "port_2", + source_component_id: "component_1", + name: "IO2", + }, + ] + + const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(errors).toHaveLength(1) + expect(errors[0].source_component_id).toBe("component_1") + expect(errors[0].source_port_ids).toEqual(["port_1", "port_2"]) + expect(errors[0].message).toContain("All pins on U1 are underspecified") + }) + + test("returns no error when at least one port on a component has pinAttributes", () => { + const circuitJson: AnyCircuitElement[] = [ + { + type: "source_component", + source_component_id: "component_1", + name: "U1", + ftype: "simple_chip", + }, + { + type: "source_port", + source_port_id: "port_1", + source_component_id: "component_1", + name: "IO1", + }, + { + type: "source_port", + source_port_id: "port_2", + source_component_id: "component_1", + name: "IO2", + must_be_connected: false, + }, + ] + + const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(errors).toHaveLength(0) + }) + + test("only returns errors for components whose all ports are underspecified", () => { + const circuitJson: AnyCircuitElement[] = [ + { + type: "source_component", + source_component_id: "component_1", + name: "U1", + ftype: "simple_chip", + }, + { + type: "source_component", + source_component_id: "component_2", + name: "U2", + ftype: "simple_chip", + }, + { + type: "source_port", + source_port_id: "u1_port_1", + source_component_id: "component_1", + name: "IO1", + }, + { + type: "source_port", + source_port_id: "u2_port_1", + source_component_id: "component_2", + name: "IO1", + provides_power: true, + }, + ] + + const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(errors).toHaveLength(1) + expect(errors[0].source_component_id).toBe("component_1") + }) +}) diff --git a/tests/lib/run-all-checks.test.ts b/tests/lib/run-all-checks.test.ts index 7f9b2dc..ce92933 100644 --- a/tests/lib/run-all-checks.test.ts +++ b/tests/lib/run-all-checks.test.ts @@ -26,6 +26,7 @@ test("runAllChecks executes checks on tscircuit code", async () => { pin_number: 1, port_hints: ["1"], source_component_id: "R1", + must_be_connected: false, }, { type: "source_port", @@ -34,6 +35,7 @@ test("runAllChecks executes checks on tscircuit code", async () => { pin_number: 2, port_hints: ["2"], source_component_id: "R1", + must_be_connected: false, }, ] @@ -59,6 +61,7 @@ test("runAllNetlistChecks excludes routing-only pcb trace connectivity checks", name: "pin1", pin_number: 1, port_hints: ["1"], + must_be_connected: false, }, { type: "source_port", @@ -67,6 +70,7 @@ test("runAllNetlistChecks excludes routing-only pcb trace connectivity checks", name: "pin2", pin_number: 2, port_hints: ["2"], + must_be_connected: false, }, { type: "source_trace", @@ -120,6 +124,7 @@ test("runAllChecks equals placement + netlist + routing checks", async () => { name: "pin1", pin_number: 1, port_hints: ["1"], + must_be_connected: false, }, { type: "source_port", @@ -128,6 +133,7 @@ test("runAllChecks equals placement + netlist + routing checks", async () => { name: "pin2", pin_number: 2, port_hints: ["2"], + must_be_connected: false, }, { type: "pcb_port", @@ -205,6 +211,7 @@ test("runAllChecks error messages never expose circuit-json ids", async () => { name: "pin1", pin_number: 1, port_hints: ["1"], + must_be_connected: false, }, { type: "source_port", @@ -213,6 +220,7 @@ test("runAllChecks error messages never expose circuit-json ids", async () => { name: "pin2", pin_number: 2, port_hints: ["2"], + must_be_connected: false, }, { type: "pcb_port", diff --git a/tests/lib/user-circuit-netlist.test.tsx b/tests/lib/user-circuit-netlist.test.tsx index 2e98dd1..cc712d0 100644 --- a/tests/lib/user-circuit-netlist.test.tsx +++ b/tests/lib/user-circuit-netlist.test.tsx @@ -63,6 +63,9 @@ test("test.tsx builds and has no netlist errors", async () => { { pcbY={-10} schX={-4} /> - - + + From 09feca009f36b97854da9e2dc06ee65b7ebe7c6f Mon Sep 17 00:00:00 2001 From: ShiboSoftwareDev Date: Mon, 9 Mar 2026 23:02:09 +0200 Subject: [PATCH 2/3] only chip --- ...ll-pins-in-component-are-underspecified.ts | 2 ++ ...ns-in-component-are-underspecified.test.ts | 27 +++++++++++++++++++ tests/lib/run-all-checks.test.ts | 8 ------ tests/lib/user-circuit-netlist.test.tsx | 21 ++------------- 4 files changed, 31 insertions(+), 27 deletions(-) diff --git a/lib/check-all-pins-in-component-are-underspecified.ts b/lib/check-all-pins-in-component-are-underspecified.ts index e9409ad..22d1e19 100644 --- a/lib/check-all-pins-in-component-are-underspecified.ts +++ b/lib/check-all-pins-in-component-are-underspecified.ts @@ -49,6 +49,8 @@ export function checkAllPinsInComponentAreUnderspecified( } for (const component of sourceComponents) { + if (component.ftype !== "simple_chip") continue + const componentPorts = portsByComponent.get(component.source_component_id) ?? [] if (componentPorts.length === 0) continue diff --git a/tests/lib/check-all-pins-in-component-are-underspecified.test.ts b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts index 42c2430..bfaec44 100644 --- a/tests/lib/check-all-pins-in-component-are-underspecified.test.ts +++ b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts @@ -92,4 +92,31 @@ describe("checkAllPinsInComponentAreUnderspecified", () => { expect(errors).toHaveLength(1) expect(errors[0].source_component_id).toBe("component_1") }) + + test("ignores non-chip components", () => { + const circuitJson: AnyCircuitElement[] = [ + { + type: "source_component", + source_component_id: "component_1", + name: "R1", + ftype: "simple_resistor", + resistance: 1000, + }, + { + type: "source_port", + source_port_id: "port_1", + source_component_id: "component_1", + name: "pos", + }, + { + type: "source_port", + source_port_id: "port_2", + source_component_id: "component_1", + name: "neg", + }, + ] + + const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(errors).toHaveLength(0) + }) }) diff --git a/tests/lib/run-all-checks.test.ts b/tests/lib/run-all-checks.test.ts index ce92933..7f9b2dc 100644 --- a/tests/lib/run-all-checks.test.ts +++ b/tests/lib/run-all-checks.test.ts @@ -26,7 +26,6 @@ test("runAllChecks executes checks on tscircuit code", async () => { pin_number: 1, port_hints: ["1"], source_component_id: "R1", - must_be_connected: false, }, { type: "source_port", @@ -35,7 +34,6 @@ test("runAllChecks executes checks on tscircuit code", async () => { pin_number: 2, port_hints: ["2"], source_component_id: "R1", - must_be_connected: false, }, ] @@ -61,7 +59,6 @@ test("runAllNetlistChecks excludes routing-only pcb trace connectivity checks", name: "pin1", pin_number: 1, port_hints: ["1"], - must_be_connected: false, }, { type: "source_port", @@ -70,7 +67,6 @@ test("runAllNetlistChecks excludes routing-only pcb trace connectivity checks", name: "pin2", pin_number: 2, port_hints: ["2"], - must_be_connected: false, }, { type: "source_trace", @@ -124,7 +120,6 @@ test("runAllChecks equals placement + netlist + routing checks", async () => { name: "pin1", pin_number: 1, port_hints: ["1"], - must_be_connected: false, }, { type: "source_port", @@ -133,7 +128,6 @@ test("runAllChecks equals placement + netlist + routing checks", async () => { name: "pin2", pin_number: 2, port_hints: ["2"], - must_be_connected: false, }, { type: "pcb_port", @@ -211,7 +205,6 @@ test("runAllChecks error messages never expose circuit-json ids", async () => { name: "pin1", pin_number: 1, port_hints: ["1"], - must_be_connected: false, }, { type: "source_port", @@ -220,7 +213,6 @@ test("runAllChecks error messages never expose circuit-json ids", async () => { name: "pin2", pin_number: 2, port_hints: ["2"], - must_be_connected: false, }, { type: "pcb_port", diff --git a/tests/lib/user-circuit-netlist.test.tsx b/tests/lib/user-circuit-netlist.test.tsx index cc712d0..3716b5d 100644 --- a/tests/lib/user-circuit-netlist.test.tsx +++ b/tests/lib/user-circuit-netlist.test.tsx @@ -75,25 +75,8 @@ test("test.tsx builds and has no netlist errors", async () => { pcbY={-10} schX={-4} /> - - + + From e9947a3f181cbc22154d259e9014b8027e6cddaa Mon Sep 17 00:00:00 2001 From: ShiboSoftwareDev Date: Tue, 10 Mar 2026 00:22:57 +0200 Subject: [PATCH 3/3] change to warning --- README.md | 4 +-- ...ll-pins-in-component-are-underspecified.ts | 29 ++++++++------- ...ns-in-component-are-underspecified.test.ts | 36 +++++++++++-------- 3 files changed, 37 insertions(+), 32 deletions(-) diff --git a/README.md b/README.md index d465ce6..76c3ee8 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ and output an array of arrays for any issues found. | Function | Description | | --- | --- | | [`checkConnectorAccessibleOrientation`](./lib/check-connector-accessible-orientation.ts) | Returns `pcb_accessibility_error` for connectors whose orientation makes them inaccessible. | -| [`checkAllPinsInComponentAreUnderspecified`](./lib/check-all-pins-in-component-are-underspecified.ts) | Returns `source_component_pins_underspecified_error` when every pin on a component lacks pin attributes. | +| [`checkAllPinsInComponentAreUnderspecified`](./lib/check-all-pins-in-component-are-underspecified.ts) | Returns `source_component_pins_underspecified_warning` when every pin on a chip lacks pin attributes. | | [`checkDifferentNetViaSpacing`](./lib/check-different-net-via-spacing.ts) | Returns `pcb_via_clearance_error` if vias on different nets are too close together. | | [`checkEachPcbPortConnectedToPcbTraces`](./lib/check-each-pcb-port-connected-to-pcb-trace.ts) | Returns `pcb_trace_error` if any `source_port` is not connected to its corresponding PCB traces. | | [`checkEachPcbTraceNonOverlapping`](./lib/check-each-pcb-trace-non-overlapping/check-each-pcb-trace-non-overlapping.ts) | Returns `pcb_trace_error` when `pcb_trace` segments overlap incompatible geometry on the same layer. | @@ -28,7 +28,7 @@ and output an array of arrays for any issues found. | Function | Description | | --- | --- | | [`runAllPlacementChecks`](./lib/run-all-checks.ts) | Runs all placement checks (`checkViasOffBoard`, `checkPcbComponentsOutOfBoard`, `checkPcbComponentOverlap`, and `checkConnectorAccessibleOrientation`). | -| [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs all netlist checks (`checkPinMustBeConnected` and `checkAllPinsInComponentAreUnderspecified`). | +| [`runAllNetlistChecks`](./lib/run-all-checks.ts) | Runs all netlist checks (e.g. `checkPinMustBeConnected`, `checkAllPinsInComponentAreUnderspecified`). | | [`runAllRoutingChecks`](./lib/run-all-checks.ts) | Runs all routing checks currently enabled (`checkEachPcbPortConnectedToPcbTraces`, `checkSourceTracesHavePcbTraces`, `checkEachPcbTraceNonOverlapping`, same/different net via spacing, and `checkPcbTracesOutOfBoard`). | | [`runAllChecks`](./lib/run-all-checks.ts) | Runs all placement, netlist, and routing checks and returns a combined list of errors. | diff --git a/lib/check-all-pins-in-component-are-underspecified.ts b/lib/check-all-pins-in-component-are-underspecified.ts index 22d1e19..48e08c0 100644 --- a/lib/check-all-pins-in-component-are-underspecified.ts +++ b/lib/check-all-pins-in-component-are-underspecified.ts @@ -3,15 +3,14 @@ import type { AnyCircuitElement, SourcePinAttributes, SourcePort, + SourceComponentBase, } from "circuit-json" import { source_pin_attributes } from "circuit-json" -type SourceComponent = Extract - -type SourceComponentPinsUnderspecifiedError = { - type: "source_component_pins_underspecified_error" - source_component_pins_underspecified_error_id: string - error_type: "source_component_pins_underspecified_error" +type SourceComponentPinsUnderspecifiedWarning = { + type: "source_component_pins_underspecified_warning" + source_component_pins_underspecified_warning_id: string + warning_type: "source_component_pins_underspecified_warning" message: string source_component_id: string source_port_ids: string[] @@ -28,16 +27,16 @@ function hasAnyPinAttribute(port: SourcePort): boolean { /** * Check that each component with ports has at least one pin attribute - * specified across its ports. Returns an error when all pins are + * specified across its ports. Returns a warning when all pins are * underspecified (no SourcePinAttributes fields set on any port). */ export function checkAllPinsInComponentAreUnderspecified( circuitJson: AnyCircuitElement[], -): SourceComponentPinsUnderspecifiedError[] { - const errors: SourceComponentPinsUnderspecifiedError[] = [] +): SourceComponentPinsUnderspecifiedWarning[] { + const warnings: SourceComponentPinsUnderspecifiedWarning[] = [] const db = cju(circuitJson) - const sourceComponents = db.source_component.list() as SourceComponent[] + const sourceComponents = db.source_component.list() as SourceComponentBase[] const sourcePorts = db.source_port.list() as SourcePort[] const portsByComponent = new Map() @@ -61,10 +60,10 @@ export function checkAllPinsInComponentAreUnderspecified( if (hasAnySpecifiedAttributes) continue - errors.push({ - type: "source_component_pins_underspecified_error", - source_component_pins_underspecified_error_id: `source_component_pins_underspecified_error_${component.source_component_id}`, - error_type: "source_component_pins_underspecified_error", + warnings.push({ + type: "source_component_pins_underspecified_warning", + source_component_pins_underspecified_warning_id: `source_component_pins_underspecified_warning_${component.source_component_id}`, + warning_type: "source_component_pins_underspecified_warning", message: `All pins on ${component.name} are underspecified (no pinAttributes set)`, source_component_id: component.source_component_id, source_port_ids: componentPorts.map((port) => port.source_port_id), @@ -72,5 +71,5 @@ export function checkAllPinsInComponentAreUnderspecified( }) } - return errors + return warnings } diff --git a/tests/lib/check-all-pins-in-component-are-underspecified.test.ts b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts index bfaec44..4906ca4 100644 --- a/tests/lib/check-all-pins-in-component-are-underspecified.test.ts +++ b/tests/lib/check-all-pins-in-component-are-underspecified.test.ts @@ -3,7 +3,7 @@ import type { AnyCircuitElement } from "circuit-json" import { checkAllPinsInComponentAreUnderspecified } from "lib/check-all-pins-in-component-are-underspecified" describe("checkAllPinsInComponentAreUnderspecified", () => { - test("returns an error when all ports on a component are missing pinAttributes", () => { + test("returns a warning when all ports on a component are missing pinAttributes", () => { const circuitJson: AnyCircuitElement[] = [ { type: "source_component", @@ -25,14 +25,20 @@ describe("checkAllPinsInComponentAreUnderspecified", () => { }, ] - const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) - expect(errors).toHaveLength(1) - expect(errors[0].source_component_id).toBe("component_1") - expect(errors[0].source_port_ids).toEqual(["port_1", "port_2"]) - expect(errors[0].message).toContain("All pins on U1 are underspecified") + const warnings = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(warnings).toHaveLength(1) + expect(warnings[0].type).toBe( + "source_component_pins_underspecified_warning", + ) + expect(warnings[0].warning_type).toBe( + "source_component_pins_underspecified_warning", + ) + expect(warnings[0].source_component_id).toBe("component_1") + expect(warnings[0].source_port_ids).toEqual(["port_1", "port_2"]) + expect(warnings[0].message).toContain("All pins on U1 are underspecified") }) - test("returns no error when at least one port on a component has pinAttributes", () => { + test("returns no warning when at least one port on a component has pinAttributes", () => { const circuitJson: AnyCircuitElement[] = [ { type: "source_component", @@ -55,11 +61,11 @@ describe("checkAllPinsInComponentAreUnderspecified", () => { }, ] - const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) - expect(errors).toHaveLength(0) + const warnings = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(warnings).toHaveLength(0) }) - test("only returns errors for components whose all ports are underspecified", () => { + test("only returns warnings for components whose all ports are underspecified", () => { const circuitJson: AnyCircuitElement[] = [ { type: "source_component", @@ -88,9 +94,9 @@ describe("checkAllPinsInComponentAreUnderspecified", () => { }, ] - const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) - expect(errors).toHaveLength(1) - expect(errors[0].source_component_id).toBe("component_1") + const warnings = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(warnings).toHaveLength(1) + expect(warnings[0].source_component_id).toBe("component_1") }) test("ignores non-chip components", () => { @@ -116,7 +122,7 @@ describe("checkAllPinsInComponentAreUnderspecified", () => { }, ] - const errors = checkAllPinsInComponentAreUnderspecified(circuitJson) - expect(errors).toHaveLength(0) + const warnings = checkAllPinsInComponentAreUnderspecified(circuitJson) + expect(warnings).toHaveLength(0) }) })