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Description
Consider the following trace obtained from a simulation run of a digital circuit:
a+ -> (b+ || c+) -> a- -> b- -> c- -> a+ -> b+ -> c+ -> a- -> b- -> c-
Note, some of the events are known to be concurrent, because the time difference between them is too small for a proper causality, so essentially this is a labelled partial order.
In general there may be more than one simulation run, possibly activating different behavioural scenarios of the circuit under observation.
Can we use existing process mining tools (e.g., pgminer, genet, ProM or POD) to derive a compact model for the circuit behaviour? If not, what needs to be done?
P.S.: Why is this problem interesting? One possible application is circuit optimisation: start with an existing circuit implementing a particular specification, perform accurate analogue simulations and then build a simplified model of the circuit, hopefully leading to a simpler, more optimal implementation.
The simplification comes from the fact that analogue simulation reveals certain timing relations that exist in the physical system but are not captured in the specification. Such timing relations can often significantly reduce the reachable state space of the circuit.