[OpenSTA] Updated SDF Generation with Internal Registers

Fixed an issue with how the post-implementation SDF annotations are
generated for black boxes with internal registers on the input or output
ports (but not both).

When neither of the input or output ports are registered, then the
circuit would be fully combinatorial. This behavior is unchanged.

When both of the input and output ports are registered, then the input
ports would have setup and hold constraints. The output ports would have
clock to Q delays. This did not annotate correctly for multi-bit ports,
so I updated the code to apply the annotations per pin in the port.

When the input port is registered and the output port is not, then the
input ports would have setup and hold constraints; however originally
the output ports did not have clock to Q delays. In a black-box model,
the output ports would have a clock to Q delay equal to the clock to Q
delay of the input ports plus the combinatorial delays from the input
ports to the output ports. I have added this logic to the SDF generation
code to include these delays.

When the output port is registered and the input port is not, then the
output ports would have clock to Q delays (as normal); however
originally the input ports were not given setup or hold constraints
(these were applied to the output ports by how the architecture file
traditionally defines these ports). For a black-box, the input ports
would have setup and hold constraints, there is just a bit of delay
before the timing arc hits the registers. Added the proper setup and
hold constraints and applied port delays on the input ports equal to
their propagation delay to the output ports.

Author: AlexandreSinger