get rid of warnings during compiatlion

soheilshahrouz · soheilshahrouz · commit bfaa5eb8a32b · 2025-09-04T17:58:58.000-04:00
diff --git a/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp b/vpr/src/route/router_lookahead/router_lookahead_map_utils.cpp
@@ -482,7 +482,7 @@ t_chan_ipins_delays compute_router_chan_ipin_lookahead(int route_verbosity) {
 
     // We assume that the routing connectivity of each instance of a physical tile is the same,
     // and so only measure one instance of each type
-    for (int layer_num = 0; layer_num < device_ctx.grid.get_num_layers(); layer_num++) {
+    for (int layer_num = 0; layer_num < (int)device_ctx.grid.get_num_layers(); layer_num++) {
         for (const t_physical_tile_type& tile_type : device_ctx.physical_tile_types) {
             if (device_ctx.grid.num_instances(&tile_type, layer_num) == 0) {
                 continue;
@@ -756,7 +756,7 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length,
                 continue;
             }
             // TODO: Temporary - After testing benchmarks this can be deleted
-            VTR_ASSERT(rr_graph.node_layer(start_node) == from_layer_num);
+            VTR_ASSERT(rr_graph.node_layer(start_node) == (int)from_layer_num);
 
             sample_nodes.emplace_back(start_node);
         }
@@ -767,13 +767,13 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length,
     //This is to ensure we sample 'unusual' wire types which may not exist in all channels
     //(e.g. clock routing)
     if (sample_nodes.empty()) {
-        //Try an exhaustive search to find a suitable sample point
+        // Try an exhaustive search to find a suitable sample point
         for (RRNodeId rr_node : rr_graph.nodes()) {
-            auto rr_type = rr_graph.node_type(rr_node);
+            e_rr_type rr_type = rr_graph.node_type(rr_node);
             if (rr_type != chan_type) continue;
-            if (rr_graph.node_layer(rr_node) != from_layer_num) continue;
+            if (rr_graph.node_layer(rr_node) != (int)from_layer_num) continue;
 
-            auto cost_index = rr_graph.node_cost_index(rr_node);
+            RRIndexedDataId cost_index = rr_graph.node_cost_index(rr_node);
             VTR_ASSERT(cost_index != RRIndexedDataId(UNDEFINED));
 
             int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index;
diff --git a/vpr/src/route/rr_graph_generation/build_switchblocks.cpp b/vpr/src/route/rr_graph_generation/build_switchblocks.cpp
@@ -453,7 +453,7 @@ t_sb_connection_map* alloc_and_load_switchblock_permutations(const t_chan_detail
         }
 
         // Iterate over the x,y, layer coordinates spanning the FPGA, filling in all the switch blocks that exist
-        for (int layer_coord = 0; layer_coord < grid.get_num_layers(); layer_coord++) {
+        for (size_t layer_coord = 0; layer_coord < grid.get_num_layers(); layer_coord++) {
             for (size_t x_coord = 0; x_coord < grid.width(); x_coord++) {
                 for (size_t y_coord = 0; y_coord <= grid.height(); y_coord++) {
                     if (sb_not_here(grid, inter_cluster_rr, x_coord, y_coord, layer_coord, sb)) {
@@ -571,7 +571,7 @@ static bool is_core_sb(const DeviceGrid& grid, const std::vector<bool>& inter_cl
 static bool is_prog_routing_avail(const DeviceGrid& grid, const std::vector<bool>& inter_cluster_rr, int layer) {
     bool is_prog_avail = true;
     //make sure layer number is legal
-    VTR_ASSERT(layer >= 0 && layer < grid.get_num_layers());
+    VTR_ASSERT(layer >= 0 && layer < (int)grid.get_num_layers());
     //check if the current layer has programmable routing resources before trying to build a custom switch blocks
     if (!inter_cluster_rr.at(layer)) {
         is_prog_avail = false;
@@ -1106,7 +1106,7 @@ static bool coords_out_of_bounds(const DeviceGrid& grid, int x_coord, int y_coor
     bool result = true;
 
     /* the layer that channel is located at must be legal regardless of chan_type*/
-    if (layer_coord < 0 || layer_coord > grid.get_num_layers()) {
+    if (layer_coord < 0 || layer_coord > (int)grid.get_num_layers()) {
         return result;
     }
 
diff --git a/vpr/src/route/rr_graph_generation/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp
@@ -2029,7 +2029,7 @@ static std::function<void(t_chan_width*)> alloc_and_load_rr_graph(RRGraphBuilder
     num_edges = 0;
     // Build opins
     int rr_edges_before_directs = 0;
-    for (int layer = 0; layer < grid.get_num_layers(); layer++) {
+    for (size_t layer = 0; layer < grid.get_num_layers(); layer++) {
         for (size_t i = 0; i < grid.width(); ++i) {
             for (size_t j = 0; j < grid.height(); ++j) {
                 for (e_side side : TOTAL_2D_SIDES) {
@@ -3345,7 +3345,7 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
 
     // Total the number of physical pins
     std::vector<int> num_phys_pins_per_layer;
-    for (int layer = 0; layer < grid.get_num_layers(); layer++) {
+    for (int layer = 0; layer < (int)grid.get_num_layers(); layer++) {
         int num_phys_pins = 0;
         for (int width = 0; width < tile_type->width; ++width) {
             for (int height = 0; height < tile_type->height; ++height) {
@@ -3364,7 +3364,7 @@ static vtr::NdMatrix<int, 6> alloc_and_load_pin_to_seg_type(const e_pin_type pin
     // (potentially in other C blocks) connect to the remaining tracks first. Doesn't matter for large Fc,
     // but should make a fairly good low Fc block that leverages the fact that usually lots of pins are logically equivalent.
 
-    for (int layer_index = 0; layer_index < grid.get_num_layers(); layer_index++) {
+    for (int layer_index = 0; layer_index < (int)grid.get_num_layers(); layer_index++) {
         const e_side init_side = LEFT;
         const int init_width = 0;
         const int init_height = 0;
diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp
@@ -140,7 +140,7 @@ static int get_track_to_chan_seg(RRGraphBuilder& rr_graph_builder,
  *
  * @return true if the connection going to another layer, false otherwise.
  */
-static bool is_sb_conn_layer_crossing(enum e_side src_side, enum e_side dest_side);
+static bool is_sb_conn_layer_crossing(e_side src_side, e_side dest_side);
 
 /**
  * @brief finds corresponding RR nodes for a 3D SB edge and fill 3D custom switch block information (offset to correct extra CHANX nodes, source tracks, ..)
@@ -1015,12 +1015,12 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
         auto& device_ctx = g_vpr_ctx.device();
         for (unsigned int i = 0; i < types.size(); i++) {
             if (!track_to_pin_map[i].empty()) {
-                for (int layer = 0; layer < device_ctx.grid.get_num_layers(); layer++) {
+                for (size_t layer = 0; layer < device_ctx.grid.get_num_layers(); layer++) {
                     for (int track = 0; track < max_chan_width; ++track) {
                         for (int width = 0; width < types[i].width; ++width) {
                             for (int height = 0; height < types[i].height; ++height) {
                                 for (int side = 0; side < 4; ++side) {
-                                    fprintf(fp, "\nTYPE:%s width:%d height:%d layer:%d\n", types[i].name.c_str(), width, height, layer);
+                                    fprintf(fp, "\nTYPE:%s width:%d height:%d layer:%lu\n", types[i].name.c_str(), width, height, layer);
                                     fprintf(fp, "\nSIDE:%d TRACK:%d \n", side, track);
                                     for (size_t con = 0; con < track_to_pin_map[i][track][width][height][layer][side].size(); con++) {
                                         fprintf(fp, "%d ", track_to_pin_map[i][track][width][height][layer][side][con]);
@@ -1036,7 +1036,7 @@ void dump_track_to_pin_map(t_track_to_pin_lookup& track_to_pin_map,
     }
 }
 
-static bool is_sb_conn_layer_crossing(enum e_side src_side, enum e_side dest_side) {
+static bool is_sb_conn_layer_crossing(e_side src_side, e_side dest_side) {
     if (src_side < NUM_2D_SIDES && dest_side < NUM_2D_SIDES) {
         return false;
     }
@@ -1075,7 +1075,7 @@ vtr::NdMatrix<int, 2> get_number_track_to_track_inter_die_conn(t_sb_connection_m
 
     for (size_t y = 0; y < grid_ctx.height(); y++) {
         for (size_t x = 0; x < grid_ctx.width(); x++) {
-            for (int layer = 0; layer < grid_ctx.get_num_layers(); layer++) {
+            for (int layer = 0; layer < (int)grid_ctx.get_num_layers(); layer++) {
 
                 int num_of_3d_conn = 0;
                 for (e_side from_side : TOTAL_3D_SIDES) {
@@ -1158,9 +1158,9 @@ int get_track_to_pins(RRGraphBuilder& rr_graph_builder,
                     side = (0 == pass ? RIGHT : LEFT);
                 }
 
-                for (int layer_index = 0; layer_index < device_ctx.grid.get_num_layers(); layer_index++) {
+                for (int layer_index = 0; layer_index < (int)device_ctx.grid.get_num_layers(); layer_index++) {
                     /* PAJ - if the pointed to is an EMPTY then shouldn't look for ipins */
-                    auto type = device_ctx.grid.get_physical_type({x, y, layer_index});
+                    t_physical_tile_type_ptr type = device_ctx.grid.get_physical_type({x, y, layer_index});
                     if (type == device_ctx.EMPTY_PHYSICAL_TILE_TYPE)
                         continue;
 
@@ -1570,8 +1570,8 @@ static void get_switchblocks_edges(RRGraphBuilder& rr_graph_builder,
                 VTR_ASSERT(to_layer != layer);
                 // Check if current connection is valid, since switch block pattern is very general,
                 // we might see invalid layer in connection, so we just skip those
-                if ((layer < 0 || layer >= device_ctx.grid.get_num_layers())
-                    || (to_layer < 0 || to_layer >= device_ctx.grid.get_num_layers())) {
+                if ((layer < 0 || layer >= (int)device_ctx.grid.get_num_layers())
+                    || (to_layer < 0 || to_layer >= (int)device_ctx.grid.get_num_layers())) {
                     continue;
                 }
 
diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp
@@ -172,7 +172,7 @@ static void load_chan_rr_indices(const int max_chan_width,
                                  int* index) {
     const auto& device_ctx = g_vpr_ctx.device();
 
-    for (int layer = 0; layer < grid.get_num_layers(); layer++) {
+    for (size_t layer = 0; layer < grid.get_num_layers(); layer++) {
         // Skip the current die if architecture file specifies that it doesn't require global resource routing
         if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) {
             continue;
@@ -335,7 +335,7 @@ void alloc_and_load_inter_die_rr_node_indices(RRGraphBuilder& rr_graph_builder,
     // 4) direction = NONE
     const auto& device_ctx = g_vpr_ctx.device();
 
-    for (int layer = 0; layer < grid.get_num_layers(); layer++) {
+    for (size_t layer = 0; layer < grid.get_num_layers(); layer++) {
         // Skip the current die if architecture file specifies that it doesn't have global resource routing
         if (!device_ctx.inter_cluster_prog_routing_resources.at(layer)) {
             continue;
diff --git a/vpr/src/route/serial_connection_router.cpp b/vpr/src/route/serial_connection_router.cpp
@@ -241,7 +241,7 @@ void SerialConnectionRouter<Heap>::timing_driven_expand_neighbour(const RTExplor
                                                                   const t_bb& bounding_box,
                                                                   RRNodeId target_node,
                                                                   const t_bb& target_bb) {
-    VTR_ASSERT(bounding_box.layer_max < g_vpr_ctx.device().grid.get_num_layers());
+    VTR_ASSERT(bounding_box.layer_max < (int)g_vpr_ctx.device().grid.get_num_layers());
 
     const RRNodeId& from_node = current.index;
 
