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AmirhosseinPooladAmirhosseinPoolad
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Change e_pin_type to enum class
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87 files changed

+527
-485
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87 files changed

+527
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‎libs/libarchfpga/src/arch_util.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -4,6 +4,7 @@
44
#include <vector>
55

66
#include "logic_types.h"
7+
#include "physical_types.h"
78
#include "vtr_assert.h"
89
#include "vtr_list.h"
910
#include "vtr_memory.h"
@@ -669,12 +670,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) {
669670
mem_pb_type->modes[0].parent_pb_type = mem_pb_type;
670671
mem_pb_type->modes[0].index = 0;
671672
mem_pb_type->modes[0].mode_power = new t_mode_power();
672-
num_pb = OPEN;
673+
num_pb = ARCH_FPGA_UNDEFINED_VAL;
673674
for (i = 0; i < mem_pb_type->num_ports; i++) {
674675
if (mem_pb_type->ports[i].port_class != nullptr
675676
&& strstr(mem_pb_type->ports[i].port_class, "data")
676677
== mem_pb_type->ports[i].port_class) {
677-
if (num_pb == OPEN) {
678+
if (num_pb == ARCH_FPGA_UNDEFINED_VAL) {
678679
num_pb = mem_pb_type->ports[i].num_pins;
679680
} else if (num_pb != mem_pb_type->ports[i].num_pins) {
680681
archfpga_throw(get_arch_file_name(), 0,
@@ -1206,7 +1207,7 @@ void setup_pin_classes(t_physical_tile_type* type) {
12061207
int num_class;
12071208

12081209
for (int i = 0; i < type->num_pins; i++) {
1209-
type->pin_class.push_back(OPEN);
1210+
type->pin_class.push_back(ARCH_FPGA_UNDEFINED_VAL);
12101211
type->is_ignored_pin.push_back(true);
12111212
type->is_pin_global.push_back(true);
12121213
}
@@ -1229,10 +1230,10 @@ void setup_pin_classes(t_physical_tile_type* type) {
12291230
class_inf.equivalence = port.equivalent;
12301231

12311232
if (port.type == IN_PORT) {
1232-
class_inf.type = RECEIVER;
1233+
class_inf.type = e_pin_type::RECEIVER;
12331234
} else {
12341235
VTR_ASSERT(port.type == OUT_PORT);
1235-
class_inf.type = DRIVER;
1236+
class_inf.type = e_pin_type::DRIVER;
12361237
}
12371238

12381239
for (int k = 0; k < port.num_pins; ++k) {
@@ -1263,10 +1264,10 @@ void setup_pin_classes(t_physical_tile_type* type) {
12631264
class_inf.equivalence = port.equivalent;
12641265

12651266
if (port.type == IN_PORT) {
1266-
class_inf.type = RECEIVER;
1267+
class_inf.type = e_pin_type::RECEIVER;
12671268
} else {
12681269
VTR_ASSERT(port.type == OUT_PORT);
1269-
class_inf.type = DRIVER;
1270+
class_inf.type = e_pin_type::DRIVER;
12701271
}
12711272

12721273
type->pin_class[pin_count] = num_class;

‎libs/libarchfpga/src/physical_types.cpp

Lines changed: 8 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,5 @@
11
#include "physical_types.h"
2+
#include "arch_types.h"
23
#include "vtr_math.h"
34
#include "vtr_util.h"
45
#include "vtr_log.h"
@@ -164,17 +165,17 @@ int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const {
164165
}
165166
}
166167

167-
return OPEN;
168+
return ARCH_FPGA_UNDEFINED_VAL;
168169
}
169170

170171
bool t_physical_tile_type::is_empty() const {
171172
return name == std::string(EMPTY_BLOCK_NAME);
172173
}
173174

174175
int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const {
175-
int ipin = OPEN;
176+
int ipin = ARCH_FPGA_UNDEFINED_VAL;
176177
int port_base_ipin = 0;
177-
int num_port_pins = OPEN;
178+
int num_port_pins = ARCH_FPGA_UNDEFINED_VAL;
178179
int pin_offset = 0;
179180

180181
bool port_found = false;
@@ -197,7 +198,7 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_
197198
pin_offset += sub_tile.num_phy_pins;
198199
}
199200

200-
if (num_port_pins != OPEN) {
201+
if (num_port_pins != ARCH_FPGA_UNDEFINED_VAL) {
201202
VTR_ASSERT(pin_index_in_port < num_port_pins);
202203

203204
ipin = port_base_ipin + pin_index_in_port + pin_offset;
@@ -207,14 +208,14 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_
207208
}
208209

209210
int t_physical_tile_type::find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const {
210-
int iclass = OPEN;
211+
int iclass = ARCH_FPGA_UNDEFINED_VAL;
211212

212213
int ipin = find_pin(port_name, pin_index_in_port);
213214

214-
if (ipin != OPEN) {
215+
if (ipin != ARCH_FPGA_UNDEFINED_VAL) {
215216
iclass = pin_class[ipin];
216217

217-
if (iclass != OPEN) {
218+
if (iclass != ARCH_FPGA_UNDEFINED_VAL) {
218219
VTR_ASSERT(class_inf[iclass].type == pin_type);
219220
}
220221
}

‎libs/libarchfpga/src/physical_types.h

Lines changed: 10 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
* Authors: Jason Luu and Kenneth Kent
2626
*/
2727

28+
#include <cstdint>
2829
#include <functional>
2930
#include <utility>
3031
#include <vector>
@@ -42,6 +43,7 @@
4243
#include "logic_types.h"
4344
#include "clock_types.h"
4445
#include "switchblock_types.h"
46+
#include "arch_types.h"
4547

4648
#include "vib_inf.h"
4749

@@ -163,7 +165,7 @@ struct t_metadata_dict : vtr::flat_map<
163165

164166
/* Pins describe I/O into clustered logic block.
165167
* A pin may be unconnected, driving a net or in the fanout, respectively. */
166-
enum e_pin_type {
168+
enum class e_pin_type : int8_t {
167169
OPEN = -1,
168170
DRIVER = 0,
169171
RECEIVER = 1
@@ -873,9 +875,9 @@ struct t_physical_pin {
873875
* above the base die, the layer_num is 1 and so on.
874876
*/
875877
struct t_physical_tile_loc {
876-
int x = OPEN;
877-
int y = OPEN;
878-
int layer_num = OPEN;
878+
int x = ARCH_FPGA_UNDEFINED_VAL;
879+
int y = ARCH_FPGA_UNDEFINED_VAL;
880+
int layer_num = ARCH_FPGA_UNDEFINED_VAL;
879881

880882
t_physical_tile_loc() = default;
881883

@@ -884,9 +886,9 @@ struct t_physical_tile_loc {
884886
, y(y_val)
885887
, layer_num(layer_num_val) {}
886888

887-
// Returns true if this type location layer_num/x/y is not equal to OPEN
889+
// Returns true if this type location layer_num/x/y is not equal to ARCH_FPGA_UNDEFINED_VAL
888890
operator bool() const {
889-
return !(x == OPEN || y == OPEN || layer_num == OPEN);
891+
return !(x == ARCH_FPGA_UNDEFINED_VAL || y == ARCH_FPGA_UNDEFINED_VAL || layer_num == ARCH_FPGA_UNDEFINED_VAL);
890892
}
891893
};
892894

@@ -1369,7 +1371,7 @@ class t_pb_graph_node {
13691371
* There is a root-level pb_graph_node assigned to each logical type. Each logical type can contain multiple primitives.
13701372
* If this pb_graph_node is associated with a primitive, a unique number is assigned to it within the logical block level.
13711373
*/
1372-
int primitive_num = OPEN;
1374+
int primitive_num = ARCH_FPGA_UNDEFINED_VAL;
13731375

13741376
/* Contains a collection of mode indices that cannot be used as they produce conflicts during VPR packing stage
13751377
*
@@ -1578,7 +1580,7 @@ class t_pb_graph_edge {
15781580
int* pack_pattern_indices;
15791581
bool infer_pattern;
15801582

1581-
int switch_type_idx = OPEN; /* architecture switch id of the edge - used when flat_routing is enabled */
1583+
int switch_type_idx = ARCH_FPGA_UNDEFINED_VAL; /* architecture switch id of the edge - used when flat_routing is enabled */
15821584

15831585
// class member functions
15841586
public:

‎libs/libarchfpga/src/physical_types_util.cpp

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,6 @@
11
#include <numeric>
2+
#include "arch_types.h"
3+
#include "physical_types.h"
24
#include "vtr_assert.h"
35
#include "vtr_util.h"
46

@@ -182,8 +184,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr
182184
pin_inst_port.logical_block_index = logical_num;
183185
pin_inst_port.pb_type_idx = pb_type_idx;
184186
pin_inst_port.pin_physical_num = pin_physical_num;
185-
pin_inst_port.port_index = OPEN;
186-
pin_inst_port.pin_index_in_port = OPEN;
187+
pin_inst_port.port_index = ARCH_FPGA_UNDEFINED_VAL;
188+
pin_inst_port.pin_index_in_port = ARCH_FPGA_UNDEFINED_VAL;
187189

188190
if (is_flat && logical_num != -1) {
189191
auto pb_pin = get_pb_pin_from_pin_physical_num(type, pin_physical_num);
@@ -200,8 +202,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr
200202
}
201203
}
202204
}
203-
VTR_ASSERT(pin_inst_port.port_index != OPEN);
204-
VTR_ASSERT(pin_inst_port.pin_index_in_port != OPEN);
205+
VTR_ASSERT(pin_inst_port.port_index != ARCH_FPGA_UNDEFINED_VAL);
206+
VTR_ASSERT(pin_inst_port.pin_index_in_port != ARCH_FPGA_UNDEFINED_VAL);
205207
return pin_inst_port;
206208
}
207209

@@ -435,7 +437,7 @@ int get_sub_tile_physical_pin(int sub_tile_index,
435437

436438
int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile,
437439
t_logical_block_type_ptr logical_block) {
438-
int sub_tile_index = OPEN;
440+
int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
439441
for (const auto& sub_tile : physical_tile->sub_tiles) {
440442
auto eq_sites = sub_tile.equivalent_sites;
441443
auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
@@ -444,7 +446,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
444446
}
445447
}
446448

447-
if (sub_tile_index == OPEN) {
449+
if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
448450
archfpga_throw(__FILE__, __LINE__,
449451
"Found no instances of logical block type '%s' within physical tile type '%s'. ",
450452
logical_block->name.c_str(), physical_tile->name.c_str());
@@ -458,7 +460,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
458460
int pin) {
459461
int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block);
460462

461-
if (sub_tile_index == OPEN) {
463+
if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
462464
archfpga_throw(__FILE__, __LINE__,
463465
"Couldn't find the corresponding physical tile type pin of the logical block type pin %d.",
464466
pin);
@@ -471,7 +473,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile,
471473
int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile,
472474
t_logical_block_type_ptr logical_block,
473475
int sub_tile_capacity) {
474-
int sub_tile_index = OPEN;
476+
int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL;
475477
for (const auto& sub_tile : physical_tile->sub_tiles) {
476478
auto eq_sites = sub_tile.equivalent_sites;
477479
auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block);
@@ -482,7 +484,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_
482484
}
483485
}
484486

485-
if (sub_tile_index == OPEN) {
487+
if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
486488
archfpga_throw(__FILE__, __LINE__,
487489
"Found no instances of logical block type '%s' within physical tile type '%s'. ",
488490
logical_block->name.c_str(), physical_tile->name.c_str());
@@ -528,7 +530,7 @@ int get_physical_pin_at_sub_tile_location(t_physical_tile_type_ptr physical_tile
528530
VTR_ASSERT(pin < physical_tile->num_pins);
529531
int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block, sub_tile_capacity);
530532

531-
if (sub_tile_index == OPEN) {
533+
if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) {
532534
archfpga_throw(__FILE__, __LINE__,
533535
"Couldn't find the corresponding physical tile type pin of the logical block type pin %d.",
534536
pin);
@@ -610,7 +612,7 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) {
610612

611613
int iclass = type->pin_class[ipin];
612614

613-
if (type->class_inf[iclass].type == DRIVER)
615+
if (type->class_inf[iclass].type == e_pin_type::DRIVER)
614616
return true;
615617
else
616618
return false;
@@ -895,7 +897,7 @@ int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat) {
895897
/** get information given pin physical number **/
896898
std::tuple<const t_sub_tile*, int> get_sub_tile_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num) {
897899
const t_sub_tile* target_sub_tile = nullptr;
898-
int target_sub_tile_cap = OPEN;
900+
int target_sub_tile_cap = ARCH_FPGA_UNDEFINED_VAL;
899901

900902
bool pin_on_tile = is_pin_on_tile(physical_tile, physical_num);
901903

@@ -926,7 +928,7 @@ t_logical_block_type_ptr get_logical_block_from_pin_physical_num(t_physical_tile
926928
t_logical_block_type_ptr logical_block = nullptr;
927929

928930
std::tie(sub_tile, sub_tile_cap) = get_sub_tile_from_pin_physical_num(physical_tile, physical_num);
929-
VTR_ASSERT(sub_tile_cap != OPEN);
931+
VTR_ASSERT(sub_tile_cap != ARCH_FPGA_UNDEFINED_VAL);
930932

931933
for (auto logical_block_pin_range_pair : sub_tile->intra_pin_range[sub_tile_cap]) {
932934
if (physical_num >= logical_block_pin_range_pair.second.low) {
@@ -1189,7 +1191,7 @@ int get_pb_pin_physical_num(t_physical_tile_type_ptr physical_tile,
11891191
t_logical_block_type_ptr logical_block,
11901192
int relative_cap,
11911193
const t_pb_graph_pin* pin) {
1192-
int pin_physical_num = OPEN;
1194+
int pin_physical_num = ARCH_FPGA_UNDEFINED_VAL;
11931195
if (pin->is_root_block_pin()) {
11941196
pin_physical_num = get_physical_pin_at_sub_tile_location(physical_tile,
11951197
logical_block,
@@ -1264,12 +1266,12 @@ bool intra_tile_nodes_connected(t_physical_tile_type_ptr physical_type,
12641266
const t_sub_tile* from_sub_tile;
12651267
int from_sub_tile_rel_cap;
12661268
std::tie(from_sub_tile, from_sub_tile_rel_cap) = get_sub_tile_from_pin_physical_num(physical_type, pin_physical_num);
1267-
VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != OPEN);
1269+
VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL);
12681270

12691271
const t_sub_tile* to_sub_tile;
12701272
int to_sub_tile_rel_cap;
12711273
std::tie(to_sub_tile, to_sub_tile_rel_cap) = get_sub_tile_from_class_physical_num(physical_type, sink_physical_num);
1272-
VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != OPEN);
1274+
VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL);
12731275

12741276
return (from_sub_tile_rel_cap == to_sub_tile_rel_cap) && (from_sub_tile == to_sub_tile);
12751277

‎libs/libarchfpga/src/read_fpga_interchange_arch.cpp

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11

22
#include "read_fpga_interchange_arch.h"
3+
#include "arch_types.h"
34

45
#ifdef VTR_ENABLE_CAPNPROTO
56

@@ -550,7 +551,7 @@ struct ArchReader {
550551
std::string wire_name = str(wire.getName());
551552

552553
// pin name, bel name
553-
int pin_id = OPEN;
554+
int pin_id = ARCH_FPGA_UNDEFINED_VAL;
554555
bool pad_exists = false;
555556
bool all_inout_pins = true;
556557
std::string pad_bel_name;
@@ -577,7 +578,7 @@ struct ArchReader {
577578
pin_id = pin;
578579
}
579580

580-
if (pin_id == OPEN) {
581+
if (pin_id == ARCH_FPGA_UNDEFINED_VAL) {
581582
// If no driver pin has been found, the assumption is that
582583
// there must be a PAD with inout pin connected to other inout pins
583584
for (auto pin : wire.getPins()) {
@@ -594,7 +595,7 @@ struct ArchReader {
594595
}
595596
}
596597

597-
VTR_ASSERT(pin_id != OPEN);
598+
VTR_ASSERT(pin_id != ARCH_FPGA_UNDEFINED_VAL);
598599

599600
auto out_pin = site.getBelPins()[pin_id];
600601
auto out_pin_bel = get_bel_reader(site, str(out_pin.getBel()));
@@ -1674,10 +1675,10 @@ struct ArchReader {
16741675
* If a bel name index is specified, the bel pins are processed, otherwise the site ports
16751676
* are processed instead.
16761677
*/
1677-
void process_block_ports(t_pb_type* pb_type, Device::SiteType::Reader& site, size_t bel_name = OPEN) {
1678+
void process_block_ports(t_pb_type* pb_type, Device::SiteType::Reader& site, size_t bel_name = ARCH_FPGA_UNDEFINED_VAL) {
16781679
// Prepare data based on pb_type level
16791680
std::set<std::tuple<std::string, PORTS, int>> pins;
1680-
if (bel_name == (size_t)OPEN) {
1681+
if (bel_name == (size_t)ARCH_FPGA_UNDEFINED_VAL) {
16811682
for (auto pin : site.getPins()) {
16821683
auto dir = pin.getDir() == INPUT ? IN_PORT : OUT_PORT;
16831684
pins.emplace(str(pin.getName()), dir, 1);

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