diff --git a/libs/EXTERNAL/CMakeLists.txt b/libs/EXTERNAL/CMakeLists.txt index 4704e011d77..816ea7f57c9 100644 --- a/libs/EXTERNAL/CMakeLists.txt +++ b/libs/EXTERNAL/CMakeLists.txt @@ -102,11 +102,6 @@ if (${WITH_PARMYS}) yosys-slang SOURCE_DIR ${SLANG_SRC_DIR} BINARY_DIR ${SLANG_BUILD_DIR} - - #Disabling UndrivenPass in slang_frontend.cc - PATCH_COMMAND - ${CMAKE_COMMAND} -E echo "Patching slang_frontend.cc to disable UndrivenPass" && - ${CMAKE_COMMAND} -DIN=${SLANG_FE} -P ${CMAKE_CURRENT_SOURCE_DIR}/patch_slang.cmake CONFIGURE_COMMAND "" diff --git a/libs/EXTERNAL/patch_slang.cmake b/libs/EXTERNAL/patch_slang.cmake deleted file mode 100644 index d3520b95411..00000000000 --- a/libs/EXTERNAL/patch_slang.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# Patch step for yosys-slang -# -# The variable 'IN' points to vtr_root/libs/EXTERNAL/yosys-slang/src/slang_frontend.cc -# This file contains the UndrivenPass that we want to disable -# -# This patch step finds the line where the UndrivenPass is called and comments out that line -# -# The UndrivenPass needs to be disabled due to unsupported synchronous rules in vtr_primitives.v - -if(NOT DEFINED IN) - message(FATAL_ERROR "patch_slang.cmake: IN (SLANG_FE) variable not set.") -endif() -file(READ "${IN}" SLANG_FRONTEND_CONTENTS) -string(REPLACE "call(design, \"undriven\");" "// call(design, \"undriven\");" SLANG_PATCHED "${SLANG_FRONTEND_CONTENTS}") - if(NOT SLANG_FRONTEND_CONTENTS STREQUAL SLANG_PATCHED) - message(STATUS "Patching slang_frontend.cc to disable UndrivenPass") - file(WRITE "${IN}" "${SLANG_PATCHED}") - endif() diff --git a/libs/EXTERNAL/yosys b/libs/EXTERNAL/yosys index 53c22ab7c0c..60f126cd00c 160000 --- a/libs/EXTERNAL/yosys +++ b/libs/EXTERNAL/yosys @@ -1 +1 @@ -Subproject commit 53c22ab7c0ced80861c7536c5dae682c30fb5834 +Subproject commit 60f126cd00c94892782470192d6c9f7abebe7c05 diff --git a/libs/EXTERNAL/yosys-slang b/libs/EXTERNAL/yosys-slang index 76b83eb5b73..55e3a2ad5b9 160000 --- a/libs/EXTERNAL/yosys-slang +++ b/libs/EXTERNAL/yosys-slang @@ -1 +1 @@ -Subproject commit 76b83eb5b73ba871797e6db7bc5fed10af380be4 +Subproject commit 55e3a2ad5b9dcdc8cf86918fb0a110fb6356def8 diff --git a/parmys/regression_test/benchmark/task/freecores/synthesis_result.json b/parmys/regression_test/benchmark/task/freecores/synthesis_result.json index 167bdecaea6..09150fb4887 100644 --- a/parmys/regression_test/benchmark/task/freecores/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/freecores/synthesis_result.json @@ -483,7 +483,7 @@ "Average Path": 3, "Estimated LUTs": 4777, "Total Node": 1957, - "Wires": 5592, + "Wires": 5594, "Wire Bits": 10106, "Public Wires": 240, "Public Wire Bits": 240, diff --git a/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json index 1bdfa3d0434..a659a9020c6 100644 --- a/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/and/synthesis_result.json @@ -95,21 +95,21 @@ "test_name": "and/replicate_and_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "and/replicate_and_ultra_wide/no_arch": { "test_name": "and/replicate_and_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "and/replicate_and_wide/no_arch": { "test_name": "and/replicate_and_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "DEFAULT": { diff --git a/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json index e24a44b3d78..dacb8c7991d 100644 --- a/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/nand/synthesis_result.json @@ -94,21 +94,21 @@ "test_name": "nand/replicate_nand_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "nand/replicate_nand_ultra_wide/no_arch": { "test_name": "nand/replicate_nand_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "nand/replicate_nand_wide/no_arch": { "test_name": "nand/replicate_nand_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "DEFAULT": { diff --git a/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json index f20c774f2c6..d3f7332e0f7 100644 --- a/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/nor/synthesis_result.json @@ -100,21 +100,21 @@ "test_name": "nor/replicate_nor_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "nor/replicate_nor_ultra_wide/no_arch": { "test_name": "nor/replicate_nor_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "nor/replicate_nor_wide/no_arch": { "test_name": "nor/replicate_nor_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "DEFAULT": { diff --git a/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json index 011b97df9e4..6c50d66faac 100644 --- a/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/or/synthesis_result.json @@ -95,21 +95,21 @@ "test_name": "or/replicate_or_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "or/replicate_or_ultra_wide/no_arch": { "test_name": "or/replicate_or_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "or/replicate_or_wide/no_arch": { "test_name": "or/replicate_or_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "DEFAULT": { diff --git a/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json index 2f042534f1d..127d568c456 100644 --- a/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/xnor/synthesis_result.json @@ -54,21 +54,21 @@ "test_name": "xnor/replicate_xnor_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xnor/replicate_xnor_ultra_wide/no_arch": { "test_name": "xnor/replicate_xnor_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xnor/replicate_xnor_wide/no_arch": { "test_name": "xnor/replicate_xnor_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xnor/xnor_indexed_port/no_arch": { diff --git a/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json b/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json index 118ef67b751..9c6e3d300ac 100644 --- a/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/keywords/xor/synthesis_result.json @@ -51,21 +51,21 @@ "test_name": "xor/replicate_xor_int_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xor/replicate_xor_ultra_wide/no_arch": { "test_name": "xor/replicate_xor_ultra_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xor/replicate_xor_wide/no_arch": { "test_name": "xor/replicate_xor_wide/no_arch", "exit": 1, "errors": [ - "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2746." + "Assert `new_cell->children.at(0)->type == AST_CELLTYPE' failed in frontends/ast/simplify.cc:2755." ] }, "xor/xor_indexed_port/no_arch": { diff --git a/parmys/regression_test/benchmark/task/koios/koios_medium/synthesis_result.json b/parmys/regression_test/benchmark/task/koios/koios_medium/synthesis_result.json index a47ba833bc1..e12670d70c5 100644 --- a/parmys/regression_test/benchmark/task/koios/koios_medium/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/koios/koios_medium/synthesis_result.json @@ -565,15 +565,15 @@ "Average Path": 5, "Estimated LUTs": 15571, "Total Node": 4795, - "Wires": 45931, - "Wire Bits": 49668, + "Wires": 45932, + "Wire Bits": 49669, "Public Wires": 5161, "Public Wire Bits": 5161, - "Total Cells": 42904, + "Total Cells": 42905, "MUX": 22203, "XOR": 15, "OR": 2990, - "AND": 2640, + "AND": 2641, "NOT": 255, "DFFs": [ "$_DFF_P_ 11798" @@ -1221,14 +1221,14 @@ "Average Path": 4, "Estimated LUTs": 13223, "Total Node": 5602, - "Wires": 28994, - "Wire Bits": 50685, + "Wires": 28995, + "Wire Bits": 50688, "Public Wires": 3999, "Public Wire Bits": 3999, - "Total Cells": 42439, + "Total Cells": 42435, "MUX": 11266, "XOR": 3492, - "OR": 5746, + "OR": 5742, "AND": 8418, "NOT": 3193, "DFFs": [ @@ -1457,7 +1457,6 @@ "Resizing cell port systolic_pe_matrix.pe0_2.in_b from 8 bits to 19 bits.", "Resizing cell port systolic_pe_matrix.pe0_1.in_b from 8 bits to 19 bits.", "Resizing cell port systolic_pe_matrix.pe0_0.in_b from 8 bits to 19 bits.", - "Ignoring module matmul_16x16_systolic because it contains processes (run 'proc' command first).", "Ignoring module top because it contains processes (run 'proc' command first).", "Ignoring module activation because it contains processes (run 'proc' command first).", "Ignoring module pool because it contains processes (run 'proc' command first).", @@ -1470,6 +1469,7 @@ "Ignoring module processing_element because it contains processes (run 'proc' command first).", "Ignoring module systolic_data_setup because it contains processes (run 'proc' command first).", "Ignoring module output_logic because it contains processes (run 'proc' command first).", + "Ignoring module matmul_16x16_systolic because it contains processes (run 'proc' command first).", "Wire processing_element.\\chainin [63] is used but has no driver.", "Wire processing_element.\\chainin [62] is used but has no driver.", "Wire processing_element.\\chainin [61] is used but has no driver.", diff --git a/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json b/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json index 0c47a2c8437..e35ae766e8f 100644 --- a/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/koios/koios_medium_no_hb/synthesis_result.json @@ -169,8 +169,8 @@ "Average Path": 3, "Estimated LUTs": 28720, "Total Node": 16803, - "Wires": 58018, - "Wire Bits": 81586, + "Wires": 58019, + "Wire Bits": 81589, "Public Wires": 8454, "Public Wire Bits": 8454, "Total Cells": 42029, @@ -464,7 +464,7 @@ "Estimated LUTs": 22752, "Total Node": 5094, "Wires": 24045, - "Wire Bits": 37590, + "Wire Bits": 37311, "Public Wires": 5228, "Public Wire Bits": 5228, "Total Cells": 24019, @@ -670,15 +670,15 @@ "Average Path": 5, "Estimated LUTs": 16387, "Total Node": 6499, - "Wires": 57055, - "Wire Bits": 60792, + "Wires": 57056, + "Wire Bits": 60793, "Public Wires": 2053, "Public Wire Bits": 2053, - "Total Cells": 51015, + "Total Cells": 51016, "MUX": 26043, "XOR": 15, "OR": 2989, - "AND": 2640, + "AND": 2641, "NOT": 255, "DFFs": [ "$_DFF_P_ 14486" @@ -1227,14 +1227,14 @@ "Average Path": 5, "Estimated LUTs": 13699, "Total Node": 7769, - "Wires": 29721, - "Wire Bits": 41696, + "Wires": 29722, + "Wire Bits": 41699, "Public Wires": 3147, "Public Wire Bits": 3147, - "Total Cells": 33385, + "Total Cells": 33386, "MUX": 8974, "XOR": 624, - "OR": 4219, + "OR": 4220, "AND": 5530, "NOT": 1685, "DFFs": [ @@ -1335,14 +1335,14 @@ "Average Path": 4, "Estimated LUTs": 13223, "Total Node": 5602, - "Wires": 28999, - "Wire Bits": 50657, + "Wires": 29005, + "Wire Bits": 50691, "Public Wires": 3999, "Public Wire Bits": 3999, - "Total Cells": 42389, + "Total Cells": 42423, "MUX": 11266, "XOR": 3492, - "OR": 5695, + "OR": 5729, "AND": 8419, "NOT": 3193, "DFFs": [ @@ -1467,14 +1467,14 @@ "Average Path": 8, "Estimated LUTs": 37160, "Total Node": 11295, - "Wires": 46405, - "Wire Bits": 117654, + "Wires": 46404, + "Wire Bits": 117642, "Public Wires": 1513, "Public Wire Bits": 1513, - "Total Cells": 70238, + "Total Cells": 70240, "MUX": 22023, "XOR": 1594, - "OR": 17552, + "OR": 17554, "AND": 10572, "NOT": 5150, "DFFs": [ diff --git a/parmys/regression_test/benchmark/task/syntax/synthesis_result.json b/parmys/regression_test/benchmark/task/syntax/synthesis_result.json index c7dd974edf9..5d55155c1f5 100644 --- a/parmys/regression_test/benchmark/task/syntax/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/syntax/synthesis_result.json @@ -2924,8 +2924,8 @@ "Average Path": 4, "Estimated LUTs": 101, "Total Node": 67, - "Wires": 212, - "Wire Bits": 268, + "Wires": 213, + "Wire Bits": 269, "Public Wires": 177, "Public Wire Bits": 177, "Total Cells": 145, @@ -2964,8 +2964,8 @@ "Average Path": 5, "Estimated LUTs": 25938, "Total Node": 34130, - "Wires": 76077, - "Wire Bits": 84563, + "Wires": 76078, + "Wire Bits": 84564, "Public Wires": 75169, "Public Wire Bits": 75169, "Total Cells": 59068, @@ -4048,8 +4048,8 @@ "Average Path": 4, "Estimated LUTs": 101, "Total Node": 33, - "Wires": 103, - "Wire Bits": 168, + "Wires": 104, + "Wire Bits": 169, "Public Wires": 71, "Public Wire Bits": 71, "Total Cells": 111, @@ -4086,8 +4086,8 @@ "Average Path": 4, "Estimated LUTs": 33, "Total Node": 33, - "Wires": 103, - "Wire Bits": 168, + "Wires": 104, + "Wire Bits": 169, "Public Wires": 71, "Public Wire Bits": 71, "Total Cells": 111, diff --git a/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json b/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json index 44d02d7c466..f919a7fac1c 100644 --- a/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/ultraembedded/synthesis_result.json @@ -318,7 +318,7 @@ "Average Path": 2, "Estimated LUTs": 2852, "Total Node": 1381, - "Wires": 3619, + "Wires": 3620, "Wire Bits": 5288, "Public Wires": 119, "Public Wire Bits": 119, diff --git a/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json b/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json index 03eecafeaa1..99742919bd1 100644 --- a/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json +++ b/parmys/regression_test/benchmark/task/vexriscv/synthesis_result.json @@ -412,14 +412,14 @@ "Average Path": 4, "Estimated LUTs": 8043, "Total Node": 4065, - "Wires": 14711, - "Wire Bits": 20350, + "Wires": 14723, + "Wire Bits": 20361, "Public Wires": 877, "Public Wire Bits": 877, - "Total Cells": 17352, + "Total Cells": 17350, "MUX": 6882, "XOR": 454, - "OR": 2550, + "OR": 2548, "AND": 1968, "NOT": 926, "DFFs": [ @@ -1068,8 +1068,8 @@ "Average Path": 4, "Estimated LUTs": 3240, "Total Node": 1609, - "Wires": 5545, - "Wire Bits": 8284, + "Wires": 5551, + "Wire Bits": 8226, "Public Wires": 421, "Public Wire Bits": 421, "Total Cells": 6825, @@ -1231,8 +1231,8 @@ "Average Path": 3, "Estimated LUTs": 3582, "Total Node": 1645, - "Wires": 5926, - "Wire Bits": 8737, + "Wires": 5932, + "Wire Bits": 8679, "Public Wires": 464, "Public Wire Bits": 464, "Total Cells": 7324, @@ -1591,8 +1591,8 @@ "Average Path": 4, "Estimated LUTs": 4666, "Total Node": 1960, - "Wires": 8363, - "Wire Bits": 11514, + "Wires": 8365, + "Wire Bits": 11515, "Public Wires": 584, "Public Wire Bits": 584, "Total Cells": 9682, @@ -1653,8 +1653,8 @@ "Average Path": 5, "Estimated LUTs": 3806, "Total Node": 1594, - "Wires": 7019, - "Wire Bits": 9660, + "Wires": 7020, + "Wire Bits": 9597, "Public Wires": 580, "Public Wire Bits": 580, "Total Cells": 7824, @@ -1716,7 +1716,7 @@ "Estimated LUTs": 3906, "Total Node": 1703, "Wires": 7427, - "Wire Bits": 10069, + "Wire Bits": 10005, "Public Wires": 694, "Public Wire Bits": 694, "Total Cells": 8164, @@ -1759,8 +1759,8 @@ "Average Path": 5, "Estimated LUTs": 3318, "Total Node": 1264, - "Wires": 5959, - "Wire Bits": 8368, + "Wires": 5960, + "Wire Bits": 8305, "Public Wires": 361, "Public Wire Bits": 361, "Total Cells": 6640, @@ -1819,7 +1819,7 @@ "Estimated LUTs": 6611, "Total Node": 2574, "Wires": 10970, - "Wire Bits": 15143, + "Wire Bits": 15142, "Public Wires": 583, "Public Wire Bits": 583, "Total Cells": 13096, @@ -1865,7 +1865,7 @@ "Average Path": 3, "Estimated LUTs": 7117, "Total Node": 3035, - "Wires": 12001, + "Wires": 12002, "Wire Bits": 16343, "Public Wires": 699, "Public Wire Bits": 699, @@ -2160,7 +2160,7 @@ "Estimated LUTs": 3513, "Total Node": 1415, "Wires": 6614, - "Wire Bits": 8861, + "Wire Bits": 8797, "Public Wires": 478, "Public Wire Bits": 478, "Total Cells": 7100, @@ -2220,8 +2220,8 @@ "Average Path": 4, "Estimated LUTs": 8969, "Total Node": 2639, - "Wires": 13228, - "Wire Bits": 18784, + "Wires": 13230, + "Wire Bits": 18722, "Public Wires": 674, "Public Wire Bits": 674, "Total Cells": 16338, @@ -2269,7 +2269,7 @@ "Estimated LUTs": 2048, "Total Node": 748, "Wires": 3124, - "Wire Bits": 4665, + "Wire Bits": 4601, "Public Wires": 349, "Public Wire Bits": 349, "Total Cells": 3750, @@ -2315,7 +2315,7 @@ "Estimated LUTs": 2023, "Total Node": 693, "Wires": 2983, - "Wire Bits": 4491, + "Wire Bits": 4427, "Public Wires": 253, "Public Wire Bits": 253, "Total Cells": 3623, @@ -2361,7 +2361,7 @@ "Estimated LUTs": 1535, "Total Node": 673, "Wires": 2398, - "Wire Bits": 3933, + "Wire Bits": 3869, "Public Wires": 253, "Public Wire Bits": 253, "Total Cells": 3009, @@ -2407,7 +2407,7 @@ "Estimated LUTs": 1190, "Total Node": 537, "Wires": 1958, - "Wire Bits": 3460, + "Wire Bits": 3396, "Public Wires": 250, "Public Wire Bits": 250, "Total Cells": 2564, diff --git a/vtr_flow/misc/yosys/slang_filelist.tcl b/vtr_flow/misc/yosys/slang_filelist.tcl index 2f5364ef21b..f5772e62445 100644 --- a/vtr_flow/misc/yosys/slang_filelist.tcl +++ b/vtr_flow/misc/yosys/slang_filelist.tcl @@ -1,24 +1,119 @@ -#Parameters: +# Helper file for synthesis.tcl +# +# Includes a function that builds a filelist of +# HDL files provided by the circuit list to be +# read by read_slang. This function also identifies +# the respective top modules of HDL files in the filelist. + + +namespace eval ::slang { + # INFO: Maps HDL files to respective top module(s) + # top_map insertion syntax: + # + array set top_map { + and_latch.v and_latch + multiclock_output_and_latch.v multiclock_output_and_latch + multiclock_reader_writer.v multiclock_reader_writer + multiclock_separate_and_latch.v multiclock_separate_and_latch + arm_core.v arm_core + bgm.v bgm + blob_merge.v RLE_BlobMerging + boundtop.v paj_boundtop_hierarchy_no_mem + ch_intrinsics.v memset + diffeq1.v diffeq_paj_convert + diffeq2.v diffeq_f_systemC + LU8PEEng.v LU8PEEng + LU32PEEng.v LU32PEEng + LU64PEEng.v LU64PEEng + mcml.v mcml + mkDelayWorker32B.v mkDelayWorker32B + mkPktMerge.v mkPktMerge + mkSMAdapter4B.v mkSMAdapter4B + or1200.v or1200_flat + raygentop.v paj_raygentop_hierarchy_no_mem + sha.v sha1 + stereovision0.v sv_chip0_hierarchy_no_mem + stereovision1.v sv_chip1_hierarchy_no_mem + stereovision2.v sv_chip2_hierarchy_no_mem + stereovision3.v sv_chip3_hierarchy_no_mem + button_controller.sv top + display_control.sv top + debounce.sv top + timer.sv top + deepfreeze.style1.sv top + pulse_led.v top + clock.sv top + single_ff.v top + single_wire.v top + PWM.v top + flattened_pulse_width_led.sv top + modify_count.sv top + time_counter.sv top + spree.v system + attention_layer.v attention_layer + bnn.v bnn + tpu_like.small.os.v top + tpu_like.small.ws.v top + dla_like.small.v DLA + conv_layer_hls.v top + conv_layer.v conv_layer + eltwise_layer.v eltwise_layer + robot_rl.v robot_maze + reduction_layer.v reduction_layer + spmv.v spmv + softmax.v softmax + } + # INFO: List of HDL includes files + # includes_map insertion syntax: + # include + array set includes_map { + hard_block_include.v include + } + + + variable top_args {} + +# Function - build_filelist: +# +# Validates file extensions of input files and writes the names +# of input files to the file list to be read by yosys-slang. Also appends +# the respective top modules of HDL files being read by slang to the read_slang command. +# +# Parameters: # # circuit_list - list of circuits passed into the flow # file_list - text file being written to that will contain # the names of circuits from circuit list. # -#Function: -# -# Validates file extensions of input files and writes the names -# of input files to the file list to be read by yosys-slang. - -proc build_filelist { circuit_list file_list } { - set fh [open $file_list "w"] - foreach f $circuit_list { - set ext [string tolower [file extension $f]] - if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { - puts $fh $f - } else { - close $fh - error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}" + proc build_filelist { circuit_list file_list } { + variable top_args + variable top_map + variable includes_map + set top_args {} + set fh [open $file_list "w"] + foreach f $circuit_list { + set ext [string tolower [file extension $f]] + if {$ext == ".sv" || $ext == ".svh" || $ext == ".v" || $ext == ".vh"} { + if {$f != "vtr_primitives.v" && $f != "vtr_blackboxes.v"} { + #Includes file + if {[info exists includes_map($f)]} { + puts $fh $f + #HDL file or top module isn't in top_map + } elseif {![info exists top_map($f)]} { + error "No top module set for $f" + #HDL file and respective top module in top_map + } else { + puts $fh $f + set top_name $top_map($f) + lappend top_args --top $top_name + } + } + } else { + close $fh + error "Unsupported file type. Yosys-Slang accepts .sv .svh .v .vh. File {$f}" + } } + close $fh + return $top_args } - close $fh } diff --git a/vtr_flow/misc/yosys/synthesis.tcl b/vtr_flow/misc/yosys/synthesis.tcl index 114c640b0ec..2a78ae819ab 100644 --- a/vtr_flow/misc/yosys/synthesis.tcl +++ b/vtr_flow/misc/yosys/synthesis.tcl @@ -1,11 +1,6 @@ yosys -import plugin -i parmys -read_verilog -nomem2reg +/parmys/vtr_primitives.v -setattr -mod -set keep_hierarchy 1 single_port_ram -setattr -mod -set keep_hierarchy 1 dual_port_ram -setattr -mod -set keep 1 dual_port_ram - # yosys-slang plugin error handling if {$env(PARSER) == "slang" } { if {![info exists ::env(yosys_slang_path)]} { @@ -39,11 +34,15 @@ if {$env(PARSER) == "slang" } { source [file join [pwd] "slang_filelist.tcl"] set readfile [file join [pwd] "filelist.txt"] #Writing names of circuit files to file list - build_filelist {XXX} $readfile + set slang_tops [::slang::build_filelist {XXX} $readfile] puts "Using Yosys read_slang command" - read_slang -C $readfile + #Read vtr_primitives library and user design verilog in same command + read_slang -v $env(PRIMITIVES) {*}$slang_tops -C $readfile } elseif {$env(PARSER) == "default" } { puts "Using Yosys read_verilog command" + read_verilog -nomem2reg +/parmys/vtr_primitives.v + setattr -mod -set keep_hierarchy 1 single_port_ram + setattr -mod -set keep_hierarchy 1 dual_port_ram read_verilog -sv -nolatches XXX } else { error "Invalid PARSER" diff --git a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py index 72415d6b83a..75843010f57 100644 --- a/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py +++ b/vtr_flow/scripts/python_libs/vtr/parmys/parmys.py @@ -251,6 +251,7 @@ def run( # set the parser if parmys_args["parser"] in YOSYS_PARSERS: os.environ["PARSER"] = parmys_args["parser"] + os.environ["PRIMITIVES"] = str(vtr.paths.vtr_primitives_path) del parmys_args["parser"] else: raise vtr.VtrError( diff --git a/vtr_flow/scripts/python_libs/vtr/paths.py b/vtr_flow/scripts/python_libs/vtr/paths.py index ce65148ffef..d6b1066f862 100644 --- a/vtr_flow/scripts/python_libs/vtr/paths.py +++ b/vtr_flow/scripts/python_libs/vtr/paths.py @@ -7,6 +7,7 @@ # VTR Paths vtr_flow_path = root_path / "vtr_flow" +vtr_primitives_path = root_path / "build" / "share" / "yosys" / "parmys" / "vtr_primitives.v" # ODIN paths odin_path = root_path / "odin_ii" diff --git a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt index 20faa1c1855..7f1269d8082 100644 --- a/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt +++ b/vtr_flow/tasks/regression_tests/vtr_reg_system_verilog/koios_sv/config/golden_results.txt @@ -1,2 +1,2 @@ arch circuit script_params vtr_flow_elapsed_time vtr_max_mem_stage vtr_max_mem error odin_synth_time max_odin_mem parmys_synth_time max_parmys_mem abc_depth abc_synth_time abc_cec_time abc_sec_time max_abc_mem ace_time max_ace_mem num_clb num_io num_memories num_mult vpr_status vpr_revision vpr_build_info vpr_compiler vpr_compiled hostname rundir max_vpr_mem num_primary_inputs num_primary_outputs num_pre_packed_nets num_pre_packed_blocks num_netlist_clocks num_post_packed_nets num_post_packed_blocks device_width device_height device_grid_tiles device_limiting_resources device_name pack_mem pack_time initial_placed_wirelength_est placed_wirelength_est total_swap accepted_swap rejected_swap aborted_swap place_mem place_time place_quench_time initial_placed_CPD_est placed_CPD_est placed_setup_TNS_est placed_setup_WNS_est placed_geomean_nonvirtual_intradomain_critical_path_delay_est place_delay_matrix_lookup_time place_quench_timing_analysis_time place_quench_sta_time place_total_timing_analysis_time place_total_sta_time ap_mem ap_time ap_full_legalizer_mem ap_full_legalizer_time min_chan_width routed_wirelength min_chan_width_route_success_iteration logic_block_area_total logic_block_area_used min_chan_width_routing_area_total min_chan_width_routing_area_per_tile min_chan_width_route_time min_chan_width_total_timing_analysis_time min_chan_width_total_sta_time crit_path_num_rr_graph_nodes crit_path_num_rr_graph_edges crit_path_collapsed_nodes crit_path_routed_wirelength crit_path_route_success_iteration crit_path_total_nets_routed crit_path_total_connections_routed crit_path_total_heap_pushes crit_path_total_heap_pops critical_path_delay geomean_nonvirtual_intradomain_critical_path_delay setup_TNS setup_WNS hold_TNS hold_WNS crit_path_routing_area_total crit_path_routing_area_per_tile router_lookahead_computation_time crit_path_route_time crit_path_create_rr_graph_time crit_path_create_intra_cluster_rr_graph_time crit_path_tile_lookahead_computation_time crit_path_router_lookahead_computation_time crit_path_total_timing_analysis_time crit_path_total_sta_time -k6_frac_N10_frac_chain_mem32K_40nm.xml deepfreeze.style1.sv common 436.14 parmys 1.86 GiB -1 -1 411.69 1951548 3 0.26 -1 -1 39048 -1 -1 569 3 0 0 success v8.0.0-13294-ga4090df7f-dirty release IPO VTR_ASSERT_LEVEL=2 debug_logging GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-07-11T13:46:55 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone/vtr_flow/scripts 84760 3 513 1838 2166 1 824 1085 30 30 900 clb auto 41.9 MiB 0.69 4207.31 1231 575104 399781 38987 136336 82.6 MiB 0.70 0.01 4.09934 2.34735 -601.556 -2.34735 2.34735 0.70 0.00153716 0.00141826 0.186598 0.172244 -1 -1 -1 -1 26 2161 10 4.8774e+07 3.06657e+07 1.76811e+06 1964.57 2.04 0.502771 0.465859 83012 347295 -1 1972 8 569 767 17591 4270 2.4085 2.4085 -599.698 -2.4085 0 0 2.17697e+06 2418.86 0.08 0.06 0.18 -1 -1 0.08 0.0661326 0.0635241 +k6_frac_N10_frac_chain_mem32K_40nm.xml deepfreeze.style1.sv common 435.28 parmys 1.87 GiB -1 -1 415.18 1962736 3 0.25 -1 -1 39104 -1 -1 569 3 0 0 success v9.0.0-candidate1-1880-g344f640f2 release IPO VTR_ASSERT_LEVEL=2 GNU 11.4.0 on Linux-6.8.0-60-generic x86_64 2025-08-01T12:04:01 llavign1-OptiPlex-7070 /home/llavign1/Gits/vtr-clone 85372 3 513 1841 2169 1 840 1085 30 30 900 clb auto 41.9 MiB 0.68 4256.38 1281 597396 415577 40471 141348 83.2 MiB 0.63 0.01 4.02124 2.14271 -588.327 -2.14271 2.14271 0.67 0.00153459 0.00141875 0.182762 0.169089 -1 -1 -1 -1 34 2075 10 4.8774e+07 3.06657e+07 2.17697e+06 2418.86 2.43 0.765454 0.707678 87508 434353 -1 1961 7 541 748 16627 4050 2.37143 2.37143 -596.655 -2.37143 0 0 2.67770e+06 2975.22 0.08 0.05 0.21 -1 -1 0.08 0.0574656 0.0553687