From d9ab71021ca590db8bffabaa0829b58f18ee7288 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Fri, 22 Aug 2025 13:55:00 -0400 Subject: [PATCH 1/2] Change e_pin_type to enum class --- libs/libarchfpga/src/arch_util.cpp | 15 +-- libs/libarchfpga/src/physical_types.cpp | 15 +-- libs/libarchfpga/src/physical_types.h | 18 ++-- libs/libarchfpga/src/physical_types_util.cpp | 34 ++++--- .../src/read_fpga_interchange_arch.cpp | 11 ++- libs/libarchfpga/src/read_xml_arch_file.cpp | 11 ++- libs/librrgraph/src/base/check_rr_graph.cpp | 7 +- libs/librrgraph/src/base/rr_edge.h | 3 +- libs/librrgraph/src/base/rr_graph_storage.cpp | 10 +- libs/librrgraph/src/base/rr_graph_storage.h | 13 +-- libs/librrgraph/src/base/rr_graph_utils.cpp | 7 +- libs/librrgraph/src/base/rr_graph_utils.h | 5 +- libs/librrgraph/src/base/rr_node.h | 7 +- .../src/io/rr_graph_uxsdcxx_serializer.h | 20 ++-- .../utils/alloc_and_load_rr_indexed_data.cpp | 23 +++-- libs/librrgraph/src/utils/librrgraph_types.h | 4 + utils/fasm/src/fasm.cpp | 2 +- utils/fasm/src/fasm_utils.h | 2 + utils/route_diag/src/main.cpp | 9 +- vpr/src/base/ShowSetup.cpp | 5 +- vpr/src/base/check_netlist.cpp | 6 +- vpr/src/base/clustered_netlist.cpp | 4 +- vpr/src/base/netlist_writer.cpp | 4 +- vpr/src/base/old_traceback.cpp | 8 +- vpr/src/base/old_traceback.h | 2 +- vpr/src/base/place_and_route.cpp | 2 +- vpr/src/base/read_netlist.cpp | 13 +-- vpr/src/base/read_route.cpp | 2 +- vpr/src/base/stats.cpp | 2 +- vpr/src/base/vpr_context.h | 2 +- vpr/src/base/vpr_types.h | 37 ++++--- vpr/src/draw/draw.cpp | 4 +- vpr/src/draw/draw_basic.cpp | 8 +- vpr/src/draw/draw_searchbar.cpp | 3 +- vpr/src/draw/draw_toggle_functions.cpp | 8 +- vpr/src/draw/draw_types.h | 2 +- vpr/src/pack/cluster_feasibility_filter.cpp | 39 ++++---- vpr/src/pack/cluster_legalizer.cpp | 2 +- vpr/src/pack/cluster_placement.cpp | 4 +- vpr/src/pack/cluster_router.cpp | 26 ++--- vpr/src/pack/lb_type_rr_graph.cpp | 8 +- vpr/src/pack/output_clustering.cpp | 10 +- vpr/src/pack/pack_types.h | 13 +-- vpr/src/pack/pb_type_graph.cpp | 12 +-- vpr/src/pack/pb_type_graph_annotations.cpp | 5 +- vpr/src/pack/post_routing_pb_pin_fixup.cpp | 7 +- vpr/src/pack/prepack.cpp | 4 +- vpr/src/place/compressed_grid.h | 7 +- .../compute_delta_delays_utils.cpp | 16 +-- .../delay_model/override_delay_model.cpp | 13 +-- vpr/src/place/initial_placement.cpp | 44 ++++----- .../centroid_move_generator.cpp | 2 +- .../move_generators/median_move_generator.cpp | 14 +-- vpr/src/place/move_utils.cpp | 18 ++-- vpr/src/place/net_cost_handler.cpp | 66 ++++++------- vpr/src/place/noc_place_checkpoint.cpp | 2 +- vpr/src/place/place_macro.cpp | 34 +++---- vpr/src/place/place_macro.h | 2 +- vpr/src/place/timing/PlacerTimingCosts.cpp | 2 +- vpr/src/power/power.cpp | 6 +- vpr/src/power/power_components.cpp | 6 +- vpr/src/route/check_route.cpp | 2 +- vpr/src/route/edge_groups.cpp | 6 +- vpr/src/route/edge_groups.h | 2 +- vpr/src/route/overuse_report.cpp | 3 +- vpr/src/route/route_common.cpp | 11 ++- vpr/src/route/route_net.tpp | 4 +- vpr/src/route/route_tree.cpp | 6 +- vpr/src/route/router_delay_profiling.cpp | 6 +- .../router_lookahead_compressed_map.cpp | 10 +- .../router_lookahead_map_utils.cpp | 17 ++-- .../router_lookahead_report.cpp | 2 +- .../router_lookahead_sampling.cpp | 13 +-- .../route/rr_graph_generation/cb_metrics.cpp | 23 ++--- .../rr_graph_generation/clb2clb_directs.cpp | 4 +- .../clock_connection_builders.h | 7 +- .../clock_network_builders.h | 44 +++++---- .../route/rr_graph_generation/rr_graph.cpp | 97 ++++++++++--------- .../route/rr_graph_generation/rr_graph2.cpp | 10 +- .../rr_graph_indexed_data.cpp | 2 +- .../rr_graph_generation/rr_node_indices.cpp | 9 +- .../tileable_rr_graph/rr_gsb.cpp | 13 +-- .../tileable_rr_graph_gsb.cpp | 2 +- .../tileable_rr_graph_node_builder.cpp | 16 +-- vpr/src/timing/PreClusterTimingManager.cpp | 4 +- vpr/src/timing/net_delay.cpp | 2 +- vpr/src/util/vpr_utils.cpp | 7 +- 87 files changed, 527 insertions(+), 485 deletions(-) create mode 100644 libs/librrgraph/src/utils/librrgraph_types.h diff --git a/libs/libarchfpga/src/arch_util.cpp b/libs/libarchfpga/src/arch_util.cpp index 8e79081c182..126cc87e95b 100644 --- a/libs/libarchfpga/src/arch_util.cpp +++ b/libs/libarchfpga/src/arch_util.cpp @@ -4,6 +4,7 @@ #include #include "logic_types.h" +#include "physical_types.h" #include "vtr_assert.h" #include "vtr_list.h" #include "vtr_memory.h" @@ -669,12 +670,12 @@ void ProcessMemoryClass(t_pb_type* mem_pb_type) { mem_pb_type->modes[0].parent_pb_type = mem_pb_type; mem_pb_type->modes[0].index = 0; mem_pb_type->modes[0].mode_power = new t_mode_power(); - num_pb = OPEN; + num_pb = ARCH_FPGA_UNDEFINED_VAL; for (i = 0; i < mem_pb_type->num_ports; i++) { if (mem_pb_type->ports[i].port_class != nullptr && strstr(mem_pb_type->ports[i].port_class, "data") == mem_pb_type->ports[i].port_class) { - if (num_pb == OPEN) { + if (num_pb == ARCH_FPGA_UNDEFINED_VAL) { num_pb = mem_pb_type->ports[i].num_pins; } else if (num_pb != mem_pb_type->ports[i].num_pins) { archfpga_throw(get_arch_file_name(), 0, @@ -1206,7 +1207,7 @@ void setup_pin_classes(t_physical_tile_type* type) { int num_class; for (int i = 0; i < type->num_pins; i++) { - type->pin_class.push_back(OPEN); + type->pin_class.push_back(ARCH_FPGA_UNDEFINED_VAL); type->is_ignored_pin.push_back(true); type->is_pin_global.push_back(true); } @@ -1229,10 +1230,10 @@ void setup_pin_classes(t_physical_tile_type* type) { class_inf.equivalence = port.equivalent; if (port.type == IN_PORT) { - class_inf.type = RECEIVER; + class_inf.type = e_pin_type::RECEIVER; } else { VTR_ASSERT(port.type == OUT_PORT); - class_inf.type = DRIVER; + class_inf.type = e_pin_type::DRIVER; } for (int k = 0; k < port.num_pins; ++k) { @@ -1263,10 +1264,10 @@ void setup_pin_classes(t_physical_tile_type* type) { class_inf.equivalence = port.equivalent; if (port.type == IN_PORT) { - class_inf.type = RECEIVER; + class_inf.type = e_pin_type::RECEIVER; } else { VTR_ASSERT(port.type == OUT_PORT); - class_inf.type = DRIVER; + class_inf.type = e_pin_type::DRIVER; } type->pin_class[pin_count] = num_class; diff --git a/libs/libarchfpga/src/physical_types.cpp b/libs/libarchfpga/src/physical_types.cpp index 0390f00f6dd..84cd5f27b24 100644 --- a/libs/libarchfpga/src/physical_types.cpp +++ b/libs/libarchfpga/src/physical_types.cpp @@ -1,4 +1,5 @@ #include "physical_types.h" +#include "arch_types.h" #include "vtr_math.h" #include "vtr_util.h" #include "vtr_log.h" @@ -164,7 +165,7 @@ int t_physical_tile_type::get_sub_tile_loc_from_pin(int pin_num) const { } } - return OPEN; + return ARCH_FPGA_UNDEFINED_VAL; } bool t_physical_tile_type::is_empty() const { @@ -172,9 +173,9 @@ bool t_physical_tile_type::is_empty() const { } int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_port) const { - int ipin = OPEN; + int ipin = ARCH_FPGA_UNDEFINED_VAL; int port_base_ipin = 0; - int num_port_pins = OPEN; + int num_port_pins = ARCH_FPGA_UNDEFINED_VAL; int pin_offset = 0; bool port_found = false; @@ -197,7 +198,7 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_ pin_offset += sub_tile.num_phy_pins; } - if (num_port_pins != OPEN) { + if (num_port_pins != ARCH_FPGA_UNDEFINED_VAL) { VTR_ASSERT(pin_index_in_port < num_port_pins); ipin = port_base_ipin + pin_index_in_port + pin_offset; @@ -207,14 +208,14 @@ int t_physical_tile_type::find_pin(std::string_view port_name, int pin_index_in_ } int t_physical_tile_type::find_pin_class(std::string_view port_name, int pin_index_in_port, e_pin_type pin_type) const { - int iclass = OPEN; + int iclass = ARCH_FPGA_UNDEFINED_VAL; int ipin = find_pin(port_name, pin_index_in_port); - if (ipin != OPEN) { + if (ipin != ARCH_FPGA_UNDEFINED_VAL) { iclass = pin_class[ipin]; - if (iclass != OPEN) { + if (iclass != ARCH_FPGA_UNDEFINED_VAL) { VTR_ASSERT(class_inf[iclass].type == pin_type); } } diff --git a/libs/libarchfpga/src/physical_types.h b/libs/libarchfpga/src/physical_types.h index 8cc8a762a75..3f1694f0457 100644 --- a/libs/libarchfpga/src/physical_types.h +++ b/libs/libarchfpga/src/physical_types.h @@ -25,6 +25,7 @@ * Authors: Jason Luu and Kenneth Kent */ +#include #include #include #include @@ -42,6 +43,7 @@ #include "logic_types.h" #include "clock_types.h" #include "switchblock_types.h" +#include "arch_types.h" #include "vib_inf.h" @@ -163,7 +165,7 @@ struct t_metadata_dict : vtr::flat_map< /* Pins describe I/O into clustered logic block. * A pin may be unconnected, driving a net or in the fanout, respectively. */ -enum e_pin_type { +enum class e_pin_type : int8_t { OPEN = -1, DRIVER = 0, RECEIVER = 1 @@ -873,9 +875,9 @@ struct t_physical_pin { * above the base die, the layer_num is 1 and so on. */ struct t_physical_tile_loc { - int x = OPEN; - int y = OPEN; - int layer_num = OPEN; + int x = ARCH_FPGA_UNDEFINED_VAL; + int y = ARCH_FPGA_UNDEFINED_VAL; + int layer_num = ARCH_FPGA_UNDEFINED_VAL; t_physical_tile_loc() = default; @@ -884,9 +886,9 @@ struct t_physical_tile_loc { , y(y_val) , layer_num(layer_num_val) {} - // Returns true if this type location layer_num/x/y is not equal to OPEN + // Returns true if this type location layer_num/x/y is not equal to ARCH_FPGA_UNDEFINED_VAL operator bool() const { - return !(x == OPEN || y == OPEN || layer_num == OPEN); + return !(x == ARCH_FPGA_UNDEFINED_VAL || y == ARCH_FPGA_UNDEFINED_VAL || layer_num == ARCH_FPGA_UNDEFINED_VAL); } }; @@ -1369,7 +1371,7 @@ class t_pb_graph_node { * There is a root-level pb_graph_node assigned to each logical type. Each logical type can contain multiple primitives. * If this pb_graph_node is associated with a primitive, a unique number is assigned to it within the logical block level. */ - int primitive_num = OPEN; + int primitive_num = ARCH_FPGA_UNDEFINED_VAL; /* Contains a collection of mode indices that cannot be used as they produce conflicts during VPR packing stage * @@ -1578,7 +1580,7 @@ class t_pb_graph_edge { int* pack_pattern_indices; bool infer_pattern; - int switch_type_idx = OPEN; /* architecture switch id of the edge - used when flat_routing is enabled */ + int switch_type_idx = ARCH_FPGA_UNDEFINED_VAL; /* architecture switch id of the edge - used when flat_routing is enabled */ // class member functions public: diff --git a/libs/libarchfpga/src/physical_types_util.cpp b/libs/libarchfpga/src/physical_types_util.cpp index 846e2f5a69f..5b3abbb2ede 100644 --- a/libs/libarchfpga/src/physical_types_util.cpp +++ b/libs/libarchfpga/src/physical_types_util.cpp @@ -1,4 +1,6 @@ #include +#include "arch_types.h" +#include "physical_types.h" #include "vtr_assert.h" #include "vtr_util.h" @@ -182,8 +184,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr pin_inst_port.logical_block_index = logical_num; pin_inst_port.pb_type_idx = pb_type_idx; pin_inst_port.pin_physical_num = pin_physical_num; - pin_inst_port.port_index = OPEN; - pin_inst_port.pin_index_in_port = OPEN; + pin_inst_port.port_index = ARCH_FPGA_UNDEFINED_VAL; + pin_inst_port.pin_index_in_port = ARCH_FPGA_UNDEFINED_VAL; if (is_flat && logical_num != -1) { auto pb_pin = get_pb_pin_from_pin_physical_num(type, pin_physical_num); @@ -200,8 +202,8 @@ static t_pin_inst_port block_type_pin_index_to_pin_inst(t_physical_tile_type_ptr } } } - VTR_ASSERT(pin_inst_port.port_index != OPEN); - VTR_ASSERT(pin_inst_port.pin_index_in_port != OPEN); + VTR_ASSERT(pin_inst_port.port_index != ARCH_FPGA_UNDEFINED_VAL); + VTR_ASSERT(pin_inst_port.pin_index_in_port != ARCH_FPGA_UNDEFINED_VAL); return pin_inst_port; } @@ -435,7 +437,7 @@ int get_sub_tile_physical_pin(int sub_tile_index, int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block) { - int sub_tile_index = OPEN; + int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL; for (const auto& sub_tile : physical_tile->sub_tiles) { auto eq_sites = sub_tile.equivalent_sites; auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block); @@ -444,7 +446,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ } } - if (sub_tile_index == OPEN) { + if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(__FILE__, __LINE__, "Found no instances of logical block type '%s' within physical tile type '%s'. ", logical_block->name.c_str(), physical_tile->name.c_str()); @@ -458,7 +460,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, int pin) { int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block); - if (sub_tile_index == OPEN) { + if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(__FILE__, __LINE__, "Couldn't find the corresponding physical tile type pin of the logical block type pin %d.", pin); @@ -471,7 +473,7 @@ int get_physical_pin(t_physical_tile_type_ptr physical_tile, int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int sub_tile_capacity) { - int sub_tile_index = OPEN; + int sub_tile_index = ARCH_FPGA_UNDEFINED_VAL; for (const auto& sub_tile : physical_tile->sub_tiles) { auto eq_sites = sub_tile.equivalent_sites; auto it = std::find(eq_sites.begin(), eq_sites.end(), logical_block); @@ -482,7 +484,7 @@ int get_logical_block_physical_sub_tile_index(t_physical_tile_type_ptr physical_ } } - if (sub_tile_index == OPEN) { + if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(__FILE__, __LINE__, "Found no instances of logical block type '%s' within physical tile type '%s'. ", logical_block->name.c_str(), physical_tile->name.c_str()); @@ -528,7 +530,7 @@ int get_physical_pin_at_sub_tile_location(t_physical_tile_type_ptr physical_tile VTR_ASSERT(pin < physical_tile->num_pins); int sub_tile_index = get_logical_block_physical_sub_tile_index(physical_tile, logical_block, sub_tile_capacity); - if (sub_tile_index == OPEN) { + if (sub_tile_index == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(__FILE__, __LINE__, "Couldn't find the corresponding physical tile type pin of the logical block type pin %d.", pin); @@ -610,7 +612,7 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) { int iclass = type->pin_class[ipin]; - if (type->class_inf[iclass].type == DRIVER) + if (type->class_inf[iclass].type == e_pin_type::DRIVER) return true; else return false; @@ -895,7 +897,7 @@ int get_tile_class_max_ptc(t_physical_tile_type_ptr tile, bool is_flat) { /** get information given pin physical number **/ std::tuple get_sub_tile_from_pin_physical_num(t_physical_tile_type_ptr physical_tile, int physical_num) { const t_sub_tile* target_sub_tile = nullptr; - int target_sub_tile_cap = OPEN; + int target_sub_tile_cap = ARCH_FPGA_UNDEFINED_VAL; bool pin_on_tile = is_pin_on_tile(physical_tile, physical_num); @@ -926,7 +928,7 @@ t_logical_block_type_ptr get_logical_block_from_pin_physical_num(t_physical_tile t_logical_block_type_ptr logical_block = nullptr; std::tie(sub_tile, sub_tile_cap) = get_sub_tile_from_pin_physical_num(physical_tile, physical_num); - VTR_ASSERT(sub_tile_cap != OPEN); + VTR_ASSERT(sub_tile_cap != ARCH_FPGA_UNDEFINED_VAL); for (auto logical_block_pin_range_pair : sub_tile->intra_pin_range[sub_tile_cap]) { if (physical_num >= logical_block_pin_range_pair.second.low) { @@ -1189,7 +1191,7 @@ int get_pb_pin_physical_num(t_physical_tile_type_ptr physical_tile, t_logical_block_type_ptr logical_block, int relative_cap, const t_pb_graph_pin* pin) { - int pin_physical_num = OPEN; + int pin_physical_num = ARCH_FPGA_UNDEFINED_VAL; if (pin->is_root_block_pin()) { pin_physical_num = get_physical_pin_at_sub_tile_location(physical_tile, logical_block, @@ -1264,12 +1266,12 @@ bool intra_tile_nodes_connected(t_physical_tile_type_ptr physical_type, const t_sub_tile* from_sub_tile; int from_sub_tile_rel_cap; std::tie(from_sub_tile, from_sub_tile_rel_cap) = get_sub_tile_from_pin_physical_num(physical_type, pin_physical_num); - VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != OPEN); + VTR_ASSERT(from_sub_tile != nullptr && from_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL); const t_sub_tile* to_sub_tile; int to_sub_tile_rel_cap; std::tie(to_sub_tile, to_sub_tile_rel_cap) = get_sub_tile_from_class_physical_num(physical_type, sink_physical_num); - VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != OPEN); + VTR_ASSERT(to_sub_tile != nullptr && to_sub_tile_rel_cap != ARCH_FPGA_UNDEFINED_VAL); return (from_sub_tile_rel_cap == to_sub_tile_rel_cap) && (from_sub_tile == to_sub_tile); diff --git a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp index bb9ec1bdbe7..d9ad5853570 100644 --- a/libs/libarchfpga/src/read_fpga_interchange_arch.cpp +++ b/libs/libarchfpga/src/read_fpga_interchange_arch.cpp @@ -1,5 +1,6 @@ #include "read_fpga_interchange_arch.h" +#include "arch_types.h" #ifdef VTR_ENABLE_CAPNPROTO @@ -550,7 +551,7 @@ struct ArchReader { std::string wire_name = str(wire.getName()); // pin name, bel name - int pin_id = OPEN; + int pin_id = ARCH_FPGA_UNDEFINED_VAL; bool pad_exists = false; bool all_inout_pins = true; std::string pad_bel_name; @@ -577,7 +578,7 @@ struct ArchReader { pin_id = pin; } - if (pin_id == OPEN) { + if (pin_id == ARCH_FPGA_UNDEFINED_VAL) { // If no driver pin has been found, the assumption is that // there must be a PAD with inout pin connected to other inout pins for (auto pin : wire.getPins()) { @@ -594,7 +595,7 @@ struct ArchReader { } } - VTR_ASSERT(pin_id != OPEN); + VTR_ASSERT(pin_id != ARCH_FPGA_UNDEFINED_VAL); auto out_pin = site.getBelPins()[pin_id]; auto out_pin_bel = get_bel_reader(site, str(out_pin.getBel())); @@ -1674,10 +1675,10 @@ struct ArchReader { * If a bel name index is specified, the bel pins are processed, otherwise the site ports * are processed instead. */ - void process_block_ports(t_pb_type* pb_type, Device::SiteType::Reader& site, size_t bel_name = OPEN) { + void process_block_ports(t_pb_type* pb_type, Device::SiteType::Reader& site, size_t bel_name = ARCH_FPGA_UNDEFINED_VAL) { // Prepare data based on pb_type level std::set> pins; - if (bel_name == (size_t)OPEN) { + if (bel_name == (size_t)ARCH_FPGA_UNDEFINED_VAL) { for (auto pin : site.getPins()) { auto dir = pin.getDir() == INPUT ? IN_PORT : OUT_PORT; pins.emplace(str(pin.getName()), dir, 1); diff --git a/libs/libarchfpga/src/read_xml_arch_file.cpp b/libs/libarchfpga/src/read_xml_arch_file.cpp index 12731299d0f..676c78d0d35 100644 --- a/libs/libarchfpga/src/read_xml_arch_file.cpp +++ b/libs/libarchfpga/src/read_xml_arch_file.cpp @@ -44,6 +44,7 @@ #include #include "logic_types.h" +#include "physical_types.h" #include "pugixml.hpp" #include "pugixml_util.hpp" @@ -643,10 +644,10 @@ static void load_pin_loc(pugi::xml_node Locations, for (int pin_num = 0; pin_num < type->num_pins; ++pin_num) { auto class_type = get_pin_type_from_pin_physical_num(type, pin_num); - if (class_type == RECEIVER) { + if (class_type == e_pin_type::RECEIVER) { input_pins.push_back(pin_num); } else { - VTR_ASSERT(class_type == DRIVER); + VTR_ASSERT(class_type == e_pin_type::DRIVER); output_pins.push_back(pin_num); } } @@ -2254,7 +2255,7 @@ static void process_switch_block_locations(pugi::xml_node switchblock_locations, //Use the specified switch sb_switch_override = find_switch_by_name(arch.switches, sb_switch_override_str); - if (sb_switch_override == OPEN) { + if (sb_switch_override == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations), vtr::string_fmt("Invalid 'switch_override' attribute '%s' (no matching switch named '%s' found)\n", sb_switch_override_str.c_str(), sb_switch_override_str.c_str()) @@ -2307,7 +2308,7 @@ static void process_switch_block_locations(pugi::xml_node switchblock_locations, //Use the specified switch internal_switch = find_switch_by_name(arch.switches, internal_switch_name); - if (internal_switch == OPEN) { + if (internal_switch == ARCH_FPGA_UNDEFINED_VAL) { archfpga_throw(loc_data.filename_c_str(), loc_data.line(switchblock_locations), vtr::string_fmt("Invalid 'internal_switch' attribute '%s' (no matching switch named '%s' found)\n", internal_switch_name.c_str(), internal_switch_name.c_str()) @@ -5034,7 +5035,7 @@ static int find_switch_by_name(const std::vector& switches, s } } - return -1; + return ARCH_FPGA_UNDEFINED_VAL; } static e_side string_to_side(const std::string& side_str) { diff --git a/libs/librrgraph/src/base/check_rr_graph.cpp b/libs/librrgraph/src/base/check_rr_graph.cpp index 0adda764668..8643ea6f55d 100644 --- a/libs/librrgraph/src/base/check_rr_graph.cpp +++ b/libs/librrgraph/src/base/check_rr_graph.cpp @@ -1,3 +1,4 @@ +#include "physical_types.h" #include "vtr_log.h" #include "vtr_util.h" @@ -470,7 +471,7 @@ void check_rr_node(const RRGraphView& rr_graph, } - e_pin_type class_type = OPEN; + e_pin_type class_type = e_pin_type::OPEN; int class_num_pins = -1; switch (rr_type) { case e_rr_type::SOURCE: @@ -478,7 +479,7 @@ void check_rr_node(const RRGraphView& rr_graph, class_type = get_class_type_from_class_physical_num(type, ptc_num); class_num_pins = get_class_num_pins_from_class_physical_num(type, ptc_num); if (ptc_num >= class_max_ptc - || class_type != ((rr_type == e_rr_type::SOURCE) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::SOURCE) ? e_pin_type::DRIVER : e_pin_type::RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } @@ -502,7 +503,7 @@ void check_rr_node(const RRGraphView& rr_graph, case e_rr_type::IPIN: class_type = get_pin_type_from_pin_physical_num(type, ptc_num); if (ptc_num >= pin_max_ptc - || class_type != ((rr_type == e_rr_type::OPIN) ? DRIVER : RECEIVER)) { + || class_type != ((rr_type == e_rr_type::OPIN) ? e_pin_type::DRIVER : e_pin_type::RECEIVER)) { VPR_ERROR(VPR_ERROR_ROUTE, "in check_rr_node: inode %d (type %d) had a ptc_num of %d.\n", inode, rr_type, ptc_num); } diff --git a/libs/librrgraph/src/base/rr_edge.h b/libs/librrgraph/src/base/rr_edge.h index 0f95a96167f..3a81c9f7a51 100644 --- a/libs/librrgraph/src/base/rr_edge.h +++ b/libs/librrgraph/src/base/rr_edge.h @@ -1,6 +1,7 @@ #pragma once #include "physical_types.h" +#include "librrgraph_types.h" #include "rr_graph_fwd.h" struct t_rr_edge_info { @@ -12,7 +13,7 @@ struct t_rr_edge_info { RRNodeId from_node = RRNodeId::INVALID(); RRNodeId to_node = RRNodeId::INVALID(); - short switch_type = OPEN; + short switch_type = LIBRRGRAPH_UNDEFINED_VAL; bool remapped = false; friend bool operator<(const t_rr_edge_info& lhs, const t_rr_edge_info& rhs) { diff --git a/libs/librrgraph/src/base/rr_graph_storage.cpp b/libs/librrgraph/src/base/rr_graph_storage.cpp index 3e9edec2520..c3ba21ccec0 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.cpp +++ b/libs/librrgraph/src/base/rr_graph_storage.cpp @@ -1,7 +1,9 @@ #include #include "arch_types.h" #include "rr_graph_storage.h" +#include "physical_types.h" #include "vtr_error.h" +#include "librrgraph_types.h" #include @@ -466,7 +468,7 @@ size_t t_rr_graph_storage::count_rr_switches( if (arch_switch_inf[iswitch].fixed_Tdel()) { //If delay is independent of fanin drop the unique fanin info - fanin = ARCH_FPGA_UNDEFINED_VAL; + fanin = LIBRRGRAPH_UNDEFINED_VAL; } if (arch_switch_fanins[iswitch].count(fanin) == 0) { //New fanin for this switch @@ -484,7 +486,7 @@ size_t t_rr_graph_storage::count_rr_switches( for(size_t iswitch = 0; iswitch < arch_switch_counts.size(); ++iswitch) { if(arch_switch_fanins[iswitch].empty()){ if(arch_switch_inf[iswitch].fixed_Tdel()){ - arch_switch_fanins[iswitch][ARCH_FPGA_UNDEFINED_VAL] = num_rr_switches++; + arch_switch_fanins[iswitch][LIBRRGRAPH_UNDEFINED_VAL] = num_rr_switches++; } } } @@ -506,8 +508,8 @@ void t_rr_graph_storage::remap_rr_node_switch_indices(const t_arch_switch_fanin& int switch_index = edge_switch_[edge]; int fanin = node_fan_in_[to_node]; - if (switch_fanin[switch_index].count(ARCH_FPGA_UNDEFINED_VAL) == 1) { - fanin = ARCH_FPGA_UNDEFINED_VAL; + if (switch_fanin[switch_index].count(LIBRRGRAPH_UNDEFINED_VAL) == 1) { + fanin = LIBRRGRAPH_UNDEFINED_VAL; } auto itr = switch_fanin[switch_index].find(fanin); diff --git a/libs/librrgraph/src/base/rr_graph_storage.h b/libs/librrgraph/src/base/rr_graph_storage.h index c4133e2f253..0bf58ff4539 100644 --- a/libs/librrgraph/src/base/rr_graph_storage.h +++ b/libs/librrgraph/src/base/rr_graph_storage.h @@ -2,6 +2,7 @@ #include +#include "librrgraph_types.h" #include "vtr_vector.h" #include "physical_types.h" #include "rr_graph_storage_utils.h" @@ -52,13 +53,13 @@ * This field is valid only for IPINs and OPINs and should be ignored * * otherwise. */ struct alignas(16) t_rr_node_data { - int16_t cost_index_ = -1; - int16_t rc_index_ = -1; + int16_t cost_index_ = LIBRRGRAPH_UNDEFINED_VAL; + int16_t rc_index_ = LIBRRGRAPH_UNDEFINED_VAL; - int16_t xlow_ = -1; - int16_t ylow_ = -1; - int16_t xhigh_ = -1; - int16_t yhigh_ = -1; + int16_t xlow_ = LIBRRGRAPH_UNDEFINED_VAL; + int16_t ylow_ = LIBRRGRAPH_UNDEFINED_VAL; + int16_t xhigh_ = LIBRRGRAPH_UNDEFINED_VAL; + int16_t yhigh_ = LIBRRGRAPH_UNDEFINED_VAL; e_rr_type type_ = e_rr_type::NUM_RR_TYPES; diff --git a/libs/librrgraph/src/base/rr_graph_utils.cpp b/libs/librrgraph/src/base/rr_graph_utils.cpp index 76c4c6c0428..614961c4c67 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.cpp +++ b/libs/librrgraph/src/base/rr_graph_utils.cpp @@ -4,6 +4,7 @@ #include "rr_graph_obj.h" #include "rr_graph_builder.h" #include "rr_graph_view.h" +#include "librrgraph_types.h" /* * @brief Walk backwards from origin SINK, and insert all cluster-edge IPINs to which origin is connected to sink_ipins @@ -98,7 +99,7 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in seg_index_of_sblock: to_node %d is of type %d.\n", to_node, to_rr_type); - return OPEN; //Should not reach here once thrown + return LIBRRGRAPH_UNDEFINED_VAL; //Should not reach here once thrown } } /* End from_rr_type is CHANX */ @@ -115,7 +116,7 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in seg_index_of_sblock: to_node %d is of type %d.\n", to_node, to_rr_type); - return OPEN; //Should not reach here once thrown + return LIBRRGRAPH_UNDEFINED_VAL; //Should not reach here once thrown } } /* End from_rr_type is CHANY */ @@ -123,7 +124,7 @@ int seg_index_of_sblock(const RRGraphView& rr_graph, int from_node, int to_node) VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in seg_index_of_sblock: from_node %d is of type %d.\n", from_node, from_rr_type); - return OPEN; //Should not reach here once thrown + return LIBRRGRAPH_UNDEFINED_VAL; //Should not reach here once thrown } } diff --git a/libs/librrgraph/src/base/rr_graph_utils.h b/libs/librrgraph/src/base/rr_graph_utils.h index 6aa15fd5fbe..ebe48e3b374 100644 --- a/libs/librrgraph/src/base/rr_graph_utils.h +++ b/libs/librrgraph/src/base/rr_graph_utils.h @@ -6,6 +6,7 @@ */ #include +#include "librrgraph_types.h" #include "rr_graph_builder.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" @@ -14,8 +15,8 @@ class RRGraphView; struct t_pin_chain_node { - int pin_physical_num = OPEN; - int nxt_node_idx = OPEN; + int pin_physical_num = LIBRRGRAPH_UNDEFINED_VAL; + int nxt_node_idx = LIBRRGRAPH_UNDEFINED_VAL; t_pin_chain_node() = default; t_pin_chain_node(int pin_num, int nxt_idx) noexcept diff --git a/libs/librrgraph/src/base/rr_node.h b/libs/librrgraph/src/base/rr_node.h index a2cd0aa9b2c..a4e50a118c3 100644 --- a/libs/librrgraph/src/base/rr_node.h +++ b/libs/librrgraph/src/base/rr_node.h @@ -1,7 +1,8 @@ #pragma once #include -#include "physical_types.h" +#include "switchblock_types.h" +#include "librrgraph_types.h" #include "rr_node_fwd.h" #include "rr_graph_fwd.h" #include "rr_node_types.h" @@ -134,8 +135,8 @@ class t_rr_node { struct t_rr_indexed_data { float base_cost = std::numeric_limits::quiet_NaN(); float saved_base_cost = std::numeric_limits::quiet_NaN(); - int ortho_cost_index = OPEN; - int seg_index = OPEN; + int ortho_cost_index = LIBRRGRAPH_UNDEFINED_VAL; + int seg_index = LIBRRGRAPH_UNDEFINED_VAL; float inv_length = std::numeric_limits::quiet_NaN(); float T_linear = std::numeric_limits::quiet_NaN(); float T_quadratic = std::numeric_limits::quiet_NaN(); diff --git a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h index 13a223b627f..ea09e79a818 100644 --- a/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h +++ b/libs/librrgraph/src/io/rr_graph_uxsdcxx_serializer.h @@ -5,6 +5,7 @@ #include #include +#include "physical_types.h" #include "rr_graph_uxsdcxx_interface.h" #include "rr_node.h" @@ -17,6 +18,7 @@ #include "check_rr_graph.h" #include "read_xml_arch_file.h" +#include "librrgraph_types.h" #include "device_grid.h" #include "alloc_and_load_rr_indexed_data.h" @@ -36,9 +38,9 @@ class MetadataBind { : is_node_(false) , is_edge_(false) , ignore_(false) - , inode_(OPEN) - , sink_node_(OPEN) - , switch_id_(OPEN) + , inode_(LIBRRGRAPH_UNDEFINED_VAL) + , sink_node_(LIBRRGRAPH_UNDEFINED_VAL) + , switch_id_(LIBRRGRAPH_UNDEFINED_VAL) , strings_(strings) , name_(empty) , value_(empty) @@ -2117,11 +2119,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { e_pin_type from_uxsd_pin_type(uxsd::enum_pin_type type) { switch (type) { case uxsd::enum_pin_type::OPEN: - return OPEN; + return e_pin_type::OPEN; case uxsd::enum_pin_type::OUTPUT: - return DRIVER; + return e_pin_type::DRIVER; case uxsd::enum_pin_type::INPUT: - return RECEIVER; + return e_pin_type::RECEIVER; default: report_error( "Unknown pin class type %d", type); @@ -2130,11 +2132,11 @@ class RrGraphSerializer final : public uxsd::RrGraphBase { uxsd::enum_pin_type to_uxsd_pin_type(e_pin_type type) { switch (type) { - case OPEN: + case e_pin_type::OPEN: return uxsd::enum_pin_type::OPEN; - case DRIVER: + case e_pin_type::DRIVER: return uxsd::enum_pin_type::OUTPUT; - case RECEIVER: + case e_pin_type::RECEIVER: return uxsd::enum_pin_type::INPUT; default: report_error( diff --git a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp index 67530e6e9ce..2007b713537 100644 --- a/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp +++ b/libs/librrgraph/src/utils/alloc_and_load_rr_indexed_data.cpp @@ -7,7 +7,7 @@ #include #include -#include "arch_types.h" +#include "librrgraph_types.h" #include "vtr_assert.h" #include "vtr_log.h" #include "vtr_math.h" @@ -70,11 +70,10 @@ void alloc_and_load_rr_indexed_data(const RRGraphView& rr_graph, * * all other fields are invalid. For SOURCES, SINKs and OPINs, all fields * * * other than base_cost are invalid. Mark invalid fields as OPEN for safety. */ - constexpr float nan = std::numeric_limits::quiet_NaN(); for (int i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) { - rr_indexed_data[RRIndexedDataId(i)].ortho_cost_index = OPEN; - rr_indexed_data[RRIndexedDataId(i)].seg_index = OPEN; - rr_indexed_data[RRIndexedDataId(i)].inv_length = nan; + rr_indexed_data[RRIndexedDataId(i)].ortho_cost_index = LIBRRGRAPH_UNDEFINED_VAL; + rr_indexed_data[RRIndexedDataId(i)].seg_index = LIBRRGRAPH_UNDEFINED_VAL; + rr_indexed_data[RRIndexedDataId(i)].inv_length = std::numeric_limits::quiet_NaN();; rr_indexed_data[RRIndexedDataId(i)].T_linear = 0.; rr_indexed_data[RRIndexedDataId(i)].T_quadratic = 0.; rr_indexed_data[RRIndexedDataId(i)].C_load = 0.; @@ -432,7 +431,7 @@ static std::vector count_rr_segment_types(const RRGraphView& rr_graph, c int seg_index = rr_indexed_data[cost_index].seg_index; - VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index != LIBRRGRAPH_UNDEFINED_VAL); if (seg_index >= int(rr_segment_type_counts.size())) { rr_segment_type_counts.resize(seg_index + 1, 0); @@ -512,7 +511,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, vtr::vector> switch_R_total(rr_indexed_data.size()); vtr::vector> switch_T_total(rr_indexed_data.size()); vtr::vector> switch_Cinternal_total(rr_indexed_data.size()); - vtr::vector switches_buffered(rr_indexed_data.size(), ARCH_FPGA_UNDEFINED_VAL); + vtr::vector switches_buffered(rr_indexed_data.size(), LIBRRGRAPH_UNDEFINED_VAL); /* * Walk through the RR graph and collect all R and C values of all the nodes, @@ -538,7 +537,7 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, double avg_switch_Cinternal = 0; int num_switches = 0; int num_shorts = 0; - short buffered = ARCH_FPGA_UNDEFINED_VAL; + short buffered = LIBRRGRAPH_UNDEFINED_VAL; calculate_average_switch(rr_graph, (size_t)rr_id, avg_switch_R, avg_switch_T, avg_switch_Cinternal, num_switches, num_shorts, buffered, fan_in_list); if (num_switches == 0) { @@ -557,13 +556,13 @@ static void load_rr_indexed_data_T_values(const RRGraphView& rr_graph, switch_R_total[cost_index].push_back(avg_switch_R); switch_T_total[cost_index].push_back(avg_switch_T); switch_Cinternal_total[cost_index].push_back(avg_switch_Cinternal); - if (buffered == ARCH_FPGA_UNDEFINED_VAL) { + if (buffered == LIBRRGRAPH_UNDEFINED_VAL) { /* this segment does not have any outgoing edges to other general routing wires */ continue; } /* need to make sure all wire switches of a given wire segment type have the same 'buffered' value */ - if (switches_buffered[cost_index] == ARCH_FPGA_UNDEFINED_VAL) { + if (switches_buffered[cost_index] == LIBRRGRAPH_UNDEFINED_VAL) { switches_buffered[cost_index] = buffered; } else { if (switches_buffered[cost_index] != buffered) { @@ -647,7 +646,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_Cinternal = 0; num_switches = 0; num_shorts = 0; - buffered = ARCH_FPGA_UNDEFINED_VAL; + buffered = LIBRRGRAPH_UNDEFINED_VAL; for (const auto& edge : fan_in_list[node]) { /* want to get C/R/Tdel/Cinternal of switches that connect this track segment to other track segments */ if (rr_graph.node_type(node) == e_rr_type::CHANX || rr_graph.node_type(node) == e_rr_type::CHANY) { @@ -662,7 +661,7 @@ static void calculate_average_switch(const RRGraphView& rr_graph, int inode, dou avg_switch_T += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Tdel; avg_switch_Cinternal += rr_graph.rr_switch_inf(RRSwitchId(switch_index)).Cinternal; - if (buffered == ARCH_FPGA_UNDEFINED_VAL) { + if (buffered == LIBRRGRAPH_UNDEFINED_VAL) { if (rr_graph.rr_switch_inf(RRSwitchId(switch_index)).buffered()) { buffered = 1; } else { diff --git a/libs/librrgraph/src/utils/librrgraph_types.h b/libs/librrgraph/src/utils/librrgraph_types.h new file mode 100644 index 00000000000..c4928c05770 --- /dev/null +++ b/libs/librrgraph/src/utils/librrgraph_types.h @@ -0,0 +1,4 @@ +#pragma once + +// Value for UNDEFINED data +constexpr int LIBRRGRAPH_UNDEFINED_VAL = -1; \ No newline at end of file diff --git a/utils/fasm/src/fasm.cpp b/utils/fasm/src/fasm.cpp index 829ae98af27..047bd7df012 100644 --- a/utils/fasm/src/fasm.cpp +++ b/utils/fasm/src/fasm.cpp @@ -118,7 +118,7 @@ void FasmWriterVisitor::check_interconnect(const t_pb_routes &pb_routes, int ino /* No previous driver implies that this is either a top-level input pin * or a primitive output pin */ int prev_node = iter->second.driver_pb_pin_id; - if(prev_node == OPEN) { + if(prev_node == fasm::UNDEFINED) { return; } diff --git a/utils/fasm/src/fasm_utils.h b/utils/fasm/src/fasm_utils.h index a812b179fc3..de9ea7ccd33 100644 --- a/utils/fasm/src/fasm_utils.h +++ b/utils/fasm/src/fasm_utils.h @@ -8,6 +8,8 @@ namespace fasm { +constexpr int UNDEFINED = -1; + // Parse a port name that may have an index. // // in="A" parts to *name="A", *index=0 diff --git a/utils/route_diag/src/main.cpp b/utils/route_diag/src/main.cpp index e89b554d5fa..3dd599504a0 100644 --- a/utils/route_diag/src/main.cpp +++ b/utils/route_diag/src/main.cpp @@ -12,6 +12,7 @@ #include +#include "vpr_types.h" #include "vtr_error.h" #include "vtr_log.h" #include "vtr_time.h" @@ -126,7 +127,7 @@ static void do_one_route(const Netlist<>& net_list, VTR_ASSERT(cheapest.index == sink_node); vtr::optional rt_node_of_sink; - std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, OPEN, nullptr, router_opts.flat_routing); + std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, UNDEFINED, nullptr, router_opts.flat_routing); //find delay float net_delay = rt_node_of_sink.value().Tdel; @@ -173,7 +174,7 @@ static void profile_source(const Netlist<>& net_list, vtr::Matrix delays({grid.width(), grid.height()}, std::numeric_limits::infinity()); - vtr::Matrix sink_nodes({grid.width(), grid.height()}, OPEN); + vtr::Matrix sink_nodes({grid.width(), grid.height()}, UNDEFINED); for (int sink_x = start_x; sink_x <= end_x; sink_x++) { for (int sink_y = start_y; sink_y <= end_y; sink_y++) { @@ -181,11 +182,11 @@ static void profile_source(const Netlist<>& net_list, continue; } - auto best_sink_ptcs = get_best_classes(RECEIVER, + auto best_sink_ptcs = get_best_classes(e_pin_type::RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, layer_num})); bool successfully_routed; for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); + VTR_ASSERT(sink_ptc != UNDEFINED); //TODO: should pass layer_num instead of 0 to node_lookup once the multi-die FPGAs support is completed RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(0, sink_x, sink_y, e_rr_type::SINK, sink_ptc); diff --git a/vpr/src/base/ShowSetup.cpp b/vpr/src/base/ShowSetup.cpp index 3b04c43c56c..8309fe73fb8 100644 --- a/vpr/src/base/ShowSetup.cpp +++ b/vpr/src/base/ShowSetup.cpp @@ -3,6 +3,7 @@ #include "ap_flow_enums.h" #include "globals.h" +#include "physical_types.h" #include "physical_types_util.h" #include "vpr_error.h" #include "vpr_types.h" @@ -141,10 +142,10 @@ ClusteredNetlistStats::ClusteredNetlistStats() { if (cluster_ctx.clb_nlist.block_net(blk_id, j) != ClusterNetId::INVALID()) { auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin); - if (pin_type == DRIVER) { + if (pin_type == e_pin_type::DRIVER) { L_num_p_inputs++; } else { - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); L_num_p_outputs++; } } diff --git a/vpr/src/base/check_netlist.cpp b/vpr/src/base/check_netlist.cpp index 63521e5af16..d0f24f901f3 100644 --- a/vpr/src/base/check_netlist.cpp +++ b/vpr/src/base/check_netlist.cpp @@ -186,11 +186,11 @@ static int check_clb_internal_nets(ClusterBlockId iblk, const IntraLbPbPinLookup VTR_ASSERT(pb_route.count(i)); - if (pb_route[i].atom_net_id || pb_route[i].driver_pb_pin_id != OPEN) { + if (pb_route[i].atom_net_id || pb_route[i].driver_pb_pin_id != UNDEFINED) { const t_pb_graph_pin* pb_gpin = pb_graph_pin_lookup.pb_gpin(type->index, i); if ((pb_gpin->port->type == IN_PORT && pb_gpin->is_root_block_pin()) || (pb_gpin->port->type == OUT_PORT && pb_gpin->parent_node->is_primitive())) { - if (pb_route[i].driver_pb_pin_id != OPEN) { + if (pb_route[i].driver_pb_pin_id != UNDEFINED) { VTR_LOG_ERROR( "Internal connectivity error in logic block #%d with output %s." " Internal node %d driven when it shouldn't be driven \n", @@ -198,7 +198,7 @@ static int check_clb_internal_nets(ClusterBlockId iblk, const IntraLbPbPinLookup error++; } } else { - if (!pb_route[i].atom_net_id || pb_route[i].driver_pb_pin_id == OPEN) { + if (!pb_route[i].atom_net_id || pb_route[i].driver_pb_pin_id == UNDEFINED) { VTR_LOG_ERROR( "Internal connectivity error in logic block #%d with output %s." " Internal node %d dangling\n", diff --git a/vpr/src/base/clustered_netlist.cpp b/vpr/src/base/clustered_netlist.cpp index 27e8effa7c9..ad6987ef18f 100644 --- a/vpr/src/base/clustered_netlist.cpp +++ b/vpr/src/base/clustered_netlist.cpp @@ -50,7 +50,7 @@ int ClusteredNetlist::block_pin_net_index(const ClusterBlockId blk_id, const int return pin_net_index(pin_id); } - return OPEN; + return UNDEFINED; } ClusterPinId ClusteredNetlist::block_pin(const ClusterBlockId blk, const int logical_pin_index) const { @@ -93,7 +93,7 @@ int ClusteredNetlist::net_pin_logical_index(const ClusterNetId net_id, int net_p return pin_logical_index(pin_id); } - return OPEN; //No valid pin found + return UNDEFINED; //No valid pin found } /* diff --git a/vpr/src/base/netlist_writer.cpp b/vpr/src/base/netlist_writer.cpp index 53bdc76908a..a4fdca7f0c6 100644 --- a/vpr/src/base/netlist_writer.cpp +++ b/vpr/src/base/netlist_writer.cpp @@ -1990,7 +1990,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::vector determine_lut_permutation(size_t num_inputs, const t_pb* atom_pb) { auto& atom_ctx = g_vpr_ctx.atom(); - std::vector permute(num_inputs, OPEN); + std::vector permute(num_inputs, UNDEFINED); #ifdef DEBUG_LUT_MASK std::cout << "\tInit Permute: {"; @@ -2049,7 +2049,7 @@ class NetlistWriterVisitor : public NetlistVisitor { std::set perm_indicies(permute.begin(), permute.end()); size_t unused_index = 0; for (size_t i = 0; i < permute.size(); i++) { - if (permute[i] == OPEN) { + if (permute[i] == UNDEFINED) { while (perm_indicies.count(unused_index)) { unused_index++; } diff --git a/vpr/src/base/old_traceback.cpp b/vpr/src/base/old_traceback.cpp index de708ca296e..351568902da 100644 --- a/vpr/src/base/old_traceback.cpp +++ b/vpr/src/base/old_traceback.cpp @@ -84,7 +84,7 @@ std::pair traceback_from_route_tree_recurr(t_trace* head, t_ t_trace* curr = alloc_trace_data(); curr->index = size_t(node.inode); curr->net_pin_index = node.net_pin_index; - curr->iswitch = OPEN; + curr->iswitch = UNDEFINED; curr->next = nullptr; if (tail) { @@ -123,11 +123,11 @@ void print_traceback(const t_trace* trace) { RRNodeId inode(trace->index); VTR_LOG("%d (%s)", inode, rr_node_typename[rr_graph.node_type(inode)]); - if (trace->iswitch == OPEN) { + if (trace->iswitch == UNDEFINED) { VTR_LOG(" !"); //End of branch } - if (prev && prev->iswitch != OPEN && !rr_graph.rr_switch_inf(RRSwitchId(prev->iswitch)).configurable()) { + if (prev && prev->iswitch != UNDEFINED && !rr_graph.rr_switch_inf(RRSwitchId(prev->iswitch)).configurable()) { VTR_LOG("*"); //Reached non-configurably } @@ -160,7 +160,7 @@ bool validate_and_update_traceback(t_trace* trace, bool verify_switch_id /* = tr continue; } - if (trace->iswitch == OPEN) { // End of a branch + if (trace->iswitch == UNDEFINED) { // End of a branch // Verify that the next element (branch point) has been already seen in the traceback so far if (!seen_rr_nodes.count(next->index)) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Traceback branch point %d not found", next->index); diff --git a/vpr/src/base/old_traceback.h b/vpr/src/base/old_traceback.h index d0c175622f1..be67b1562b8 100644 --- a/vpr/src/base/old_traceback.h +++ b/vpr/src/base/old_traceback.h @@ -20,7 +20,7 @@ * which do not correspond to an actual netlist connection), * the value for this member should be set to OPEN (-1). * @param iswitch Index of the switch type used to go from this rr_node to - * the next one in the routing. OPEN if there is no next node + * the next one in the routing. UNDEFINED if there is no next node * (i.e. this node is the last one (a SINK) in a branch of the * net's routing). * @param next Pointer to the next traceback element in this route. diff --git a/vpr/src/base/place_and_route.cpp b/vpr/src/base/place_and_route.cpp index 138d411539d..cab083045e2 100644 --- a/vpr/src/base/place_and_route.cpp +++ b/vpr/src/base/place_and_route.cpp @@ -576,7 +576,7 @@ static float comp_width(t_chan* chan, float x, float separation) { default: VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in comp_width: Unknown channel type %d.\n", chan->type); - val = OPEN; + val = UNDEFINED; break; } diff --git a/vpr/src/base/read_netlist.cpp b/vpr/src/base/read_netlist.cpp index f149b9abba7..cbc943debed 100644 --- a/vpr/src/base/read_netlist.cpp +++ b/vpr/src/base/read_netlist.cpp @@ -11,6 +11,7 @@ #include #include +#include "physical_types.h" #include "physical_types_util.h" #include "pugixml.hpp" #include "pugixml_loc.hpp" @@ -484,7 +485,7 @@ static void processPb(pugi::xml_node Parent, const ClusterBlockId index, t_pb* p } found = false; - pb_index = OPEN; + pb_index = UNDEFINED; for (i = 0; i < pb_type->modes[pb->mode].num_pb_type_children; i++) { if (pb_type->modes[pb->mode].pb_type_children[i].name == tokens[0].data) { pb_index = vtr::atoi(tokens[2].data); @@ -579,7 +580,7 @@ static int add_net_to_hash(t_hash** nhash, const char* net_name, int* ncount) { t_hash* hash_value; if (strcmp(net_name, "open") == 0) { - return OPEN; + return UNDEFINED; } hash_value = insert_in_hash_table(nhash, net_name, *ncount); @@ -986,7 +987,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { if (clb_net_id != ClusterNetId::INVALID()) { //Verify old and new CLB netlists have the same # of pins per net - if (RECEIVER == get_pin_type_from_pin_physical_num(tile_type, physical_pin)) { + if (e_pin_type::RECEIVER == get_pin_type_from_pin_physical_num(tile_type, physical_pin)) { count[clb_net_id]++; if (count[clb_net_id] > (int)clb_nlist.net_sinks(clb_net_id).size()) { @@ -1013,7 +1014,7 @@ static void load_external_nets_and_cb(ClusteredNetlist& clb_nlist) { /* Error check performed later to ensure no mixing of ignored and non ignored signals */ } else { - VTR_ASSERT(DRIVER == get_pin_type_from_pin_physical_num(tile_type, physical_pin)); + VTR_ASSERT(e_pin_type::DRIVER == get_pin_type_from_pin_physical_num(tile_type, physical_pin)); VTR_ASSERT(j == clb_nlist.pin_logical_index(*(clb_nlist.net_pins(clb_net_id).begin()))); VTR_ASSERT(j == clb_nlist.net_pin_logical_index(clb_net_id, 0)); } @@ -1126,7 +1127,7 @@ static void load_internal_to_block_net_nums(const t_logical_block_type_ptr type, for (int i = 0; i < num_pins; i++) { if (!pb_route.count(i)) continue; - if (pb_route[i].driver_pb_pin_id != OPEN && !pb_route[i].atom_net_id) { + if (pb_route[i].driver_pb_pin_id != UNDEFINED && !pb_route[i].atom_net_id) { load_atom_index_for_pb_pin(pb_route, i); } } @@ -1135,7 +1136,7 @@ static void load_internal_to_block_net_nums(const t_logical_block_type_ptr type, static void load_atom_index_for_pb_pin(t_pb_routes& pb_route, int ipin) { int driver = pb_route[ipin].driver_pb_pin_id; - VTR_ASSERT(driver != OPEN); + VTR_ASSERT(driver != UNDEFINED); VTR_ASSERT(!pb_route[ipin].atom_net_id); if (!pb_route[driver].atom_net_id) { diff --git a/vpr/src/base/read_route.cpp b/vpr/src/base/read_route.cpp index 691169fd81d..188b9697f5e 100644 --- a/vpr/src/base/read_route.cpp +++ b/vpr/src/base/read_route.cpp @@ -483,7 +483,7 @@ static void process_nodes(const Netlist<>& net_list, "%d (sink) node does not have net pin index. If you are using an old .route file without this information, please re-generate the routing.", inode); } } else { - net_pin_index = OPEN; // net pin index is invalid for non-SINKs + net_pin_index = UNDEFINED; // net pin index is invalid for non-SINKs } /* Allocate and load correct values to trace.head */ diff --git a/vpr/src/base/stats.cpp b/vpr/src/base/stats.cpp index 6718d67678e..125e8154333 100644 --- a/vpr/src/base/stats.cpp +++ b/vpr/src/base/stats.cpp @@ -507,7 +507,7 @@ void print_lambda() { VTR_ASSERT(type != nullptr); if (!type->is_io()) { for (int ipin = 0; ipin < type->num_pins; ipin++) { - if (get_pin_type_from_pin_physical_num(type, ipin) == RECEIVER) { + if (get_pin_type_from_pin_physical_num(type, ipin) == e_pin_type::RECEIVER) { ClusterNetId net_id = cluster_ctx.clb_nlist.block_net(blk_id, ipin); if (net_id != ClusterNetId::INVALID()) /* Pin is connected? */ if (!cluster_ctx.clb_nlist.net_is_ignored(net_id)) /* Not a global clock */ diff --git a/vpr/src/base/vpr_context.h b/vpr/src/base/vpr_context.h index 5518b43bc7c..2f813bd9284 100644 --- a/vpr/src/base/vpr_context.h +++ b/vpr/src/base/vpr_context.h @@ -261,7 +261,7 @@ struct DeviceContext : public Context { std::map all_sw_inf; - int delayless_switch_idx = OPEN; + int delayless_switch_idx = UNDEFINED; bool rr_graph_is_flat = false; diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 7e2594a2d56..54d2c8f93fb 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -93,9 +93,8 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #define NOT_VALID (-10000) /* Marks gains that aren't valid */ /* Ensure no gain can ever be this negative! */ -#ifndef UNDEFINED -#define UNDEFINED (-1) -#endif + +constexpr int UNDEFINED = -1; ///@brief Router lookahead types. enum class e_router_lookahead { @@ -342,7 +341,7 @@ class t_pb { ///@brief Representation of intra-logic block routing struct t_pb_route { AtomNetId atom_net_id; /// sink_pb_pin_ids; ///= ymin_); VTR_ASSERT(layer_max_ >= layer_min_); } - int xmin = OPEN; - int xmax = OPEN; - int ymin = OPEN; - int ymax = OPEN; - int layer_min = OPEN; - int layer_max = OPEN; + int xmin = UNDEFINED; + int xmax = UNDEFINED; + int ymin = UNDEFINED; + int ymax = UNDEFINED; + int layer_min = UNDEFINED; + int layer_max = UNDEFINED; }; /** @@ -459,11 +458,11 @@ struct t_2D_bb { VTR_ASSERT(layer_num_ >= 0); } - int xmin = OPEN; - int xmax = OPEN; - int ymin = OPEN; - int ymax = OPEN; - int layer_num = OPEN; + int xmin = UNDEFINED; + int xmax = UNDEFINED; + int ymin = UNDEFINED; + int ymax = UNDEFINED; + int layer_num = UNDEFINED; }; /** @@ -573,10 +572,10 @@ struct t_pl_loc { , sub_tile(sub_tile_loc) , layer(phy_loc.layer_num) {} - int x = OPEN; - int y = OPEN; - int sub_tile = OPEN; - int layer = OPEN; + int x = UNDEFINED; + int y = UNDEFINED; + int sub_tile = UNDEFINED; + int layer = UNDEFINED; t_pl_loc& operator+=(const t_pl_offset& rhs) { layer += rhs.layer; diff --git a/vpr/src/draw/draw.cpp b/vpr/src/draw/draw.cpp index 1cf80399d2b..3a8a3dcab3c 100644 --- a/vpr/src/draw/draw.cpp +++ b/vpr/src/draw/draw.cpp @@ -530,7 +530,7 @@ int get_track_num(int inode, const vtr::OffsetMatrix& chanx_track, const vt vpr_throw(VPR_ERROR_OTHER, __FILE__, __LINE__, "in get_track_num: Unexpected node type %d for node %d.\n", rr_type, inode); - return OPEN; + return UNDEFINED; } } @@ -767,7 +767,7 @@ t_edge_size find_edge(RRNodeId prev_inode, RRNodeId inode) { } } VTR_ASSERT(false); - return OPEN; + return UNDEFINED; } ezgl::color to_ezgl_color(vtr::Color color) { diff --git a/vpr/src/draw/draw_basic.cpp b/vpr/src/draw/draw_basic.cpp index 139868d8768..7a51c42b994 100644 --- a/vpr/src/draw/draw_basic.cpp +++ b/vpr/src/draw/draw_basic.cpp @@ -467,14 +467,14 @@ void draw_routing_costs(ezgl::renderer* g) { void draw_routing_bb(ezgl::renderer* g) { t_draw_state* draw_state = get_draw_state_vars(); - if (draw_state->show_routing_bb == OPEN) { + if (draw_state->show_routing_bb == UNDEFINED) { return; } const RoutingContext& route_ctx = g_vpr_ctx.routing(); const ClusteringContext& cluster_ctx = g_vpr_ctx.clustering(); - VTR_ASSERT(draw_state->show_routing_bb != OPEN); + VTR_ASSERT(draw_state->show_routing_bb != UNDEFINED); VTR_ASSERT(draw_state->show_routing_bb < (int)route_ctx.route_bb.size()); t_draw_coords* draw_coords = get_draw_coords_vars(); @@ -705,8 +705,8 @@ void draw_placement_macros(ezgl::renderer* g) { int xhigh = std::numeric_limits::min(); int yhigh = std::numeric_limits::min(); - int x_root = OPEN; - int y_root = OPEN; + int x_root = UNDEFINED; + int y_root = UNDEFINED; for (size_t imember = 0; imember < pl_macro.members.size(); ++imember) { const t_pl_macro_member& member = pl_macro.members[imember]; diff --git a/vpr/src/draw/draw_searchbar.cpp b/vpr/src/draw/draw_searchbar.cpp index 00814b6ed34..ba140979105 100644 --- a/vpr/src/draw/draw_searchbar.cpp +++ b/vpr/src/draw/draw_searchbar.cpp @@ -1,4 +1,5 @@ /*draw_searchbar.cpp contains all functions related to searchbar actions.*/ +#include "physical_types.h" #ifndef NO_GRAPHICS #include @@ -95,7 +96,7 @@ void draw_highlight_blocks_color(t_logical_block_type_ptr type, auto class_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin); - if (class_type == DRIVER) { /* Fanout */ + if (class_type == e_pin_type::DRIVER) { /* Fanout */ if (draw_state->block_color(blk_id) == SELECTED_COLOR) { /* If block already highlighted, de-highlight the fanout. (the deselect case)*/ draw_state->net_color[net_id] = ezgl::BLACK; diff --git a/vpr/src/draw/draw_toggle_functions.cpp b/vpr/src/draw/draw_toggle_functions.cpp index 5c80b00a963..0bf26dec6b1 100644 --- a/vpr/src/draw/draw_toggle_functions.cpp +++ b/vpr/src/draw/draw_toggle_functions.cpp @@ -188,11 +188,9 @@ void toggle_routing_bbox_cbk(GtkSpinButton* self, ezgl::application* app) { // use the pointer to get the active value int new_value = gtk_spin_button_get_value_as_int(self); - // assign value to draw_state->show_routing_bb, bound check + set OPEN when it's -1 (draw nothing) - if (new_value < -1) - draw_state->show_routing_bb = -1; - else if (new_value == -1) - draw_state->show_routing_bb = OPEN; + // assign value to draw_state->show_routing_bb, bound check + set UNDEFINED when it's -1 (draw nothing) + if (new_value <= -1) + draw_state->show_routing_bb = UNDEFINED; else if (new_value >= (int)(route_ctx.route_bb.size())) draw_state->show_routing_bb = route_ctx.route_bb.size() - 1; else diff --git a/vpr/src/draw/draw_types.h b/vpr/src/draw/draw_types.h index 6ddc62de0ff..0538c374841 100644 --- a/vpr/src/draw/draw_types.h +++ b/vpr/src/draw/draw_types.h @@ -210,7 +210,7 @@ struct t_draw_state { ///@brief Toggles whether placement macros are shown e_draw_placement_macros show_placement_macros = DRAW_NO_PLACEMENT_MACROS; - int show_routing_bb = OPEN; + int show_routing_bb = UNDEFINED; ///@brief toggles whether routing util is shown e_draw_routing_util show_routing_util = DRAW_NO_ROUTING_UTIL; diff --git a/vpr/src/pack/cluster_feasibility_filter.cpp b/vpr/src/pack/cluster_feasibility_filter.cpp index 86e4d13906b..d51b340267a 100644 --- a/vpr/src/pack/cluster_feasibility_filter.cpp +++ b/vpr/src/pack/cluster_feasibility_filter.cpp @@ -31,6 +31,7 @@ #include "physical_types.h" #include "vtr_assert.h" #include "vtr_log.h" +#include "vpr_types.h" #include "hash.h" #include "cluster_feasibility_filter.h" @@ -94,7 +95,7 @@ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node) { for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { pb_graph_node->input_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth]; for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - pb_graph_node->input_pins[i][j].parent_pin_class[k] = OPEN; + pb_graph_node->input_pins[i][j].parent_pin_class[k] = UNDEFINED; } } } @@ -106,7 +107,7 @@ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node) { for (k = 0; k < pb_graph_node->pb_type->depth; k++) { pb_graph_node->output_pins[i][j].list_of_connectable_input_pin_ptrs[k] = nullptr; pb_graph_node->output_pins[i][j].num_connectable_primitive_input_pins[k] = 0; - pb_graph_node->output_pins[i][j].parent_pin_class[k] = OPEN; + pb_graph_node->output_pins[i][j].parent_pin_class[k] = UNDEFINED; } } } @@ -114,7 +115,7 @@ static void alloc_pin_classes_in_pb_graph_node(t_pb_graph_node* pb_graph_node) { for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { pb_graph_node->clock_pins[i][j].parent_pin_class = new int[pb_graph_node->pb_type->depth]; for (k = 0; k < pb_graph_node->pb_type->depth; k++) { - pb_graph_node->clock_pins[i][j].parent_pin_class[k] = OPEN; + pb_graph_node->clock_pins[i][j].parent_pin_class[k] = UNDEFINED; } } } @@ -160,17 +161,17 @@ static void reset_pin_class_scratch_pad_rec(t_pb_graph_node* pb_graph_node) { for (i = 0; i < pb_graph_node->num_input_ports; i++) { for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_node->input_pins[i][j].scratch_pad = OPEN; + pb_graph_node->input_pins[i][j].scratch_pad = UNDEFINED; } } for (i = 0; i < pb_graph_node->num_output_ports; i++) { for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].scratch_pad = OPEN; + pb_graph_node->output_pins[i][j].scratch_pad = UNDEFINED; } } for (i = 0; i < pb_graph_node->num_clock_ports; i++) { for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - pb_graph_node->clock_pins[i][j].scratch_pad = OPEN; + pb_graph_node->clock_pins[i][j].scratch_pad = UNDEFINED; } } @@ -195,7 +196,7 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node, /* At primitive, determine which pin class each of its pins belong to */ for (i = 0; i < pb_graph_node->num_input_ports; i++) { for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - if (pb_graph_node->input_pins[i][j].parent_pin_class[depth] == OPEN) { + if (pb_graph_node->input_pins[i][j].parent_pin_class[depth] == UNDEFINED) { expand_pb_graph_node_and_load_pin_class_by_depth(&pb_graph_node->input_pins[i][j], &pb_graph_node->input_pins[i][j], depth, input_count, output_count); @@ -205,7 +206,7 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node, } for (i = 0; i < pb_graph_node->num_output_ports; i++) { for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - if (pb_graph_node->output_pins[i][j].parent_pin_class[depth] == OPEN) { + if (pb_graph_node->output_pins[i][j].parent_pin_class[depth] == UNDEFINED) { expand_pb_graph_node_and_load_pin_class_by_depth(&pb_graph_node->output_pins[i][j], &pb_graph_node->output_pins[i][j], depth, input_count, output_count); @@ -215,7 +216,7 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node, } for (i = 0; i < pb_graph_node->num_clock_ports; i++) { for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - if (pb_graph_node->clock_pins[i][j].parent_pin_class[depth] == OPEN) { + if (pb_graph_node->clock_pins[i][j].parent_pin_class[depth] == UNDEFINED) { expand_pb_graph_node_and_load_pin_class_by_depth(&pb_graph_node->clock_pins[i][j], &pb_graph_node->clock_pins[i][j], depth, input_count, output_count); @@ -232,17 +233,17 @@ static void load_pin_class_by_depth(t_pb_graph_node* pb_graph_node, *output_count = 0; for (i = 0; i < pb_graph_node->num_input_ports; i++) { for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { - pb_graph_node->input_pins[i][j].pin_class = OPEN; + pb_graph_node->input_pins[i][j].pin_class = UNDEFINED; } } for (i = 0; i < pb_graph_node->num_output_ports; i++) { for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { - pb_graph_node->output_pins[i][j].pin_class = OPEN; + pb_graph_node->output_pins[i][j].pin_class = UNDEFINED; } } for (i = 0; i < pb_graph_node->num_clock_ports; i++) { for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { - pb_graph_node->clock_pins[i][j].pin_class = OPEN; + pb_graph_node->clock_pins[i][j].pin_class = UNDEFINED; } } } @@ -307,7 +308,7 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph const int depth) { int i; - if (current_pb_graph_pin->scratch_pad == OPEN + if (current_pb_graph_pin->scratch_pad == UNDEFINED && current_pb_graph_pin->parent_node->pb_type->depth > depth) { current_pb_graph_pin->scratch_pad = 1; for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { @@ -346,8 +347,8 @@ static void expand_pb_graph_node_and_load_output_to_input_connections(t_pb_graph */ static void unmark_fanout_intermediate_nodes(t_pb_graph_pin* current_pb_graph_pin) { int i; - if (current_pb_graph_pin->scratch_pad != OPEN) { - current_pb_graph_pin->scratch_pad = OPEN; + if (current_pb_graph_pin->scratch_pad != UNDEFINED) { + current_pb_graph_pin->scratch_pad = UNDEFINED; for (i = 0; i < current_pb_graph_pin->num_output_edges; i++) { VTR_ASSERT(current_pb_graph_pin->output_edges[i]->num_output_pins == 1); unmark_fanout_intermediate_nodes(current_pb_graph_pin->output_edges[i]->output_pins[0]); @@ -381,7 +382,7 @@ static void expand_pb_graph_node_and_load_pin_class_by_depth(t_pb_graph_pin* cur if (current_pb_graph_pin->is_primitive_pin()) { current_pb_graph_pin->scratch_pad = marker; /* This is a primitive, determine what pins cans share the same pin class as the reference pin */ - if (current_pb_graph_pin->parent_pin_class[depth] == OPEN + if (current_pb_graph_pin->parent_pin_class[depth] == UNDEFINED && reference_pb_graph_pin->port->is_clock == current_pb_graph_pin->port->is_clock && reference_pb_graph_pin->port->type == current_pb_graph_pin->port->type) { current_pb_graph_pin->parent_pin_class[depth] = active_pin_class; @@ -451,7 +452,7 @@ static void sum_pin_class(t_pb_graph_node* pb_graph_node) { for (i = 0; i < pb_graph_node->num_input_ports; i++) { for (j = 0; j < pb_graph_node->num_input_pins[i]; j++) { VTR_ASSERT(pb_graph_node->input_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); - if (pb_graph_node->input_pins[i][j].pin_class == OPEN) { + if (pb_graph_node->input_pins[i][j].pin_class == UNDEFINED) { VTR_LOG_WARN("%s[%d].%s[%d] unconnected pin in architecture.\n", pb_graph_node->pb_type->name, pb_graph_node->placement_index, @@ -465,7 +466,7 @@ static void sum_pin_class(t_pb_graph_node* pb_graph_node) { for (i = 0; i < pb_graph_node->num_output_ports; i++) { for (j = 0; j < pb_graph_node->num_output_pins[i]; j++) { VTR_ASSERT(pb_graph_node->output_pins[i][j].pin_class < pb_graph_node->num_output_pin_class); - if (pb_graph_node->output_pins[i][j].pin_class == OPEN) { + if (pb_graph_node->output_pins[i][j].pin_class == UNDEFINED) { VTR_LOG_WARN("%s[%d].%s[%d] unconnected pin in architecture.\n", pb_graph_node->pb_type->name, pb_graph_node->placement_index, @@ -479,7 +480,7 @@ static void sum_pin_class(t_pb_graph_node* pb_graph_node) { for (i = 0; i < pb_graph_node->num_clock_ports; i++) { for (j = 0; j < pb_graph_node->num_clock_pins[i]; j++) { VTR_ASSERT(pb_graph_node->clock_pins[i][j].pin_class < pb_graph_node->num_input_pin_class); - if (pb_graph_node->clock_pins[i][j].pin_class == OPEN) { + if (pb_graph_node->clock_pins[i][j].pin_class == UNDEFINED) { VTR_LOG_WARN("%s[%d].%s[%d] unconnected pin in architecture.\n", pb_graph_node->pb_type->name, pb_graph_node->placement_index, diff --git a/vpr/src/pack/cluster_legalizer.cpp b/vpr/src/pack/cluster_legalizer.cpp index 7256a2c84f7..065b7b7e7ef 100644 --- a/vpr/src/pack/cluster_legalizer.cpp +++ b/vpr/src/pack/cluster_legalizer.cpp @@ -673,7 +673,7 @@ static void compute_and_mark_lookahead_pins_used_for_pin(const t_pb_graph_pin* p for (auto cur_pb = primitive_pb->parent_pb; cur_pb; cur_pb = cur_pb->parent_pb) { const auto depth = cur_pb->pb_graph_node->pb_type->depth; const auto pin_class = pb_graph_pin->parent_pin_class[depth]; - VTR_ASSERT(pin_class != OPEN); + VTR_ASSERT(pin_class != UNDEFINED); const auto driver_blk_id = atom_ctx.netlist().net_driver_block(net_id); diff --git a/vpr/src/pack/cluster_placement.cpp b/vpr/src/pack/cluster_placement.cpp index fb2cb5298f5..275e2f0b60e 100644 --- a/vpr/src/pack/cluster_placement.cpp +++ b/vpr/src/pack/cluster_placement.cpp @@ -86,7 +86,7 @@ void t_intra_cluster_placement_stats::move_primitive_to_inflight(int pb_type_ind void t_intra_cluster_placement_stats::insert_primitive_in_valid_primitives(std::pair cluster_placement_primitive) { int i; bool success = false; - int null_index = OPEN; + int null_index = UNDEFINED; t_cluster_placement_primitive* input_cluster_placement_primitive = cluster_placement_primitive.second; for (i = 0; i < num_pb_types && !success; i++) { @@ -102,7 +102,7 @@ void t_intra_cluster_placement_stats::insert_primitive_in_valid_primitives(std:: } } if (!success) { - VTR_ASSERT(null_index != OPEN); + VTR_ASSERT(null_index != UNDEFINED); valid_primitives[null_index].insert(cluster_placement_primitive); } } diff --git a/vpr/src/pack/cluster_router.cpp b/vpr/src/pack/cluster_router.cpp index 1f08f5d3ea1..bfcdbf7d891 100644 --- a/vpr/src/pack/cluster_router.cpp +++ b/vpr/src/pack/cluster_router.cpp @@ -502,8 +502,8 @@ bool try_intra_lb_route(t_lb_router_data* router_data, if (router_data->explore_id_index > 2000000000) { /* overflow protection */ for (unsigned int id = 0; id < lb_type_graph.size(); id++) { - router_data->explored_node_tb[id].explored_id = OPEN; - router_data->explored_node_tb[id].enqueue_id = OPEN; + router_data->explored_node_tb[id].explored_id = UNDEFINED; + router_data->explored_node_tb[id].enqueue_id = UNDEFINED; router_data->explore_id_index = 1; } } @@ -565,7 +565,7 @@ t_pb_routes alloc_and_load_pb_route(const std::vector* intra_lb_ t_pb_routes pb_route; for (const auto& lb_net : lb_nets) { - load_trace_to_pb_route(pb_route, lb_net.atom_net_id, OPEN, lb_net.rt_tree, logic_block_type, intra_lb_pb_pin_lookup); + load_trace_to_pb_route(pb_route, lb_net.atom_net_id, UNDEFINED, lb_net.rt_tree, logic_block_type, intra_lb_pb_pin_lookup); } return pb_route; @@ -603,7 +603,7 @@ static void load_trace_to_pb_route(t_pb_routes& pb_route, const IntraLbPbPinLookup& intra_lb_pb_pin_lookup) { int ipin = trace->current_node; int driver_pb_pin_id = prev_pin_id; - int cur_pin_id = OPEN; + int cur_pin_id = UNDEFINED; const int total_pins = logic_block_type->pb_graph_head->total_pb_pins; if (ipin < total_pins) { /* This routing node corresponds with a pin. This node is virtual (ie. sink or source node) */ @@ -717,7 +717,7 @@ static void add_pin_to_rt_terminals(t_lb_router_data* router_data, const AtomPin VTR_ASSERT_MSG(lb_type_graph[lb_nets[ipos].terminals[0]].type == LB_SOURCE, "Driver must be a source"); - int sink_terminal = OPEN; + int sink_terminal = UNDEFINED; if (lb_nets[ipos].terminals.size() < atom_ctx.netlist().net_pins(net_id).size()) { //Not all of the pins are within the cluster if (lb_nets[ipos].terminals.size() == 1) { @@ -1018,7 +1018,7 @@ static void commit_remove_rt(t_lb_trace* rt, t_lb_router_data* router_data, e_co } } else { incr = -1; - explored_node_tb[inode].inet = OPEN; + explored_node_tb[inode].inet = UNDEFINED; } lb_rr_node_stats[inode].occ += incr; @@ -1089,7 +1089,7 @@ static void expand_rt(t_lb_router_data* router_data, int inet, reservable_pqexplored_node_tb, pq, irt_net, router_data->explore_id_index); + expand_rt_rec(lb_nets[inet].rt_tree, UNDEFINED, router_data->explored_node_tb, pq, irt_net, router_data->explore_id_index); } /* Expand all nodes found in route tree into priority queue recursively */ @@ -1102,7 +1102,7 @@ static void expand_rt_rec(t_lb_trace* rt, int prev_index, t_explored_node_tb* ex enode.prev_index = prev_index; pq.push(enode); explored_node_tb[enode.node_index].inet = irt_net; - explored_node_tb[enode.node_index].explored_id = OPEN; + explored_node_tb[enode.node_index].explored_id = UNDEFINED; explored_node_tb[enode.node_index].enqueue_id = explore_id_index; explored_node_tb[enode.node_index].enqueue_cost = 0; explored_node_tb[enode.node_index].prev_index = prev_index; @@ -1238,7 +1238,7 @@ static bool add_to_rt(t_lb_trace* rt, int node_index, t_lb_router_data* router_d while (explored_node_tb[rt_index].inet != irt_net) { trace_forward.push_back(rt_index); rt_index = explored_node_tb[rt_index].prev_index; - VTR_ASSERT(rt_index != OPEN); + VTR_ASSERT(rt_index != UNDEFINED); } /* Find rt_index on the route tree */ @@ -1342,10 +1342,10 @@ static void print_trace(FILE* fp, t_lb_trace* trace, t_lb_router_data* router_da static void reset_explored_node_tb(t_lb_router_data* router_data) { std::vector& lb_type_graph = *router_data->lb_type_graph; for (unsigned int inode = 0; inode < lb_type_graph.size(); inode++) { - router_data->explored_node_tb[inode].prev_index = OPEN; - router_data->explored_node_tb[inode].explored_id = OPEN; - router_data->explored_node_tb[inode].inet = OPEN; - router_data->explored_node_tb[inode].enqueue_id = OPEN; + router_data->explored_node_tb[inode].prev_index = UNDEFINED; + router_data->explored_node_tb[inode].explored_id = UNDEFINED; + router_data->explored_node_tb[inode].inet = UNDEFINED; + router_data->explored_node_tb[inode].enqueue_id = UNDEFINED; router_data->explored_node_tb[inode].enqueue_cost = 0; } } diff --git a/vpr/src/pack/lb_type_rr_graph.cpp b/vpr/src/pack/lb_type_rr_graph.cpp index bb93177ffd2..a903e40ba43 100644 --- a/vpr/src/pack/lb_type_rr_graph.cpp +++ b/vpr/src/pack/lb_type_rr_graph.cpp @@ -302,7 +302,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n /* alloc and load input pins that connect to sinks */ for (int iport = 0; iport < pb_graph_node->num_input_ports; iport++) { PortEquivalence port_equivalent = PortEquivalence::NONE; - int sink_index = OPEN; + int sink_index = UNDEFINED; for (int ipin = 0; ipin < pb_graph_node->num_input_pins[iport]; ipin++) { /* load intermediate indices */ pb_pin = &pb_graph_node->input_pins[iport][ipin]; @@ -322,7 +322,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n lb_type_rr_node_graph[pin_index].type = LB_INTERMEDIATE; lb_type_rr_node_graph[pin_index].pb_graph_pin = pb_pin; - if (port_equivalent == PortEquivalence::NONE || sink_index == OPEN) { + if (port_equivalent == PortEquivalence::NONE || sink_index == UNDEFINED) { /* Create new sink for input to primitive */ t_lb_type_rr_node new_sink; if (port_equivalent != PortEquivalence::NONE) { @@ -394,7 +394,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n /* alloc and load clock pins that connect to sinks */ for (int iport = 0; iport < pb_graph_node->num_clock_ports; iport++) { PortEquivalence port_equivalent = PortEquivalence::NONE; - int sink_index = OPEN; + int sink_index = UNDEFINED; for (int ipin = 0; ipin < pb_graph_node->num_clock_pins[iport]; ipin++) { /* load intermediate indices */ pb_pin = &pb_graph_node->clock_pins[iport][ipin]; @@ -412,7 +412,7 @@ static void alloc_and_load_lb_type_rr_graph_for_pb_graph_node(const t_pb_graph_n lb_type_rr_node_graph[pin_index].type = LB_INTERMEDIATE; lb_type_rr_node_graph[pin_index].pb_graph_pin = pb_pin; - if (port_equivalent == PortEquivalence::NONE || sink_index == OPEN) { + if (port_equivalent == PortEquivalence::NONE || sink_index == UNDEFINED) { /* Create new sink for clock to primitive */ t_lb_type_rr_node new_sink; if (port_equivalent != PortEquivalence::NONE) { diff --git a/vpr/src/pack/output_clustering.cpp b/vpr/src/pack/output_clustering.cpp index 9cdc27ac399..ee40949fe23 100644 --- a/vpr/src/pack/output_clustering.cpp +++ b/vpr/src/pack/output_clustering.cpp @@ -50,9 +50,9 @@ static void count_clb_inputs_and_outputs_from_pb_route(const t_pb* pb, AtomNetId atom_net_id = pb->pb_route[pb_graph_pin_id].atom_net_id; if (atom_net_id) { nets_absorbed[atom_net_id] = false; - if (pin_type == RECEIVER) { + if (pin_type == e_pin_type::RECEIVER) { num_clb_inputs_used[logical_block->index]++; - } else if (pin_type == DRIVER) { + } else if (pin_type == e_pin_type::DRIVER) { num_clb_outputs_used[logical_block->index]++; } } @@ -115,9 +115,9 @@ static void count_stats_from_netlist(std::unordered_map& nets_a VTR_ASSERT(net_id); nets_absorbed[net_id] = false; - if (pin_type == RECEIVER) { + if (pin_type == e_pin_type::RECEIVER) { num_clb_inputs_used[logical_block->index]++; - } else if (pin_type == DRIVER) { + } else if (pin_type == e_pin_type::DRIVER) { num_clb_outputs_used[logical_block->index]++; } } @@ -226,7 +226,7 @@ static std::string clustering_xml_interconnect_text(t_logical_block_type_ptr typ int prev_node = pb_route[inode].driver_pb_pin_id; int prev_edge; - if (prev_node == OPEN) { + if (prev_node == UNDEFINED) { /* No previous driver implies that this is either a top-level input pin or a primitive output pin */ const t_pb_graph_pin* cur_pin = pb_graph_pin_lookup_from_index_by_type.pb_gpin(type->index, inode); VTR_ASSERT(cur_pin->parent_node->pb_type->is_root() || (cur_pin->is_primitive_pin() && cur_pin->port->type == OUT_PORT)); diff --git a/vpr/src/pack/pack_types.h b/vpr/src/pack/pack_types.h index 1d3c336072c..d40115a485d 100644 --- a/vpr/src/pack/pack_types.h +++ b/vpr/src/pack/pack_types.h @@ -11,6 +11,7 @@ #include "atom_netlist_fwd.h" #include "physical_types.h" +#include "vpr_types.h" class t_pack_molecule; @@ -149,8 +150,8 @@ struct t_expansion_node { float cost; t_expansion_node() { - node_index = OPEN; - prev_index = OPEN; + node_index = UNDEFINED; + prev_index = UNDEFINED; cost = 0; } }; @@ -175,10 +176,10 @@ struct t_explored_node_tb { float enqueue_cost; /* cost of node pused on exploration priority queue */ t_explored_node_tb() { - prev_index = OPEN; - explored_id = OPEN; - enqueue_id = OPEN; - inet = OPEN; + prev_index = UNDEFINED; + explored_id = UNDEFINED; + enqueue_id = UNDEFINED; + inet = UNDEFINED; enqueue_cost = 0; } }; diff --git a/vpr/src/pack/pb_type_graph.cpp b/vpr/src/pack/pb_type_graph.cpp index 10d750e381f..f515e2b41c6 100644 --- a/vpr/src/pack/pb_type_graph.cpp +++ b/vpr/src/pack/pb_type_graph.cpp @@ -618,10 +618,10 @@ static int add_port_logical_classes(t_logical_block_type* logical_block, class_inf.equivalence = port->equivalent; if (port->type == IN_PORT) { - class_inf.type = RECEIVER; + class_inf.type = e_pin_type::RECEIVER; } else { VTR_ASSERT(port->type == OUT_PORT); - class_inf.type = DRIVER; + class_inf.type = e_pin_type::DRIVER; } for (int pin_idx = 0; pin_idx < num_pins[port_idx]; pin_idx++) { @@ -639,10 +639,10 @@ static int add_port_logical_classes(t_logical_block_type* logical_block, class_inf.equivalence = port->equivalent; if (port->type == IN_PORT) { - class_inf.type = RECEIVER; + class_inf.type = e_pin_type::RECEIVER; } else { VTR_ASSERT(port->type == OUT_PORT); - class_inf.type = DRIVER; + class_inf.type = e_pin_type::DRIVER; } auto pb_graph_pin = &(pb_graph_pins[port_idx][pin_idx]); @@ -1323,8 +1323,8 @@ static bool realloc_and_load_pb_graph_pin_ptrs_at_var(const int line_num, mode = pb_graph_children_nodes[0][0].pb_type->parent_mode; } - pb_msb = pb_lsb = OPEN; - pin_msb = pin_lsb = OPEN; + pb_msb = pb_lsb = UNDEFINED; + pin_msb = pin_lsb = UNDEFINED; // parse pb bool found = false; diff --git a/vpr/src/pack/pb_type_graph_annotations.cpp b/vpr/src/pack/pb_type_graph_annotations.cpp index 030ae8bba4f..f60a6bf9124 100644 --- a/vpr/src/pack/pb_type_graph_annotations.cpp +++ b/vpr/src/pack/pb_type_graph_annotations.cpp @@ -14,6 +14,7 @@ #include "vtr_token.h" #include "vpr_error.h" +#include "vpr_types.h" #include "pb_type_graph.h" #include "pb_type_graph_annotations.h" @@ -50,7 +51,7 @@ void load_pb_graph_pin_to_pin_annotations(t_pb_graph_node* pb_graph_node) { || key == E_ANNOT_PIN_TO_PIN_DELAY_CLOCK_TO_Q_MIN || key == E_ANNOT_PIN_TO_PIN_DELAY_TSETUP || key == E_ANNOT_PIN_TO_PIN_DELAY_THOLD) { - load_delay_annotations(annotation.line_num, pb_graph_node, OPEN, + load_delay_annotations(annotation.line_num, pb_graph_node, UNDEFINED, annotation.format, (enum e_pin_to_pin_delay_annotations)key, annotation.input_pins, annotation.output_pins, @@ -207,7 +208,7 @@ static void load_delay_annotations(const int line_num, /* Determine what pins to read based on delay type */ num_inputs = num_outputs = 0; - if (mode == OPEN) { + if (mode == UNDEFINED) { children = nullptr; } else { children = pb_graph_node->child_pb_graph_nodes[mode]; diff --git a/vpr/src/pack/post_routing_pb_pin_fixup.cpp b/vpr/src/pack/post_routing_pb_pin_fixup.cpp index eb71dabc48e..79de264a198 100644 --- a/vpr/src/pack/post_routing_pb_pin_fixup.cpp +++ b/vpr/src/pack/post_routing_pb_pin_fixup.cpp @@ -3,6 +3,7 @@ * after routing optimization *******************************************************************/ /* Headers from vtrutil library */ +#include "physical_types.h" #include "physical_types_util.h" #include "vtr_time.h" #include "vtr_assert.h" @@ -125,10 +126,10 @@ static void update_cluster_pin_with_post_routing_results(const Netlist<>& net_li auto pin_type = get_pin_type_from_pin_physical_num(physical_tile, physical_pin); e_rr_type rr_node_type; - if (pin_type == DRIVER) { + if (pin_type == e_pin_type::DRIVER) { rr_node_type = e_rr_type::OPIN; } else { - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); rr_node_type = e_rr_type::IPIN; } @@ -682,7 +683,7 @@ static void update_cluster_regular_routing_traces_with_post_routing_results(Atom /* Modify the source pb_graph_pin if we reuse routing trace from another pin */ if (new_pb_route.pb_graph_pin != pb_graph_pin) { new_pb_route.pb_graph_pin = pb_graph_pin; - new_pb_route.driver_pb_pin_id = OPEN; + new_pb_route.driver_pb_pin_id = UNDEFINED; } /* Check if the sink pb_pins are accessible from the driver pb_pin diff --git a/vpr/src/pack/prepack.cpp b/vpr/src/pack/prepack.cpp index 502b595ed82..d0502dba7be 100644 --- a/vpr/src/pack/prepack.cpp +++ b/vpr/src/pack/prepack.cpp @@ -908,12 +908,12 @@ void Prepacker::alloc_and_load_pack_molecules(std::multimapblock_id == OPEN) { + if (pattern_block == nullptr || pattern_block->block_id == UNDEFINED) { /* already traversed, return */ return; } pattern_block_list[pattern_block->block_id] = pattern_block; - pattern_block->block_id = OPEN; + pattern_block->block_id = UNDEFINED; connection = pattern_block->connections; while (connection) { free_pack_pattern_block(connection->from_block, pattern_block_list); diff --git a/vpr/src/place/compressed_grid.h b/vpr/src/place/compressed_grid.h index f078d31300b..459349fe0c9 100644 --- a/vpr/src/place/compressed_grid.h +++ b/vpr/src/place/compressed_grid.h @@ -5,6 +5,7 @@ #include "vtr_assert.h" #include "vtr_flat_map.h" +#include "vpr_types.h" struct t_compressed_block_grid { // The compressed grid of a block type stores only the coordinates that are occupied by that particular block type. @@ -40,8 +41,8 @@ struct t_compressed_block_grid { } inline t_physical_tile_loc grid_loc_to_compressed_loc(t_physical_tile_loc grid_loc) const { - int cx = OPEN; - int cy = OPEN; + int cx = UNDEFINED; + int cy = UNDEFINED; int layer_num = grid_loc.layer_num; auto itr_x = std::lower_bound(compressed_to_grid_x[layer_num].begin(), compressed_to_grid_x[layer_num].end(), grid_loc.x); @@ -130,7 +131,7 @@ struct t_compressed_block_grid { // no compatible locations for a block of the given type. Returns OPEN // in that case. if (compressed_grid_dim.size() == 0) { - return OPEN; + return UNDEFINED; } // Find the first element not less than loc diff --git a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp index f49fdbf5b1f..99cea912f76 100644 --- a/vpr/src/place/delay_model/compute_delta_delays_utils.cpp +++ b/vpr/src/place/delay_model/compute_delta_delays_utils.cpp @@ -529,9 +529,9 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou vtr::Matrix found_matrix({matrix.dim_size(0), matrix.dim_size(1)}, false); - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); + auto best_driver_ptcs = get_best_classes(e_pin_type::DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, from_layer_num})); for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); + VTR_ASSERT(driver_ptc != UNDEFINED); RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(from_layer_num, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); @@ -563,9 +563,9 @@ static void generic_compute_matrix_dijkstra_expansion(RouterDelayProfiler& /*rou } } else { bool found_a_sink = false; - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); + auto best_sink_ptcs = get_best_classes(e_pin_type::RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, to_layer_num})); for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); + VTR_ASSERT(sink_ptc != UNDEFINED); RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(to_layer_num, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) @@ -648,17 +648,17 @@ static float route_connection_delay(RouterDelayProfiler& route_profiler, bool successfully_routed = false; // Get the rr nodes to route between - auto best_driver_ptcs = get_best_classes(DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, source_layer})); - auto best_sink_ptcs = get_best_classes(RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, sink_layer})); + auto best_driver_ptcs = get_best_classes(e_pin_type::DRIVER, device_ctx.grid.get_physical_type({source_x, source_y, source_layer})); + auto best_sink_ptcs = get_best_classes(e_pin_type::RECEIVER, device_ctx.grid.get_physical_type({sink_x, sink_y, sink_layer})); for (int driver_ptc : best_driver_ptcs) { - VTR_ASSERT(driver_ptc != OPEN); + VTR_ASSERT(driver_ptc != UNDEFINED); RRNodeId source_rr_node = device_ctx.rr_graph.node_lookup().find_node(source_layer, source_x, source_y, e_rr_type::SOURCE, driver_ptc); VTR_ASSERT(source_rr_node != RRNodeId::INVALID()); for (int sink_ptc : best_sink_ptcs) { - VTR_ASSERT(sink_ptc != OPEN); + VTR_ASSERT(sink_ptc != UNDEFINED); RRNodeId sink_rr_node = device_ctx.rr_graph.node_lookup().find_node(sink_layer, sink_x, sink_y, e_rr_type::SINK, sink_ptc); if (sink_rr_node == RRNodeId::INVALID()) diff --git a/vpr/src/place/delay_model/override_delay_model.cpp b/vpr/src/place/delay_model/override_delay_model.cpp index a3d99c73c9d..f4e8bec7962 100644 --- a/vpr/src/place/delay_model/override_delay_model.cpp +++ b/vpr/src/place/delay_model/override_delay_model.cpp @@ -2,6 +2,7 @@ #include "override_delay_model.h" #include "compute_delta_delays_utils.h" +#include "physical_types.h" #include "physical_types_util.h" #ifdef VTR_ENABLE_CAPNPROTO @@ -65,14 +66,14 @@ void OverrideDelayModel::compute_override_delay_model_(RouterDelayProfiler& rout int from_pin = from_type->find_pin(from_port.port_name(), from_port.port_low_index() + iconn); int to_pin = to_type->find_pin(to_port.port_name(), to_port.port_low_index() + iconn); - VTR_ASSERT(from_pin != OPEN); - VTR_ASSERT(to_pin != OPEN); + VTR_ASSERT(from_pin != UNDEFINED); + VTR_ASSERT(to_pin != UNDEFINED); - int from_pin_class = from_type->find_pin_class(from_port.port_name(), from_port.port_low_index() + iconn, DRIVER); - VTR_ASSERT(from_pin_class != OPEN); + int from_pin_class = from_type->find_pin_class(from_port.port_name(), from_port.port_low_index() + iconn, e_pin_type::DRIVER); + VTR_ASSERT(from_pin_class != UNDEFINED); - int to_pin_class = to_type->find_pin_class(to_port.port_name(), to_port.port_low_index() + iconn, RECEIVER); - VTR_ASSERT(to_pin_class != OPEN); + int to_pin_class = to_type->find_pin_class(to_port.port_name(), to_port.port_low_index() + iconn, e_pin_type::RECEIVER); + VTR_ASSERT(to_pin_class != UNDEFINED); bool found_sample_points; RRNodeId src_rr, sink_rr; diff --git a/vpr/src/place/initial_placement.cpp b/vpr/src/place/initial_placement.cpp index 7f3d5ce9fbf..0bacfcac783 100644 --- a/vpr/src/place/initial_placement.cpp +++ b/vpr/src/place/initial_placement.cpp @@ -415,7 +415,7 @@ static bool find_centroid_neighbor(ClusterBlockId block_id, const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[block_type->index]; const int num_layers = g_vpr_ctx.device().grid.get_num_layers(); const int centroid_loc_layer_num = centroid_loc.layer; - VTR_ASSERT(centroid_loc_layer_num != OPEN); + VTR_ASSERT(centroid_loc_layer_num != UNDEFINED); //Determine centroid location in the compressed space of the current block auto compressed_centroid_loc = get_compressed_loc_approx(compressed_block_grid, @@ -425,8 +425,8 @@ static bool find_centroid_neighbor(ClusterBlockId block_id, // If no compressed location can be found on this layer, return false. // TODO: Maybe search in the layers above or below. const t_physical_tile_loc& compressed_loc_on_layer = compressed_centroid_loc[centroid_loc.layer]; - if (compressed_loc_on_layer.x == OPEN || compressed_loc_on_layer.y == OPEN) { - VTR_ASSERT_MSG(compressed_loc_on_layer.x == OPEN && compressed_loc_on_layer.y == OPEN, + if (compressed_loc_on_layer.x == UNDEFINED || compressed_loc_on_layer.y == UNDEFINED) { + VTR_ASSERT_MSG(compressed_loc_on_layer.x == UNDEFINED && compressed_loc_on_layer.y == UNDEFINED, "When searching for a compressed location, and a location cannot be found " "both x and y should be OPEN."); return false; @@ -455,8 +455,8 @@ static bool find_centroid_neighbor(ClusterBlockId block_id, } //Block has not been placed yet, so the "from" coords will be (-1, -1) - int cx_from = OPEN; - int cy_from = OPEN; + int cx_from = UNDEFINED; + int cy_from = UNDEFINED; int layer_from = centroid_loc_layer_num; t_physical_tile_loc to_compressed_loc; @@ -498,7 +498,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, // For now, we put the macro in the same layer as the head block int head_layer_num = block_locs[head_blk].loc.layer; // If block is placed, we use the layer of the block. Otherwise, the layer will be determined later - if (head_layer_num == OPEN) { + if (head_layer_num == UNDEFINED) { find_layer = true; } std::vector connected_blocks_to_update; @@ -537,7 +537,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(sink_pin_id); if (find_layer) { - VTR_ASSERT(tile_loc.layer_num != OPEN); + VTR_ASSERT(tile_loc.layer_num != UNDEFINED); layer_count[tile_loc.layer_num]++; } acc_x += tile_loc.x; @@ -557,7 +557,7 @@ static std::vector find_centroid_loc(const t_pl_macro& pl_macro, t_physical_tile_loc tile_loc = blk_loc_registry.get_coordinate_of_pin(source_pin); if (find_layer) { - VTR_ASSERT(tile_loc.layer_num != OPEN); + VTR_ASSERT(tile_loc.layer_num != UNDEFINED); layer_count[tile_loc.layer_num]++; } acc_x += tile_loc.x; @@ -702,8 +702,8 @@ static inline int get_first_available_sub_tile_at_grid_loc(const t_physical_tile } } - // If one cannot be found, return OPEN. - return OPEN; + // If one cannot be found, return UNDEFINED. + return UNDEFINED; } /** @@ -747,7 +747,7 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat per_layer_visited[layer].resize({num_cols, num_rows}, false); } float best_dist = std::numeric_limits::max(); - t_pl_loc best_loc(OPEN, OPEN, OPEN, OPEN); + t_pl_loc best_loc(UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED); // Get the closest (approximately) compressed location to the src location // on each layer and enqueue them. We only want to enqueue locations onto @@ -758,7 +758,7 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat for (int layer_num : compressed_block_grid.get_layer_nums()) { t_physical_tile_loc src_grid_loc(src_flat_loc.x, src_flat_loc.y, layer_num); const t_physical_tile_loc compressed_src_loc = compressed_block_grid.grid_loc_to_compressed_loc_approx(src_grid_loc); - if (compressed_src_loc.x != OPEN && compressed_src_loc.y != OPEN) + if (compressed_src_loc.x != UNDEFINED && compressed_src_loc.y != UNDEFINED) loc_queue.push(compressed_src_loc); } @@ -811,7 +811,7 @@ static inline t_pl_loc find_nearest_compatible_loc(const t_flat_pl_loc& src_flat blk_loc_registry, device_grid, compressed_block_grid); - if (new_sub_tile != OPEN) { + if (new_sub_tile != UNDEFINED) { // If a sub-tile is available, set this to be the first sub-tile // available and check if this site is legal for this macro. // Note: We are using the fully legality check here to check for @@ -883,7 +883,7 @@ static bool try_centroid_placement(ClusterBlockId block_id, vtr::RngContainer& rng) { auto& block_locs = blk_loc_registry.mutable_block_locs(); - t_pl_loc centroid_loc(OPEN, OPEN, OPEN, OPEN); + t_pl_loc centroid_loc(UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED); std::vector unplaced_blocks_to_update_their_score; bool found_legal_subtile = false; @@ -909,7 +909,7 @@ static bool try_centroid_placement(ClusterBlockId block_id, // Also the location it returns will be on the chip and in the PR // by construction. Could save time by skipping those checks if // needed. - if (centroid_loc.x == OPEN) { + if (centroid_loc.x == UNDEFINED) { // If we cannot find a nearest block, fall back on the original // find_centroid_loc function. // FIXME: We should really just skip this block and come back @@ -1025,8 +1025,8 @@ static std::vector init_blk_types_empty_locations( std::vector block_type_empty_locs; for (int layer_num = 0; layer_num < num_layers; layer_num++) { - int min_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({0, OPEN, layer_num}).x; - int max_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({(int)grid.width() - 1, OPEN, layer_num}).x; + int min_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({0, UNDEFINED, layer_num}).x; + int max_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({(int)grid.width() - 1, UNDEFINED, layer_num}).x; //traverse all column and store their empty locations in block_type_empty_locs for (int x_loc = min_cx; x_loc <= max_cx; x_loc++) { @@ -1168,12 +1168,12 @@ bool try_place_macro_exhaustively(const t_pl_macro& pl_macro, const auto [layer_low, layer_high] = regions[reg].get_layer_range(); for (int layer_num = layer_low; layer_num <= layer_high; layer_num++) { - int min_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({reg_rect.xmin(), OPEN, layer_num}).x; - int max_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({reg_rect.xmax(), OPEN, layer_num}).x; + int min_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({reg_rect.xmin(), UNDEFINED, layer_num}).x; + int max_cx = compressed_block_grid.grid_loc_to_compressed_loc_approx({reg_rect.xmax(), UNDEFINED, layer_num}).x; // There isn't any block of this type in this region - if (min_cx == OPEN) { - VTR_ASSERT(max_cx == OPEN); + if (min_cx == UNDEFINED) { + VTR_ASSERT(max_cx == UNDEFINED); continue; } @@ -1832,7 +1832,7 @@ static inline bool place_blocks_min_displacement(std::vector& cl // If a location could not be found, add to list of unplaced blocks // and skip. - if (centroid_loc.x == OPEN) { + if (centroid_loc.x == UNDEFINED) { unplaced_blocks.push_back(blk_to_place); continue; } diff --git a/vpr/src/place/move_generators/centroid_move_generator.cpp b/vpr/src/place/move_generators/centroid_move_generator.cpp index 68850ac6b98..b1acf934aee 100644 --- a/vpr/src/place/move_generators/centroid_move_generator.cpp +++ b/vpr/src/place/move_generators/centroid_move_generator.cpp @@ -218,7 +218,7 @@ t_pl_loc CentroidMoveGenerator::calculate_centroid_loc_(ClusterBlockId b_from, float weight = 1; int from_block_layer_num = block_locs[b_from].loc.layer; - VTR_ASSERT(from_block_layer_num != OPEN); + VTR_ASSERT(from_block_layer_num != UNDEFINED); //iterate over the from block pins for (ClusterPinId pin_id : cluster_ctx.clb_nlist.block_pins(b_from)) { diff --git a/vpr/src/place/move_generators/median_move_generator.cpp b/vpr/src/place/move_generators/median_move_generator.cpp index f3652d97789..56a75287462 100644 --- a/vpr/src/place/move_generators/median_move_generator.cpp +++ b/vpr/src/place/move_generators/median_move_generator.cpp @@ -56,7 +56,7 @@ e_create_move MedianMoveGenerator::propose_move(t_pl_blocks_to_be_moved& blocks_ /* Calculate the median region */ t_pl_loc to; - t_bb coords(OPEN, OPEN, OPEN, OPEN, OPEN, OPEN); + t_bb coords(UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED); t_bb limit_coords; //clear the vectors that saves X & Y coords @@ -193,12 +193,12 @@ void MedianMoveGenerator::get_bb_from_scratch_excluding_block(ClusterNetId net_i * as the moving block. If not, we set this flag to false. */ skip_net = true; - int xmin = OPEN; - int xmax = OPEN; - int ymin = OPEN; - int ymax = OPEN; - int layer_min = OPEN; - int layer_max = OPEN; + int xmin = UNDEFINED; + int xmax = UNDEFINED; + int ymin = UNDEFINED; + int ymax = UNDEFINED; + int layer_min = UNDEFINED; + int layer_max = UNDEFINED; ClusterBlockId driver_block_id = cluster_ctx.clb_nlist.net_driver_block(net_id); bool first_block = false; diff --git a/vpr/src/place/move_utils.cpp b/vpr/src/place/move_utils.cpp index c36c1ffba3e..6eba67368f3 100644 --- a/vpr/src/place/move_utils.cpp +++ b/vpr/src/place/move_utils.cpp @@ -671,7 +671,7 @@ bool find_to_loc_uniform(t_logical_block_type_ptr type, const t_compressed_block_grid& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[type->index]; const int num_layers = g_vpr_ctx.device().grid.get_num_layers(); const int to_layer_num = get_random_layer(type, rng); - VTR_ASSERT(to_layer_num != OPEN); + VTR_ASSERT(to_layer_num != UNDEFINED); //Determine the coordinates in the compressed grid space of the current block std::vector compressed_locs = get_compressed_loc(compressed_block_grid, @@ -744,7 +744,7 @@ bool find_to_loc_median(t_logical_block_type_ptr blk_type, vtr::RngContainer& rng) { int num_layers = g_vpr_ctx.device().grid.get_num_layers(); const int to_layer_num = to_loc.layer; - VTR_ASSERT(to_layer_num != OPEN); + VTR_ASSERT(to_layer_num != UNDEFINED); const auto& compressed_block_grid = g_vpr_ctx.placement().compressed_block_grids[blk_type->index]; //Determine the coordinates in the compressed grid space of the current block @@ -855,8 +855,8 @@ bool find_to_loc_centroid(t_logical_block_type_ptr blk_type, // If no compressed location can be found on this layer, return false. // TODO: Maybe search in the layers above or below. const t_physical_tile_loc& compressed_loc_on_layer = centroid_compressed_loc[to_layer_num]; - if (compressed_loc_on_layer.x == OPEN || compressed_loc_on_layer.y == OPEN) { - VTR_ASSERT_MSG(compressed_loc_on_layer.x == OPEN && compressed_loc_on_layer.y == OPEN, + if (compressed_loc_on_layer.x == UNDEFINED || compressed_loc_on_layer.y == UNDEFINED) { + VTR_ASSERT_MSG(compressed_loc_on_layer.x == UNDEFINED && compressed_loc_on_layer.y == UNDEFINED, "When searching for a compressed location, and a location cannot be found " "both x and y should be OPEN."); return false; @@ -1120,7 +1120,7 @@ t_bb get_compressed_grid_target_search_range(const t_compressed_block_grid& comp float rlim) { t_bb search_ranges; int layer_num = compressed_loc.layer_num; - VTR_ASSERT(compressed_loc.x != OPEN && compressed_loc.y != OPEN && compressed_loc.layer_num != OPEN); + VTR_ASSERT(compressed_loc.x != UNDEFINED && compressed_loc.y != UNDEFINED && compressed_loc.layer_num != UNDEFINED); int rlim_x_max_range = std::min((int)compressed_block_grid.get_num_columns(layer_num), rlim); int rlim_y_max_range = std::min((int)compressed_block_grid.get_num_rows(layer_num), rlim); /* for aspect_ratio != 1 case. */ @@ -1146,8 +1146,8 @@ t_bb get_compressed_grid_bounded_search_range(const t_compressed_block_grid& com int min_cx, max_cx, min_cy, max_cy; //TODO: This if condition is added because blocks are only moved in the same layer. After the update, this condition should be replaced with an assertion - VTR_ASSERT(from_compressed_loc.x != OPEN && from_compressed_loc.y != OPEN && from_compressed_loc.layer_num != OPEN); - VTR_ASSERT(target_compressed_loc.x != OPEN && target_compressed_loc.y != OPEN && target_compressed_loc.layer_num != OPEN); + VTR_ASSERT(from_compressed_loc.x != UNDEFINED && from_compressed_loc.y != UNDEFINED && from_compressed_loc.layer_num != UNDEFINED); + VTR_ASSERT(target_compressed_loc.x != UNDEFINED && target_compressed_loc.y != UNDEFINED && target_compressed_loc.layer_num != UNDEFINED); int layer_num = target_compressed_loc.layer_num; int rlim_x_max_range = std::min(compressed_block_grid.get_num_columns(layer_num), rlim); @@ -1273,7 +1273,7 @@ int find_free_layer(t_logical_block_type_ptr logical_block, // TODO: Compatible layer vector should be shuffled first, and then iterated through int free_layer = loc.layer; - VTR_ASSERT(loc.layer != OPEN); + VTR_ASSERT(loc.layer != UNDEFINED); if (device_ctx.grid.get_num_layers() > 1) { const auto& compatible_layers = compressed_grids[logical_block->index].get_layer_nums(); if (compatible_layers.size() > 1) { @@ -1296,7 +1296,7 @@ int find_free_layer(t_logical_block_type_ptr logical_block, int get_random_layer(t_logical_block_type_ptr logical_block, vtr::RngContainer& rng) { const auto& compatible_layers = g_vpr_ctx.placement().compressed_block_grids[logical_block->index].get_layer_nums(); VTR_ASSERT(!compatible_layers.empty()); - int layer_num = OPEN; + int layer_num = UNDEFINED; if (compatible_layers.size() == 1) { layer_num = compatible_layers[0]; } else { diff --git a/vpr/src/place/net_cost_handler.cpp b/vpr/src/place/net_cost_handler.cpp index 6282a3e8720..17d7ca04e23 100644 --- a/vpr/src/place/net_cost_handler.cpp +++ b/vpr/src/place/net_cost_handler.cpp @@ -120,8 +120,8 @@ NetCostHandler::NetCostHandler(const t_placer_opts& placer_opts, } /* This initializes the whole matrix to OPEN which is an invalid value*/ - ts_layer_sink_pin_count_.resize({num_nets, size_t(num_layers)}, OPEN); - num_sink_pin_layer_.resize({num_nets, size_t(num_layers)}, OPEN); + ts_layer_sink_pin_count_.resize({num_nets, size_t(num_layers)}, UNDEFINED); + num_sink_pin_layer_.resize({num_nets, size_t(num_layers)}, UNDEFINED); ts_nets_to_update_.resize(num_nets, ClusterNetId::INVALID()); @@ -1366,7 +1366,7 @@ double NetCostHandler::get_net_per_layer_bb_cost_(ClusterNetId net_id, bool use_ int num_layers = g_vpr_ctx.device().grid.get_num_layers(); for (int layer_num = 0; layer_num < num_layers; layer_num++) { - VTR_ASSERT(layer_pin_sink_count[layer_num] != OPEN); + VTR_ASSERT(layer_pin_sink_count[layer_num] != UNDEFINED); if (layer_pin_sink_count[layer_num] == 0) { continue; } @@ -1425,7 +1425,7 @@ double NetCostHandler::get_net_wirelength_from_layer_bb_(ClusterNetId net_id) co VTR_ASSERT_SAFE((int)bb.size() == g_vpr_ctx.device().grid.get_num_layers()); for (size_t layer_num = 0; layer_num < bb.size(); layer_num++) { - VTR_ASSERT_SAFE(net_layer_pin_sink_count[layer_num] != OPEN); + VTR_ASSERT_SAFE(net_layer_pin_sink_count[layer_num] != UNDEFINED); if (net_layer_pin_sink_count[layer_num] == 0) { continue; } @@ -1640,32 +1640,32 @@ t_bb NetCostHandler::union_2d_bb(ClusterNetId net_id) const { t_bb merged_bb; const std::vector& bb_vec = layer_bb_coords_[net_id]; - // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to OPEN), + // Not all 2d_bbs are valid. Thus, if one of the coordinates in the 2D_bb is not valid (equal to UNDEFINED), // we need to skip it. for (const t_2D_bb& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_DEBUG(layer_bb.xmax == OPEN); - VTR_ASSERT_DEBUG(layer_bb.ymin == OPEN); - VTR_ASSERT_DEBUG(layer_bb.ymax == OPEN); - VTR_ASSERT_DEBUG(layer_bb.layer_num == OPEN); + if (layer_bb.xmin == UNDEFINED) { + VTR_ASSERT_DEBUG(layer_bb.xmax == UNDEFINED); + VTR_ASSERT_DEBUG(layer_bb.ymin == UNDEFINED); + VTR_ASSERT_DEBUG(layer_bb.ymax == UNDEFINED); + VTR_ASSERT_DEBUG(layer_bb.layer_num == UNDEFINED); continue; } - if (merged_bb.xmin == OPEN || layer_bb.xmin < merged_bb.xmin) { + if (merged_bb.xmin == UNDEFINED || layer_bb.xmin < merged_bb.xmin) { merged_bb.xmin = layer_bb.xmin; } - if (merged_bb.xmax == OPEN || layer_bb.xmax > merged_bb.xmax) { + if (merged_bb.xmax == UNDEFINED || layer_bb.xmax > merged_bb.xmax) { merged_bb.xmax = layer_bb.xmax; } - if (merged_bb.ymin == OPEN || layer_bb.ymin < merged_bb.ymin) { + if (merged_bb.ymin == UNDEFINED || layer_bb.ymin < merged_bb.ymin) { merged_bb.ymin = layer_bb.ymin; } - if (merged_bb.ymax == OPEN || layer_bb.ymax > merged_bb.ymax) { + if (merged_bb.ymax == UNDEFINED || layer_bb.ymax > merged_bb.ymax) { merged_bb.ymax = layer_bb.ymax; } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num < merged_bb.layer_min) { + if (merged_bb.layer_min == UNDEFINED || layer_bb.layer_num < merged_bb.layer_min) { merged_bb.layer_min = layer_bb.layer_num; } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num > merged_bb.layer_max) { + if (merged_bb.layer_max == UNDEFINED || layer_bb.layer_num > merged_bb.layer_max) { merged_bb.layer_max = layer_bb.layer_num; } } @@ -1681,61 +1681,61 @@ std::pair NetCostHandler::union_2d_bb_incr(ClusterNetId net_id) cons const std::vector& bb_vec = layer_bb_coords_[net_id]; for (const t_2D_bb& layer_bb : bb_vec) { - if (layer_bb.xmin == OPEN) { - VTR_ASSERT_SAFE(layer_bb.xmax == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymin == OPEN); - VTR_ASSERT_SAFE(layer_bb.ymax == OPEN); - VTR_ASSERT_SAFE(layer_bb.layer_num == OPEN); + if (layer_bb.xmin == UNDEFINED) { + VTR_ASSERT_SAFE(layer_bb.xmax == UNDEFINED); + VTR_ASSERT_SAFE(layer_bb.ymin == UNDEFINED); + VTR_ASSERT_SAFE(layer_bb.ymax == UNDEFINED); + VTR_ASSERT_SAFE(layer_bb.layer_num == UNDEFINED); continue; } - if (merged_bb.xmin == OPEN || layer_bb.xmin <= merged_bb.xmin) { + if (merged_bb.xmin == UNDEFINED || layer_bb.xmin <= merged_bb.xmin) { if (layer_bb.xmin == merged_bb.xmin) { - VTR_ASSERT_SAFE(merged_num_edge.xmin != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.xmin != UNDEFINED); merged_num_edge.xmin += num_edge_vec[layer_bb.layer_num].xmin; } else { merged_num_edge.xmin = num_edge_vec[layer_bb.layer_num].xmin; } merged_bb.xmin = layer_bb.xmin; } - if (merged_bb.xmax == OPEN || layer_bb.xmax >= merged_bb.xmax) { + if (merged_bb.xmax == UNDEFINED || layer_bb.xmax >= merged_bb.xmax) { if (layer_bb.xmax == merged_bb.xmax) { - VTR_ASSERT_SAFE(merged_num_edge.xmax != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.xmax != UNDEFINED); merged_num_edge.xmax += num_edge_vec[layer_bb.layer_num].xmax; } else { merged_num_edge.xmax = num_edge_vec[layer_bb.layer_num].xmax; } merged_bb.xmax = layer_bb.xmax; } - if (merged_bb.ymin == OPEN || layer_bb.ymin <= merged_bb.ymin) { + if (merged_bb.ymin == UNDEFINED || layer_bb.ymin <= merged_bb.ymin) { if (layer_bb.ymin == merged_bb.ymin) { - VTR_ASSERT_SAFE(merged_num_edge.ymin != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.ymin != UNDEFINED); merged_num_edge.ymin += num_edge_vec[layer_bb.layer_num].ymin; } else { merged_num_edge.ymin = num_edge_vec[layer_bb.layer_num].ymin; } merged_bb.ymin = layer_bb.ymin; } - if (merged_bb.ymax == OPEN || layer_bb.ymax >= merged_bb.ymax) { + if (merged_bb.ymax == UNDEFINED || layer_bb.ymax >= merged_bb.ymax) { if (layer_bb.ymax == merged_bb.ymax) { - VTR_ASSERT_SAFE(merged_num_edge.ymax != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.ymax != UNDEFINED); merged_num_edge.ymax += num_edge_vec[layer_bb.layer_num].ymax; } else { merged_num_edge.ymax = num_edge_vec[layer_bb.layer_num].ymax; } merged_bb.ymax = layer_bb.ymax; } - if (merged_bb.layer_min == OPEN || layer_bb.layer_num <= merged_bb.layer_min) { + if (merged_bb.layer_min == UNDEFINED || layer_bb.layer_num <= merged_bb.layer_min) { if (layer_bb.layer_num == merged_bb.layer_min) { - VTR_ASSERT_SAFE(merged_num_edge.layer_min != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.layer_min != UNDEFINED); merged_num_edge.layer_min += num_edge_vec[layer_bb.layer_num].layer_num; } else { merged_num_edge.layer_min = num_edge_vec[layer_bb.layer_num].layer_num; } merged_bb.layer_min = layer_bb.layer_num; } - if (merged_bb.layer_max == OPEN || layer_bb.layer_num >= merged_bb.layer_max) { + if (merged_bb.layer_max == UNDEFINED || layer_bb.layer_num >= merged_bb.layer_max) { if (layer_bb.layer_num == merged_bb.layer_max) { - VTR_ASSERT_SAFE(merged_num_edge.layer_max != OPEN); + VTR_ASSERT_SAFE(merged_num_edge.layer_max != UNDEFINED); merged_num_edge.layer_max += num_edge_vec[layer_bb.layer_num].layer_num; } else { merged_num_edge.layer_max = num_edge_vec[layer_bb.layer_num].layer_num; diff --git a/vpr/src/place/noc_place_checkpoint.cpp b/vpr/src/place/noc_place_checkpoint.cpp index f479d46c486..d01269f2e42 100644 --- a/vpr/src/place/noc_place_checkpoint.cpp +++ b/vpr/src/place/noc_place_checkpoint.cpp @@ -15,7 +15,7 @@ NoCPlacementCheckpoint::NoCPlacementCheckpoint(NocCostHandler& noc_cost_handler) // Initializes checkpoint locations to invalid for (const ClusterBlockId router_bid : router_bids) { - router_locations_[router_bid] = t_pl_loc(OPEN, OPEN, OPEN, OPEN); + router_locations_[router_bid] = t_pl_loc(UNDEFINED, UNDEFINED, UNDEFINED, UNDEFINED); } } diff --git a/vpr/src/place/place_macro.cpp b/vpr/src/place/place_macro.cpp index b4ddc01c247..b31bc390dca 100644 --- a/vpr/src/place/place_macro.cpp +++ b/vpr/src/place/place_macro.cpp @@ -163,7 +163,7 @@ PlaceMacros::PlaceMacros(const std::vector& directs, ClusterBlockId PlaceMacros::macro_head(ClusterBlockId blk) const { int macro_index = get_imacro_from_iblk(blk); - if (macro_index == OPEN) { + if (macro_index == UNDEFINED) { return ClusterBlockId::INVALID(); } else { return pl_macros_[macro_index].members[0].blk_index; @@ -211,7 +211,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Note that the restriction that constant nets are not driven from another direct ensures that // blocks in the middle of a chain with internal constant signals are not detected as potential // head blocks. - if (to_src_or_sink == RECEIVER && to_idirect != OPEN + if (to_src_or_sink == e_pin_type::RECEIVER && to_idirect != UNDEFINED && (to_net_id == ClusterNetId::INVALID() || (is_constant_clb_net(to_net_id, atom_lookup, atom_nlist) && !net_is_driven_by_direct_(to_net_id, clb_nlist)))) { for (int from_iblk_pin = 0; from_iblk_pin < num_blk_pins; from_iblk_pin++) { int from_physical_pin = get_physical_pin(physical_tile, logical_block, from_iblk_pin); @@ -224,7 +224,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // // The output SOURCE (from_pin) of a true head macro will: // * drive another block with the same direct connection - if (from_src_or_sink == DRIVER && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { + if (from_src_or_sink == e_pin_type::DRIVER && to_idirect == from_idirect && from_net_id != ClusterNetId::INVALID()) { // Mark down that this is the first block in the macro pl_macro_member_blk_num_of_this_blk[0] = blk_id; pl_macro_idirect[num_macro] = to_idirect; @@ -249,7 +249,7 @@ int PlaceMacros::find_all_the_macro_(const ClusteredNetlist& clb_nlist, // Assume that the from_iblk_pin index is the same for the next block VTR_ASSERT(idirect_from_blk_pin_[physical_tile->index][from_physical_pin] == from_idirect - && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == DRIVER); + && direct_type_from_blk_pin_[physical_tile->index][from_physical_pin] == e_pin_type::DRIVER); next_net_id = clb_nlist.block_net(next_blk_id, from_iblk_pin); // Mark down this block as a member of the macro @@ -409,7 +409,7 @@ int PlaceMacros::get_imacro_from_iblk(ClusterBlockId iblk) const { // Return the imacro for the block. imacro = imacro_from_iblk_[iblk]; } else { - imacro = OPEN; //No valid block, so no valid macro + imacro = UNDEFINED; //No valid block, so no valid macro } return imacro; @@ -417,7 +417,7 @@ int PlaceMacros::get_imacro_from_iblk(ClusterBlockId iblk) const { void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector& directs, const std::vector& physical_tile_types) { - // Allocate and initialize the values to OPEN (-1). + // Allocate and initialize the values to UNDEFINED (-1). idirect_from_blk_pin_.resize(physical_tile_types.size()); direct_type_from_blk_pin_.resize(physical_tile_types.size()); for (const t_physical_tile_type& type : physical_tile_types) { @@ -425,8 +425,8 @@ void PlaceMacros::alloc_and_load_idirect_from_blk_pin_(const std::vector /* Allocate and initialize the values to OPEN (-1). */ for (auto blk_id : clb_nlist.blocks()) { - imacro_from_iblk_.insert(blk_id, OPEN); + imacro_from_iblk_.insert(blk_id, UNDEFINED); } /* Load the values */ @@ -629,15 +629,15 @@ void PlaceMacros::write_place_macros_(std::string filename, int itype = type.index; for (int ipin = 0; ipin < type.num_pins; ++ipin) { - if (idirect_from_blk_pin_[itype][ipin] != OPEN) { - if (direct_type_from_blk_pin_[itype][ipin] == DRIVER) { + if (idirect_from_blk_pin_[itype][ipin] != UNDEFINED) { + if (direct_type_from_blk_pin_[itype][ipin] == e_pin_type::DRIVER) { fprintf(f, "%-9s %-9d true SOURCE \n", type.name.c_str(), ipin); } else { - VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == RECEIVER); + VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == e_pin_type::RECEIVER); fprintf(f, "%-9s %-9d true SINK \n", type.name.c_str(), ipin); } } else { - VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == OPEN); + VTR_ASSERT(direct_type_from_blk_pin_[itype][ipin] == e_pin_type::OPEN); } } } @@ -664,7 +664,7 @@ bool PlaceMacros::net_is_driven_by_direct_(ClusterNetId clb_net, auto direct = idirect_from_blk_pin_[physical_tile->index][physical_pin]; - return direct != OPEN; + return direct != UNDEFINED; } const t_pl_macro& PlaceMacros::operator[](int idx) const { diff --git a/vpr/src/place/place_macro.h b/vpr/src/place/place_macro.h index d3eacc2e6f0..79a0f9f2602 100644 --- a/vpr/src/place/place_macro.h +++ b/vpr/src/place/place_macro.h @@ -200,7 +200,7 @@ class PlaceMacros { /** * @brief This array allow us to quickly find pins that could be in a direct connection. * @details Values stored is the index of the possible direct connection as specified in the arch file, - * OPEN (-1) is stored for pins that could not be part of a direct chain connection. + * UNDEFINED (-1) is stored for pins that could not be part of a direct chain connection. * [0...device_ctx.num_block_types-1][0...num_pins-1] */ std::vector> idirect_from_blk_pin_; diff --git a/vpr/src/place/timing/PlacerTimingCosts.cpp b/vpr/src/place/timing/PlacerTimingCosts.cpp index 483111a14e6..6a7a85f8d66 100644 --- a/vpr/src/place/timing/PlacerTimingCosts.cpp +++ b/vpr/src/place/timing/PlacerTimingCosts.cpp @@ -12,7 +12,7 @@ PlacerTimingCosts::PlacerTimingCosts(const ClusteredNetlist& nlist) { // The placer always skips 'ignored' nets, so they don't affect timing // costs, so we also skip them here if (nlist.net_is_ignored(net)) { - net_start_indices_[net] = OPEN; + net_start_indices_[net] = UNDEFINED; continue; } diff --git a/vpr/src/power/power.cpp b/vpr/src/power/power.cpp index 493740f5159..b327a1c41fa 100644 --- a/vpr/src/power/power.cpp +++ b/vpr/src/power/power.cpp @@ -828,7 +828,7 @@ static void power_usage_routing(t_power_usage* power_usage, for (t_edge_size edge_idx = 0; edge_idx < rr_graph.num_edges(rt_node.inode); edge_idx++) { const auto& next_node_id = size_t(rr_graph.edge_sink_node(rt_node.inode, edge_idx)); - if (next_node_id != size_t(OPEN)) { + if (next_node_id != size_t(UNDEFINED)) { t_rr_node_power* next_node_power = &rr_node_power[next_node_id]; switch (rr_graph.node_type(RRNodeId(next_node_id))) { @@ -1201,7 +1201,7 @@ void power_routing_init(const t_det_routing_arch& routing_arch) { rr_node_power = new t_rr_node_power[rr_graph.num_nodes()]; for (const RRNodeId& rr_id : device_ctx.rr_graph.nodes()) { rr_node_power[(size_t)rr_id] = t_rr_node_power(); - rr_node_power[(size_t)rr_id].driver_switch_type = OPEN; + rr_node_power[(size_t)rr_id].driver_switch_type = UNDEFINED; } /* Initialize Mux Architectures */ @@ -1267,7 +1267,7 @@ void power_routing_init(const t_det_routing_arch& routing_arch) { for (const RRNodeId& rr_node_idx : device_ctx.rr_graph.nodes()) { for (t_edge_size edge_idx = 0; edge_idx < rr_graph.num_edges(rr_node_idx); edge_idx++) { if (size_t(rr_graph.edge_sink_node(rr_node_idx, edge_idx))) { - if (rr_node_power[size_t(rr_graph.edge_sink_node(rr_node_idx, edge_idx))].driver_switch_type == OPEN) { + if (rr_node_power[size_t(rr_graph.edge_sink_node(rr_node_idx, edge_idx))].driver_switch_type == UNDEFINED) { rr_node_power[size_t(rr_graph.edge_sink_node(rr_node_idx, edge_idx))].driver_switch_type = rr_graph.edge_switch(rr_node_idx, edge_idx); } else { VTR_ASSERT(rr_node_power[size_t(rr_graph.edge_sink_node(rr_node_idx, edge_idx))].driver_switch_type == rr_graph.edge_switch(rr_node_idx, edge_idx)); diff --git a/vpr/src/power/power_components.cpp b/vpr/src/power/power_components.cpp index 38e99fae6f7..b0542e64f9f 100644 --- a/vpr/src/power/power_components.cpp +++ b/vpr/src/power/power_components.cpp @@ -453,7 +453,7 @@ void power_usage_local_interc_mux(t_power_usage* power_usage, t_pb* pb, t_interc for (pin_idx = 0; pin_idx < interc->interconnect_power->num_pins_per_port; pin_idx++) { - int selected_input = OPEN; + int selected_input = UNDEFINED; /* Clear input densities */ for (in_port_idx = 0; @@ -490,7 +490,7 @@ void power_usage_local_interc_mux(t_power_usage* power_usage, t_pb* pb, t_interc } /* Check that the input pin was found with a matching net to the output pin */ - VTR_ASSERT(selected_input != OPEN); + VTR_ASSERT(selected_input != UNDEFINED); } } else { selected_input = 0; @@ -546,7 +546,7 @@ void power_usage_mux_multilevel(t_power_usage* power_usage, auto& power_ctx = g_vpr_ctx.power(); - VTR_ASSERT(selected_input != OPEN); + VTR_ASSERT(selected_input != UNDEFINED); power_zero_usage(power_usage); diff --git a/vpr/src/route/check_route.cpp b/vpr/src/route/check_route.cpp index d464bfff6c2..b4153c40fd0 100644 --- a/vpr/src/route/check_route.cpp +++ b/vpr/src/route/check_route.cpp @@ -218,7 +218,7 @@ static void check_sink(const Netlist<>& net_list, VTR_ASSERT(rr_graph.node_type(inode) == e_rr_type::SINK); - if (net_pin_index == OPEN) { /* If there is no legal net pin index associated with this sink node */ + if (net_pin_index == UNDEFINED) { /* If there is no legal net pin index associated with this sink node */ VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "in check_sink: node %d does not connect to any terminal of net %s #%lu.\n" "This error is usually caused by incorrectly specified logical equivalence in your architecture file.\n" diff --git a/vpr/src/route/edge_groups.cpp b/vpr/src/route/edge_groups.cpp index d23d4d248ee..595c3b991dc 100644 --- a/vpr/src/route/edge_groups.cpp +++ b/vpr/src/route/edge_groups.cpp @@ -20,7 +20,7 @@ void EdgeGroups::create_sets() { // https://en.wikipedia.org/wiki/Component_(graph_theory)#Algorithms std::vector group_size; for (auto& node : graph_) { - if (node.second.set == OPEN) { + if (node.second.set == UNDEFINED) { node.second.set = group_size.size(); group_size.push_back(add_connected_group(node.second)); } @@ -28,7 +28,7 @@ void EdgeGroups::create_sets() { // Sanity check the node sets. for (const auto& node : graph_) { - VTR_ASSERT(node.second.set != OPEN); + VTR_ASSERT(node.second.set != UNDEFINED); for (const auto& e : node.second.edges) { int set = graph_[e].set; VTR_ASSERT(set == node.second.set); @@ -98,7 +98,7 @@ size_t EdgeGroups::add_connected_group(const node_data& node) { for (auto e : top->edges) { auto& next = graph_[e]; if (next.set != node.set) { - VTR_ASSERT(next.set == OPEN); + VTR_ASSERT(next.set == UNDEFINED); n++; next.set = node.set; stack.push(&next); diff --git a/vpr/src/route/edge_groups.h b/vpr/src/route/edge_groups.h index 766758ecb67..624bbce31e5 100644 --- a/vpr/src/route/edge_groups.h +++ b/vpr/src/route/edge_groups.h @@ -43,7 +43,7 @@ class EdgeGroups { private: struct node_data { std::unordered_set edges; // Set of indices into graph_ - int set = OPEN; // Index into rr_non_config_node_sets_ + int set = UNDEFINED; // Index into rr_non_config_node_sets_ }; // Perform a DFS traversal marking everything reachable with the same set id diff --git a/vpr/src/route/overuse_report.cpp b/vpr/src/route/overuse_report.cpp index 8d4e36be696..2722d219cca 100644 --- a/vpr/src/route/overuse_report.cpp +++ b/vpr/src/route/overuse_report.cpp @@ -2,6 +2,7 @@ #include #include "globals.h" +#include "physical_types.h" #include "physical_types_util.h" #include "vpr_utils.h" #include "vtr_log.h" @@ -487,7 +488,7 @@ static void print_block_pins_nets(std::ostream& os, } for (int pin = pin_num_range.low; pin <= pin_num_range.high; pin++) { - e_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; + e_rr_type rr_type = (get_pin_type_from_pin_physical_num(physical_type, pin) == e_pin_type::DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = get_pin_rr_node_id(rr_graph.node_lookup(), physical_type, layer, root_x, root_y, pin); // When flat router is enabled, RR Node chains collapse into a single node. Thus, when // looking up the RR Node ID, it may return an invalid node ID. In this case, we skip diff --git a/vpr/src/route/route_common.cpp b/vpr/src/route/route_common.cpp index 6ae41b5bb51..932419e9c09 100644 --- a/vpr/src/route/route_common.cpp +++ b/vpr/src/route/route_common.cpp @@ -6,6 +6,7 @@ #include "connection_router_interface.h" #include "describe_rr_node.h" #include "logic_types.h" +#include "physical_types.h" #include "physical_types_util.h" #include "route_export.h" #include "vpr_utils.h" @@ -390,14 +391,14 @@ static t_clb_opins_used alloc_and_load_clb_opins_used_locally() { if (port_eq == PortEquivalence::INSTANCE) { //The pin is part of an instance equivalent class, hence we need to reserve a pin - VTR_ASSERT(get_pin_type_from_pin_physical_num(type, clb_pin) == DRIVER); + VTR_ASSERT(get_pin_type_from_pin_physical_num(type, clb_pin) == e_pin_type::DRIVER); /* Check to make sure class is in same range as that assigned to block */ VTR_ASSERT(iclass >= class_range.low && iclass <= class_range.high); - //We push back OPEN to reserve space to store the exact pin which + //We push back UNDEFINED to reserve space to store the exact pin which //will be reserved (determined later) - clb_opins_used_locally[blk_id][iclass].emplace_back(OPEN); + clb_opins_used_locally[blk_id][iclass].emplace_back(UNDEFINED); } } } @@ -642,10 +643,10 @@ static vtr::vector> load_rr_clb_sources(con t_block_loc blk_loc; blk_loc = get_block_loc(blk_id, is_flat); auto class_type = get_class_type_from_class_physical_num(type, iclass); - if (class_type == DRIVER) { + if (class_type == e_pin_type::DRIVER) { rr_type = e_rr_type::SOURCE; } else { - VTR_ASSERT(class_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::RECEIVER); rr_type = e_rr_type::SINK; } diff --git a/vpr/src/route/route_net.tpp b/vpr/src/route/route_net.tpp index dc1cc75dab4..b413f6ff337 100644 --- a/vpr/src/route/route_net.tpp +++ b/vpr/src/route/route_net.tpp @@ -353,9 +353,9 @@ inline NetResultFlags pre_route_to_clock_root(ConnectionRouterType& router, /* This is a special pre-route to a sink that does not correspond to any * * netlist pin, but which can be reached from the global clock root drive * * points. Therefore, we can set the net pin index of the sink node to * - * OPEN (meaning illegal) as it is not meaningful for this sink. */ + * UNDEFINED (meaning illegal) as it is not meaningful for this sink. */ vtr::optional new_branch, new_sink; - std::tie(new_branch, new_sink) = tree.update_from_heap(&cheapest, OPEN, ((high_fanout) ? &spatial_rt_lookup : nullptr), is_flat); + std::tie(new_branch, new_sink) = tree.update_from_heap(&cheapest, UNDEFINED, ((high_fanout) ? &spatial_rt_lookup : nullptr), is_flat); VTR_ASSERT_DEBUG(!high_fanout || validate_route_tree_spatial_lookup(tree.root(), spatial_rt_lookup)); diff --git a/vpr/src/route/route_tree.cpp b/vpr/src/route/route_tree.cpp index 542116cdcea..e78f9febb3f 100644 --- a/vpr/src/route/route_tree.cpp +++ b/vpr/src/route/route_tree.cpp @@ -18,7 +18,7 @@ RouteTreeNode::RouteTreeNode(RRNodeId _inode, RRSwitchId _parent_switch, RouteTr const auto& rr_graph = device_ctx.rr_graph; re_expand = true; - net_pin_index = OPEN; + net_pin_index = UNDEFINED; C_downstream = rr_graph.node_C(_inode); R_upstream = rr_graph.node_R(_inode); Tdel = 0.5 * R_upstream * C_downstream; @@ -505,7 +505,7 @@ RouteTree::update_from_heap(RTExploredNode* hptr, int target_net_pin_index, Spat update_route_tree_spatial_lookup_recur(*start_of_new_subtree_rt_node, *spatial_rt_lookup); } - if (_net_id.is_valid() && target_net_pin_index != OPEN) /* We don't have this lookup if the tree isn't associated with a net */ + if (_net_id.is_valid() && target_net_pin_index != UNDEFINED) /* We don't have this lookup if the tree isn't associated with a net */ _is_isink_reached.set(target_net_pin_index, true); return {*start_of_new_subtree_rt_node, *sink_rt_node}; @@ -626,7 +626,7 @@ void RouteTree::add_non_configurable_nodes(RouteTreeNode* rt_node, RouteTreeNode* new_node = new RouteTreeNode(to_rr_node, edge_switch, rt_node); add_node(rt_node, new_node); - new_node->net_pin_index = OPEN; + new_node->net_pin_index = UNDEFINED; if (rr_graph.node_type(to_rr_node) == e_rr_type::IPIN && !is_flat) { new_node->re_expand = false; } else { diff --git a/vpr/src/route/router_delay_profiling.cpp b/vpr/src/route/router_delay_profiling.cpp index f1e80b06462..fcfa10335d7 100644 --- a/vpr/src/route/router_delay_profiling.cpp +++ b/vpr/src/route/router_delay_profiling.cpp @@ -108,7 +108,7 @@ bool RouterDelayProfiler::calculate_delay(RRNodeId source_node, VTR_ASSERT(cheapest.index == sink_node); vtr::optional rt_node_of_sink; - std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, OPEN, nullptr, is_flat_); + std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&cheapest, UNDEFINED, nullptr, is_flat_); //find delay *net_delay = rt_node_of_sink->Tdel; @@ -178,7 +178,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src is_flat, /*route_verbosity=*/1); RouterStats router_stats; - ConnectionParameters conn_params(ParentNetId::INVALID(), OPEN, false, std::unordered_map()); + ConnectionParameters conn_params(ParentNetId::INVALID(), UNDEFINED, false, std::unordered_map()); vtr::vector shortest_paths = router.timing_driven_find_all_shortest_paths_from_route_tree(tree.root(), cost_params, bounding_box, @@ -198,7 +198,7 @@ vtr::vector calculate_all_path_delays_from_rr_node(RRNodeId src //Build the routing tree to get the delay tree = RouteTree(RRNodeId(src_rr_node)); vtr::optional rt_node_of_sink; - std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&shortest_paths[sink_rr_node], OPEN, nullptr, router_opts.flat_routing); + std::tie(std::ignore, rt_node_of_sink) = tree.update_from_heap(&shortest_paths[sink_rr_node], UNDEFINED, nullptr, router_opts.flat_routing); VTR_ASSERT(rt_node_of_sink->inode == RRNodeId(sink_rr_node)); diff --git a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp index 1db5f89e440..86decb42482 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_compressed_map.cpp @@ -47,7 +47,7 @@ static util::Cost_Entry get_wire_cost_entry_compressed_lookahead(e_rr_type rr_ty static int initialize_compressed_loc_structs(const std::vector& segment_inf_vec) { const auto& grid = g_vpr_ctx.device().grid; - compressed_loc_index_map.resize({grid.width(), grid.height()}, OPEN); + compressed_loc_index_map.resize({grid.width(), grid.height()}, UNDEFINED); int max_seg_lenght = std::numeric_limits::min(); @@ -187,7 +187,7 @@ static void set_compressed_lookahead_map_costs(int from_layer_num, int segment_i } util::Expansion_Cost_Entry& expansion_cost_entry = routing_cost_map[to_layer][ix][iy]; int compressed_idx = compressed_loc_index_map[ix][iy]; - VTR_ASSERT(compressed_idx != OPEN); + VTR_ASSERT(compressed_idx != UNDEFINED); f_compressed_wire_cost_map[from_layer_num][chan_index][segment_index][to_layer][compressed_idx] = expansion_cost_entry.get_representative_cost_entry(util::e_representative_entry_method::SMALLEST); } @@ -297,7 +297,7 @@ static util::Cost_Entry get_nearby_cost_entry_average_neighbour(const std::map tile_max_ptc(device_ctx.physical_tile_types.size(), OPEN); + std::vector tile_max_ptc(device_ctx.physical_tile_types.size(), UNDEFINED); // Get the maximum OPIN ptc for each tile type to reserve src_opin_delays for (int itile = 0; itile < (int)device_ctx.physical_tile_types.size(); itile++) { @@ -399,7 +400,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat, continue; } for (e_rr_type rr_type : {e_rr_type::SOURCE, e_rr_type::OPIN}) { - t_physical_tile_loc sample_loc(OPEN, OPEN, OPEN); + t_physical_tile_loc sample_loc(UNDEFINED, UNDEFINED, UNDEFINED); size_t num_sampled_locs = 0; bool ptcs_with_no_delays = true; @@ -410,7 +411,7 @@ t_src_opin_delays compute_router_src_opin_lookahead(bool is_flat, &device_ctx.physical_tile_types[itile], sample_loc); - if (sample_loc.x == OPEN && sample_loc.y == OPEN && sample_loc.layer_num == OPEN) { + if (sample_loc.x == UNDEFINED && sample_loc.y == UNDEFINED && sample_loc.layer_num == UNDEFINED) { //No untried instances of the current tile type left VTR_LOGV_WARN(route_verbosity > 1, "Found no %ssample locations for %s in %s\n", @@ -486,11 +487,11 @@ t_chan_ipins_delays compute_router_chan_ipin_lookahead(int route_verbosity) { if (device_ctx.grid.num_instances(&tile_type, layer_num) == 0) { continue; } - t_physical_tile_loc sample_loc(OPEN, OPEN, OPEN); + t_physical_tile_loc sample_loc(UNDEFINED, UNDEFINED, UNDEFINED); sample_loc = pick_sample_tile(layer_num, &tile_type, sample_loc); - if (sample_loc.x == OPEN && sample_loc.y == OPEN && sample_loc.layer_num == OPEN) { + if (sample_loc.x == UNDEFINED && sample_loc.y == UNDEFINED && sample_loc.layer_num == UNDEFINED) { //No untried instances of the current tile type left VTR_LOGV_WARN(route_verbosity > 1, "Found no sample locations for %s\n", @@ -777,7 +778,7 @@ t_routing_cost_map get_routing_cost_map(int longest_seg_length, if (rr_graph.node_layer(rr_node) != from_layer_num) continue; auto cost_index = rr_graph.node_cost_index(rr_node); - VTR_ASSERT(cost_index != RRIndexedDataId(OPEN)); + VTR_ASSERT(cost_index != RRIndexedDataId(UNDEFINED)); int seg_index = device_ctx.rr_indexed_data[cost_index].seg_index; @@ -1180,7 +1181,7 @@ static int get_tile_src_opin_max_ptc(int itile) { static t_physical_tile_loc pick_sample_tile(int layer_num, t_physical_tile_type_ptr tile_type, t_physical_tile_loc prev) { //Very simple for now, just pick the fist matching tile found - t_physical_tile_loc loc(OPEN, OPEN, OPEN); + t_physical_tile_loc loc(UNDEFINED, UNDEFINED, UNDEFINED); //VTR_LOG("Prev: %d,%d\n", prev.x, prev.y); @@ -1209,7 +1210,7 @@ static t_physical_tile_loc pick_sample_tile(int layer_num, t_physical_tile_type_ } } - if (loc.x != OPEN && loc.y != OPEN && loc.layer_num != OPEN) { + if (loc.x != UNDEFINED && loc.y != UNDEFINED && loc.layer_num != UNDEFINED) { break; } else { y_init = 0; //Prepare to search next column diff --git a/vpr/src/route/router_lookahead/router_lookahead_report.cpp b/vpr/src/route/router_lookahead/router_lookahead_report.cpp index 66d459c9210..bd006e4a513 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_report.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_report.cpp @@ -126,7 +126,7 @@ static void profile_sample_routes(std::ofstream& os, RouteTree tree(sample_rr_node); e_rr_type sample_rr_node_type = rr_graph.node_type(sample_rr_node); RouterStats router_stats; - ConnectionParameters conn_params(ParentNetId::INVALID(), OPEN, false, std::unordered_map()); + ConnectionParameters conn_params(ParentNetId::INVALID(), UNDEFINED, false, std::unordered_map()); vtr::vector shortest_paths = router.timing_driven_find_all_shortest_paths_from_route_tree(tree.root(), cost_params, bounding_box, diff --git a/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp b/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp index c8e71ad6267..31acc96f27c 100644 --- a/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp +++ b/vpr/src/route/router_lookahead/router_lookahead_sampling.cpp @@ -3,6 +3,7 @@ #include #include "globals.h" +#include "vpr_types.h" #include "vtr_math.h" #include "vtr_geometry.h" #include "vtr_time.h" @@ -131,11 +132,11 @@ static std::tuple get_node_info(const t_rr_node& node, int num_se RRNodeId rr_node = node.id(); if (rr_graph.node_type(rr_node) != e_rr_type::CHANX && rr_graph.node_type(rr_node) != e_rr_type::CHANY) { - return std::tuple(OPEN, OPEN, OPEN); + return std::tuple(UNDEFINED, UNDEFINED, UNDEFINED); } if (rr_graph.node_capacity(rr_node) == 0 || rr_graph.num_edges(rr_node) == 0) { - return std::tuple(OPEN, OPEN, OPEN); + return std::tuple(UNDEFINED, UNDEFINED, UNDEFINED); } int x = rr_graph.node_xlow(rr_node); @@ -143,7 +144,7 @@ static std::tuple get_node_info(const t_rr_node& node, int num_se int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(rr_node)].seg_index; - VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index != UNDEFINED); VTR_ASSERT(seg_index < num_segments); return std::tuple(seg_index, x, y); @@ -207,7 +208,7 @@ std::vector find_sample_regions(int num_segments) { if (rr_graph.node_capacity(node.id()) == 0 || rr_graph.num_edges(node.id()) == 0) continue; int seg_index = device_ctx.rr_indexed_data[rr_graph.node_cost_index(node.id())].seg_index; - VTR_ASSERT(seg_index != OPEN); + VTR_ASSERT(seg_index != UNDEFINED); VTR_ASSERT(seg_index < num_segments); bounding_box_for_segment[seg_index].expand_bounding_box(bounding_box_for_node(node.id())); @@ -224,7 +225,7 @@ std::vector find_sample_regions(int num_segments) { int seg_index, x, y; std::tie(seg_index, x, y) = get_node_info(node, num_segments); - if (seg_index == OPEN) continue; + if (seg_index == UNDEFINED) continue; segment_counts[seg_index][x][y] += 1; } @@ -250,7 +251,7 @@ std::vector find_sample_regions(int num_segments) { int seg_index, x, y; std::tie(seg_index, x, y) = get_node_info(node, num_segments); - if (seg_index == OPEN) continue; + if (seg_index == UNDEFINED) continue; auto point = sample_point_index.find(std::make_tuple(seg_index, x, y)); if (point != sample_point_index.end()) { diff --git a/vpr/src/route/rr_graph_generation/cb_metrics.cpp b/vpr/src/route/rr_graph_generation/cb_metrics.cpp index 6664bd91d41..c16f37f14a0 100644 --- a/vpr/src/route/rr_graph_generation/cb_metrics.cpp +++ b/vpr/src/route/rr_graph_generation/cb_metrics.cpp @@ -28,6 +28,7 @@ #include #include +#include "physical_types.h" #include "physical_types_util.h" #include "vtr_random.h" #include "vtr_log.h" @@ -152,9 +153,9 @@ void adjust_cb_metric(const e_metric metric, const float target, const float tar /* get the number of block pins that are of pin_type */ int num_pin_type_pins = 0; - if (DRIVER == pin_type) { + if (e_pin_type::DRIVER == pin_type) { num_pin_type_pins = block_type->num_drivers; - } else if (RECEIVER == pin_type) { + } else if (e_pin_type::RECEIVER == pin_type) { num_pin_type_pins = block_type->num_receivers; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Found unexpected pin type when adjusting CB wire metric: %d\n", pin_type); @@ -196,9 +197,9 @@ void get_conn_block_metrics(const t_physical_tile_type_ptr block_type, int***** /* get the number of block pins that are of pin_type */ int num_pin_type_pins = UNDEFINED; - if (DRIVER == pin_type) { + if (e_pin_type::DRIVER == pin_type) { num_pin_type_pins = block_type->num_drivers; - } else if (RECEIVER == pin_type) { + } else if (e_pin_type::RECEIVER == pin_type) { num_pin_type_pins = block_type->num_receivers; } else { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Found unexpected pin type when adjusting CB wire metric: %d\n", pin_type); @@ -211,7 +212,7 @@ void get_conn_block_metrics(const t_physical_tile_type_ptr block_type, int***** /* check based on block type whether we should account for pins on both sides of a channel when computing the relevant CB metrics * (i.e. from a block on the left and from a block on the right for a vertical channel, for instance) */ bool both_sides = false; - if (block_type->name == "clb" && DRIVER == pin_type) { + if (block_type->name == "clb" && e_pin_type::DRIVER == pin_type) { /* many CLBs are adjacent to each other, so connections from one CLB * will share the channel segment with its neighbor. We'd like to take this into * account for the applicable metrics. */ @@ -234,7 +235,7 @@ void get_conn_block_metrics(const t_physical_tile_type_ptr block_type, int***** /* initializes the fields of the cb_metrics class */ static void init_cb_structs(const t_physical_tile_type_ptr block_type, int***** tracks_connected_to_pin, const int num_segments, const t_segment_inf* segment_inf, const e_pin_type pin_type, const int num_pin_type_pins, const int nodes_per_chan, const int Fc, Conn_Block_Metrics* cb_metrics) { /* can not calculate CB metrics for open pins */ - if (OPEN == pin_type) { + if (e_pin_type::OPEN == pin_type) { VPR_FATAL_ERROR(VPR_ERROR_ROUTE, "Can not initialize CB metric structures for pins of OPEN type\n"); } @@ -698,7 +699,7 @@ static double try_move(const e_metric metric, /* for the CLB block types it is appropriate to account for pins on both sides of a channel segment when * calculating a CB metric (because CLBs are often found side by side) */ bool both_sides = false; - if (block_type->name == "clb" && DRIVER == pin_type) { + if (block_type->name == "clb" && e_pin_type::DRIVER == pin_type) { /* many CLBs are adjacent to each other, so connections from one CLB * will share the channel segment with its neighbor. We'd like to take this into * account for the applicable metrics. */ @@ -1349,13 +1350,13 @@ void analyze_conn_blocks(const int***** opin_cb, const int***** ipin_cb, const t int nodes_per_chan = chan_width_inf->x_min; /* get Fc */ - int Fc_out = get_max_Fc(Fc_array_out, block_type, DRIVER); - int Fc_in = get_max_Fc(Fc_array_in, block_type, RECEIVER); + int Fc_out = get_max_Fc(Fc_array_out, block_type, e_pin_type::DRIVER); + int Fc_in = get_max_Fc(Fc_array_in, block_type, e_pin_type::RECEIVER); /* get the basic input and output conn block crossbars */ t_xbar_matrix output_xbar, input_xbar; - get_xbar_matrix(opin_cb, block_type, DRIVER, 0, true, nodes_per_chan, Fc_out, &output_xbar); - get_xbar_matrix(ipin_cb, block_type, RECEIVER, 0, false, nodes_per_chan, Fc_in, &input_xbar); + get_xbar_matrix(opin_cb, block_type, e_pin_type::DRIVER, 0, true, nodes_per_chan, Fc_out, &output_xbar); + get_xbar_matrix(ipin_cb, block_type, e_pin_type::RECEIVER, 0, false, nodes_per_chan, Fc_in, &input_xbar); input_xbar = transpose_xbar(&input_xbar); /* 'normalize' the output_xbar such that each entry which was formerly equal to '1' will now diff --git a/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp b/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp index ceedb7467f2..94f0bb2dd49 100644 --- a/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp +++ b/vpr/src/route/rr_graph_generation/clb2clb_directs.cpp @@ -34,7 +34,7 @@ std::vector alloc_and_load_clb_to_clb_directs(const std::v t_physical_tile_port tile_port = find_tile_port_by_name(physical_tile, port_name); - if (start_pin_index == OPEN) { + if (start_pin_index == UNDEFINED) { VTR_ASSERT(start_pin_index == end_pin_index); start_pin_index = 0; end_pin_index = tile_port.num_pins - 1; @@ -58,7 +58,7 @@ std::vector alloc_and_load_clb_to_clb_directs(const std::v tile_port = find_tile_port_by_name(physical_tile, port_name); - if (start_pin_index == OPEN) { + if (start_pin_index == UNDEFINED) { VTR_ASSERT(start_pin_index == end_pin_index); start_pin_index = 0; end_pin_index = tile_port.num_pins - 1; diff --git a/vpr/src/route/rr_graph_generation/clock_connection_builders.h b/vpr/src/route/rr_graph_generation/clock_connection_builders.h index 72ee94278b4..fd4aacf2fa4 100644 --- a/vpr/src/route/rr_graph_generation/clock_connection_builders.h +++ b/vpr/src/route/rr_graph_generation/clock_connection_builders.h @@ -3,6 +3,7 @@ #include #include "rr_graph_clock.h" +#include "vpr_types.h" class ClockRRGraphBuilder; @@ -32,7 +33,7 @@ class RoutingToClockConnection : public ClockConnection { std::string clock_to_connect_to; std::string switch_point_name; t_physical_tile_loc switch_location; - int arch_switch_idx = OPEN; + int arch_switch_idx = UNDEFINED; float fc = 0.; int seed = 101; @@ -62,7 +63,7 @@ class ClockToClockConneciton : public ClockConnection { std::string from_switch; std::string to_clock; std::string to_switch; - int arch_switch_idx = OPEN; + int arch_switch_idx = UNDEFINED; float fc = 0.; public: @@ -90,7 +91,7 @@ class ClockToPinsConnection : public ClockConnection { private: std::string clock_to_connect_from; std::string switch_point_name; - int arch_switch_idx = OPEN; + int arch_switch_idx = UNDEFINED; float fc = 0.; public: diff --git a/vpr/src/route/rr_graph_generation/clock_network_builders.h b/vpr/src/route/rr_graph_generation/clock_network_builders.h index 4b9db746d60..608fd718c8c 100644 --- a/vpr/src/route/rr_graph_generation/clock_network_builders.h +++ b/vpr/src/route/rr_graph_generation/clock_network_builders.h @@ -8,6 +8,8 @@ #include "rr_graph_clock.h" #include "rr_graph_type.h" +#include "vpr_types.h" + class t_rr_graph_storage; class ClockRRGraphBuilder; @@ -24,44 +26,44 @@ struct MetalLayer { struct Wire { MetalLayer layer; - int start = OPEN; - int length = OPEN; - int position = OPEN; + int start = UNDEFINED; + int length = UNDEFINED; + int position = UNDEFINED; }; struct WireRepeat { - int x = OPEN; - int y = OPEN; + int x = UNDEFINED; + int y = UNDEFINED; }; struct RibDrive { std::string name; - int offset = OPEN; - int switch_idx = OPEN; + int offset = UNDEFINED; + int switch_idx = UNDEFINED; }; struct RibTaps { std::string name; - int offset = OPEN; - int increment = OPEN; + int offset = UNDEFINED; + int increment = UNDEFINED; }; struct SpineDrive { std::string name; - int offset = OPEN; - int switch_idx = OPEN; + int offset = UNDEFINED; + int switch_idx = UNDEFINED; }; struct SpineTaps { std::string name; - int offset = OPEN; - int increment = OPEN; + int offset = UNDEFINED; + int increment = UNDEFINED; }; struct HtreeDrive { std::string name; t_physical_tile_loc offset; - int switch_idx = OPEN; + int switch_idx = UNDEFINED; }; struct HtreeTaps { @@ -73,7 +75,7 @@ struct HtreeTaps { class ClockNetwork { protected: std::string clock_name_; - int num_inst_ = OPEN; + int num_inst_ = UNDEFINED; public: /* @@ -127,9 +129,9 @@ class ClockRib : public ClockNetwork { RibTaps tap; // segment indices - int right_seg_idx = OPEN; - int left_seg_idx = OPEN; - int drive_seg_idx = OPEN; + int right_seg_idx = UNDEFINED; + int left_seg_idx = UNDEFINED; + int drive_seg_idx = UNDEFINED; public: /** Constructor**/ @@ -204,9 +206,9 @@ class ClockSpine : public ClockNetwork { * right nodes for the network. We now use segment indices realtive to the **parallel** vector of segments to setup the cost index, so these * will be remapped later in the map_relative_seg_indices. */ - int right_seg_idx = OPEN; - int left_seg_idx = OPEN; - int drive_seg_idx = OPEN; + int right_seg_idx = UNDEFINED; + int left_seg_idx = UNDEFINED; + int drive_seg_idx = UNDEFINED; public: /* diff --git a/vpr/src/route/rr_graph_generation/rr_graph.cpp b/vpr/src/route/rr_graph_generation/rr_graph.cpp index 32fc4d289b7..139f5bc99be 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph.cpp @@ -5,6 +5,7 @@ #include #include "alloc_and_load_rr_indexed_data.h" #include "get_parallel_segs.h" +#include "physical_types.h" #include "physical_types_util.h" #include "rr_graph_view.h" #include "rr_rc_data.h" @@ -781,7 +782,7 @@ void create_rr_graph(e_graph_type graph_type, if (is_flat) { int delayless_switch = get_delayless_switch_id(det_routing_arch, load_rr_graph); - VTR_ASSERT(delayless_switch != OPEN); + VTR_ASSERT(delayless_switch != UNDEFINED); build_intra_cluster_rr_graph(graph_type, grid, block_types, @@ -1275,12 +1276,12 @@ static void build_rr_graph(e_graph_type graph_type, for (size_t itype = 0; itype < types.size(); ++itype) { std::set type_layer = get_layers_of_physical_types(&types[itype]); - ipin_to_track_map_x[itype] = alloc_and_load_pin_to_track_map(RECEIVER, + ipin_to_track_map_x[itype] = alloc_and_load_pin_to_track_map(e_pin_type::RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, segment_inf_x, sets_per_seg_type_x); - ipin_to_track_map_y[itype] = alloc_and_load_pin_to_track_map(RECEIVER, + ipin_to_track_map_y[itype] = alloc_and_load_pin_to_track_map(e_pin_type::RECEIVER, Fc_in[itype], &types[itype], type_layer, perturb_ipins[itype], directionality, segment_inf_y, sets_per_seg_type_y); @@ -1318,7 +1319,7 @@ static void build_rr_graph(e_graph_type graph_type, std::set type_layer = get_layers_of_physical_types(&types[itype]); std::vector perturb_opins = alloc_and_load_perturb_opins(&types[itype], Fc_out[itype], max_chan_width, segment_inf); - opin_to_track_map[itype] = alloc_and_load_pin_to_track_map(DRIVER, + opin_to_track_map[itype] = alloc_and_load_pin_to_track_map(e_pin_type::DRIVER, Fc_out[itype], &types[itype], type_layer, perturb_opins, directionality, segment_inf, sets_per_seg_type); } @@ -1505,7 +1506,7 @@ static void build_intra_cluster_rr_graph(e_graph_type graph_type, static int get_delayless_switch_id(const t_det_routing_arch& det_routing_arch, bool load_rr_graph) { const auto& device_ctx = g_vpr_ctx.device(); - int delayless_switch = OPEN; + int delayless_switch = UNDEFINED; if (load_rr_graph) { const auto& rr_switches = device_ctx.rr_graph.rr_switch(); for (size_t switch_id = 0; switch_id < rr_switches.size(); switch_id++) { @@ -1627,7 +1628,7 @@ void alloc_and_load_rr_switch_inf(RRGraphBuilder& rr_graph_builder, // //Instead of throwing an error we issue a warning. This means that check_rr_graph() etc. will run to give more information //and allow graphics to be brought up for users to debug their architectures. - (*wire_to_rr_ipin_switch) = OPEN; + (*wire_to_rr_ipin_switch) = UNDEFINED; VTR_LOG_WARN("No switch found for the ipin cblock in RR graph. Check if there is an error in arch file, or if no connection blocks are being built in RR graph\n"); } } @@ -2251,7 +2252,7 @@ static vtr::vector> get_pin_chains_flat( const auto& cluster_pin_chain_num = pin_chains[cluster_id].pin_chain_idx; chain_pin_nums[cluster_id].reserve(cluster_pin_chain_num.size()); for (int pin_num = 0; pin_num < (int)cluster_pin_chain_num.size(); pin_num++) { - if (cluster_pin_chain_num[pin_num] != OPEN) { + if (cluster_pin_chain_num[pin_num] != UNDEFINED) { chain_pin_nums[cluster_id].insert(pin_num); } } @@ -2353,11 +2354,11 @@ static void add_classes_rr_graph(RRGraphBuilder& rr_graph_builder, RRNodeId class_inode = get_class_rr_node_id(rr_graph_builder.node_lookup(), physical_type, layer, root_x, root_y, class_num); VTR_ASSERT(class_inode != RRNodeId::INVALID()); int class_num_pins = get_class_num_pins_from_class_physical_num(physical_type, class_num); - if (class_type == DRIVER) { + if (class_type == e_pin_type::DRIVER) { rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SOURCE_COST_INDEX)); rr_graph_builder.set_node_type(class_inode, e_rr_type::SOURCE); } else { - VTR_ASSERT(class_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::RECEIVER); rr_graph_builder.set_node_cost_index(class_inode, RRIndexedDataId(SINK_COST_INDEX)); rr_graph_builder.set_node_type(class_inode, e_rr_type::SINK); @@ -2385,7 +2386,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, const RRSpatialLookup& node_lookup = rr_graph_builder.node_lookup(); for (int pin_num : pin_num_vec) { e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type, pin_num); - VTR_ASSERT(pin_type == DRIVER || pin_type == RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::DRIVER || pin_type == e_pin_type::RECEIVER); std::vector x_offset_vec; std::vector y_offset_vec; std::vector pin_sides_vec; @@ -2395,7 +2396,7 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, int x_offset = x_offset_vec[pin_coord]; int y_offset = y_offset_vec[pin_coord]; e_side pin_side = pin_sides_vec[pin_coord]; - e_rr_type node_type = (pin_type == DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; + e_rr_type node_type = (pin_type == e_pin_type::DRIVER) ? e_rr_type::OPIN : e_rr_type::IPIN; RRNodeId node_id = node_lookup.find_node(layer, i + x_offset, j + y_offset, @@ -2403,10 +2404,10 @@ static void add_pins_rr_graph(RRGraphBuilder& rr_graph_builder, pin_num, pin_side); if (node_id != RRNodeId::INVALID()) { - if (pin_type == RECEIVER) { + if (pin_type == e_pin_type::RECEIVER) { rr_graph_builder.set_node_cost_index(node_id, RRIndexedDataId(IPIN_COST_INDEX)); } else { - VTR_ASSERT(pin_type == DRIVER); + VTR_ASSERT(pin_type == e_pin_type::DRIVER); rr_graph_builder.set_node_cost_index(node_id, RRIndexedDataId(OPIN_COST_INDEX)); } @@ -2459,12 +2460,12 @@ static void connect_tile_src_sink_to_pins(RRGraphBuilder& rr_graph_builder, continue; } auto pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); - if (class_type == DRIVER) { - VTR_ASSERT(pin_type == DRIVER); + if (class_type == e_pin_type::DRIVER) { + VTR_ASSERT(pin_type == e_pin_type::DRIVER); rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, false); } else { - VTR_ASSERT(class_type == RECEIVER); - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, false); } } @@ -2497,12 +2498,12 @@ static void connect_src_sink_to_pins(RRGraphBuilder& rr_graph_builder, continue; } e_pin_type pin_type = get_pin_type_from_pin_physical_num(physical_type_ptr, pin_num); - if (class_type == DRIVER) { - VTR_ASSERT(pin_type == DRIVER); + if (class_type == e_pin_type::DRIVER) { + VTR_ASSERT(pin_type == e_pin_type::DRIVER); rr_edges_to_create.emplace_back(class_rr_node_id, pin_rr_node_id, delayless_switch, switches_remapped); } else { - VTR_ASSERT(class_type == RECEIVER); - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); rr_edges_to_create.emplace_back(pin_rr_node_id, class_rr_node_id, delayless_switch, switches_remapped); } } @@ -2599,7 +2600,7 @@ static void build_bidir_rr_opins(RRGraphBuilder& rr_graph_builder, for (int pin_index = 0; pin_index < type->num_pins; ++pin_index) { // We only are working with opins so skip non-drivers - if (get_pin_type_from_pin_physical_num(type, pin_index) != DRIVER) { + if (get_pin_type_from_pin_physical_num(type, pin_index) != e_pin_type::DRIVER) { continue; } @@ -2761,7 +2762,7 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, int chain_num = pin_chain_idx[pin_physical_num]; bool primitive_pin = is_primitive_pin(physical_type, pin_physical_num); bool pin_on_tile = is_pin_on_tile(physical_type, pin_physical_num); - if (chain_num != OPEN && chain_sinks[chain_num] != pin_physical_num && !primitive_pin && !pin_on_tile) { + if (chain_num != UNDEFINED && chain_sinks[chain_num] != pin_physical_num && !primitive_pin && !pin_on_tile) { continue; } auto parent_pin_node_id = get_pin_rr_node_id(rr_graph_builder.node_lookup(), @@ -2781,7 +2782,7 @@ static void add_pb_edges(RRGraphBuilder& rr_graph_builder, int conn_pin_chain_num = pin_chain_idx[conn_pin_physical_num]; primitive_pin = is_primitive_pin(physical_type, conn_pin_physical_num); pin_on_tile = is_pin_on_tile(physical_type, conn_pin_physical_num); - if (conn_pin_chain_num != OPEN && chain_sinks[conn_pin_chain_num] != conn_pin_physical_num && !primitive_pin && !pin_on_tile) { + if (conn_pin_chain_num != UNDEFINED && chain_sinks[conn_pin_chain_num] != conn_pin_physical_num && !primitive_pin && !pin_on_tile) { continue; } auto conn_pin_node_id = get_pin_rr_node_id(rr_graph_builder.node_lookup(), @@ -2942,7 +2943,7 @@ static void add_chain_node_fan_in_edges(RRGraphBuilder& rr_graph_builder, pin_physical_num); for (auto src_pin : src_pins) { // If the source pin is located on the current chain no edge should be added since the nodes should be collapsed. - if (pin_chain_idx[src_pin] != OPEN) { + if (pin_chain_idx[src_pin] != UNDEFINED) { if ((pin_chain_idx[src_pin] == chain_idx)) { continue; } else { @@ -3282,7 +3283,7 @@ static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const const e_directionality directionality, const std::vector& seg_inf, const std::vector& sets_per_seg_type) { - // allocate 'result' matrix and initialize entries to OPEN. also allocate and intialize matrix which will be used + // allocate 'result' matrix and initialize entries to UNDEFINED. also allocate and intialize matrix which will be used // to index into the correct entries when loading up 'result' auto& grid = g_vpr_ctx.device().grid; auto result = vtr::NdMatrix, 5>({ @@ -3328,7 +3329,7 @@ static vtr::NdMatrix, 5> alloc_and_load_pin_to_track_map(const for (int iconn = 0; iconn < cur_Fc; iconn++) { for (auto connected_layer : get_layers_pin_is_connected_to(tile_type, type_layer_index, ipin)) { int relative_track_ind = pin_to_seg_type_map[ipin][iwidth][iheight][connected_layer][iside][iconn]; - if (relative_track_ind != OPEN) { + if (relative_track_ind != UNDEFINED) { VTR_ASSERT(relative_track_ind <= num_seg_type_tracks); int absolute_track_ind = relative_track_ind + seg_type_start_track; @@ -3367,7 +3368,7 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin // no pin on that side, or that pin is of the wrong type. // Probably not enough memory to worry about, esp. as it's temporary. // If pin ipin on side iside does not exist or is of the wrong type, - // tracks_connected_to_pin[ipin][iside][0] = OPEN. + // tracks_connected_to_pin[ipin][iside][0] = UNDEFINED. auto& grid = g_vpr_ctx.device().grid; @@ -3383,7 +3384,7 @@ static vtr::NdMatrix alloc_and_load_pin_to_seg_type(const e_pin_type pin NUM_2D_SIDES, // [0..NUM_2D_SIDES-1] size_t(max_Fc) // [0..Fc-1] }, - OPEN); // Unconnected + UNDEFINED); // Unconnected // Number of *physical* pins on each side. // Note that his may be more than the logical number of pins (i.e. @@ -3957,7 +3958,7 @@ static void check_all_tracks_reach_pins(t_logical_block_type_ptr type, for (int width = 0; width < type->width; ++width) { for (int height = 0; height < type->height; ++height) { for (int side = 0; side < 4; ++side) { - if (tracks_connected_to_pin[pin][width][height][side][0] != OPEN) { /* Pin exists */ + if (tracks_connected_to_pin[pin][width][height][side][0] != UNDEFINED) { /* Pin exists */ for (int conn = 0; conn < Fc; ++conn) { int track = tracks_connected_to_pin[pin][width][height][side][conn]; num_conns_to_track[track]++; @@ -4090,7 +4091,7 @@ static void build_unidir_rr_opins(RRGraphBuilder& rr_graph_builder, for (int pin_index = 0; pin_index < type->num_pins; ++pin_index) { /* Skip global pins and pins that are not of DRIVER type */ e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, pin_index); - if (pin_type != DRIVER) { + if (pin_type != e_pin_type::DRIVER) { continue; } if (type->is_ignored_pin[pin_index]) { @@ -4228,7 +4229,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, && z + directs[i].sub_tile_offset < int(target_type->capacity) && z + directs[i].sub_tile_offset >= 0) { // Compute index of opin with regards to given pins - int max_index = OPEN, min_index = OPEN; + int max_index = UNDEFINED, min_index = UNDEFINED; bool swap = false; if (clb_to_clb_directs[i].from_clb_pin_start_index > clb_to_clb_directs[i].from_clb_pin_end_index) { swap = true; @@ -4243,7 +4244,7 @@ static int get_opin_direct_connections(RRGraphBuilder& rr_graph_builder, if (max_index >= relative_opin && min_index <= relative_opin) { int offset = relative_opin - min_index; // This opin is specified to connect directly to an ipin, now compute which ipin to connect to - int relative_ipin = OPEN; + int relative_ipin = UNDEFINED; if (clb_to_clb_directs[i].to_clb_pin_start_index > clb_to_clb_directs[i].to_clb_pin_end_index) { if (swap) { relative_ipin = clb_to_clb_directs[i].to_clb_pin_end_index + offset; @@ -4340,7 +4341,7 @@ static std::vector alloc_and_load_perturb_opins(const t_physical_tile_type /* get Fc_max */ for (i = 0; i < type->num_pins; ++i) { auto pin_type = get_pin_type_from_pin_physical_num(type, i); - if (Fc_out[i][0] > Fc_max && pin_type == DRIVER) { + if (Fc_out[i][0] > Fc_max && pin_type == e_pin_type::DRIVER) { Fc_max = Fc_out[i][0]; } } @@ -4521,7 +4522,7 @@ bool pins_connected(t_block_loc cluster_loc, logical_block, rel_cap, from_pb_pin); - VTR_ASSERT(from_pin_physical_num != OPEN); + VTR_ASSERT(from_pin_physical_num != UNDEFINED); auto to_pb_pin = logical_block->pin_logical_num_to_pb_pin_mapping.at(to_pin_logical_num); int to_pin_physical_num = get_pb_pin_physical_num(physical_type, @@ -4530,7 +4531,7 @@ bool pins_connected(t_block_loc cluster_loc, rel_cap, to_pb_pin); - VTR_ASSERT(to_pin_physical_num != OPEN); + VTR_ASSERT(to_pin_physical_num != UNDEFINED); RRNodeId from_node = get_pin_rr_node_id(rr_spatial_look_up, physical_type, layer, x, y, from_pin_physical_num); VTR_ASSERT(from_node != RRNodeId::INVALID()); @@ -4556,7 +4557,7 @@ static t_cluster_pin_chain get_cluster_directly_connected_nodes(const std::vecto std::unordered_set cluster_pins_set(cluster_pins.begin(), cluster_pins.end()); // Faster for search VTR_ASSERT(is_flat); - std::vector pin_index_vec(get_tile_total_num_pin(physical_type), OPEN); + std::vector pin_index_vec(get_tile_total_num_pin(physical_type), UNDEFINED); std::vector> chains; for (auto pin_physical_num : cluster_pins) { @@ -4565,7 +4566,7 @@ static t_cluster_pin_chain get_cluster_directly_connected_nodes(const std::vecto physical_type, logical_block, pin_physical_num); - VTR_ASSERT(pin_type != OPEN); + VTR_ASSERT(pin_type != e_pin_type::OPEN); // Continue if the fan-out or fan-in of pin_physical_num is not equal to one or pin is already assigned to a chain. if (pin_index_vec[pin_physical_num] >= 0 || conn_sink_pins.size() != 1) { continue; @@ -4653,7 +4654,7 @@ static bool is_node_chain_sorted(t_physical_tile_type_ptr physical_type, if (pin_index_vec[curr_pin_num] != chain_idx) { return false; } - if (nxt_idx == OPEN) { + if (nxt_idx == UNDEFINED) { continue; } auto conn_pin_vec = get_sink_pins_in_cluster(pins_in_cluster, physical_type, logical_block, curr_node.pin_physical_num); @@ -4676,7 +4677,7 @@ static std::vector get_node_chain_sinks(const std::vector get_src_pins_in_cluster(const std::unordered_set& p } static int get_chain_idx(const std::vector& pin_idx_vec, const std::vector& pin_chain, int new_idx) { - int chain_idx = OPEN; + int chain_idx = UNDEFINED; for (auto pin_num : pin_chain) { int pin_chain_num = pin_idx_vec[pin_num]; - if (pin_chain_num != OPEN) { + if (pin_chain_num != UNDEFINED) { chain_idx = pin_chain_num; break; } } - if (chain_idx == OPEN) { + if (chain_idx == UNDEFINED) { chain_idx = new_idx; } return chain_idx; @@ -4756,7 +4757,7 @@ static void add_pin_chain(const std::vector& pin_chain, int nxt_node_idx = 1; for (auto pin_num : pin_chain) { // Since we assume that none of the pins in the pin_chain has seen before - VTR_ASSERT(pin_index_vec[pin_num] == OPEN); + VTR_ASSERT(pin_index_vec[pin_num] == UNDEFINED); // Assign the pin its chain index pin_index_vec[pin_num] = chain_idx; new_pin_chain.emplace_back(pin_num, nxt_node_idx); @@ -4764,7 +4765,7 @@ static void add_pin_chain(const std::vector& pin_chain, } // For the last pin in the chain, there is no next pin. - new_pin_chain[new_pin_chain.size() - 1].nxt_node_idx = OPEN; + new_pin_chain[new_pin_chain.size() - 1].nxt_node_idx = UNDEFINED; all_chains.push_back(new_pin_chain); @@ -4780,7 +4781,7 @@ static void add_pin_chain(const std::vector& pin_chain, bool is_new_pin_added = false; bool found_pin_in_chain = false; for (auto pin_num : pin_chain) { - if (pin_index_vec[pin_num] == OPEN) { + if (pin_index_vec[pin_num] == UNDEFINED) { pin_index_vec[pin_num] = chain_idx; node_chain.emplace_back(pin_num, nxt_node_idx); nxt_node_idx++; @@ -4788,7 +4789,7 @@ static void add_pin_chain(const std::vector& pin_chain, } else { found_pin_in_chain = true; // pin_num is the pin_number of a pin which is the first pin in the chain that is added to all_chains - int first_pin_in_chain_idx = OPEN; + int first_pin_in_chain_idx = UNDEFINED; for (int pin_idx = 0; pin_idx < pin_chain_init_size; pin_idx++) { if (node_chain[pin_idx].pin_physical_num == pin_num) { first_pin_in_chain_idx = pin_idx; @@ -4796,7 +4797,7 @@ static void add_pin_chain(const std::vector& pin_chain, } } // We assume that this pin is already added to all_chains - VTR_ASSERT(first_pin_in_chain_idx != OPEN); + VTR_ASSERT(first_pin_in_chain_idx != UNDEFINED); // We assume than if this block is being run, at least one new pin should be added to the chain VTR_ASSERT(is_new_pin_added); diff --git a/vpr/src/route/rr_graph_generation/rr_graph2.cpp b/vpr/src/route/rr_graph_generation/rr_graph2.cpp index 89a7e19a0f4..4e88d42e068 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph2.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph2.cpp @@ -703,9 +703,9 @@ int get_bidir_opin_connections(RRGraphBuilder& rr_graph_builder, for (int to_track : opin_to_track_map[type->index][ipin][width_offset][height_offset][track_layer][side]) { /* Skip unconnected connections */ - if (OPEN == to_track || is_connected_track) { + if (UNDEFINED == to_track || is_connected_track) { is_connected_track = true; - VTR_ASSERT(OPEN == opin_to_track_map[type->index][ipin][width_offset][height_offset][track_layer][side][0]); + VTR_ASSERT(UNDEFINED == opin_to_track_map[type->index][ipin][width_offset][height_offset][track_layer][side][0]); continue; } @@ -1494,7 +1494,7 @@ static int get_bidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, /* There are up to two switch edges allowed from track to track */ for (i = 0; i < 2; ++i) { /* If the switch_type entry is empty, skip it */ - if (OPEN == switch_types[i]) { + if (UNDEFINED == switch_types[i]) { continue; } @@ -1782,7 +1782,7 @@ static int get_unidir_track_to_chan_seg(RRGraphBuilder& rr_graph_builder, if (should_apply_switch_override(switch_override)) { iswitch = switch_override; } - VTR_ASSERT(iswitch != OPEN); + VTR_ASSERT(iswitch != UNDEFINED); /* Add edge to list. */ rr_edges_to_create.emplace_back(from_rr_node, to_node, iswitch, false); @@ -1836,7 +1836,7 @@ static void get_switch_type(bool is_from_sblock, * and what type of switch is used to connect *to* each type of node * * (from_node_switch and to_node_switch). It decides what type of switch, * * if any, should be used to go from from_node to to_node. If no switch * - * should be inserted (i.e. no connection), it returns OPEN. Its returned * + * should be inserted (i.e. no connection), it returns NO_SWITCH. Its returned * * values are in the switch_types array. It needs to return an array * * because some topologies (e.g. bi-dir pass gates) result in two switches.*/ diff --git a/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp index 09bad36ad28..fe9706fc302 100644 --- a/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp +++ b/vpr/src/route/rr_graph_generation/rr_graph_indexed_data.cpp @@ -6,7 +6,7 @@ void load_rr_index_segments(const int num_segment) { int iseg, i, index; for (i = SOURCE_COST_INDEX; i <= IPIN_COST_INDEX; i++) { - device_ctx.rr_indexed_data[RRIndexedDataId(i)].seg_index = OPEN; + device_ctx.rr_indexed_data[RRIndexedDataId(i)].seg_index = UNDEFINED; } /* X-directed segments. */ diff --git a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp index c1340e8d3b6..0cf638ef487 100644 --- a/vpr/src/route/rr_graph_generation/rr_node_indices.cpp +++ b/vpr/src/route/rr_graph_generation/rr_node_indices.cpp @@ -3,6 +3,7 @@ #include "describe_rr_node.h" #include "globals.h" +#include "physical_types.h" #include "physical_types_util.h" #include "rr_graph2.h" #include "vpr_utils.h" @@ -243,10 +244,10 @@ static void add_classes_spatial_lookup(RRGraphBuilder& rr_graph_builder, for (const int class_num : class_num_vec) { e_pin_type class_type = get_class_type_from_class_physical_num(physical_type_ptr, class_num); e_rr_type node_type = e_rr_type::SINK; - if (class_type == DRIVER) { + if (class_type == e_pin_type::DRIVER) { node_type = e_rr_type::SOURCE; } else { - VTR_ASSERT(class_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::RECEIVER); } for (int x_offset = 0; x_offset < block_width; x_offset++) { @@ -290,11 +291,11 @@ static void add_pins_spatial_lookup(RRGraphBuilder& rr_graph_builder, int x_tile = root_x + x_offset[pin_coord_idx]; int y_tile = root_y + y_offset[pin_coord_idx]; e_side side = pin_sides[pin_coord_idx]; - if (pin_type == DRIVER) { + if (pin_type == e_pin_type::DRIVER) { rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::OPIN, pin_num, side); assigned_to_rr_node = true; } else { - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); rr_graph_builder.node_lookup().add_node(RRNodeId(*index), layer, x_tile, y_tile, e_rr_type::IPIN, pin_num, side); assigned_to_rr_node = true; } diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp index ac1aad9f4fc..ca9b0d8935d 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/rr_gsb.cpp @@ -2,6 +2,7 @@ * Member functions for class RRGSB ***********************************************************************/ /* Headers from vtrutil library */ +#include "vpr_types.h" #include "vtr_log.h" #include "vtr_assert.h" #include "vpr_error.h" @@ -877,7 +878,7 @@ void RRGSB::sort_chan_node_in_edges(const RRGraphView& rr_graph, } VTR_ASSERT(NUM_2D_SIDES != side); - VTR_ASSERT(OPEN != index); + VTR_ASSERT(UNDEFINED != index); if (e_rr_type::OPIN == rr_graph.node_type(src_node)) { from_grid_edge_map[side][index] = edge; @@ -965,14 +966,14 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } /* The driver routing channel node can be either an input or an output to the GSB. * Just try to find a qualified one. */ - int index = OPEN; + int index = UNDEFINED; index = get_node_index(rr_graph, src_node, chan_side, IN_PORT); - if (OPEN == index) { + if (UNDEFINED == index) { index = get_node_index(rr_graph, src_node, chan_side, OUT_PORT); } /* Must have valid side and index */ - if (OPEN == index) { + if (UNDEFINED == index) { VTR_LOG_DEBUG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG_DEBUG("----------------------------------\n"); VTR_LOG_DEBUG("SRC node:\n"); @@ -992,7 +993,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, } } - VTR_ASSERT(OPEN != index); + VTR_ASSERT(UNDEFINED != index); VTR_ASSERT((e_rr_type::CHANX == rr_graph.node_type(src_node)) || (e_rr_type::CHANY == rr_graph.node_type(src_node))); @@ -1013,7 +1014,7 @@ void RRGSB::sort_ipin_node_in_edges(const RRGraphView& rr_graph, cb_opin_index); VTR_ASSERT((-1 != cb_opin_index) && (NUM_2D_SIDES != cb_opin_side)); /* Must have valid side and index */ - if (OPEN == cb_opin_index || NUM_2D_SIDES == cb_opin_side) { + if (UNDEFINED == cb_opin_index || NUM_2D_SIDES == cb_opin_side) { VTR_LOG_DEBUG("GSB[%lu][%lu]:\n", get_x(), get_y()); VTR_LOG_DEBUG("----------------------------------\n"); VTR_LOG_DEBUG("SRC node:\n"); diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp index 9980bb402d2..541a0b76b72 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_gsb.cpp @@ -1726,7 +1726,7 @@ void build_direct_connections_for_one_gsb(const RRGraphView& rr_graph, if ((to_grid_coordinate.x() < grids.width() - 1) && (to_grid_coordinate.y() < grids.height() - 1)) { - int ipin = OPEN; + int ipin = UNDEFINED; if (clb_to_clb_directs[i].to_clb_pin_start_index > clb_to_clb_directs[i].to_clb_pin_end_index) { if (true == swap) { diff --git a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp index c8ed6bbf7cf..45a631b254a 100644 --- a/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp +++ b/vpr/src/route/rr_graph_generation/tileable_rr_graph/tileable_rr_graph_node_builder.cpp @@ -51,19 +51,19 @@ static size_t estimate_num_grid_rr_nodes_by_type(const DeviceGrid& grids, switch (node_type) { case e_rr_type::OPIN: // get the number of OPINs - num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, DRIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, e_pin_type::DRIVER, io_side); break; case e_rr_type::IPIN: // get the number of IPINs - num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, RECEIVER, io_side); + num_grid_rr_nodes += get_grid_num_pins(grids, layer, ix, iy, e_pin_type::RECEIVER, io_side); break; case e_rr_type::SOURCE: // SOURCE: number of classes whose type is DRIVER - num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, DRIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, e_pin_type::DRIVER); break; case e_rr_type::SINK: // SINK: number of classes whose type is RECEIVER - num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, RECEIVER); + num_grid_rr_nodes += get_grid_num_classes(grids, layer, ix, iy, e_pin_type::RECEIVER); break; default: VPR_FATAL_ERROR(VPR_ERROR_ROUTE, @@ -463,7 +463,7 @@ static void load_one_grid_opin_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager side_manager(side); // Find OPINs // Configure pins by pins - std::vector opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), DRIVER, side_manager.get_side(), + std::vector opin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), e_pin_type::DRIVER, side_manager.get_side(), width, height); for (const int& pin_num : opin_list) { // Create a new node and fill information @@ -517,7 +517,7 @@ static void load_one_grid_ipin_nodes_basic_info(RRGraphBuilder& rr_graph_builder SideManager side_manager(side); // Find IPINs // Configure pins by pins - std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), RECEIVER, side_manager.get_side(), width, height); + std::vector ipin_list = get_grid_side_pins(grids, layer, grid_coordinate.x(), grid_coordinate.y(), e_pin_type::RECEIVER, side_manager.get_side(), width, height); for (const int& pin_num : ipin_list) { // Create a new node and fill information RRNodeId node = rr_graph_builder.create_node(layer, grid_coordinate.x() + width, grid_coordinate.y() + height, e_rr_type::IPIN, pin_num, side); @@ -564,7 +564,7 @@ static void load_one_grid_source_nodes_basic_info(RRGraphBuilder& rr_graph_build t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { // Set a SINK rr_node for the OPIN - if (DRIVER != phy_tile_type->class_inf[iclass].type) { + if (e_pin_type::DRIVER != phy_tile_type->class_inf[iclass].type) { continue; } @@ -610,7 +610,7 @@ static void load_one_grid_sink_nodes_basic_info(RRGraphBuilder& rr_graph_builder t_physical_tile_type_ptr phy_tile_type = grids.get_physical_type(tile_loc); for (size_t iclass = 0; iclass < phy_tile_type->class_inf.size(); ++iclass) { // Set a SINK rr_node for the OPIN - if (RECEIVER != phy_tile_type->class_inf[iclass].type) { + if (e_pin_type::RECEIVER != phy_tile_type->class_inf[iclass].type) { continue; } diff --git a/vpr/src/timing/PreClusterTimingManager.cpp b/vpr/src/timing/PreClusterTimingManager.cpp index d1f7d44b77a..d7f78c1150b 100644 --- a/vpr/src/timing/PreClusterTimingManager.cpp +++ b/vpr/src/timing/PreClusterTimingManager.cpp @@ -221,10 +221,10 @@ static void get_intercluster_switch_fanin_estimates(const t_arch& arch, for (int ipin : fc_spec.pins) { e_pin_type pin_type = get_pin_type_from_pin_physical_num(type, ipin); - if (pin_type == DRIVER) { + if (pin_type == e_pin_type::DRIVER) { Fc_out = std::max(Fc, Fc_out); } else { - VTR_ASSERT(pin_type == RECEIVER); + VTR_ASSERT(pin_type == e_pin_type::RECEIVER); Fc_in = std::max(Fc, Fc_in); } } diff --git a/vpr/src/timing/net_delay.cpp b/vpr/src/timing/net_delay.cpp index 1f2b9bd509a..9b698d351ea 100644 --- a/vpr/src/timing/net_delay.cpp +++ b/vpr/src/timing/net_delay.cpp @@ -91,7 +91,7 @@ static void load_one_net_delay(const Netlist<>& net_list, static void load_one_net_delay_recurr(const RouteTreeNode& rt_node, ParentNetId net_id) { /* This routine recursively traverses the route tree, and copies the Tdel of the sink_type nodes * * into the map. */ - if (rt_node.net_pin_index != OPEN) { // value of OPEN indicates a non-SINK + if (rt_node.net_pin_index != UNDEFINED) { // value of UNDEFINED indicates a non-SINK ipin_to_Tdel_map[rt_node.net_pin_index] = rt_node.Tdel; // add to the map, process current sink-type node } diff --git a/vpr/src/util/vpr_utils.cpp b/vpr/src/util/vpr_utils.cpp index 7c3eb18846f..7d868de81f0 100644 --- a/vpr/src/util/vpr_utils.cpp +++ b/vpr/src/util/vpr_utils.cpp @@ -4,6 +4,7 @@ #include #include "pack_types.h" +#include "vpr_types.h" #include "physical_types_util.h" #include "vpr_context.h" #include "vtr_assert.h" @@ -665,7 +666,7 @@ InstPort parse_inst_port(const std::string& str) { int num_pins = find_tile_port_by_name(blk_type, inst_port.port_name()).num_pins; - if (num_pins == OPEN) { + if (num_pins == UNDEFINED) { VPR_FATAL_ERROR(VPR_ERROR_ARCH, "Failed to find port %s on block type %s", inst_port.port_name().c_str(), inst_port.instance_name().c_str()); } @@ -1700,7 +1701,7 @@ RRNodeId get_class_rr_node_id(const RRSpatialLookup& rr_spatial_lookup, const int j, int class_physical_num) { auto class_type = get_class_type_from_class_physical_num(physical_tile, class_physical_num); - VTR_ASSERT(class_type == DRIVER || class_type == RECEIVER); + VTR_ASSERT(class_type == e_pin_type::DRIVER || class_type == e_pin_type::RECEIVER); e_rr_type node_type = (class_type == e_pin_type::DRIVER) ? e_rr_type::SOURCE : e_rr_type::SINK; return rr_spatial_lookup.find_node(layer, i, j, node_type, class_physical_num); } @@ -1901,7 +1902,7 @@ std::vector get_cluster_netlist_intra_tile_pins_at_loc(const int layer, if (it == cluster_pin_chains.end()) { pin_num_vec.push_back(pin); } else { - VTR_ASSERT(cluster_pin_chain_idx[pin] != OPEN); + VTR_ASSERT(cluster_pin_chain_idx[pin] != UNDEFINED); if (is_pin_on_tile(physical_type, pin) || is_primitive_pin(physical_type, pin) || cluster_chain_sinks[cluster_pin_chain_idx[pin]] == pin) { pin_num_vec.push_back(pin); } From 80644f451c7ac7e7d48843882240f3f9e6e7baf0 Mon Sep 17 00:00:00 2001 From: Amir Poolad Date: Mon, 25 Aug 2025 15:32:28 -0400 Subject: [PATCH 2/2] Add comment for vpr UNDEFINED --- vpr/src/base/vpr_types.h | 1 + 1 file changed, 1 insertion(+) diff --git a/vpr/src/base/vpr_types.h b/vpr/src/base/vpr_types.h index 54d2c8f93fb..fe08be0b365 100644 --- a/vpr/src/base/vpr_types.h +++ b/vpr/src/base/vpr_types.h @@ -94,6 +94,7 @@ constexpr bool VTR_ENABLE_DEBUG_LOGGING_CONST_EXPR = false; #define NOT_VALID (-10000) /* Marks gains that aren't valid */ /* Ensure no gain can ever be this negative! */ +// Used for illegal/undefined values of indices, where legal values should be greater or equal to zero constexpr int UNDEFINED = -1; ///@brief Router lookahead types.