Hands-on exercises for the Computer Architecture course at the School of Computer Science, University of Las Palmas de Gran Canaria (Spain) using Nios V-based soft SoCs and DE0-Nano board
Source code for lab exercises.
Lab 1. RISC-V instruction set architecture and programming of NiosV/m processor
Lab 2. Performance evaluation of the memory hierarchy of a computer and reverse engineering of the data cache memory
Lab 3. Performance evaluation of pipelined processors
Lab 4. Nios V multiprocessor implementation, parallel programming, and performance evaluation
Lab 5. Nios V processor with customized architecture for a software application
Laboratory infrastructure - hardware:
- Terasic DE0-Nano board
- Desktop computer
- USB-A - miniUSB cable
Laboratory infrastructure - software:
- Windows 10
- Nios V Command Shell 23.1 Standard