From 8dd5352e0b958d950dd40dc2effca44f25b2e432 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Thu, 5 Feb 2026 17:14:50 +0000
Subject: [PATCH 1/9] dialects: (riscv) add riscv32 and riscv64 load immediate
 instruction

---
 xdsl/dialects/__init__.py |  12 ++++
 xdsl/dialects/rv32.py     | 117 ++++++++++++++++++++++++++++++++++++++
 xdsl/dialects/rv64.py     | 117 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 246 insertions(+)
 create mode 100644 xdsl/dialects/rv32.py
 create mode 100644 xdsl/dialects/rv64.py

diff --git a/xdsl/dialects/__init__.py b/xdsl/dialects/__init__.py
index 21a948c573..56acee35e7 100644
--- a/xdsl/dialects/__init__.py
+++ b/xdsl/dialects/__init__.py
@@ -253,6 +253,16 @@ def get_riscv():
 
         return RISCV
 
+    def get_RV32():
+        from xdsl.dialects.rv32 import RV32
+
+        return RV32
+
+    def get_RV64():
+        from xdsl.dialects.rv64 import RV64
+
+        return RV64
+
     def get_riscv_func():
         from xdsl.dialects.riscv_func import RISCV_Func
 
@@ -417,6 +427,8 @@ def get_transform():
         "printf": get_printf,
         "ptr_xdsl": get_ptr_xdsl,
         "riscv": get_riscv,
+        "rv32": get_RV32,
+        "rv64": get_RV64,
         "riscv_debug": get_riscv_debug,
         "riscv_func": get_riscv_func,
         "riscv_scf": get_riscv_scf,
diff --git a/xdsl/dialects/rv32.py b/xdsl/dialects/rv32.py
new file mode 100644
index 0000000000..aa7fe5142e
--- /dev/null
+++ b/xdsl/dialects/rv32.py
@@ -0,0 +1,117 @@
+"""
+RISC-V 32-bit (RV32) dialect operations and types.
+
+This module defines the RV32-specific variant of RISC-V operations,
+using 5-bit shift immediates for 32-bit architectures.
+"""
+
+from __future__ import annotations
+
+from abc import ABC
+from collections.abc import Sequence
+from collections.abc import Set as AbstractSet
+
+from xdsl.dialects.builtin import I32, IntegerAttr, StringAttr, i32
+from xdsl.dialects.riscv import (
+    AssemblyInstructionArg,
+    IntRegisterType,
+    LabelAttr,
+    LiOpHasCanonicalizationPatternTrait,
+    Registers,
+    RISCVCustomFormatOperation,
+    RISCVInstruction,
+    parse_immediate_value,
+    print_immediate_value,
+)
+from xdsl.interfaces import ConstantLikeInterface
+from xdsl.ir import (
+    Attribute,
+    Dialect,
+)
+from xdsl.irdl import (
+    attr_def,
+    irdl_op_definition,
+    result_def,
+    traits_def,
+)
+from xdsl.parser import Parser
+from xdsl.printer import Printer
+from xdsl.traits import (
+    Pure,
+)
+
+
+@irdl_op_definition
+class LiOp(RISCVCustomFormatOperation, RISCVInstruction, ConstantLikeInterface, ABC):
+    """
+    Loads a 32-bit immediate into rd.
+
+    This is an assembler pseudo-instruction.
+
+    See external [documentation](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc).
+    """
+
+    name = "rv32.li"
+
+    rd = result_def(IntRegisterType)
+    immediate = attr_def(IntegerAttr[I32] | LabelAttr)
+
+    traits = traits_def(Pure(), LiOpHasCanonicalizationPatternTrait())
+
+    def __init__(
+        self,
+        immediate: int | IntegerAttr[I32] | str | LabelAttr,
+        *,
+        rd: IntRegisterType = Registers.UNALLOCATED_INT,
+        comment: str | StringAttr | None = None,
+    ):
+        if isinstance(immediate, int):
+            immediate = IntegerAttr(immediate, i32)
+        elif isinstance(immediate, str):
+            immediate = LabelAttr(immediate)
+        if isinstance(comment, str):
+            comment = StringAttr(comment)
+
+        super().__init__(
+            result_types=[rd],
+            attributes={
+                "immediate": immediate,
+                "comment": comment,
+            },
+        )
+
+    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
+        return self.rd, self.immediate
+
+    def get_constant_value(self):
+        return self.immediate
+
+    @classmethod
+    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
+        attributes = dict[str, Attribute]()
+        attributes["immediate"] = parse_immediate_value(parser, i32)
+        return attributes
+
+    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
+        printer.print_string(" ")
+        print_immediate_value(printer, self.immediate)
+        return {"immediate", "fastmath"}
+
+    @classmethod
+    def parse_op_type(
+        cls, parser: Parser
+    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
+        parser.parse_punctuation(":")
+        res_type = parser.parse_attribute()
+        return (), (res_type,)
+
+    def print_op_type(self, printer: Printer) -> None:
+        printer.print_string(" : ")
+        printer.print_attribute(self.rd.type)
+
+
+RV32 = Dialect(
+    "rv32",
+    [LiOp],
+    [],
+)
diff --git a/xdsl/dialects/rv64.py b/xdsl/dialects/rv64.py
new file mode 100644
index 0000000000..a6d5c6203f
--- /dev/null
+++ b/xdsl/dialects/rv64.py
@@ -0,0 +1,117 @@
+"""
+RISC-V 32-bit (RV32) dialect operations and types.
+
+This module defines the RV32-specific variant of RISC-V operations,
+using 5-bit shift immediates for 32-bit architectures.
+"""
+
+from __future__ import annotations
+
+from abc import ABC
+from collections.abc import Sequence
+from collections.abc import Set as AbstractSet
+
+from xdsl.dialects.builtin import I64, IntegerAttr, StringAttr, i64
+from xdsl.dialects.riscv import (
+    AssemblyInstructionArg,
+    IntRegisterType,
+    LabelAttr,
+    LiOpHasCanonicalizationPatternTrait,
+    Registers,
+    RISCVCustomFormatOperation,
+    RISCVInstruction,
+    parse_immediate_value,
+    print_immediate_value,
+)
+from xdsl.interfaces import ConstantLikeInterface
+from xdsl.ir import (
+    Attribute,
+    Dialect,
+)
+from xdsl.irdl import (
+    attr_def,
+    irdl_op_definition,
+    result_def,
+    traits_def,
+)
+from xdsl.parser import Parser
+from xdsl.printer import Printer
+from xdsl.traits import (
+    Pure,
+)
+
+
+@irdl_op_definition
+class LiOp(RISCVCustomFormatOperation, RISCVInstruction, ConstantLikeInterface, ABC):
+    """
+    Loads a 64-bit immediate into rd.
+
+    This is an assembler pseudo-instruction.
+
+    See external [documentation](https://github.com/riscv-non-isa/riscv-asm-manual/blob/main/src/asm-manual.adoc).
+    """
+
+    name = "rv64.li"
+
+    rd = result_def(IntRegisterType)
+    immediate = attr_def(IntegerAttr[I64] | LabelAttr)
+
+    traits = traits_def(Pure(), LiOpHasCanonicalizationPatternTrait())
+
+    def __init__(
+        self,
+        immediate: int | IntegerAttr[I64] | str | LabelAttr,
+        *,
+        rd: IntRegisterType = Registers.UNALLOCATED_INT,
+        comment: str | StringAttr | None = None,
+    ):
+        if isinstance(immediate, int):
+            immediate = IntegerAttr(immediate, i64)
+        elif isinstance(immediate, str):
+            immediate = LabelAttr(immediate)
+        if isinstance(comment, str):
+            comment = StringAttr(comment)
+
+        super().__init__(
+            result_types=[rd],
+            attributes={
+                "immediate": immediate,
+                "comment": comment,
+            },
+        )
+
+    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
+        return self.rd, self.immediate
+
+    def get_constant_value(self):
+        return self.immediate
+
+    @classmethod
+    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
+        attributes = dict[str, Attribute]()
+        attributes["immediate"] = parse_immediate_value(parser, i64)
+        return attributes
+
+    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
+        printer.print_string(" ")
+        print_immediate_value(printer, self.immediate)
+        return {"immediate", "fastmath"}
+
+    @classmethod
+    def parse_op_type(
+        cls, parser: Parser
+    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
+        parser.parse_punctuation(":")
+        res_type = parser.parse_attribute()
+        return (), (res_type,)
+
+    def print_op_type(self, printer: Printer) -> None:
+        printer.print_string(" : ")
+        printer.print_attribute(self.rd.type)
+
+
+RV64 = Dialect(
+    "rv64",
+    [LiOp],
+    [],
+)

From 00f30358e1aac8ebe74165672670a96b7867c909 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Thu, 5 Feb 2026 17:17:26 +0000
Subject: [PATCH 2/9] comments

---
 xdsl/dialects/rv32.py | 2 +-
 xdsl/dialects/rv64.py | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/xdsl/dialects/rv32.py b/xdsl/dialects/rv32.py
index aa7fe5142e..9322f60034 100644
--- a/xdsl/dialects/rv32.py
+++ b/xdsl/dialects/rv32.py
@@ -2,7 +2,7 @@
 RISC-V 32-bit (RV32) dialect operations and types.
 
 This module defines the RV32-specific variant of RISC-V operations,
-using 5-bit shift immediates for 32-bit architectures.
+using 5-bit immediates for 32-bit architectures.
 """
 
 from __future__ import annotations
diff --git a/xdsl/dialects/rv64.py b/xdsl/dialects/rv64.py
index a6d5c6203f..1ea5a3d1ad 100644
--- a/xdsl/dialects/rv64.py
+++ b/xdsl/dialects/rv64.py
@@ -1,8 +1,8 @@
 """
-RISC-V 32-bit (RV32) dialect operations and types.
+RISC-V 64-bit (RV64) dialect operations and types.
 
-This module defines the RV32-specific variant of RISC-V operations,
-using 5-bit shift immediates for 32-bit architectures.
+This module defines the RV64-specific variant of RISC-V operations,
+using 6-bit immediates for 64-bit architectures.
 """
 
 from __future__ import annotations

From 42f4e42c3a3b456931f6d470a98ee3980bca6dcb Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Fri, 6 Feb 2026 15:39:11 +0000
Subject: [PATCH 3/9] remove LiOp from riscv, fix tests

---
 docs/marimo/riscv_dialects.py                 |  22 ++--
 tests/dialects/test_riscv.py                  |  12 +-
 .../convert_riscv_scf_to_riscv_cf.mlir        |  40 +++---
 ...t_riscv_scf_to_riscv_cf_with_regalloc.mlir |   8 +-
 .../filecheck/backend/riscv/canonicalize.mlir |  44 +++----
 .../backend/riscv/convert_arith_to_riscv.mlir |  22 ++--
 .../riscv/convert_riscv_scf_for_to_frep.mlir  |   4 +-
 .../backend/riscv/memref_to_riscv.mlir        |  62 ++++-----
 .../backend/riscv/memref_to_riscv_opt.mlir    |   4 +-
 .../riscv/prologue_epilogue_insertion.mlir    |   2 +-
 .../riscv/register-allocation/frep.mlir       |   8 +-
 .../riscv/register-allocation/generic.mlir    |  20 +--
 .../liveness_block_naive.mlir                 | 124 +++++++++---------
 .../register-allocation/preallocated.mlir     |   8 +-
 .../backend/rvscf_lowering_labels.mlir        |  36 ++---
 .../riscv/riscv_assembly_emission.mlir        |   8 +-
 tests/filecheck/dialects/riscv/riscv_ops.mlir |  18 +--
 .../dialects/riscv_cf/canonicalize.mlir       |  14 +-
 .../dialects/riscv_func/lower_riscv_func.mlir |  12 +-
 .../riscv_func/lower_riscv_func_main.mlir     |   2 +-
 .../riscv_scf/loop_range_folding.mlir         |  20 +--
 tests/filecheck/dialects/riscv_scf/ops.mlir   |  16 +--
 .../dialects/riscv_scf/verification.mlir      |   8 +-
 .../snitch/snitch_to_riscv_lowering.mlir      |  24 ++--
 .../convert_snitch_stream_to_snitch.mlir      |  48 +++----
 .../filecheck/dialects/snitch_stream/ops.mlir |   6 +-
 .../dialects/x86_scf/x86_scf_invalid.mlir     |   8 +-
 .../add_snitch_stream.mlir                    |   8 +-
 .../riscv-backend-paper/bottom_up_f32.mlir    |   6 +-
 .../riscv-backend-paper/ddot_regalloc.mlir    |  12 +-
 .../relu_snitch_stream.mlir                   |  10 +-
 tests/filecheck/runner/riscv.mlir             |   4 +-
 tests/filecheck/runner/riscv_scf.mlir         |   8 +-
 .../transforms/convert_riscv_to_llvm.mlir     |   8 +-
 .../transforms/individual_rewrite/riscv.mlir  |  14 +-
 .../riscv-allocate-infinite-registers.mlir    |  12 +-
 tests/filecheck/transforms/riscv_cse.mlir     |  46 +++----
 .../transforms/snitch-allocate-registers.mlir |   4 +-
 .../with-riscemu/riscv_emulation.mlir         |  20 +--
 .../with-riscemu/rvscf_lowering_emu.mlir      |  10 +-
 tests/interactive/test_app.py                 |   2 +-
 tests/interactive/test_pass_metrics.py        |   4 +-
 tests/interpreters/test_riscv_emulator.py     |  14 +-
 tests/interpreters/test_riscv_interpreter.py  |   6 +-
 .../test_riscv_scf_interpreter.py             |  14 +-
 .../test_riscv_snitch_interpreter.py          |   4 +-
 .../test_snitch_stream_interpreter.py         |   4 +-
 .../riscv/lowering/convert_arith_to_riscv.py  |  18 +--
 .../riscv/lowering/convert_memref_to_riscv.py |  12 +-
 .../convert_snitch_stream_to_snitch.py        |   9 +-
 xdsl/dialects/riscv/__init__.py               |   2 -
 xdsl/dialects/riscv/ops.py                    |  74 -----------
 xdsl/dialects/rv32.py                         |   2 +-
 xdsl/dialects/rv64.py                         |   2 +-
 xdsl/interpreters/__init__.py                 |   4 +
 xdsl/interpreters/riscv.py                    |  10 --
 xdsl/interpreters/rv32.py                     |  25 ++++
 xdsl/interpreters/rv64.py                     |  25 ++++
 .../canonicalization_patterns/riscv.py        |  42 +++---
 .../convert_riscv_scf_for_to_frep.py          |   4 +-
 xdsl/transforms/lower_riscv_func.py           |   4 +-
 xdsl/transforms/lower_snitch.py               |   4 +-
 .../riscv_scf_loop_range_folding.py           |   6 +-
 63 files changed, 509 insertions(+), 544 deletions(-)
 create mode 100644 xdsl/interpreters/rv32.py
 create mode 100644 xdsl/interpreters/rv64.py

diff --git a/docs/marimo/riscv_dialects.py b/docs/marimo/riscv_dialects.py
index 1e6858d716..65cb15abea 100644
--- a/docs/marimo/riscv_dialects.py
+++ b/docs/marimo/riscv_dialects.py
@@ -438,23 +438,23 @@ def _(mo):
       %zero = riscv.get_register : !riscv.reg<zero>
       riscv_cf.bge %zero: !riscv.reg<zero>, %num :!riscv.reg<a0>, ^bb4(), ^bb1()
     ^bb1():
-      %a_init = riscv.li 1 : !riscv.reg<a2>
-      %b_init = riscv.li 1 : !riscv.reg<a3>
+      %a_init = rv32.li 1 : !riscv.reg<a2>
+      %b_init = rv32.li 1 : !riscv.reg<a3>
       riscv_cf.branch ^bb2 (%num : !riscv.reg<a0>, %a_init : !riscv.reg<a2>, %b_init : !riscv.reg<a3>)
     ^bb2(%i : !riscv.reg<a0>, %a_in : !riscv.reg<a2>, %b_in : !riscv.reg<a3>):
       riscv.label ".LBB1_2"
-      %sum = riscv.li 2 : !riscv.reg<a4>
-      %i_next = riscv.li 3 : !riscv.reg<a0>
-      %temp = riscv.li 4 : !riscv.reg<a1>
-      %a_next = riscv.li 5 : !riscv.reg<a2>
-      %b_next = riscv.li 6 : !riscv.reg<a3>
+      %sum = rv32.li 2 : !riscv.reg<a4>
+      %i_next = rv32.li 3 : !riscv.reg<a0>
+      %temp = rv32.li 4 : !riscv.reg<a1>
+      %a_next = rv32.li 5 : !riscv.reg<a2>
+      %b_next = rv32.li 6 : !riscv.reg<a3>
       riscv_cf.bne %zero: !riscv.reg<zero>, %i_next : !riscv.reg<a0>, ^bb2(%i_next : !riscv.reg<a0>, %a_next : !riscv.reg<a2>, %b_next : !riscv.reg<a3>), ^bb3()
     ^bb3():
       %res = riscv.mv %temp : (!riscv.reg<a1>) -> !riscv.reg<a0>
       riscv_func.return %num : !riscv.reg<a0>
     ^bb4():
       riscv.label ".LBB1_4"
-      %res_early = riscv.li 1 : !riscv.reg<a0>
+      %res_early = rv32.li 1 : !riscv.reg<a0>
       riscv_func.return %res_early : !riscv.reg<a0>
     }""", language="javascript")
     return (fib_editor,)
@@ -504,8 +504,8 @@ def _():
       %zero = riscv.get_register : !riscv.reg<zero>
       riscv_cf.bge %zero: !riscv.reg<zero>, %num :!riscv.reg<a0>, ^bb4(), ^bb1()
     ^bb1():
-      %a_init = riscv.li 1 : !riscv.reg<a2>
-      %b_init = riscv.li 1 : !riscv.reg<a3>
+      %a_init = rv32.li 1 : !riscv.reg<a2>
+      %b_init = rv32.li 1 : !riscv.reg<a3>
       riscv_cf.branch ^bb2 (%num : !riscv.reg<a0>, %a_init : !riscv.reg<a2>, %b_init : !riscv.reg<a3>)
     ^bb2(%i : !riscv.reg<a0>, %a_in : !riscv.reg<a2>, %b_in : !riscv.reg<a3>):
       riscv.label ".LBB1_2"
@@ -520,7 +520,7 @@ def _():
       riscv_func.return %num : !riscv.reg<a0>
     ^bb4():
       riscv.label ".LBB1_4"
-      %res_early = riscv.li 1 : !riscv.reg<a0>
+      %res_early = rv32.li 1 : !riscv.reg<a0>
       riscv_func.return %res_early : !riscv.reg<a0>
     }
     """
diff --git a/tests/dialects/test_riscv.py b/tests/dialects/test_riscv.py
index d2075a3049..9e2c0fafea 100644
--- a/tests/dialects/test_riscv.py
+++ b/tests/dialects/test_riscv.py
@@ -1,7 +1,7 @@
 import pytest
 
 from xdsl.context import Context
-from xdsl.dialects import riscv
+from xdsl.dialects import riscv, rv32
 from xdsl.dialects.builtin import (
     IntAttr,
     IntegerAttr,
@@ -217,13 +217,13 @@ def test_immediate_pseudo_inst():
 
     # Pseudo-Instruction with custom handling
     with pytest.raises(VerifyException):
-        riscv.LiOp(ub, rd=riscv.Registers.A0)
+        rv32.LiOp(ub, rd=riscv.Registers.A0)
 
     with pytest.raises(VerifyException):
-        riscv.LiOp(lb - 1, rd=riscv.Registers.A0)
+        rv32.LiOp(lb - 1, rd=riscv.Registers.A0)
 
-    riscv.LiOp(ub - 1, rd=riscv.Registers.A0)
-    riscv.LiOp(lb, rd=riscv.Registers.A0)
+    rv32.LiOp(ub - 1, rd=riscv.Registers.A0)
+    rv32.LiOp(lb, rd=riscv.Registers.A0)
 
 
 def test_immediate_shift_inst():
@@ -275,7 +275,7 @@ def test_asm_section():
 
 
 def test_get_constant_value():
-    li_op = riscv.LiOp(1)
+    li_op = rv32.LiOp(1)
     li_val = get_constant_value(li_op.rd)
     assert li_val == IntegerAttr.from_int_and_width(1, 32)
     # LiOp implements ConstantLikeInterface so it also has a get_constant_value method:
diff --git a/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf.mlir b/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf.mlir
index 5e712d33c3..920b3d6a54 100644
--- a/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf.mlir
+++ b/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf.mlir
@@ -3,9 +3,9 @@
 
 builtin.module {
     riscv_func.func @copy10(%src : !riscv.reg<a0>, %dst : !riscv.reg<a1>) {
-        %zero = riscv.li 0 : !riscv.reg<a2>
-        %step = riscv.li 4 : !riscv.reg<a3>
-        %forty = riscv.li 40 : !riscv.reg<a4>
+        %zero = rv32.li 0 : !riscv.reg<a2>
+        %step = rv32.li 4 : !riscv.reg<a3>
+        %forty = rv32.li 40 : !riscv.reg<a4>
         riscv_scf.for %offset : !riscv.reg<a5> = %zero to %forty step %step {
             %srcptr = riscv.add %src, %offset : (!riscv.reg<a0>, !riscv.reg<a5>) -> !riscv.reg<a6>
             %dstptr = riscv.add %dst, %offset : (!riscv.reg<a1>, !riscv.reg<a5>) -> !riscv.reg<a7>
@@ -19,9 +19,9 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @copy10(%src : !riscv.reg<a0>, %dst : !riscv.reg<a1>) {
-// CHECK-NEXT:      %zero = riscv.li 0 : !riscv.reg<a2>
-// CHECK-NEXT:      %step = riscv.li 4 : !riscv.reg<a3>
-// CHECK-NEXT:      %forty = riscv.li 40 : !riscv.reg<a4>
+// CHECK-NEXT:      %zero = rv32.li 0 : !riscv.reg<a2>
+// CHECK-NEXT:      %step = rv32.li 4 : !riscv.reg<a3>
+// CHECK-NEXT:      %forty = rv32.li 40 : !riscv.reg<a4>
 // CHECK-NEXT:      %0 = riscv.mv %zero : (!riscv.reg<a2>) -> !riscv.reg<a5>
 // CHECK-NEXT:      riscv_cf.bge %0 : !riscv.reg<a5>, %forty : !riscv.reg<a4>, ^bb0(%0 : !riscv.reg<a5>), ^bb1(%0 : !riscv.reg<a5>)
 // CHECK-NEXT:    ^bb1(%offset : !riscv.reg<a5>):
@@ -45,8 +45,8 @@ builtin.module {
 
 builtin.module {
     riscv_func.func @sum_range(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-        %2 = riscv.li 1 : !riscv.reg<a2>
-        %3 = riscv.li 0 : !riscv.reg<a3>
+        %2 = rv32.li 1 : !riscv.reg<a2>
+        %3 = rv32.li 0 : !riscv.reg<a3>
         %4 = riscv_scf.for %5 : !riscv.reg<a4> = %0 to %1 step %2 iter_args(%6 = %3) -> (!riscv.reg<a3>) {
             %7 = riscv.add %5, %6 : (!riscv.reg<a4>, !riscv.reg<a3>) -> !riscv.reg<a3>
             riscv_scf.yield %7 : !riscv.reg<a3>
@@ -58,8 +58,8 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @sum_range(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<a2>
-// CHECK-NEXT:      %3 = riscv.li 0 : !riscv.reg<a3>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<a2>
+// CHECK-NEXT:      %3 = rv32.li 0 : !riscv.reg<a3>
 // CHECK-NEXT:      %4 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<a4>
 // CHECK-NEXT:      riscv_cf.bge %4 : !riscv.reg<a4>, %1 : !riscv.reg<a1>, ^bb0(%4 : !riscv.reg<a4>, %3 : !riscv.reg<a3>), ^bb1(%4 : !riscv.reg<a4>, %3 : !riscv.reg<a3>)
 // CHECK-NEXT:    ^bb1(%5 : !riscv.reg<a4>, %6 : !riscv.reg<a3>):
@@ -78,12 +78,12 @@ builtin.module {
 
 builtin.module {
     riscv_func.func @nested(%arg0 : !riscv.reg<a0>) {
-        %0 = riscv.li 0 : !riscv.reg<a1>
-        %1 = riscv.li 0 : !riscv.reg<a2>
-        %2 = riscv.li 1 : !riscv.reg<a3>
+        %0 = rv32.li 0 : !riscv.reg<a1>
+        %1 = rv32.li 0 : !riscv.reg<a2>
+        %2 = rv32.li 1 : !riscv.reg<a3>
         %3 = riscv_scf.for %arg1 : !riscv.reg<a2> = %1 to %arg0 step %2 iter_args(%arg2 = %0) -> (!riscv.reg<a1>) {
-            %4 = riscv.li 0 : !riscv.reg<a4>
-            %5 = riscv.li 1 : !riscv.reg<a5>
+            %4 = rv32.li 0 : !riscv.reg<a4>
+            %5 = rv32.li 1 : !riscv.reg<a5>
             %6 = riscv_scf.for %arg3 : !riscv.reg<a4> = %4 to %arg0 step %5 iter_args(%arg4 = %arg2) -> (!riscv.reg<a1>) {
                 %7 = riscv.add %arg1, %arg3 : (!riscv.reg<a2>, !riscv.reg<a4>) -> !riscv.reg<a0>
                 %8 = riscv.add %arg4, %7 : (!riscv.reg<a1>, !riscv.reg<a0>) -> !riscv.reg<a1>
@@ -97,15 +97,15 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @nested(%arg0 : !riscv.reg<a0>) {
-// CHECK-NEXT:      %0 = riscv.li 0 : !riscv.reg<a1>
-// CHECK-NEXT:      %1 = riscv.li 0 : !riscv.reg<a2>
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<a3>
+// CHECK-NEXT:      %0 = rv32.li 0 : !riscv.reg<a1>
+// CHECK-NEXT:      %1 = rv32.li 0 : !riscv.reg<a2>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<a3>
 // CHECK-NEXT:      %3 = riscv.mv %1 : (!riscv.reg<a2>) -> !riscv.reg<a2>
 // CHECK-NEXT:      riscv_cf.bge %3 : !riscv.reg<a2>, %arg0 : !riscv.reg<a0>, ^bb0(%3 : !riscv.reg<a2>, %0 : !riscv.reg<a1>), ^bb1(%3 : !riscv.reg<a2>, %0 : !riscv.reg<a1>)
 // CHECK-NEXT:    ^bb1(%arg1 : !riscv.reg<a2>, %arg2 : !riscv.reg<a1>):
 // CHECK-NEXT:      riscv.label "scf_body_1_for"
-// CHECK-NEXT:      %4 = riscv.li 0 : !riscv.reg<a4>
-// CHECK-NEXT:      %5 = riscv.li 1 : !riscv.reg<a5>
+// CHECK-NEXT:      %4 = rv32.li 0 : !riscv.reg<a4>
+// CHECK-NEXT:      %5 = rv32.li 1 : !riscv.reg<a5>
 // CHECK-NEXT:      %6 = riscv.mv %4 : (!riscv.reg<a4>) -> !riscv.reg<a4>
 // CHECK-NEXT:      riscv_cf.bge %6 : !riscv.reg<a4>, %arg0 : !riscv.reg<a0>, ^bb2(%6 : !riscv.reg<a4>, %arg2 : !riscv.reg<a1>), ^bb3(%6 : !riscv.reg<a4>, %arg2 : !riscv.reg<a1>)
 // CHECK-NEXT:    ^bb3(%arg3 : !riscv.reg<a4>, %arg4 : !riscv.reg<a1>):
diff --git a/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf_with_regalloc.mlir b/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf_with_regalloc.mlir
index 57d69e0eff..06b3d1b1af 100644
--- a/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf_with_regalloc.mlir
+++ b/tests/filecheck/backend/convert_riscv_scf_to_riscv_cf_with_regalloc.mlir
@@ -2,8 +2,8 @@
 
 builtin.module {
     riscv_func.func @sum_range(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-        %2 = riscv.li 1 : !riscv.reg
-        %3 = riscv.li 0 : !riscv.reg
+        %2 = rv32.li 1 : !riscv.reg
+        %3 = rv32.li 0 : !riscv.reg
         %arg = riscv.mv %3 : (!riscv.reg) -> !riscv.reg
         %4 = riscv_scf.for %5 : !riscv.reg = %0 to %1 step %2 iter_args(%6 = %arg) -> (!riscv.reg) {
             %7 = riscv.add %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg
@@ -16,8 +16,8 @@ builtin.module {
 
 // CHECK:        builtin.module {
 // CHECK-NEXT:    riscv_func.func @sum_range(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<t2>
-// CHECK-NEXT:      %3 = riscv.li 0 : !riscv.reg<zero>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<t2>
+// CHECK-NEXT:      %3 = rv32.li 0 : !riscv.reg<zero>
 // CHECK-NEXT:      %arg = riscv.mv %3 : (!riscv.reg<zero>) -> !riscv.reg<t0>
 // CHECK-NEXT:      %4 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<t1>
 // CHECK-NEXT:      riscv_cf.bge %4 : !riscv.reg<t1>, %1 : !riscv.reg<a1>, ^bb0(%4 : !riscv.reg<t1>, %arg : !riscv.reg<t0>), ^bb1(%4 : !riscv.reg<t1>, %arg : !riscv.reg<t0>)
diff --git a/tests/filecheck/backend/riscv/canonicalize.mlir b/tests/filecheck/backend/riscv/canonicalize.mlir
index 359ea0cf38..734f73f03d 100644
--- a/tests/filecheck/backend/riscv/canonicalize.mlir
+++ b/tests/filecheck/backend/riscv/canonicalize.mlir
@@ -7,7 +7,7 @@ builtin.module {
   %o2 = riscv.mv %i2 : (!riscv.reg) -> !riscv.reg
   "test.op"(%o0, %o1, %o2) : (!riscv.reg<a0>, !riscv.reg<a2>, !riscv.reg) -> ()
 
-  %i3 = riscv.li 100 : !riscv.reg
+  %i3 = rv32.li 100 : !riscv.reg
   %i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
   %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
   "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()
@@ -22,15 +22,15 @@ builtin.module {
   "test.op"(%fo0, %fo1, %fo2, %fo3, %fo4, %fo5) : (!riscv.freg<fa0>, !riscv.freg<fa2>, !riscv.freg, !riscv.freg<fa0>, !riscv.freg<fa2>, !riscv.freg) -> ()
 
   %zero = riscv.get_register : !riscv.reg<zero>
-  %c0 = riscv.li 0 : !riscv.reg
-  %c1 = riscv.li 1 : !riscv.reg
-  %c2 = riscv.li 2 : !riscv.reg
-  %c3 = riscv.li 3 : !riscv.reg
+  %c0 = rv32.li 0 : !riscv.reg
+  %c1 = rv32.li 1 : !riscv.reg
+  %c2 = rv32.li 2 : !riscv.reg
+  %c3 = rv32.li 3 : !riscv.reg
 
   // Don't optimise out unused immediates
   "test.op"(%zero, %c0, %c1, %c2, %c3) : (!riscv.reg<zero>, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg) -> ()
 
-  %load_zero_zero = riscv.li 0 : !riscv.reg<zero>
+  %load_zero_zero = rv32.li 0 : !riscv.reg<zero>
   "test.op"(%load_zero_zero) : (!riscv.reg<zero>) -> ()
 
   %add_immediate_zero_reg = riscv.addi %zero, 1 : (!riscv.reg<zero>) -> !riscv.reg<a0>
@@ -170,7 +170,7 @@ builtin.module {
 // CHECK-NEXT:   %{{.*}} = riscv.mv %{{.*}} : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:   "test.op"(%i0, %o1, %o2) : (!riscv.reg<a0>, !riscv.reg<a2>, !riscv.reg) -> ()
 
-// CHECK-NEXT:   %i3 = riscv.li 100 : !riscv.reg
+// CHECK-NEXT:   %i3 = rv32.li 100 : !riscv.reg
 // CHECK-NEXT:   %i4 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:   %i5 = riscv.mv %i3 : (!riscv.reg) -> !riscv.reg<j_0>
 // CHECK-NEXT:   "test.op"(%i3, %i4, %i5) : (!riscv.reg, !riscv.reg, !riscv.reg<j_0>) -> ()
@@ -185,18 +185,18 @@ builtin.module {
 // CHECK-NEXT:   %zero = riscv.get_register : !riscv.reg<zero>
 // CHECK-NEXT:   %c0 = riscv.get_register : !riscv.reg<zero>
 // CHECK-NEXT:   %c0_1 = riscv.mv %c0 : (!riscv.reg<zero>) -> !riscv.reg
-// CHECK-NEXT:   %c1 = riscv.li 1 : !riscv.reg
-// CHECK-NEXT:   %c2 = riscv.li 2 : !riscv.reg
-// CHECK-NEXT:   %c3 = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:   %c1 = rv32.li 1 : !riscv.reg
+// CHECK-NEXT:   %c2 = rv32.li 2 : !riscv.reg
+// CHECK-NEXT:   %c3 = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:   "test.op"(%zero, %c0_1, %c1, %c2, %c3) : (!riscv.reg<zero>, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg) -> ()
 
 // CHECK-NEXT:   %load_zero_zero = riscv.get_register : !riscv.reg<zero>
 // CHECK-NEXT:   "test.op"(%load_zero_zero) : (!riscv.reg<zero>) -> ()
 
-// CHECK-NEXT:   %add_immediate_zero_reg = riscv.li 1 : !riscv.reg<a0>
+// CHECK-NEXT:   %add_immediate_zero_reg = rv32.li 1 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_immediate_zero_reg) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %multiply_immediates = riscv.li 6 : !riscv.reg<a0>
+// CHECK-NEXT:   %multiply_immediates = rv32.li 6 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%multiply_immediates) : (!riscv.reg<a0>) -> ()
 
 // CHECK-NEXT:   %multiply_immediate_r0 = riscv.mv %c0_1 : (!riscv.reg) -> !riscv.reg<a0>
@@ -220,7 +220,7 @@ builtin.module {
 // CHECK-NEXT:   %add_rhs_immediate = riscv.addi %i2, 2 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_rhs_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %add_immediates = riscv.li 5 : !riscv.reg<a0>
+// CHECK-NEXT:   %add_immediates = rv32.li 5 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_immediates) : (!riscv.reg<a0>) -> ()
 
 // CHECK-NEXT:   %add_vars = riscv.add %i0, %i1 : (!riscv.reg<a0>, !riscv.reg<a1>) -> !riscv.reg<a0>
@@ -229,7 +229,7 @@ builtin.module {
 // CHECK-NEXT:   %add_immediate_zero = riscv.mv %i2 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_immediate_zero) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %add_immediate_constant = riscv.li 3 : !riscv.reg<a0>
+// CHECK-NEXT:   %add_immediate_constant = rv32.li 3 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_immediate_constant) : (!riscv.reg<a0>) -> ()
 
   // Unchanged
@@ -240,7 +240,7 @@ builtin.module {
 // CHECK-NEXT:   %sub_rhs_immediate = riscv.addi %i2, -2 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%sub_rhs_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %sub_immediates = riscv.li -1 : !riscv.reg<a0>
+// CHECK-NEXT:   %sub_immediates = rv32.li -1 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%sub_immediates) : (!riscv.reg<a0>) -> ()
 
 // CHECK-NEXT:   %sub_lhs_rhs = riscv.get_register : !riscv.reg<zero>
@@ -252,16 +252,16 @@ builtin.module {
 // CHECK-NEXT:   "test.op"(%add_vars) : (!riscv.reg<a0>) -> ()
 
 // Optimise out an arithmetic operation
-// CHECK-NEXT:   %sub_add_immediate = riscv.li 2 : !riscv.reg<a0>
+// CHECK-NEXT:   %sub_add_immediate = rv32.li 2 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%sub_add_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %andi_immediate = riscv.li 4 : !riscv.reg<a0>
+// CHECK-NEXT:   %andi_immediate = rv32.li 4 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%andi_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %shift_left_immediate = riscv.li 32 : !riscv.reg<a0>
+// CHECK-NEXT:   %shift_left_immediate = rv32.li 32 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%shift_left_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %shift_right_immediate = riscv.li 4 : !riscv.reg<a0>
+// CHECK-NEXT:   %shift_right_immediate = rv32.li 4 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%shift_right_immediate) : (!riscv.reg<a0>) -> ()
 
 // CHECK-NEXT:   %load_float_known_offset = riscv.flw %i2, 12 : (!riscv.reg) -> !riscv.freg<fa0>
@@ -274,7 +274,7 @@ builtin.module {
 
 // CHECK-NEXT:   riscv.fsd %i2, %f2, 12 : (!riscv.reg, !riscv.freg) -> ()
 
-// CHECK-NEXT:   %add_lhs_rhs = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:   %add_lhs_rhs = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:   %add_lhs_rhs_1 = riscv.mul %i1, %add_lhs_rhs : (!riscv.reg<a1>, !riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%add_lhs_rhs_1) : (!riscv.reg<a0>) -> ()
 
@@ -306,10 +306,10 @@ builtin.module {
 // CHECK-NEXT:   %xor_bitwise_zero_r0 = riscv.mv %c1 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%xor_bitwise_zero_r0) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %ori_immediate = riscv.li 103 : !riscv.reg<a0>
+// CHECK-NEXT:   %ori_immediate = rv32.li 103 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%ori_immediate) : (!riscv.reg<a0>) -> ()
 
-// CHECK-NEXT:   %xori_immediate = riscv.li 99 : !riscv.reg<a0>
+// CHECK-NEXT:   %xori_immediate = rv32.li 99 : !riscv.reg<a0>
 // CHECK-NEXT:   "test.op"(%xori_immediate) : (!riscv.reg<a0>) -> ()
 
 // CHECK-NEXT:   %shift_left_zero_r0 = riscv.mv %i2 : (!riscv.reg) -> !riscv.reg<a0>
diff --git a/tests/filecheck/backend/riscv/convert_arith_to_riscv.mlir b/tests/filecheck/backend/riscv/convert_arith_to_riscv.mlir
index 527e4404c1..d2d893aac4 100644
--- a/tests/filecheck/backend/riscv/convert_arith_to_riscv.mlir
+++ b/tests/filecheck/backend/riscv/convert_arith_to_riscv.mlir
@@ -1,22 +1,22 @@
 // RUN: xdsl-opt -p convert-arith-to-riscv,reconcile-unrealized-casts %s | filecheck %s
 builtin.module {
     %lhsi32 = "arith.constant"() {value = 1 : i32} : () -> i32
-    // CHECK: %{{.*}} = riscv.li 1 : !riscv.reg
+    // CHECK: %{{.*}} = rv32.li 1 : !riscv.reg
     %rhsi32 = "arith.constant"() {value = 2 : i32} : () -> i32
-    // CHECK-NEXT: %{{.*}} = riscv.li 2 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 2 : !riscv.reg
     %lhsindex = "arith.constant"() {value = 1 : index} : () -> index
-    // CHECK-NEXT: %{{.*}} = riscv.li 1 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
     %rhsindex = "arith.constant"() {value = 2 : index} : () -> index
-    // CHECK-NEXT: %{{.*}} = riscv.li 2 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 2 : !riscv.reg
     %lhsf32 = "arith.constant"() {value = 1.000000e+00 : f32} : () -> f32
-    // CHECK-NEXT: %{{.*}} = riscv.li 1065353216 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1065353216 : !riscv.reg
     // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %lhsf32 : (!riscv.reg) -> !riscv.freg
     %rhsf32 = "arith.constant"() {value = 2.000000e+00 : f32} : () -> f32
-    // CHECK-NEXT: %{{.*}} = riscv.li 1073741824 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1073741824 : !riscv.reg
     // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %rhsf32 : (!riscv.reg) -> !riscv.freg
 
     %constf64zero = arith.constant 0.0 : f64
-    // CHECK-NEXT: %{{.*}} = riscv.li 0 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 0 : !riscv.reg
     // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %{{.*}} : (!riscv.reg) -> !riscv.freg
 
     %lhsf64_reg, %rhsf64_reg = "test.op"() : () -> (!riscv.freg, !riscv.freg)
@@ -27,9 +27,9 @@ builtin.module {
 
     %f64 = "arith.constant"() {value = 1234.5678 : f64} : () -> f64
     // CHECK-NEXT: %{{.*}} = riscv.get_register : !riscv.reg<sp>
-    // CHECK-NEXT: %{{.*}} = riscv.li 1083394629 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1083394629 : !riscv.reg
     // CHECK-NEXT: riscv.sw %{{.*}}, %{{.*}}, -4 : (!riscv.reg<sp>, !riscv.reg) -> ()
-    // CHECK-NEXT: %{{.*}} = riscv.li 1834810029 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1834810029 : !riscv.reg
     // CHECK-NEXT: riscv.sw %{{.*}}, %{{.*}}, -8 : (!riscv.reg<sp>, !riscv.reg) -> ()
     // CHECK-NEXT: %{{.*}} = riscv.fld %{{.*}}, -8 : (!riscv.reg<sp>) -> !riscv.freg
 
@@ -173,7 +173,7 @@ builtin.module {
     // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %lhsi32 : (!riscv.reg) -> !riscv.freg
 
     %cmpf0 = "arith.cmpf"(%lhsf32, %rhsf32) {"predicate" = 0 : i32} : (f32, f32) -> i1
-    // CHECK-NEXT: %{{.*}} = riscv.li 0 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 0 : !riscv.reg
     %cmpf1 = "arith.cmpf"(%lhsf32, %rhsf32) {"predicate" = 1 : i32} : (f32, f32) -> i1
     // CHECK-NEXT: %{{.*}} = riscv.feq.s %lhsf32_1, %rhsf32_1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
     %cmpf2 = "arith.cmpf"(%lhsf32, %rhsf32) {"predicate" = 2 : i32} : (f32, f32) -> i1
@@ -218,7 +218,7 @@ builtin.module {
     // CHECK-NEXT: %{{.*}} = riscv.and %cmpf14_1, %cmpf14 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     // CHECK-NEXT: %{{.*}} = riscv.xori %cmpf14_2, 1 : (!riscv.reg) -> !riscv.reg
     %cmpf15 = "arith.cmpf"(%lhsf32, %rhsf32) {"predicate" = 15 : i32} : (f32, f32) -> i1
-    // CHECK-NEXT: %{{.*}} = riscv.li 1 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
 
     // tests with fastmath flags when set to "fast"
     %cmpf1_fm = "arith.cmpf"(%lhsf32, %rhsf32) {"predicate" = 1 : i32, "fastmath" = #arith.fastmath<fast>} : (f32, f32) -> i1
diff --git a/tests/filecheck/backend/riscv/convert_riscv_scf_for_to_frep.mlir b/tests/filecheck/backend/riscv/convert_riscv_scf_for_to_frep.mlir
index dbe7d5faf1..3b45ee2081 100644
--- a/tests/filecheck/backend/riscv/convert_riscv_scf_for_to_frep.mlir
+++ b/tests/filecheck/backend/riscv/convert_riscv_scf_for_to_frep.mlir
@@ -4,8 +4,8 @@
 %i1 = riscv.get_register : !riscv.reg
 %i2 = riscv.get_register : !riscv.reg
 
-%c1 = riscv.li 1 : !riscv.reg
-%c2 = riscv.li 2 : !riscv.reg
+%c1 = rv32.li 1 : !riscv.reg
+%c2 = rv32.li 2 : !riscv.reg
 
 %readable = riscv_snitch.get_stream : !snitch.readable<!riscv.freg<ft0>>
 %writable = riscv_snitch.get_stream : !snitch.writable<!riscv.freg<ft1>>
diff --git a/tests/filecheck/backend/riscv/memref_to_riscv.mlir b/tests/filecheck/backend/riscv/memref_to_riscv.mlir
index ad2cc71631..78dfd30589 100644
--- a/tests/filecheck/backend/riscv/memref_to_riscv.mlir
+++ b/tests/filecheck/backend/riscv/memref_to_riscv.mlir
@@ -13,10 +13,10 @@
 // CHECK-NEXT:    %m_f32_1 = builtin.unrealized_conversion_cast %m_f32 : memref<3x2xf32> to !riscv.reg
 // CHECK-NEXT:    %r_1 = builtin.unrealized_conversion_cast %r : index to !riscv.reg
 // CHECK-NEXT:    %c_1 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset = riscv.mul %r_1, %pointer_dim_stride : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset = riscv.add %pointer_dim_offset, %c_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element = riscv.li 4 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element = rv32.li 4 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %pointer_offset, %bytes_per_element {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_f32_1, %scaled_pointer_offset : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.fsw %offset_pointer, %v_f32_1, 0 {comment = "store float value to memref of shape (3, 2)"} : (!riscv.reg, !riscv.freg) -> ()
@@ -25,10 +25,10 @@ memref.store %v_f32, %m_f32[%r, %c] {"nontemporal" = false} : memref<3x2xf32>
 // CHECK-NEXT:    %m_f32_2 = builtin.unrealized_conversion_cast %m_f32 : memref<3x2xf32> to !riscv.reg
 // CHECK-NEXT:    %r_2 = builtin.unrealized_conversion_cast %r : index to !riscv.reg
 // CHECK-NEXT:    %c_2 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_1 = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_1 = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_1 = riscv.mul %r_2, %pointer_dim_stride_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_1 = riscv.add %pointer_dim_offset_1, %c_2 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_1 = riscv.li 4 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_1 = rv32.li 4 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_1 = riscv.mul %pointer_offset_1, %bytes_per_element_1 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_1 = riscv.add %m_f32_2, %scaled_pointer_offset_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %x_f32 = riscv.flw %offset_pointer_1, 0 {comment = "load float from memref of shape (3, 2)"} : (!riscv.reg) -> !riscv.freg
@@ -38,7 +38,7 @@ memref.store %v_f32, %m_f32[%r, %c] {"nontemporal" = false} : memref<3x2xf32>
 // CHECK-NEXT:    %v_i32_1 = builtin.unrealized_conversion_cast %v_i32 : i32 to !riscv.reg
 // CHECK-NEXT:    %m_i32_1 = builtin.unrealized_conversion_cast %m_i32 : memref<3xi32> to !riscv.reg
 // CHECK-NEXT:    %c_3 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_2 = riscv.li 4 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_2 = rv32.li 4 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_2 = riscv.mul %c_3, %bytes_per_element_2 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_2 = riscv.add %m_i32_1, %scaled_pointer_offset_2 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.sw %offset_pointer_2, %v_i32_1, 0 {comment = "store int value to memref of shape (3,)"} : (!riscv.reg, !riscv.reg) -> ()
@@ -46,7 +46,7 @@ memref.store %v_i32, %m_i32[%c] {"nontemporal" = false} : memref<3xi32>
 
 // CHECK-NEXT:    %m_i32_2 = builtin.unrealized_conversion_cast %m_i32 : memref<3xi32> to !riscv.reg
 // CHECK-NEXT:    %c_4 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_3 = riscv.li 4 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_3 = rv32.li 4 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_3 = riscv.mul %c_4, %bytes_per_element_3 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_3 = riscv.add %m_i32_2, %scaled_pointer_offset_3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %x_i32 = riscv.lw %offset_pointer_3, 0 {comment = "load word from memref of shape (3,)"} : (!riscv.reg) -> !riscv.reg
@@ -57,10 +57,10 @@ memref.store %v_i32, %m_i32[%c] {"nontemporal" = false} : memref<3xi32>
 // CHECK-NEXT:    %m_f64_1 = builtin.unrealized_conversion_cast %m_f64 : memref<3x2xf64> to !riscv.reg
 // CHECK-NEXT:    %r_3 = builtin.unrealized_conversion_cast %r : index to !riscv.reg
 // CHECK-NEXT:    %c_5 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_2 = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_2 = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_2 = riscv.mul %r_3, %pointer_dim_stride_2 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_2 = riscv.add %pointer_dim_offset_2, %c_5 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_4 = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_4 = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_4 = riscv.mul %pointer_offset_2, %bytes_per_element_4 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_4 = riscv.add %m_f64_1, %scaled_pointer_offset_4 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.fsd %offset_pointer_4, %v_f64_1, 0 {comment = "store double value to memref of shape (3, 2)"} : (!riscv.reg, !riscv.freg) -> ()
@@ -79,10 +79,10 @@ memref.store %scalar_x_i32, %m_scalar_i32[] {"nontemporal" = false} : memref<i32
 // CHECK-NEXT:    %m_f64_2 = builtin.unrealized_conversion_cast %m_f64 : memref<3x2xf64> to !riscv.reg
 // CHECK-NEXT:    %r_4 = builtin.unrealized_conversion_cast %r : index to !riscv.reg
 // CHECK-NEXT:    %c_6 = builtin.unrealized_conversion_cast %c : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_3 = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_3 = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_3 = riscv.mul %r_4, %pointer_dim_stride_3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_3 = riscv.add %pointer_dim_offset_3, %c_6 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_5 = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_5 = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_5 = riscv.mul %pointer_offset_3, %bytes_per_element_5 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_5 = riscv.add %m_f64_2, %scaled_pointer_offset_5 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %x_f64 = riscv.fld %offset_pointer_5, 0 {comment = "load double from memref of shape (3, 2)"} : (!riscv.reg) -> !riscv.freg
@@ -95,7 +95,7 @@ memref.store %scalar_x_i32, %m_scalar_i32[] {"nontemporal" = false} : memref<i32
 // CHECK-NEXT:   }
 "memref.global"() <{"sym_name" = "global", "sym_visibility" = "public", "type" = memref<2xf64>, "initial_value" = dense<[1, 2]> : tensor<2xf64>}> : () -> ()
 
-// CHECK-NEXT:    %global = riscv.li "global" : !riscv.reg
+// CHECK-NEXT:    %global = rv32.li "global" : !riscv.reg
 // CHECK-NEXT:    %global_1 = builtin.unrealized_conversion_cast %global : !riscv.reg to memref<2xi32>
 %global = memref.get_global @global : memref<2xi32>
 
@@ -105,14 +105,14 @@ memref.store %scalar_x_i32, %m_scalar_i32[] {"nontemporal" = false} : memref<i32
 
 // CHECK:       builtin.module {
 
-// CHECK-NEXT:    %m0 = riscv.li 4 {comment = "memref alloc size"} : !riscv.reg
+// CHECK-NEXT:    %m0 = rv32.li 4 {comment = "memref alloc size"} : !riscv.reg
 // CHECK-NEXT:    %m0_1 = riscv.mv %m0 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:    %m0_2 = riscv_func.call @malloc(%m0_1) : (!riscv.reg<a0>) -> !riscv.reg<a0>
 // CHECK-NEXT:    %m0_3 = riscv.mv %m0_2 : (!riscv.reg<a0>) -> !riscv.reg
 // CHECK-NEXT:    %m0_4 = builtin.unrealized_conversion_cast %m0_3 : !riscv.reg to memref<1x1xf32>
 %m0 = memref.alloc() : memref<1x1xf32>
 
-// CHECK-NEXT:    %m1 = riscv.li 8 {comment = "memref alloc size"} : !riscv.reg
+// CHECK-NEXT:    %m1 = rv32.li 8 {comment = "memref alloc size"} : !riscv.reg
 // CHECK-NEXT:    %m1_1 = riscv.mv %m1 : (!riscv.reg) -> !riscv.reg<a0>
 // CHECK-NEXT:    %m1_2 = riscv_func.call @malloc(%m1_1) : (!riscv.reg<a0>) -> !riscv.reg<a0>
 // CHECK-NEXT:    %m1_3 = riscv.mv %m1_2 : (!riscv.reg<a0>) -> !riscv.reg
@@ -150,7 +150,7 @@ memref.store %scalar_x_i32, %m_scalar_i32[] {"nontemporal" = false} : memref<i32
 // CHECK-NEXT:    %v_1 = builtin.unrealized_conversion_cast %v : i8 to !riscv.reg
 // CHECK-NEXT:    %m_1 = builtin.unrealized_conversion_cast %m : memref<1xi8> to !riscv.reg
 // CHECK-NEXT:    %d0_1 = builtin.unrealized_conversion_cast %d0 : index to !riscv.reg
-// CHECK-NEXT:    %bytes_per_element = riscv.li 1 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element = rv32.li 1 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %d0_1, %bytes_per_element {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_1, %scaled_pointer_offset : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.sw %offset_pointer, %v_1, 0 {comment = "store int value to memref of shape (1,)"} : (!riscv.reg, !riscv.reg) -> ()
@@ -168,7 +168,7 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi8>
 // CHECK-NEXT:    %v_1 = builtin.unrealized_conversion_cast %v : i16 to !riscv.reg
 // CHECK-NEXT:    %m_1 = builtin.unrealized_conversion_cast %m : memref<1xi16> to !riscv.reg
 // CHECK-NEXT:    %d0_1 = builtin.unrealized_conversion_cast %d0 : index to !riscv.reg
-// CHECK-NEXT:    %bytes_per_element = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %d0_1, %bytes_per_element {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_1, %scaled_pointer_offset : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.sw %offset_pointer, %v_1, 0 {comment = "store int value to memref of shape (1,)"} : (!riscv.reg, !riscv.reg) -> ()
@@ -186,7 +186,7 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi16>
 // CHECK-NEXT:    %v_1 = builtin.unrealized_conversion_cast %v : i64 to !riscv.reg
 // CHECK-NEXT:    %m_1 = builtin.unrealized_conversion_cast %m : memref<1xi64> to !riscv.reg
 // CHECK-NEXT:    %d0_1 = builtin.unrealized_conversion_cast %d0 : index to !riscv.reg
-// CHECK-NEXT:    %bytes_per_element = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %d0_1, %bytes_per_element {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_1, %scaled_pointer_offset : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv.sw %offset_pointer, %v_1, 0 {comment = "store int value to memref of shape (1,)"} : (!riscv.reg, !riscv.reg) -> ()
@@ -216,15 +216,15 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi64>
 
 // CHECK-NEXT:    %dynamic_subview = builtin.unrealized_conversion_cast %original : memref<4x3x2xf64> to !riscv.reg
 // CHECK-NEXT:    %subview_dim_index = builtin.unrealized_conversion_cast %offset : index to !riscv.reg
-// CHECK-NEXT:    %subview_dim_index_1 = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:    %subview_dim_index_2 = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride = riscv.li 6 : !riscv.reg
+// CHECK-NEXT:    %subview_dim_index_1 = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:    %subview_dim_index_2 = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride = rv32.li 6 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset = riscv.mul %subview_dim_index, %pointer_dim_stride : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_1 = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_1 = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_1 = riscv.mul %subview_dim_index_1, %pointer_dim_stride_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset = riscv.add %pointer_dim_offset, %pointer_dim_offset_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_1 = riscv.add %pointer_offset, %subview_dim_index_2 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %pointer_offset_1, %bytes_per_element {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer = riscv.add %dynamic_subview, %scaled_pointer_offset : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %dynamic_subview_1 = builtin.unrealized_conversion_cast %offset_pointer : !riscv.reg to memref<3x2xf64, strided<[2, 1], offset: ?>>
@@ -236,18 +236,18 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi64>
 // CHECK-NEXT:    %larger_dynamic_subview = builtin.unrealized_conversion_cast %larger_original : memref<5x4x3x2xf64> to !riscv.reg
 // CHECK-NEXT:    %subview_dim_index_3 = builtin.unrealized_conversion_cast %offset : index to !riscv.reg
 // CHECK-NEXT:    %subview_dim_index_4 = builtin.unrealized_conversion_cast %offset : index to !riscv.reg
-// CHECK-NEXT:    %subview_dim_index_5 = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:    %subview_dim_index_6 = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_2 = riscv.li 24 : !riscv.reg
+// CHECK-NEXT:    %subview_dim_index_5 = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:    %subview_dim_index_6 = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_2 = rv32.li 24 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_2 = riscv.mul %subview_dim_index_3, %pointer_dim_stride_2 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_3 = riscv.li 6 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_3 = rv32.li 6 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_3 = riscv.mul %subview_dim_index_4, %pointer_dim_stride_3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_2 = riscv.add %pointer_dim_offset_2, %pointer_dim_offset_3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride_4 = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:    %pointer_dim_stride_4 = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:    %pointer_dim_offset_4 = riscv.mul %subview_dim_index_5, %pointer_dim_stride_4 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_3 = riscv.add %pointer_offset_2, %pointer_dim_offset_4 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %pointer_offset_4 = riscv.add %pointer_offset_3, %subview_dim_index_6 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %bytes_per_element_1 = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:    %bytes_per_element_1 = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:    %scaled_pointer_offset_1 = riscv.mul %pointer_offset_4, %bytes_per_element_1 {comment = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %offset_pointer_1 = riscv.add %larger_dynamic_subview, %scaled_pointer_offset_1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %larger_dynamic_subview_1 = builtin.unrealized_conversion_cast %offset_pointer_1 : !riscv.reg to memref<3x2xf64, strided<[2, 1], offset: ?>>
@@ -275,10 +275,10 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi64>
 // CHECK:         %m_1 = builtin.unrealized_conversion_cast %m : memref<2x3xf64, strided<[6, 1], offset: ?>> to !riscv.reg
 // CHECK-NEXT:    %i0_1 = builtin.unrealized_conversion_cast %i0 : index to !riscv.reg
 // CHECK-NEXT:    %i1_1 = builtin.unrealized_conversion_cast %i1 : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride = riscv.li 6
+// CHECK-NEXT:    %pointer_dim_stride = rv32.li 6
 // CHECK-NEXT:    %pointer_dim_offset = riscv.mul %i0_1, %pointer_dim_stride
 // CHECK-NEXT:    %pointer_offset = riscv.add %pointer_dim_offset, %i1_1
-// CHECK-NEXT:    %bytes_per_element = riscv.li 8
+// CHECK-NEXT:    %bytes_per_element = rv32.li 8
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %pointer_offset, %bytes_per_element
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_1, %scaled_pointer_offset
 // CHECK-NEXT:    %v = riscv.fld %offset_pointer, 0
@@ -295,10 +295,10 @@ memref.store %v, %m[%d0] {"nontemporal" = false} : memref<1xi64>
 // CHECK-NEXT:    %m_1 = builtin.unrealized_conversion_cast %m : memref<2x3xf64, strided<[6, 1], offset: ?>> to !riscv.reg
 // CHECK-NEXT:    %i0_1 = builtin.unrealized_conversion_cast %i0 : index to !riscv.reg
 // CHECK-NEXT:    %i1_1 = builtin.unrealized_conversion_cast %i1 : index to !riscv.reg
-// CHECK-NEXT:    %pointer_dim_stride = riscv.li 6
+// CHECK-NEXT:    %pointer_dim_stride = rv32.li 6
 // CHECK-NEXT:    %pointer_dim_offset = riscv.mul %i0_1, %pointer_dim_stride
 // CHECK-NEXT:    %pointer_offset = riscv.add %pointer_dim_offset, %i1_1
-// CHECK-NEXT:    %bytes_per_element = riscv.li 8
+// CHECK-NEXT:    %bytes_per_element = rv32.li 8
 // CHECK-NEXT:    %scaled_pointer_offset = riscv.mul %pointer_offset, %bytes_per_element
 // CHECK-NEXT:    %offset_pointer = riscv.add %m_1, %scaled_pointer_offset
 // CHECK-NEXT:    riscv.fsd %offset_pointer, %v_1, 0
diff --git a/tests/filecheck/backend/riscv/memref_to_riscv_opt.mlir b/tests/filecheck/backend/riscv/memref_to_riscv_opt.mlir
index 41519937a9..a6bb2d219a 100644
--- a/tests/filecheck/backend/riscv/memref_to_riscv_opt.mlir
+++ b/tests/filecheck/backend/riscv/memref_to_riscv_opt.mlir
@@ -10,8 +10,8 @@ builtin.module {
     %mf = builtin.unrealized_conversion_cast %mf_reg : !riscv.reg to memref<3x2xf32>
     %md = builtin.unrealized_conversion_cast %md_reg : !riscv.reg to memref<3x2xf64>
     %mi = builtin.unrealized_conversion_cast %mi_reg : !riscv.reg to memref<3x2xi32>
-    %r_reg = riscv.li 1 : !riscv.reg
-    %c_reg = riscv.li 1 : !riscv.reg
+    %r_reg = rv32.li 1 : !riscv.reg
+    %c_reg = rv32.li 1 : !riscv.reg
     %r = builtin.unrealized_conversion_cast %r_reg : !riscv.reg to index
     %c = builtin.unrealized_conversion_cast %c_reg : !riscv.reg to index
     "memref.store"(%vf, %mf, %r, %c) {"nontemporal" = false} : (f32, memref<3x2xf32>, index, index) -> ()
diff --git a/tests/filecheck/backend/riscv/prologue_epilogue_insertion.mlir b/tests/filecheck/backend/riscv/prologue_epilogue_insertion.mlir
index e38458548a..1c20cba9d9 100644
--- a/tests/filecheck/backend/riscv/prologue_epilogue_insertion.mlir
+++ b/tests/filecheck/backend/riscv/prologue_epilogue_insertion.mlir
@@ -60,7 +60,7 @@ riscv_func.func @simple(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) -> !riscv.reg<
   // CHECK-SAME: (!riscv.reg<a0>) -> !riscv.reg<t0>
   %2 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<t0>
   %3 = riscv.mv %1 : (!riscv.reg<a1>) -> !riscv.reg<t2>
-  %4 = riscv.li 10 : !riscv.reg<t1>
+  %4 = rv32.li 10 : !riscv.reg<t1>
   %5 = riscv.add %2, %3 : (!riscv.reg<t0>, !riscv.reg<t2>) -> !riscv.reg<t0>
   %6 = riscv.add %5, %4 : (!riscv.reg<t0>, !riscv.reg<t1>) -> !riscv.reg<t0>
   %7 = riscv.mv %6 : (!riscv.reg<t0>) -> !riscv.reg<a0>
diff --git a/tests/filecheck/backend/riscv/register-allocation/frep.mlir b/tests/filecheck/backend/riscv/register-allocation/frep.mlir
index 63881adb49..bc1ca46b44 100644
--- a/tests/filecheck/backend/riscv/register-allocation/frep.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/frep.mlir
@@ -1,8 +1,8 @@
 // RUN: xdsl-opt -p "riscv-allocate-registers{allocation_strategy=LivenessBlockNaive}" %s | filecheck %s --check-prefix=CHECK-LIVENESS-BLOCK-NAIVE
 
 riscv_func.func @main() {
-  %0 = riscv.li 6 : !riscv.reg
-  %1 = riscv.li 5 : !riscv.reg<s0>
+  %0 = rv32.li 6 : !riscv.reg
+  %1 = rv32.li 5 : !riscv.reg<s0>
   %2 = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
   %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg
   %4 = riscv.fadd.s %2, %3 : (!riscv.freg, !riscv.freg) -> !riscv.freg
@@ -20,8 +20,8 @@ riscv_func.func @main() {
 
 //   CHECK-LIVENESS-BLOCK-NAIVE:       builtin.module {
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:    riscv_func.func @main() {
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = riscv.li 6 : !riscv.reg<t1>
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = riscv.li 5 : !riscv.reg<s0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = rv32.li 6 : !riscv.reg<t1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = rv32.li 5 : !riscv.reg<s0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<t1>) -> !riscv.freg<ft0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<s0>) -> !riscv.freg<ft1>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft0>
diff --git a/tests/filecheck/backend/riscv/register-allocation/generic.mlir b/tests/filecheck/backend/riscv/register-allocation/generic.mlir
index 04b645e305..12299e3106 100644
--- a/tests/filecheck/backend/riscv/register-allocation/generic.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/generic.mlir
@@ -3,9 +3,9 @@
 riscv_func.func @external() -> ()
 
 riscv_func.func @main() {
-  %zero = riscv.li 0 : !riscv.reg
-  %0 = riscv.li 6 : !riscv.reg
-  %1 = riscv.li 5 : !riscv.reg<s0>
+  %zero = rv32.li 0 : !riscv.reg
+  %0 = rv32.li 6 : !riscv.reg
+  %1 = rv32.li 5 : !riscv.reg<s0>
   %2 = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
   %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg
   %4 = riscv.fadd.s %2, %3 : (!riscv.freg, !riscv.freg) -> !riscv.freg
@@ -19,8 +19,8 @@ riscv_func.func @main() {
     riscv_scf.yield %10 : !riscv.reg
   }
 
-  %zero_0 = riscv.li 0 : !riscv.reg
-  %zero_1 = riscv.li 0 : !riscv.reg<a0>
+  %zero_0 = rv32.li 0 : !riscv.reg
+  %zero_1 = rv32.li 0 : !riscv.reg<a0>
 
   riscv_func.return
 }
@@ -28,9 +28,9 @@ riscv_func.func @main() {
 //   CHECK-LIVENESS-BLOCK-NAIVE:       builtin.module {
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:    riscv_func.func @external() -> ()
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:    riscv_func.func @main() {
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero = riscv.li 0 : !riscv.reg<zero>
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %0 = riscv.li 6 : !riscv.reg<t1>
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %1 = riscv.li 5 : !riscv.reg<s0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero = rv32.li 0 : !riscv.reg<zero>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %0 = rv32.li 6 : !riscv.reg<t1>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %1 = rv32.li 5 : !riscv.reg<s0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %2 = riscv.fcvt.s.w %0 : (!riscv.reg<t1>) -> !riscv.freg<ft0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %3 = riscv.fcvt.s.w %1 : (!riscv.reg<s0>) -> !riscv.freg<ft1>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %4 = riscv.fadd.s %2, %3 : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft0>
@@ -41,8 +41,8 @@ riscv_func.func @main() {
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:        %10 = riscv.mv %9 : (!riscv.reg<t0>) -> !riscv.reg<t0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:        riscv_scf.yield %10 : !riscv.reg<t0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      }
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero_1 = riscv.li 0 : !riscv.reg<zero>
-//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero_2 = riscv.li 0 : !riscv.reg<a0>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero_1 = rv32.li 0 : !riscv.reg<zero>
+//   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      %zero_2 = rv32.li 0 : !riscv.reg<a0>
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:      riscv_func.return
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:    }
 //   CHECK-LIVENESS-BLOCK-NAIVE-NEXT:  }
diff --git a/tests/filecheck/backend/riscv/register-allocation/liveness_block_naive.mlir b/tests/filecheck/backend/riscv/register-allocation/liveness_block_naive.mlir
index 57dcd5066c..4e9f10998a 100644
--- a/tests/filecheck/backend/riscv/register-allocation/liveness_block_naive.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/liveness_block_naive.mlir
@@ -2,38 +2,38 @@
 
 builtin.module {
   riscv_func.func @main() {
-    %0 = riscv.li 6 : !riscv.reg
-    %1 = riscv.li 5 : !riscv.reg<s0>
+    %0 = rv32.li 6 : !riscv.reg
+    %1 = rv32.li 5 : !riscv.reg<s0>
     %2 = riscv.add %0, %1 : (!riscv.reg, !riscv.reg<s0>) -> !riscv.reg
-    %3 = riscv.li 29 : !riscv.reg
-    %4 = riscv.li 28 : !riscv.reg
-    %5 = riscv.li 27 : !riscv.reg
-    %6 = riscv.li 26 : !riscv.reg
-    %7 = riscv.li 25 : !riscv.reg
-    %8 = riscv.li 24 : !riscv.reg
-    %9 = riscv.li 23 : !riscv.reg
-    %10 = riscv.li 22 : !riscv.reg
-    %11 = riscv.li 21 : !riscv.reg
-    %12 = riscv.li 20 : !riscv.reg
-    %13 = riscv.li 19 : !riscv.reg
-    %14 = riscv.li 18 : !riscv.reg
-    %15 = riscv.li 17 : !riscv.reg
-    %16 = riscv.li 16 : !riscv.reg
-    %17 = riscv.li 15 : !riscv.reg
-    %18 = riscv.li 14 : !riscv.reg
-    %19 = riscv.li 13 : !riscv.reg
-    %20 = riscv.li 12 : !riscv.reg
-    %21 = riscv.li 11 : !riscv.reg
-    %22 = riscv.li 10 : !riscv.reg
-    %23 = riscv.li 9 : !riscv.reg
-    %24 = riscv.li 8 : !riscv.reg
-    %25 = riscv.li 7 : !riscv.reg
-    %26 = riscv.li 6 : !riscv.reg
-    %27 = riscv.li 5 : !riscv.reg
-    %28 = riscv.li 4 : !riscv.reg
-    %29 = riscv.li 3 : !riscv.reg
-    %30 = riscv.li 2 : !riscv.reg
-    %31 = riscv.li 1 : !riscv.reg
+    %3 = rv32.li 29 : !riscv.reg
+    %4 = rv32.li 28 : !riscv.reg
+    %5 = rv32.li 27 : !riscv.reg
+    %6 = rv32.li 26 : !riscv.reg
+    %7 = rv32.li 25 : !riscv.reg
+    %8 = rv32.li 24 : !riscv.reg
+    %9 = rv32.li 23 : !riscv.reg
+    %10 = rv32.li 22 : !riscv.reg
+    %11 = rv32.li 21 : !riscv.reg
+    %12 = rv32.li 20 : !riscv.reg
+    %13 = rv32.li 19 : !riscv.reg
+    %14 = rv32.li 18 : !riscv.reg
+    %15 = rv32.li 17 : !riscv.reg
+    %16 = rv32.li 16 : !riscv.reg
+    %17 = rv32.li 15 : !riscv.reg
+    %18 = rv32.li 14 : !riscv.reg
+    %19 = rv32.li 13 : !riscv.reg
+    %20 = rv32.li 12 : !riscv.reg
+    %21 = rv32.li 11 : !riscv.reg
+    %22 = rv32.li 10 : !riscv.reg
+    %23 = rv32.li 9 : !riscv.reg
+    %24 = rv32.li 8 : !riscv.reg
+    %25 = rv32.li 7 : !riscv.reg
+    %26 = rv32.li 6 : !riscv.reg
+    %27 = rv32.li 5 : !riscv.reg
+    %28 = rv32.li 4 : !riscv.reg
+    %29 = rv32.li 3 : !riscv.reg
+    %30 = rv32.li 2 : !riscv.reg
+    %31 = rv32.li 1 : !riscv.reg
     %32 = riscv.fcvt.s.w %30 : (!riscv.reg) -> !riscv.freg
     %33 = riscv.fcvt.s.w %31 : (!riscv.reg) -> !riscv.freg
     %34 = riscv.fadd.s %32, %33 : (!riscv.freg, !riscv.freg) -> !riscv.freg
@@ -43,38 +43,38 @@ builtin.module {
 
 // CHECK:      builtin.module {
 // CHECK-NEXT:  riscv_func.func @main() {
-// CHECK-NEXT:    %{{\d+}} = riscv.li 6 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 5 : !riscv.reg<s0>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 6 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 5 : !riscv.reg<s0>
 // CHECK-NEXT:    %{{\d+}} = riscv.add %{{\d+}}, %{{\d+}} : (!riscv.reg<t1>, !riscv.reg<s0>) -> !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 29 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 28 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 27 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 26 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 25 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 24 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 23 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 22 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 21 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 20 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 19 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 18 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 17 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 16 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 15 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 14 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 13 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 12 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 11 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 10 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 9 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 8 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 7 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 6 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 5 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 4 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 3 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 2 : !riscv.reg<t1>
-// CHECK-NEXT:    %{{\d+}} = riscv.li 1 : !riscv.reg<t0>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 29 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 28 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 27 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 26 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 25 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 24 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 23 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 22 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 21 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 20 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 19 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 18 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 17 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 16 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 15 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 14 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 13 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 12 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 11 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 10 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 9 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 8 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 7 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 6 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 5 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 4 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 3 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 2 : !riscv.reg<t1>
+// CHECK-NEXT:    %{{\d+}} = rv32.li 1 : !riscv.reg<t0>
 // CHECK-NEXT:    %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<t1>) -> !riscv.freg<ft0>
 // CHECK-NEXT:    %{{\d+}} = riscv.fcvt.s.w %{{\d+}} : (!riscv.reg<t0>) -> !riscv.freg<ft1>
 // CHECK-NEXT:    %{{\d+}} = riscv.fadd.s %{{\d+}}, %{{\d+}} : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft0>
diff --git a/tests/filecheck/backend/riscv/register-allocation/preallocated.mlir b/tests/filecheck/backend/riscv/register-allocation/preallocated.mlir
index 18395df95d..b031785756 100644
--- a/tests/filecheck/backend/riscv/register-allocation/preallocated.mlir
+++ b/tests/filecheck/backend/riscv/register-allocation/preallocated.mlir
@@ -1,8 +1,8 @@
 // RUN: xdsl-opt -p "riscv-allocate-registers{allocation_strategy=LivenessBlockNaive add-regalloc-stats=true}" %s | filecheck %s --check-prefix=LIVE-BNAIVE
 
 riscv_func.func @main() {
-  %0 = riscv.li 6 : !riscv.reg
-  %1 = riscv.li 5 : !riscv.reg<t0>
+  %0 = rv32.li 6 : !riscv.reg
+  %1 = rv32.li 5 : !riscv.reg<t0>
   %3 = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg<ft0>
   %4 = riscv.fcvt.s.w %1 : (!riscv.reg<t0>) -> !riscv.freg
   %5 = riscv.fadd.s %3, %4 : (!riscv.freg<ft0>, !riscv.freg) -> !riscv.freg
@@ -13,8 +13,8 @@ riscv_func.func @main() {
 // LIVE-BNAIVE:       builtin.module {
 // LIVE-BNAIVE-NEXT:    riscv.comment {comment = "Regalloc stats: {\"preallocated_float\": [\"ft0\"], \"preallocated_int\": [\"t0\"], \"allocated_float\": [\"ft0\", \"ft1\"], \"allocated_int\": [\"t0\", \"t1\"]}"} : () -> ()
 // LIVE-BNAIVE-NEXT:    riscv_func.func @main() {
-// LIVE-BNAIVE-NEXT:      %0 = riscv.li 6 : !riscv.reg<t1>
-// LIVE-BNAIVE-NEXT:      %1 = riscv.li 5 : !riscv.reg<t0>
+// LIVE-BNAIVE-NEXT:      %0 = rv32.li 6 : !riscv.reg<t1>
+// LIVE-BNAIVE-NEXT:      %1 = rv32.li 5 : !riscv.reg<t0>
 // LIVE-BNAIVE-NEXT:      %2 = riscv.fcvt.s.w %0 : (!riscv.reg<t1>) -> !riscv.freg<ft0>
 // LIVE-BNAIVE-NEXT:      %3 = riscv.fcvt.s.w %1 : (!riscv.reg<t0>) -> !riscv.freg<ft1>
 // LIVE-BNAIVE-NEXT:      %4 = riscv.fadd.s %2, %3 : (!riscv.freg<ft0>, !riscv.freg<ft1>) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/backend/rvscf_lowering_labels.mlir b/tests/filecheck/backend/rvscf_lowering_labels.mlir
index 1c94ea1eee..47f46d8092 100644
--- a/tests/filecheck/backend/rvscf_lowering_labels.mlir
+++ b/tests/filecheck/backend/rvscf_lowering_labels.mlir
@@ -4,8 +4,8 @@
 
 builtin.module {
     riscv_func.func @foo(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-        %2 = riscv.li 1 : !riscv.reg<a2>
-        %3 = riscv.li 0 : !riscv.reg<a3>
+        %2 = rv32.li 1 : !riscv.reg<a2>
+        %3 = rv32.li 0 : !riscv.reg<a3>
         %4 = riscv_scf.for %5 : !riscv.reg<a4> = %0 to %1 step %2 iter_args(%6 = %3) -> (!riscv.reg<a3>) {
             %7 = riscv.add %5, %6 : (!riscv.reg<a4>, !riscv.reg<a3>) -> !riscv.reg<a3>
             "riscv_scf.yield"(%7) : (!riscv.reg<a3>) -> ()
@@ -17,8 +17,8 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @foo(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<a2>
-// CHECK-NEXT:      %3 = riscv.li 0 : !riscv.reg<a3>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<a2>
+// CHECK-NEXT:      %3 = rv32.li 0 : !riscv.reg<a3>
 // CHECK-NEXT:      %4 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<a4>
 // CHECK-NEXT:      riscv.label "scf_cond_0_for"
 // CHECK-NEXT:      riscv.bge %4, %1, "scf_body_end_0_for" : (!riscv.reg<a4>, !riscv.reg<a1>) -> ()
@@ -40,8 +40,8 @@ builtin.module {
 
   builtin.module {
     riscv_func.func @foo(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-        %2 = riscv.li 1 : !riscv.reg<a2>
-        %3 = riscv.li 0 : !riscv.reg<a3>
+        %2 = rv32.li 1 : !riscv.reg<a2>
+        %3 = rv32.li 0 : !riscv.reg<a3>
         %4 = riscv.fcvt.s.w %3 : (!riscv.reg<a3>) -> !riscv.freg<fa0>
         %5 = riscv_scf.for %6 : !riscv.reg<a0> = %0 to %1 step %2 iter_args(%7 = %4) -> (!riscv.freg<fa0>) {
             %8 = riscv.fcvt.s.w %6 : (!riscv.reg<a0>) -> !riscv.freg<fa1>
@@ -55,8 +55,8 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @foo(%0 : !riscv.reg<a0>, %1 : !riscv.reg<a1>) {
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<a2>
-// CHECK-NEXT:      %3 = riscv.li 0 : !riscv.reg<a3>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<a2>
+// CHECK-NEXT:      %3 = rv32.li 0 : !riscv.reg<a3>
 // CHECK-NEXT:      %4 = riscv.fcvt.s.w %3 : (!riscv.reg<a3>) -> !riscv.freg<fa0>
 // CHECK-NEXT:      %5 = riscv.mv %0 : (!riscv.reg<a0>) -> !riscv.reg<a0>
 // CHECK-NEXT:      riscv.label "scf_cond_0_for"
@@ -79,12 +79,12 @@ builtin.module {
 
 builtin.module {
     riscv_func.func @foo(%arg0 : !riscv.reg<a0>) {
-        %0 = riscv.li 0 : !riscv.reg<a1>
-        %1 = riscv.li 0 : !riscv.reg<a2>
-        %2 = riscv.li 1 : !riscv.reg<a3>
+        %0 = rv32.li 0 : !riscv.reg<a1>
+        %1 = rv32.li 0 : !riscv.reg<a2>
+        %2 = rv32.li 1 : !riscv.reg<a3>
         %3 = riscv_scf.for %arg1 : !riscv.reg<a2> = %1 to %arg0 step %2 iter_args(%arg2 = %0) -> (!riscv.reg<a1>) {
-            %4 = riscv.li 0 : !riscv.reg<a4>
-            %5 = riscv.li 1 : !riscv.reg<a5>
+            %4 = rv32.li 0 : !riscv.reg<a4>
+            %5 = rv32.li 1 : !riscv.reg<a5>
             %6 = riscv_scf.for %arg3 : !riscv.reg<a4> = %4 to %arg0 step %5 iter_args(%arg4 = %arg2) -> (!riscv.reg<a1>) {
                 %7 = riscv.add %arg1, %arg3 : (!riscv.reg<a2>, !riscv.reg<a4>) -> !riscv.reg<a0>
                 %8 = riscv.add %arg4, %7 : (!riscv.reg<a1>, !riscv.reg<a0>) -> !riscv.reg<a1>
@@ -98,17 +98,17 @@ builtin.module {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @foo(%arg0 : !riscv.reg<a0>) {
-// CHECK-NEXT:      %0 = riscv.li 0 : !riscv.reg<a1>
-// CHECK-NEXT:      %1 = riscv.li 0 : !riscv.reg<a2>
-// CHECK-NEXT:      %2 = riscv.li 1 : !riscv.reg<a3>
+// CHECK-NEXT:      %0 = rv32.li 0 : !riscv.reg<a1>
+// CHECK-NEXT:      %1 = rv32.li 0 : !riscv.reg<a2>
+// CHECK-NEXT:      %2 = rv32.li 1 : !riscv.reg<a3>
 // CHECK-NEXT:      %3 = riscv.mv %1 : (!riscv.reg<a2>) -> !riscv.reg<a2>
 // CHECK-NEXT:      riscv.label "scf_cond_0_for"
 // CHECK-NEXT:      riscv.bge %3, %arg0, "scf_body_end_0_for" : (!riscv.reg<a2>, !riscv.reg<a0>) -> ()
 // CHECK-NEXT:      riscv.label "scf_body_0_for"
 // CHECK-NEXT:      %arg2 = riscv.get_register : !riscv.reg<a1>
 // CHECK-NEXT:      %arg1 = riscv.get_register : !riscv.reg<a2>
-// CHECK-NEXT:      %4 = riscv.li 0 : !riscv.reg<a4>
-// CHECK-NEXT:      %5 = riscv.li 1 : !riscv.reg<a5>
+// CHECK-NEXT:      %4 = rv32.li 0 : !riscv.reg<a4>
+// CHECK-NEXT:      %5 = rv32.li 1 : !riscv.reg<a5>
 // CHECK-NEXT:      %6 = riscv.mv %4 : (!riscv.reg<a4>) -> !riscv.reg<a4>
 // CHECK-NEXT:      riscv.label "scf_cond_1_for"
 // CHECK-NEXT:      riscv.bge %6, %arg0, "scf_body_end_1_for" : (!riscv.reg<a4>, !riscv.reg<a0>) -> ()
diff --git a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
index da0b22777e..8291489c86 100644
--- a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
@@ -2,9 +2,9 @@
 
 "builtin.module"() ({
   riscv_func.func @main() {
-    %0 = riscv.li 6 : !riscv.reg<zero>
+    %0 = rv32.li 6 : !riscv.reg<zero>
     // CHECK:      li zero, 6
-    %1 = riscv.li 5 : !riscv.reg<j_1>
+    %1 = rv32.li 5 : !riscv.reg<j_1>
     // CHECK-NEXT: li j_1, 5
     %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
     // CHECK-NEXT: add j_2, zero, j_1
@@ -157,7 +157,7 @@
     // CHECK-NEXT: csrrwi zero, 1024, 8
 
     // Assembler pseudo-instructions
-    %li = riscv.li 1: !riscv.reg<j_0>
+    %li = rv32.li 1: !riscv.reg<j_0>
     // CHECK-NEXT: li j_0, 1
     // Environment Call and Breakpoints
     riscv.ecall
@@ -171,7 +171,7 @@
     riscv.directive ".align" "2"
     // CHECK-NEXT: .align 2
     riscv.assembly_section ".text" {
-      %inner = riscv.li 5 : !riscv.reg<j_1>
+      %inner = rv32.li 5 : !riscv.reg<j_1>
       %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
     }
     // CHECK-NEXT:  li j_1, 5
diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir
index 0159b85deb..9ae2bbb3c8 100644
--- a/tests/filecheck/dialects/riscv/riscv_ops.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_ops.mlir
@@ -273,8 +273,8 @@
 
     // Assembler pseudo-instructions
 
-    %li = riscv.li 1 : !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.li 1 : !riscv.reg
+    %li = rv32.li 1 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
     // Environment Call and Breakpoints
     riscv.ecall
     // CHECK-NEXT: riscv.ecall
@@ -285,17 +285,17 @@
     riscv.directive ".align" "2"
     // CHECK-NEXT: riscv.directive ".align" "2"
     riscv.assembly_section ".text" attributes {"foo" = i32} {
-      %nested_li = riscv.li 1 : !riscv.reg
+      %nested_li = rv32.li 1 : !riscv.reg
     }
     // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
-    // CHECK-NEXT:    %{{.*}} = riscv.li 1 : !riscv.reg
+    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
     // CHECK-NEXT:  }
 
     riscv.assembly_section ".text" {
-      %nested_li = riscv.li 1 : !riscv.reg
+      %nested_li = rv32.li 1 : !riscv.reg
     }
     // CHECK-NEXT:  riscv.assembly_section ".text" {
-    // CHECK-NEXT:    %{{.*}} = riscv.li 1 : !riscv.reg
+    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
     // CHECK-NEXT:  }
 
     // Custom instruction
@@ -573,16 +573,16 @@
 // CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %li = "riscv.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "riscv.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "riscv.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
 // CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
 // CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
diff --git a/tests/filecheck/dialects/riscv_cf/canonicalize.mlir b/tests/filecheck/dialects/riscv_cf/canonicalize.mlir
index f09fbe8e27..c1b3a80592 100644
--- a/tests/filecheck/dialects/riscv_cf/canonicalize.mlir
+++ b/tests/filecheck/dialects/riscv_cf/canonicalize.mlir
@@ -1,8 +1,8 @@
 // RUN: xdsl-opt -p canonicalize %s | filecheck %s
 
 riscv_func.func @at_least_once() {
-    %one = riscv.li 1 : !riscv.reg
-    %three = riscv.li 3 : !riscv.reg
+    %one = rv32.li 1 : !riscv.reg
+    %three = rv32.li 3 : !riscv.reg
     %0 = riscv.mv %one : (!riscv.reg) -> !riscv.reg
     riscv_cf.bge %0 : !riscv.reg, %three : !riscv.reg, ^bb1(%0 : !riscv.reg), ^bb0(%0 : !riscv.reg)
 ^bb0(%i : !riscv.reg):
@@ -15,8 +15,8 @@ riscv_func.func @at_least_once() {
     riscv_func.return
 }
 riscv_func.func @never() {
-    %one = riscv.li 1 : !riscv.reg
-    %three = riscv.li 3 : !riscv.reg
+    %one = rv32.li 1 : !riscv.reg
+    %three = rv32.li 3 : !riscv.reg
     %0 = riscv.mv %one : (!riscv.reg) -> !riscv.reg
     riscv_cf.bge %three : !riscv.reg, %one : !riscv.reg, ^bb1(%0 : !riscv.reg), ^bb0(%0 : !riscv.reg)
 ^bb0(%i : !riscv.reg):
@@ -30,8 +30,8 @@ riscv_func.func @never() {
 }
 
 // CHECK:       riscv_func.func @at_least_once() {
-// CHECK-NEXT:    %one = riscv.li 1 : !riscv.reg
-// CHECK-NEXT:    %three = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:    %one = rv32.li 1 : !riscv.reg
+// CHECK-NEXT:    %three = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:    %0 = riscv.mv %one : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv_cf.branch ^bb0(%0 : !riscv.reg) attributes {comment = "Constant folded riscv_cf.bge"}
 // CHECK-NEXT:  ^bb0(%i : !riscv.reg):
@@ -45,7 +45,7 @@ riscv_func.func @never() {
 // CHECK-NEXT:  }
 
 // CHECK-NEXT:  riscv_func.func @never() {
-// CHECK-NEXT:    %one = riscv.li 1 : !riscv.reg
+// CHECK-NEXT:    %one = rv32.li 1 : !riscv.reg
 // CHECK-NEXT:    %0 = riscv.mv %one : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv_cf.j ^bb0(%0 : !riscv.reg) attributes {comment = "Constant folded riscv_cf.bge"}
 // CHECK-NEXT:  ^bb0(%1 : !riscv.reg):
diff --git a/tests/filecheck/dialects/riscv_func/lower_riscv_func.mlir b/tests/filecheck/dialects/riscv_func/lower_riscv_func.mlir
index 55558426be..874c87c030 100644
--- a/tests/filecheck/dialects/riscv_func/lower_riscv_func.mlir
+++ b/tests/filecheck/dialects/riscv_func/lower_riscv_func.mlir
@@ -3,18 +3,18 @@
 "builtin.module"() ({
 // CHECK:      builtin.module {
 
-    %file = riscv.li 0 : !riscv.reg<s0>
+    %file = rv32.li 0 : !riscv.reg<s0>
     %success = "riscv_func.syscall"(%file) {"syscall_num" = 64 : i32}: (!riscv.reg<s0>) -> !riscv.reg<s1>
-// CHECK-NEXT:     %file = riscv.li 0 : !riscv.reg<s0>
+// CHECK-NEXT:     %file = rv32.li 0 : !riscv.reg<s0>
 // CHECK-NEXT:     %{{.+}} = riscv.mv %{{.+}} : (!riscv.reg<s0>) -> !riscv.reg<a0>
-// CHECK-NEXT:     %{{.+}} = riscv.li 64 : !riscv.reg<a7>
+// CHECK-NEXT:     %{{.+}} = rv32.li 64 : !riscv.reg<a7>
 // CHECK-NEXT:     riscv.ecall
 // CHECK-NEXT:     %{{.+}} = riscv.get_register : !riscv.reg<a0>
 // CHECK-NEXT:     %{{.+}} = riscv.mv %{{.+}} : (!riscv.reg<a0>) -> !riscv.reg<s1>
 
 
     "riscv_func.syscall"() {"syscall_num" = 93 : i32} : () -> ()
-// CHECK-NEXT:     %{{.+}} = riscv.li 93 : !riscv.reg<a7>
+// CHECK-NEXT:     %{{.+}} = rv32.li 93 : !riscv.reg<a7>
 // CHECK-NEXT:     riscv.ecall
 
     riscv_func.func @main() {
@@ -43,12 +43,12 @@
 // CHECK-NEXT:   }
 
     riscv_func.func @get_one() {
-        %0 = riscv.li 1 : !riscv.reg
+        %0 = rv32.li 1 : !riscv.reg
         riscv_func.return %0 : !riscv.reg
     }
 
 // CHECK-NEXT:   riscv_func.func @get_one() {
-// CHECK-NEXT:       %{{\d+}} = riscv.li 1 : !riscv.reg
+// CHECK-NEXT:       %{{\d+}} = rv32.li 1 : !riscv.reg
 // CHECK-NEXT:       riscv_func.return %{{\d+}} : !riscv.reg
 // CHECK-NEXT:   }
 
diff --git a/tests/filecheck/dialects/riscv_func/lower_riscv_func_main.mlir b/tests/filecheck/dialects/riscv_func/lower_riscv_func_main.mlir
index 10a0f8d0f1..deb71052ff 100644
--- a/tests/filecheck/dialects/riscv_func/lower_riscv_func_main.mlir
+++ b/tests/filecheck/dialects/riscv_func/lower_riscv_func_main.mlir
@@ -8,7 +8,7 @@
     }
 
 // CHECK-NEXT:     riscv_func.func @main() {
-// CHECK-NEXT:         %{{.*}} = riscv.li 93 : !riscv.reg<a7>
+// CHECK-NEXT:         %{{.*}} = rv32.li 93 : !riscv.reg<a7>
 // CHECK-NEXT:         riscv.ecall
 // CHECK-NEXT:         riscv_func.return
 // CHECK-NEXT:     }
diff --git a/tests/filecheck/dialects/riscv_scf/loop_range_folding.mlir b/tests/filecheck/dialects/riscv_scf/loop_range_folding.mlir
index 2305c58471..f38aa5a00c 100644
--- a/tests/filecheck/dialects/riscv_scf/loop_range_folding.mlir
+++ b/tests/filecheck/dialects/riscv_scf/loop_range_folding.mlir
@@ -9,46 +9,46 @@
 
 riscv_scf.for %2 : !riscv.reg = %lb to %ub step %step {
     // mul by constant
-    %3 = riscv.li 3 : !riscv.reg
+    %3 = rv32.li 3 : !riscv.reg
     %4 = riscv.mul %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     // add with constant
-    %5 = riscv.li 5 : !riscv.reg
+    %5 = rv32.li 5 : !riscv.reg
     %6 = riscv.add %4, %5 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     "test.op"(%6) : (!riscv.reg) -> ()
 }
-// CHECK-NEXT:    %{{.*}} = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:    %{{.*}} = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:    %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-NEXT:    %{{.*}} = riscv.li 5 : !riscv.reg
+// CHECK-NEXT:    %{{.*}} = rv32.li 5 : !riscv.reg
 // CHECK-NEXT:    %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:    riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} {
-// CHECK-NEXT:      %{{.*}} = riscv.li 3 : !riscv.reg
-// CHECK-NEXT:      %{{.*}} = riscv.li 5 : !riscv.reg
+// CHECK-NEXT:      %{{.*}} = rv32.li 3 : !riscv.reg
+// CHECK-NEXT:      %{{.*}} = rv32.li 5 : !riscv.reg
 // CHECK-NEXT:      "test.op"(%{{.*}}) : (!riscv.reg) -> ()
 // CHECK-NEXT:    }
 
 // Don't fold
 riscv_scf.for %2 : !riscv.reg = %lb to %ub step %step {
     // Two uses of mul -> can't fold
-    %3 = riscv.li 3 : !riscv.reg
+    %3 = rv32.li 3 : !riscv.reg
     %4 = riscv.mul %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     "test.op"(%4, %2) : (!riscv.reg, !riscv.reg) -> ()
 }
 riscv_scf.for %2 : !riscv.reg = %lb to %ub step %step {
     // Two uses of add -> can't fold
-    %3 = riscv.li 3 : !riscv.reg
+    %3 = rv32.li 3 : !riscv.reg
     %4 = riscv.add %2, %3 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     "test.op"(%4, %2) : (!riscv.reg, !riscv.reg) -> ()
 }
 // CHECK-NEXT:    riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} {
-// CHECK-NEXT:      %{{.*}} = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:      %{{.*}} = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:      %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:      "test.op"(%{{.*}}, %{{.*}}) : (!riscv.reg, !riscv.reg) -> ()
 // CHECK-NEXT:    }
 // CHECK-NEXT:    riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} {
-// CHECK-NEXT:      %{{.*}} = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:      %{{.*}} = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:      %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:      "test.op"(%{{.*}}, %{{.*}}) : (!riscv.reg, !riscv.reg) -> ()
 // CHECK-NEXT:    }
diff --git a/tests/filecheck/dialects/riscv_scf/ops.mlir b/tests/filecheck/dialects/riscv_scf/ops.mlir
index 21c88a3006..942cdbbb65 100644
--- a/tests/filecheck/dialects/riscv_scf/ops.mlir
+++ b/tests/filecheck/dialects/riscv_scf/ops.mlir
@@ -1,9 +1,9 @@
 // RUN: XDSL_ROUNDTRIP
 
-%lb = "riscv.li"() {"immediate" = 0: i32} : () -> !riscv.reg
-%ub = "riscv.li"() {"immediate" = 100: i32} : () -> !riscv.reg
-%step = "riscv.li"() {"immediate" = 1: i32} : () -> !riscv.reg
-%acc = "riscv.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
+%lb = "rv32.li"() {"immediate" = 0: i32} : () -> !riscv.reg
+%ub = "rv32.li"() {"immediate" = 100: i32} : () -> !riscv.reg
+%step = "rv32.li"() {"immediate" = 1: i32} : () -> !riscv.reg
+%acc = "rv32.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
 riscv_scf.for %i : !riscv.reg = %lb to %ub step %step {
     riscv.addi %acc, 1 : (!riscv.reg<t0>) -> !riscv.reg<t0>
 }
@@ -21,10 +21,10 @@ riscv_scf.rof %j : !riscv.reg = %ub down to %lb step %step {
 }
 
 // CHECK:      builtin.module {
-// CHECK-NEXT:   %lb = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:   %ub = riscv.li 100 : !riscv.reg
-// CHECK-NEXT:   %step = riscv.li 1 : !riscv.reg
-// CHECK-NEXT:   %acc = riscv.li 0 : !riscv.reg<t0>
+// CHECK-NEXT:   %lb = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:   %ub = rv32.li 100 : !riscv.reg
+// CHECK-NEXT:   %step = rv32.li 1 : !riscv.reg
+// CHECK-NEXT:   %acc = rv32.li 0 : !riscv.reg<t0>
 // CHECK-NEXT:   riscv_scf.for %i : !riscv.reg = %lb to %ub step %step {
 // CHECK-NEXT:     %0 = riscv.addi %acc, 1 : (!riscv.reg<t0>) -> !riscv.reg<t0>
 // CHECK-NEXT:   }
diff --git a/tests/filecheck/dialects/riscv_scf/verification.mlir b/tests/filecheck/dialects/riscv_scf/verification.mlir
index 6641f808cc..153ff3ecad 100644
--- a/tests/filecheck/dialects/riscv_scf/verification.mlir
+++ b/tests/filecheck/dialects/riscv_scf/verification.mlir
@@ -2,10 +2,10 @@
 
 
 
-%lb = "riscv.li"() {"immediate" = 0: i32} : () -> !riscv.reg
-%ub = "riscv.li"() {"immediate" = 100: i32} : () -> !riscv.reg
-%step = "riscv.li"() {"immediate" = 1: i32} : () -> !riscv.reg
-%acc = "riscv.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
+%lb = "rv32.li"() {"immediate" = 0: i32} : () -> !riscv.reg
+%ub = "rv32.li"() {"immediate" = 100: i32} : () -> !riscv.reg
+%step = "rv32.li"() {"immediate" = 1: i32} : () -> !riscv.reg
+%acc = "rv32.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
 
 %i_last, %ub_last, %step_last = riscv_scf.while (%i0 = %lb, %step_arg0 = %step) : (!riscv.reg, !riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg, !riscv.reg) {
     %cond = riscv.slt %i0, %ub_arg0 : (!riscv.reg, !riscv.reg) -> !riscv.reg
diff --git a/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir b/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir
index fc449e99e3..20ab93572b 100644
--- a/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir
+++ b/tests/filecheck/dialects/snitch/snitch_to_riscv_lowering.mlir
@@ -1,37 +1,37 @@
 // RUN: xdsl-opt -p lower-snitch %s | filecheck %s
 builtin.module {
   %addr = "test.op"() : () -> !riscv.reg
-  %bound = riscv.li 9 : !riscv.reg
-  %stride = riscv.li 4 : !riscv.reg
-  %rep = riscv.li 0 : !riscv.reg
+  %bound = rv32.li 9 : !riscv.reg
+  %stride = rv32.li 4 : !riscv.reg
+  %rep = rv32.li 0 : !riscv.reg
   // SSR setup sequence for dimension 0
   "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 64 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 64 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %bound, %{{.*}} {comment = "dm 0 dim 0 bound"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 192 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 192 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %stride, %{{.*}} {comment = "dm 0 dim 0 stride"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 768 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 768 : !riscv.reg
   // riscv_snitch.scfgw %addr, %{{.*}} {comment = "dm 0 dim 0 source"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<0>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 896 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 896 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %addr, %{{.*}} {comment = "dm 0 dim 0 destination"} : (!riscv.reg, !riscv.reg) -> ()
   // SSR setup sequence for dimension 3
   "snitch.ssr_set_dimension_bound"(%bound) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 160 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 160 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %bound, %{{.*}} {comment = "dm 0 dim 3 bound"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_stride"(%stride) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 288 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 288 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %stride, %{{.*}} {comment = "dm 0 dim 3 stride"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_source"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 864 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 864 : !riscv.reg
   // riscv_snitch.scfgw %addr, %{{.*}} {comment = "dm 0 dim 3 source"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_dimension_destination"(%addr) {"dm" = #builtin.int<0>, "dimension" = #builtin.int<3>} : (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 992 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 992 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %addr, %{{.*}} {comment = "dm 0 dim 3 destination"} : (!riscv.reg, !riscv.reg) -> ()
   "snitch.ssr_set_stream_repetition"(%rep) {"dm" = #builtin.int<0>}: (!riscv.reg) -> ()
-  // CHECK: %{{.*}} = riscv.li 32 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 32 : !riscv.reg
   // CHECK-NEXT: riscv_snitch.scfgw %rep, %{{.*}} {comment = "dm 0 repeat"} : (!riscv.reg, !riscv.reg) -> ()
   // On/Off switching sequence
   "snitch.ssr_enable"() : () -> ()
diff --git a/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir b/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir
index baae3f5c5c..a44d652b28 100644
--- a/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir
+++ b/tests/filecheck/dialects/snitch_stream/convert_snitch_stream_to_snitch.mlir
@@ -16,34 +16,34 @@
 ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
     "test.op"() : () -> ()
 }) : (!riscv.reg, !riscv.reg, !riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<0>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<0>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_stream_repetition"(%{{.*}}) {dm = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 2 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 2 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<1>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<1>, dimension = #builtin.int<1>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 24 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 24 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<1>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<1>, dimension = #builtin.int<1>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_stream_repetition"(%{{.*}}) {dm = #builtin.int<1>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 2 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 3 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 4 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 5 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 2 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 3 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 4 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 5 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<2>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
@@ -52,12 +52,12 @@
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<2>, dimension = #builtin.int<2>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<2>, dimension = #builtin.int<3>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 480 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 160 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 40 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 480 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 160 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 40 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<2>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
@@ -70,7 +70,7 @@
 // CHECK-NEXT:  %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<2>, dimension = #builtin.int<3>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_stream_repetition"(%{{.*}}) {dm = #builtin.int<2>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%A) {dm = #builtin.int<0>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%B) {dm = #builtin.int<1>, dimension = #builtin.int<1>} : (!riscv.reg) -> ()
@@ -89,13 +89,13 @@
     "test.op"() : () -> ()
 }) : (!riscv.reg, !riscv.reg) -> ()
 
-// CHECK-NEXT:  %{{.*}} = riscv.li 2 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 2 : !riscv.reg
 // CHECK-NEXT:  %{{.*}} = riscv.addi %{{.*}}, -1 : (!riscv.reg) -> !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_bound"(%{{.*}}) {dm = #builtin.int<31>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_dimension_stride"(%{{.*}}) {dm = #builtin.int<31>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:  %{{.*}} = riscv.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:  %{{.*}} = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  "snitch.ssr_set_stream_repetition"(%{{.*}}) {dm = #builtin.int<31>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  "snitch.ssr_set_dimension_source"(%A) {dm = #builtin.int<0>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
 // CHECK-NEXT:  "snitch.ssr_set_dimension_destination"(%B) {dm = #builtin.int<1>, dimension = #builtin.int<0>} : (!riscv.reg) -> ()
diff --git a/tests/filecheck/dialects/snitch_stream/ops.mlir b/tests/filecheck/dialects/snitch_stream/ops.mlir
index 40d9698060..4cd1c260c2 100644
--- a/tests/filecheck/dialects/snitch_stream/ops.mlir
+++ b/tests/filecheck/dialects/snitch_stream/ops.mlir
@@ -9,7 +9,7 @@ snitch_stream.streaming_region {
     ]
 } ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
 ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
-    %c5 = riscv.li 5 : !riscv.reg
+    %c5 = rv32.li 5 : !riscv.reg
     riscv_snitch.frep_outer %c5 {
         %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
         %b = riscv_snitch.read from %b_stream : !riscv.freg<ft1>
@@ -27,7 +27,7 @@ snitch_stream.streaming_region {
 // CHECK-NEXT:      ]
 // CHECK-NEXT:    } ins(%X, %Y : !riscv.reg, !riscv.reg) outs(%Z : !riscv.reg) {
 // CHECK-NEXT:    ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
-// CHECK-NEXT:      %c5 = riscv.li 5 : !riscv.reg
+// CHECK-NEXT:      %c5 = rv32.li 5 : !riscv.reg
 // CHECK-NEXT:      riscv_snitch.frep_outer %c5 {
 // CHECK-NEXT:        %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
 // CHECK-NEXT:        %b = riscv_snitch.read from %b_stream : !riscv.freg<ft1>
@@ -39,7 +39,7 @@ snitch_stream.streaming_region {
 // CHECK-GENERIC:         %X, %Y, %Z = "test.op"() : () -> (!riscv.reg, !riscv.reg, !riscv.reg)
 // CHECK-GENERIC-NEXT:    "snitch_stream.streaming_region"(%X, %Y, %Z) <{stride_patterns = [#snitch_stream.stride_pattern<ub = [8, 16], strides = [128, 8]>], operandSegmentSizes = array<i32: 2, 1>}> ({
 // CHECK-GENERIC-NEXT:    ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
-// CHECK-GENERIC-NEXT:      %c5 = "riscv.li"() {immediate = 5 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %c5 = "rv32.li"() {immediate = 5 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      "riscv_snitch.frep_outer"(%c5) ({
 // CHECK-GENERIC-NEXT:        %a = "riscv_snitch.read"(%a_stream) : (!snitch.readable<!riscv.freg<ft0>>) -> !riscv.freg<ft0>
 // CHECK-GENERIC-NEXT:        %b = "riscv_snitch.read"(%b_stream) : (!snitch.readable<!riscv.freg<ft1>>) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/dialects/x86_scf/x86_scf_invalid.mlir b/tests/filecheck/dialects/x86_scf/x86_scf_invalid.mlir
index 6641f808cc..153ff3ecad 100644
--- a/tests/filecheck/dialects/x86_scf/x86_scf_invalid.mlir
+++ b/tests/filecheck/dialects/x86_scf/x86_scf_invalid.mlir
@@ -2,10 +2,10 @@
 
 
 
-%lb = "riscv.li"() {"immediate" = 0: i32} : () -> !riscv.reg
-%ub = "riscv.li"() {"immediate" = 100: i32} : () -> !riscv.reg
-%step = "riscv.li"() {"immediate" = 1: i32} : () -> !riscv.reg
-%acc = "riscv.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
+%lb = "rv32.li"() {"immediate" = 0: i32} : () -> !riscv.reg
+%ub = "rv32.li"() {"immediate" = 100: i32} : () -> !riscv.reg
+%step = "rv32.li"() {"immediate" = 1: i32} : () -> !riscv.reg
+%acc = "rv32.li"() {"immediate" = 0 : i32} : () -> !riscv.reg<t0>
 
 %i_last, %ub_last, %step_last = riscv_scf.while (%i0 = %lb, %step_arg0 = %step) : (!riscv.reg, !riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg, !riscv.reg) {
     %cond = riscv.slt %i0, %ub_arg0 : (!riscv.reg, !riscv.reg) -> !riscv.reg
diff --git a/tests/filecheck/projects/riscv-backend-paper/add_snitch_stream.mlir b/tests/filecheck/projects/riscv-backend-paper/add_snitch_stream.mlir
index d57ad8af47..018062548e 100644
--- a/tests/filecheck/projects/riscv-backend-paper/add_snitch_stream.mlir
+++ b/tests/filecheck/projects/riscv-backend-paper/add_snitch_stream.mlir
@@ -10,15 +10,15 @@ builtin.module {
     riscv.directive ".word" "0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0"
   }
   riscv_func.func public @main() {
-    %A = riscv.li "a" : !riscv.reg
-    %B = riscv.li "b" : !riscv.reg
-    %C = riscv.li "c" : !riscv.reg
+    %A = rv32.li "a" : !riscv.reg
+    %B = rv32.li "b" : !riscv.reg
+    %C = rv32.li "c" : !riscv.reg
     "snitch_stream.streaming_region"(%A, %B, %C) <{
       "stride_patterns" = [#snitch_stream.stride_pattern<ub = [2, 3], strides = [24, 8]>],
       operandSegmentSizes = array<i32: 2, 1>
     }> ({
     ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.readable<!riscv.freg<ft1>>, %c_stream : !snitch.writable<!riscv.freg<ft2>>):
-        %c5 = riscv.li 5 : !riscv.reg
+        %c5 = rv32.li 5 : !riscv.reg
         riscv_snitch.frep_outer %c5 {
             %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
             %b = riscv_snitch.read from %b_stream : !riscv.freg<ft1>
diff --git a/tests/filecheck/projects/riscv-backend-paper/bottom_up_f32.mlir b/tests/filecheck/projects/riscv-backend-paper/bottom_up_f32.mlir
index 2b74d5d5c1..c3bd9277ba 100644
--- a/tests/filecheck/projects/riscv-backend-paper/bottom_up_f32.mlir
+++ b/tests/filecheck/projects/riscv-backend-paper/bottom_up_f32.mlir
@@ -169,9 +169,9 @@ func.func public @pooling_nchw_max_d1_s2_3x3(
         ]
       } ins(%X_1 : !riscv.reg) outs(%Y_1 : !riscv.reg) {
       ^bb0(%x : !snitch.readable<!riscv.freg<ft0>>, %0 : !snitch.writable<!riscv.freg<ft1>>):
-        %c128 = riscv.li 128 : !riscv.reg
-        %c0 = riscv.li 0 : !riscv.reg
-        %c1 = riscv.li 1 : !riscv.reg
+        %c128 = rv32.li 128 : !riscv.reg
+        %c0 = rv32.li 0 : !riscv.reg
+        %c1 = rv32.li 1 : !riscv.reg
         riscv_scf.for %i : !riscv.reg = %c0 to %c128 step %c1 {
           %x_1 = riscv_snitch.read from %x : !riscv.freg<ft0>
           %y = riscv_snitch.vfmax.s %x_1, %zero_vector : (!riscv.freg<ft0>, !riscv.freg) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/projects/riscv-backend-paper/ddot_regalloc.mlir b/tests/filecheck/projects/riscv-backend-paper/ddot_regalloc.mlir
index 6a0f8389df..bce5eebe9f 100644
--- a/tests/filecheck/projects/riscv-backend-paper/ddot_regalloc.mlir
+++ b/tests/filecheck/projects/riscv-backend-paper/ddot_regalloc.mlir
@@ -6,9 +6,9 @@ riscv.assembly_section ".text" {
         %Y_moved = riscv.mv %Y : (!riscv.reg<a1>) -> !riscv.reg
         %Z_moved = riscv.mv %Z : (!riscv.reg<a2>) -> !riscv.reg
         %init = riscv.fld %Z_moved, 0 : (!riscv.reg) -> !riscv.freg
-        %lb = riscv.li 0 : !riscv.reg
-        %ub = riscv.li 1024 : !riscv.reg
-        %c8 = riscv.li 8 : !riscv.reg
+        %lb = rv32.li 0 : !riscv.reg
+        %ub = rv32.li 1024 : !riscv.reg
+        %c8 = rv32.li 8 : !riscv.reg
         %res = riscv_scf.for %i : !riscv.reg = %lb to %ub step %c8 iter_args(%acc_in = %init) -> (!riscv.freg) {
             %x_ptr = riscv.add %X_moved, %i : (!riscv.reg, !riscv.reg) -> !riscv.reg
             %x = riscv.fld %x_ptr, 0 : (!riscv.reg) -> !riscv.freg
@@ -30,9 +30,9 @@ riscv.assembly_section ".text" {
 // CHECK-NEXT:          %Y_moved = riscv.mv %Y : (!riscv.reg<a1>) -> !riscv.reg<t1>
 // CHECK-NEXT:          %Z_moved = riscv.mv %Z : (!riscv.reg<a2>) -> !riscv.reg<t0>
 // CHECK-NEXT:          %init = riscv.fld %Z_moved, 0 : (!riscv.reg<t0>) -> !riscv.freg<ft0>
-// CHECK-NEXT:          %lb = riscv.li 0 : !riscv.reg<zero>
-// CHECK-NEXT:          %ub = riscv.li 1024 : !riscv.reg<t4>
-// CHECK-NEXT:          %c8 = riscv.li 8 : !riscv.reg<t5>
+// CHECK-NEXT:          %lb = rv32.li 0 : !riscv.reg<zero>
+// CHECK-NEXT:          %ub = rv32.li 1024 : !riscv.reg<t4>
+// CHECK-NEXT:          %c8 = rv32.li 8 : !riscv.reg<t5>
 // CHECK-NEXT:          %res = riscv_scf.for %i : !riscv.reg<t3> = %lb to %ub step %c8 iter_args(%acc_in = %init) -> (!riscv.freg<ft0>) {
 // CHECK-NEXT:              %x_ptr = riscv.add %X_moved, %i : (!riscv.reg<t2>, !riscv.reg<t3>) -> !riscv.reg<t6>
 // CHECK-NEXT:              %x = riscv.fld %x_ptr, 0 : (!riscv.reg<t6>) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/projects/riscv-backend-paper/relu_snitch_stream.mlir b/tests/filecheck/projects/riscv-backend-paper/relu_snitch_stream.mlir
index 8d68597c71..60c0bb2e04 100644
--- a/tests/filecheck/projects/riscv-backend-paper/relu_snitch_stream.mlir
+++ b/tests/filecheck/projects/riscv-backend-paper/relu_snitch_stream.mlir
@@ -10,12 +10,12 @@ builtin.module {
     riscv.directive ".word" "0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0,0x0"
   }
   riscv_func.func public @main() attributes {p2align = 2 : i8} {
-    %A = riscv.li "a" : !riscv.reg
-    %B = riscv.li "b" : !riscv.reg
+    %A = rv32.li "a" : !riscv.reg
+    %B = rv32.li "b" : !riscv.reg
     %zero = riscv.get_register : !riscv.reg<sp>
-    %zero_1 = riscv.li 0 : !riscv.reg
+    %zero_1 = rv32.li 0 : !riscv.reg
     riscv.sw %zero, %zero_1, -4 : (!riscv.reg<sp>, !riscv.reg) -> ()
-    %zero_2 = riscv.li 0 : !riscv.reg
+    %zero_2 = rv32.li 0 : !riscv.reg
     riscv.sw %zero, %zero_2, -8 : (!riscv.reg<sp>, !riscv.reg) -> ()
     %zero_3 = riscv.fld %zero, -8 : (!riscv.reg<sp>) -> !riscv.freg
     "snitch_stream.streaming_region"(%A, %B) <{
@@ -23,7 +23,7 @@ builtin.module {
       operandSegmentSizes = array<i32: 1, 1>
     }> ({
     ^bb0(%a_stream : !snitch.readable<!riscv.freg<ft0>>, %b_stream : !snitch.writable<!riscv.freg<ft1>>):
-      %c5 = riscv.li 5 : !riscv.reg
+      %c5 = rv32.li 5 : !riscv.reg
       riscv_snitch.frep_outer %c5 {
         %a = riscv_snitch.read from %a_stream : !riscv.freg<ft0>
         %b = riscv.fmax.d %a, %zero_3 : (!riscv.freg<ft0>, !riscv.freg) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/runner/riscv.mlir b/tests/filecheck/runner/riscv.mlir
index 8360f082d2..1d763771a8 100644
--- a/tests/filecheck/runner/riscv.mlir
+++ b/tests/filecheck/runner/riscv.mlir
@@ -7,8 +7,8 @@ riscv_func.func @putchar(!riscv.reg) -> !riscv.reg
 riscv_func.func @free(!riscv.reg) -> ()
 
 riscv_func.func @main() -> () {
-    %33 = riscv.li 33 : !riscv.reg
-    %newline = riscv.li 10 : !riscv.reg
+    %33 = rv32.li 33 : !riscv.reg
+    %newline = rv32.li 10 : !riscv.reg
     %ptr = riscv_func.call @malloc(%33) : (!riscv.reg) -> !riscv.reg
     riscv.sw %ptr, %33, 0 : (!riscv.reg, !riscv.reg) -> ()
 
diff --git a/tests/filecheck/runner/riscv_scf.mlir b/tests/filecheck/runner/riscv_scf.mlir
index 121f899346..7dd6512549 100644
--- a/tests/filecheck/runner/riscv_scf.mlir
+++ b/tests/filecheck/runner/riscv_scf.mlir
@@ -3,9 +3,9 @@
 
 builtin.module {
   func.func @sum_to(%0 : !riscv.reg) -> !riscv.reg {
-    %1 = riscv.li 0 : !riscv.reg
-    %2 = riscv.li 1 : !riscv.reg
-    %3 = riscv.li 0 : !riscv.reg
+    %1 = rv32.li 0 : !riscv.reg
+    %2 = rv32.li 1 : !riscv.reg
+    %3 = rv32.li 0 : !riscv.reg
     %4 = riscv_scf.for %5 : !riscv.reg = %1 to %0 step %2 iter_args(%6 = %3) -> (!riscv.reg) {
       %7 = riscv.add %5, %6 : (!riscv.reg, !riscv.reg) -> !riscv.reg
       riscv_scf.yield %7 : !riscv.reg
@@ -13,7 +13,7 @@ builtin.module {
     func.return %4 : !riscv.reg
   }
   func.func @main() -> !riscv.reg {
-    %c5 = riscv.li 5 : !riscv.reg
+    %c5 = rv32.li 5 : !riscv.reg
     %res = func.call @sum_to(%c5) : (!riscv.reg) -> !riscv.reg
     return %res : !riscv.reg
   }
diff --git a/tests/filecheck/transforms/convert_riscv_to_llvm.mlir b/tests/filecheck/transforms/convert_riscv_to_llvm.mlir
index 57873f19be..df63169281 100644
--- a/tests/filecheck/transforms/convert_riscv_to_llvm.mlir
+++ b/tests/filecheck/transforms/convert_riscv_to_llvm.mlir
@@ -2,8 +2,8 @@
 // RUN: xdsl-opt %s -p convert-riscv-to-llvm,reconcile-unrealized-casts,dce | filecheck %s --check-prefix COMPACT
 
 
-%reg = riscv.li 0 : !riscv.reg
-%a0 = riscv.li 0 : !riscv.reg<a0>
+%reg = rv32.li 0 : !riscv.reg
+%a0 = rv32.li 0 : !riscv.reg<a0>
 %x0 = riscv.get_register : !riscv.reg<zero>
 
 // CHECK: builtin.module {
@@ -15,7 +15,7 @@
 
 // standard risc-v instructions
 
-%li = riscv.li 0 : !riscv.reg
+%li = rv32.li 0 : !riscv.reg
 // CHECK-NEXT:  %li = "llvm.inline_asm"() <{asm_string = "li $0, 0", constraints = "=r", asm_dialect = 0 : i64, tail_call_kind = #llvm.tailcallkind<none>}> : () -> i32
 // CHECK-NEXT:  %li_1 = builtin.unrealized_conversion_cast %li : i32 to !riscv.reg
 
@@ -33,7 +33,7 @@
 
 // named riscv registers:
 
-%li_named = riscv.li 0 : !riscv.reg<a0>
+%li_named = rv32.li 0 : !riscv.reg<a0>
 // CHECK-NEXT:  %li_named = "llvm.inline_asm"() <{asm_string = "li $0, 0", constraints = "=r", asm_dialect = 0 : i64, tail_call_kind = #llvm.tailcallkind<none>}> : () -> i32
 // CHECK-NEXT:  %li_named_1 = builtin.unrealized_conversion_cast %li_named : i32 to !riscv.reg<a0>
 
diff --git a/tests/filecheck/transforms/individual_rewrite/riscv.mlir b/tests/filecheck/transforms/individual_rewrite/riscv.mlir
index fac82b4921..fd11b75452 100644
--- a/tests/filecheck/transforms/individual_rewrite/riscv.mlir
+++ b/tests/filecheck/transforms/individual_rewrite/riscv.mlir
@@ -1,16 +1,16 @@
 // RUN:xdsl-opt %s -p 'apply-individual-rewrite{matched_operation_index=4 operation_name="riscv.add" pattern_name="AddImmediates"}'| filecheck %s
 
-%a = riscv.li 1 : !riscv.reg
-%b = riscv.li 2 : !riscv.reg
-%c = riscv.li 3 : !riscv.reg
+%a = rv32.li 1 : !riscv.reg
+%b = rv32.li 2 : !riscv.reg
+%c = rv32.li 3 : !riscv.reg
 %d = riscv.add %a, %b : (!riscv.reg, !riscv.reg) -> !riscv.reg
 %e = riscv.add %b, %c : (!riscv.reg, !riscv.reg) -> !riscv.reg
 
 
 //CHECK:         builtin.module {
-// CHECK-NEXT:       %a = riscv.li 1 : !riscv.reg
-// CHECK-NEXT:       %b = riscv.li 2 : !riscv.reg
-// CHECK-NEXT:       %c = riscv.li 3 : !riscv.reg
-// CHECK-NEXT:       %d = riscv.li 3 : !riscv.reg
+// CHECK-NEXT:       %a = rv32.li 1 : !riscv.reg
+// CHECK-NEXT:       %b = rv32.li 2 : !riscv.reg
+// CHECK-NEXT:       %c = rv32.li 3 : !riscv.reg
+// CHECK-NEXT:       %d = rv32.li 3 : !riscv.reg
 // CHECK-NEXT:       %e = riscv.add %b, %c : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-NEXT:     }
diff --git a/tests/filecheck/transforms/riscv-allocate-infinite-registers.mlir b/tests/filecheck/transforms/riscv-allocate-infinite-registers.mlir
index 470f1b1252..d6e198926d 100644
--- a/tests/filecheck/transforms/riscv-allocate-infinite-registers.mlir
+++ b/tests/filecheck/transforms/riscv-allocate-infinite-registers.mlir
@@ -2,10 +2,10 @@
 
 builtin.module {
   riscv_func.func @main() {
-    %zero = riscv.li 0 : !riscv.reg<zero>
+    %zero = rv32.li 0 : !riscv.reg<zero>
     // j_1 shouldn't be allocated to t0
-    %0 = riscv.li 6 : !riscv.reg<j_1>
-    %1 = riscv.li 5 : !riscv.reg<t0>
+    %0 = rv32.li 6 : !riscv.reg<j_1>
+    %1 = rv32.li 5 : !riscv.reg<t0>
     %2 = riscv.add %0, %1 : (!riscv.reg<j_1>, !riscv.reg<t0>) -> !riscv.reg<j_0>
     // floats work
     %3 = riscv.fcvt.s.w %1 : (!riscv.reg<t0>) -> !riscv.freg<fj_0>
@@ -17,9 +17,9 @@ builtin.module {
 }
 // CHECK:       builtin.module {
 // CHECK-NEXT:    riscv_func.func @main() {
-// CHECK-NEXT:      %zero = riscv.li 0 : !riscv.reg<zero>
-// CHECK-NEXT:      %0 = riscv.li 6 : !riscv.reg<t1>
-// CHECK-NEXT:      %1 = riscv.li 5 : !riscv.reg<t0>
+// CHECK-NEXT:      %zero = rv32.li 0 : !riscv.reg<zero>
+// CHECK-NEXT:      %0 = rv32.li 6 : !riscv.reg<t1>
+// CHECK-NEXT:      %1 = rv32.li 5 : !riscv.reg<t0>
 // CHECK-NEXT:      %2 = riscv.add %0, %1 : (!riscv.reg<t1>, !riscv.reg<t0>) -> !riscv.reg<t2>
 // CHECK-NEXT:      %3 = riscv.fcvt.s.w %1 : (!riscv.reg<t0>) -> !riscv.freg<ft0>
 // CHECK-NEXT:      %4 = riscv.fcvt.s.w %0 : (!riscv.reg<t1>) -> !riscv.freg<ft1>
diff --git a/tests/filecheck/transforms/riscv_cse.mlir b/tests/filecheck/transforms/riscv_cse.mlir
index dfb62c7cd4..78f8ecb337 100644
--- a/tests/filecheck/transforms/riscv_cse.mlir
+++ b/tests/filecheck/transforms/riscv_cse.mlir
@@ -1,28 +1,28 @@
 // RUN: xdsl-opt -p cse --split-input-file %s | filecheck %s
 
-%a8 = riscv.li 8 : !riscv.reg
-%b8 = riscv.li 8 : !riscv.reg
-%c8 = riscv.li 8 : !riscv.reg
+%a8 = rv32.li 8 : !riscv.reg
+%b8 = rv32.li 8 : !riscv.reg
+%c8 = rv32.li 8 : !riscv.reg
 
-%a7 = riscv.li 7 : !riscv.reg
-%b7 = riscv.li 7 : !riscv.reg
+%a7 = rv32.li 7 : !riscv.reg
+%b7 = rv32.li 7 : !riscv.reg
 
 riscv.assembly_section ".text" {
-    %d8 = riscv.li 8 : !riscv.reg
-    %e8 = riscv.li 8 : !riscv.reg
+    %d8 = rv32.li 8 : !riscv.reg
+    %e8 = rv32.li 8 : !riscv.reg
 
     "test.op"(%d8, %e8) : (!riscv.reg, !riscv.reg) -> ()
 }
 
-%f8 = riscv.li 8 : !riscv.reg
+%f8 = rv32.li 8 : !riscv.reg
 
 "test.op"(%a8, %b8, %c8, %a7, %a7, %b7, %f8) : (!riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg) -> ()
 
 // CHECK:       builtin.module {
-// CHECK-NEXT:    %a8 = riscv.li 8 : !riscv.reg
-// CHECK-NEXT:    %a7 = riscv.li 7 : !riscv.reg
+// CHECK-NEXT:    %a8 = rv32.li 8 : !riscv.reg
+// CHECK-NEXT:    %a7 = rv32.li 7 : !riscv.reg
 // CHECK-NEXT:    riscv.assembly_section ".text" {
-// CHECK-NEXT:      %d8 = riscv.li 8 : !riscv.reg
+// CHECK-NEXT:      %d8 = rv32.li 8 : !riscv.reg
 // CHECK-NEXT:      "test.op"(%d8, %d8) : (!riscv.reg, !riscv.reg) -> ()
 // CHECK-NEXT:    }
 // CHECK-NEXT:    "test.op"(%a8, %a8, %a8, %a7, %a7, %a7, %a8) : (!riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg, !riscv.reg) -> ()
@@ -32,17 +32,17 @@ riscv.assembly_section ".text" {
 
 %0, %1, %2 = "test.op"() : () -> (!snitch.readable<!riscv.freg>, !snitch.readable<!riscv.freg>, !riscv.reg)
 
-%8 = riscv.li 8 : !riscv.reg
-%9 = riscv.li 8 : !riscv.reg
-%10 = riscv.li 8 : !riscv.reg
-%11 = riscv.li 0 : !riscv.reg
-%12 = riscv.li 1 : !riscv.reg
+%8 = rv32.li 8 : !riscv.reg
+%9 = rv32.li 8 : !riscv.reg
+%10 = rv32.li 8 : !riscv.reg
+%11 = rv32.li 0 : !riscv.reg
+%12 = rv32.li 1 : !riscv.reg
 riscv_scf.for %13 : !riscv.reg = %11 to %8 step %12 {
     riscv_scf.for %14 : !riscv.reg = %11 to %9 step %12 {
-        %15 = riscv.li 8 : !riscv.reg
+        %15 = rv32.li 8 : !riscv.reg
         %16 = riscv.mul %15, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg
         %17 = riscv.add %16, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-        %18 = riscv.li 8 : !riscv.reg
+        %18 = rv32.li 8 : !riscv.reg
         %19 = riscv.mul %17, %18 {"comment" = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
         %20 = riscv.add %2, %19 : (!riscv.reg, !riscv.reg) -> !riscv.reg
         %21 = riscv.fld %20, 0 {"comment" = "load double from memref of shape (8, 8)"} : (!riscv.reg) -> !riscv.freg
@@ -54,10 +54,10 @@ riscv_scf.for %13 : !riscv.reg = %11 to %8 step %12 {
             %29 = riscv.fadd.d %21, %28 : (!riscv.freg, !riscv.freg) -> !riscv.freg
             riscv_scf.yield %29 : !riscv.freg
         }
-        %30 = riscv.li 8 : !riscv.reg
+        %30 = rv32.li 8 : !riscv.reg
         %31 = riscv.mul %30, %13 : (!riscv.reg, !riscv.reg) -> !riscv.reg
         %32 = riscv.add %31, %14 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-        %33 = riscv.li 8 : !riscv.reg
+        %33 = rv32.li 8 : !riscv.reg
         %34 = riscv.mul %32, %33 {"comment" = "multiply by element size"} : (!riscv.reg, !riscv.reg) -> !riscv.reg
         %35 = riscv.add %2, %34 : (!riscv.reg, !riscv.reg) -> !riscv.reg
         riscv.fsd %35, %23, 0 {"comment" = "store double value to memref of shape (8, 8)"} : (!riscv.reg, !riscv.freg) -> ()
@@ -66,9 +66,9 @@ riscv_scf.for %13 : !riscv.reg = %11 to %8 step %12 {
 
 // CHECK:       builtin.module {
 // CHECK-NEXT:    %{{.*}}, %{{.*}}, %{{.*}} = "test.op"() : () -> (!snitch.readable<!riscv.freg>, !snitch.readable<!riscv.freg>, !riscv.reg)
-// CHECK-NEXT:    %{{.*}} = riscv.li 8 : !riscv.reg
-// CHECK-NEXT:    %{{.*}} = riscv.li 0 : !riscv.reg
-// CHECK-NEXT:    %{{.*}} = riscv.li 1 : !riscv.reg
+// CHECK-NEXT:    %{{.*}} = rv32.li 8 : !riscv.reg
+// CHECK-NEXT:    %{{.*}} = rv32.li 0 : !riscv.reg
+// CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
 // CHECK-NEXT:    riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} {
 // CHECK-NEXT:      riscv_scf.for %{{.*}} : !riscv.reg = %{{.*}} to %{{.*}} step %{{.*}} {
 // CHECK-NEXT:        %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
diff --git a/tests/filecheck/transforms/snitch-allocate-registers.mlir b/tests/filecheck/transforms/snitch-allocate-registers.mlir
index 819d10e78f..d1a641a489 100644
--- a/tests/filecheck/transforms/snitch-allocate-registers.mlir
+++ b/tests/filecheck/transforms/snitch-allocate-registers.mlir
@@ -7,7 +7,7 @@
     operandSegmentSizes = array<i32: 2, 1>
 }> ({
 ^bb0(%s0 : !snitch.readable<!riscv.freg>, %s1 : !snitch.readable<!riscv.freg>, %s2 : !snitch.writable<!riscv.freg>):
-    %c5 = riscv.li 5 : !riscv.reg
+    %c5 = rv32.li 5 : !riscv.reg
     riscv_snitch.frep_outer %c5 {
         %x = riscv_snitch.read from %s0 : !riscv.freg
         %y = riscv_snitch.read from %s1 : !riscv.freg
@@ -25,7 +25,7 @@
 // CHECK-NEXT:      ]
 // CHECK-NEXT:    } ins(%ptr0, %ptr1 : !riscv.reg, !riscv.reg) outs(%ptr2 : !riscv.reg) {
 // CHECK-NEXT:    ^{{.*}}(%s0 : !snitch.readable<!riscv.freg<ft0>>, %s1 : !snitch.readable<!riscv.freg<ft1>>, %s2 : !snitch.writable<!riscv.freg<ft2>>):
-// CHECK-NEXT:      %c5 = riscv.li 5 : !riscv.reg
+// CHECK-NEXT:      %c5 = rv32.li 5 : !riscv.reg
 // CHECK-NEXT:      riscv_snitch.frep_outer %c5 {
 // CHECK-NEXT:        %x = riscv_snitch.read from %s0 : !riscv.freg<ft0>
 // CHECK-NEXT:        %y = riscv_snitch.read from %s1 : !riscv.freg<ft1>
diff --git a/tests/filecheck/with-riscemu/riscv_emulation.mlir b/tests/filecheck/with-riscemu/riscv_emulation.mlir
index e5e07159b9..eb31d72ebc 100644
--- a/tests/filecheck/with-riscemu/riscv_emulation.mlir
+++ b/tests/filecheck/with-riscemu/riscv_emulation.mlir
@@ -2,11 +2,11 @@
 
 builtin.module {
   riscv_func.func public @main() {
-    %0 = riscv.li 6 : !riscv.reg<j_0>
-    %1 = riscv.li 7 : !riscv.reg<j_1>
+    %0 = rv32.li 6 : !riscv.reg<j_0>
+    %1 = rv32.li 7 : !riscv.reg<j_1>
     %2 = riscv.mul %0, %1 : (!riscv.reg<j_0>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
     riscv.custom_assembly_instruction %2 {"instruction_name" = "print"} : (!riscv.reg<j_2>) -> ()
-    %3 = riscv.li 93 : !riscv.reg<a7>
+    %3 = rv32.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
   }
@@ -18,12 +18,12 @@ builtin.module {
 
 builtin.module {
   riscv_func.func public @main() {
-    %0 = riscv.li 3 : !riscv.reg<a0>
-    %1 = riscv.li 2 : !riscv.reg<a1>
-    %2 = riscv.li 1 : !riscv.reg<a2>
+    %0 = rv32.li 3 : !riscv.reg<a0>
+    %1 = rv32.li 2 : !riscv.reg<a1>
+    %2 = rv32.li 1 : !riscv.reg<a2>
     %xyz = riscv_func.call @muladd(%0, %1, %2) : (!riscv.reg<a0>, !riscv.reg<a1>, !riscv.reg<a2>) -> !riscv.reg<a0>
     riscv.custom_assembly_instruction %xyz {"instruction_name" = "print"} : (!riscv.reg<a0>) -> ()
-    %4 = riscv.li 93 : !riscv.reg<a7>
+    %4 = rv32.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
   }
@@ -71,11 +71,11 @@ builtin.module {
 
 builtin.module {
   riscv_func.func public @main() {
-    %0 = riscv.li 6 : !riscv.reg<j_0>
-    %1 = riscv.li 7 : !riscv.reg<j_1>
+    %0 = rv32.li 6 : !riscv.reg<j_0>
+    %1 = rv32.li 7 : !riscv.reg<j_1>
     %2 = riscv.mul %0, %1 : (!riscv.reg<j_0>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
     riscv_debug.printf %0, %1, %2 "{} x {} = {}" : (!riscv.reg<j_0>, !riscv.reg<j_1>, !riscv.reg<j_2>) -> ()
-    %3 = riscv.li 93 : !riscv.reg<a7>
+    %3 = rv32.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
   }
diff --git a/tests/filecheck/with-riscemu/rvscf_lowering_emu.mlir b/tests/filecheck/with-riscemu/rvscf_lowering_emu.mlir
index 49795804c5..ad8c46c0ce 100644
--- a/tests/filecheck/with-riscemu/rvscf_lowering_emu.mlir
+++ b/tests/filecheck/with-riscemu/rvscf_lowering_emu.mlir
@@ -3,17 +3,17 @@
 
 builtin.module {
   riscv_func.func @main() {
-    %0 = riscv.li 0 : !riscv.reg<a0>
-    %1 = riscv.li 10 : !riscv.reg<a1>
-    %2 = riscv.li 1 : !riscv.reg<a2>
-    %3 = riscv.li 0 : !riscv.reg<a3>
+    %0 = rv32.li 0 : !riscv.reg<a0>
+    %1 = rv32.li 10 : !riscv.reg<a1>
+    %2 = rv32.li 1 : !riscv.reg<a2>
+    %3 = rv32.li 0 : !riscv.reg<a3>
     %4 = riscv_scf.for %5 : !riscv.reg<a0> = %0 to %1 step %2 iter_args(%6 = %3) -> (!riscv.reg<a3>) {
       %7 = riscv.add %5, %6 : (!riscv.reg<a0>, !riscv.reg<a3>) -> !riscv.reg<a3>
       riscv_scf.yield %7 : !riscv.reg<a3>
     }
     %8 = riscv.mv %4 : (!riscv.reg<a3>) -> !riscv.reg<a0>
     riscv.custom_assembly_instruction %4 {"instruction_name" = "print"} : (!riscv.reg<a3>) -> ()
-    riscv.li 93 : !riscv.reg<a7>
+    rv32.li 93 : !riscv.reg<a7>
     riscv.ecall
     riscv_func.return
   }
diff --git a/tests/interactive/test_app.py b/tests/interactive/test_app.py
index 4ed7bbce9c..e2106f77da 100644
--- a/tests/interactive/test_app.py
+++ b/tests/interactive/test_app.py
@@ -184,7 +184,7 @@ async def test_buttons():
   riscv_func.func public @hello(%n : !riscv.reg<a0>) -> !riscv.reg<a0> attributes {p2align = 2 : i8} {
     %0 = riscv.mv %n : (!riscv.reg<a0>) -> !riscv.reg
     %n_1 = builtin.unrealized_conversion_cast %0 : !riscv.reg to index
-    %two = riscv.li 2 : !riscv.reg
+    %two = rv32.li 2 : !riscv.reg
     %two_1 = builtin.unrealized_conversion_cast %two : !riscv.reg to index
     %res = builtin.unrealized_conversion_cast %n_1 : index to !riscv.reg
     %res_1 = builtin.unrealized_conversion_cast %two_1 : index to !riscv.reg
diff --git a/tests/interactive/test_pass_metrics.py b/tests/interactive/test_pass_metrics.py
index 4bd59ef288..9e80902072 100644
--- a/tests/interactive/test_pass_metrics.py
+++ b/tests/interactive/test_pass_metrics.py
@@ -88,7 +88,7 @@ def test_get_diff_operation_count():
     # get output module
     output_text = """builtin.module {
   func.func @hello(%n : index) -> index {
-    %two = riscv.li 2 : !riscv.reg
+    %two = rv32.li 2 : !riscv.reg
     %two_1 = builtin.unrealized_conversion_cast %two : !riscv.reg to index
     %res = builtin.unrealized_conversion_cast %n : index to !riscv.reg
     %res_1 = builtin.unrealized_conversion_cast %two_1 : index to !riscv.reg
@@ -108,7 +108,7 @@ def test_get_diff_operation_count():
         ("builtin.unrealized_conversion_cast", 4, "+4"),
         ("func.func", 1, "="),
         ("func.return", 1, "="),
-        ("riscv.li", 1, "+1"),
+        ("rv32.li", 1, "+1"),
         ("riscv.mul", 1, "+1"),
     )
 
diff --git a/tests/interpreters/test_riscv_emulator.py b/tests/interpreters/test_riscv_emulator.py
index 363c9b74fd..f9788b9390 100644
--- a/tests/interpreters/test_riscv_emulator.py
+++ b/tests/interpreters/test_riscv_emulator.py
@@ -5,7 +5,7 @@
 
 from xdsl.builder import Builder
 from xdsl.context import Context
-from xdsl.dialects import riscv, riscv_debug, riscv_func
+from xdsl.dialects import riscv, riscv_debug, riscv_func, rv32
 from xdsl.dialects.builtin import ModuleOp
 from xdsl.ir import BlockArgument
 from xdsl.transforms.riscv_allocate_registers import RISCVAllocateRegistersPass
@@ -24,8 +24,8 @@ def test_simple():
     def module():
         @Builder.implicit_region
         def body():
-            six = riscv.LiOp(6).rd
-            seven = riscv.LiOp(7).rd
+            six = rv32.LiOp(6).rd
+            seven = rv32.LiOp(7).rd
             forty_two = riscv.MulOp(six, seven).rd
             riscv_debug.PrintfOp("{}", (forty_two,))
             riscv.ReturnOp()
@@ -52,15 +52,15 @@ def test_multiply_add():
     def module():
         @Builder.implicit_region
         def main():
-            riscv.LiOp(3, rd=riscv.Registers.A0)
-            riscv.LiOp(2, rd=riscv.Registers.A1)
-            riscv.LiOp(1, rd=riscv.Registers.A2)
+            rv32.LiOp(3, rd=riscv.Registers.A0)
+            rv32.LiOp(2, rd=riscv.Registers.A1)
+            rv32.LiOp(1, rd=riscv.Registers.A2)
 
             riscv.JalOp("muladd")
             res = riscv.GetRegisterOp(riscv.Registers.A0).res
             riscv_debug.PrintfOp("{}", (res,))
 
-            riscv.LiOp(93, rd=riscv.Registers.A7)
+            rv32.LiOp(93, rd=riscv.Registers.A7)
             riscv.EcallOp()
 
         riscv_func.FuncOp("main", main, ((), ()), visibility="public")
diff --git a/tests/interpreters/test_riscv_interpreter.py b/tests/interpreters/test_riscv_interpreter.py
index ff81a496c3..11e31e7916 100644
--- a/tests/interpreters/test_riscv_interpreter.py
+++ b/tests/interpreters/test_riscv_interpreter.py
@@ -3,7 +3,7 @@
 import pytest
 
 from xdsl.builder import Builder, ImplicitBuilder
-from xdsl.dialects import riscv
+from xdsl.dialects import riscv, rv32
 from xdsl.dialects.builtin import (
     DenseIntOrFPElementsAttr,
     IntegerAttr,
@@ -55,10 +55,10 @@ def my_custom_instruction(
     interpreter = Interpreter(module_op)
     interpreter.register_implementations(riscv_functions)
 
-    assert interpreter.run_op(riscv.LiOp("label0"), ()) == (
+    assert interpreter.run_op(rv32.LiOp("label0"), ()) == (
         TypedPtr.new_int32((42,)).raw,
     )
-    assert interpreter.run_op(riscv.LiOp("label1"), ()) == (
+    assert interpreter.run_op(rv32.LiOp("label1"), ()) == (
         TypedPtr.new_int32((59,)).raw,
     )
     assert interpreter.run_op(riscv.MVOp(create_ssa_value(register)), (42,)) == (42,)
diff --git a/tests/interpreters/test_riscv_scf_interpreter.py b/tests/interpreters/test_riscv_scf_interpreter.py
index 40caf000e5..915affb3eb 100644
--- a/tests/interpreters/test_riscv_scf_interpreter.py
+++ b/tests/interpreters/test_riscv_scf_interpreter.py
@@ -1,7 +1,7 @@
 import pytest
 
 from xdsl.builder import Builder, ImplicitBuilder
-from xdsl.dialects import func, riscv, riscv_scf
+from xdsl.dialects import func, riscv, riscv_scf, rv32
 from xdsl.dialects.builtin import IndexType, ModuleOp
 from xdsl.interpreter import Interpreter
 from xdsl.interpreters.func import FuncFunctions
@@ -29,9 +29,9 @@ def sum_to_for_op():
     with ImplicitBuilder(func.FuncOp("sum_to", ((register,), (register,))).body) as (
         ub,
     ):
-        lb = riscv.LiOp(0)
-        step = riscv.LiOp(1)
-        initial = riscv.LiOp(0)
+        lb = rv32.LiOp(0)
+        step = rv32.LiOp(1)
+        initial = rv32.LiOp(0)
 
         @Builder.implicit_region((register, register))
         def for_loop_region(args: tuple[BlockArgument, ...]):
@@ -59,9 +59,9 @@ def sum_to_while_op():
     with ImplicitBuilder(func.FuncOp("sum_to", ((register,), (register,))).body) as (
         ub,
     ):
-        lb = riscv.LiOp(0)
-        step = riscv.LiOp(1)
-        initial = riscv.LiOp(0)
+        lb = rv32.LiOp(0)
+        step = rv32.LiOp(1)
+        initial = rv32.LiOp(0)
 
         @Builder.implicit_region((register, register, register, register))
         def before_region(args: tuple[BlockArgument, ...]):
diff --git a/tests/interpreters/test_riscv_snitch_interpreter.py b/tests/interpreters/test_riscv_snitch_interpreter.py
index 3387211b40..3a325f639e 100644
--- a/tests/interpreters/test_riscv_snitch_interpreter.py
+++ b/tests/interpreters/test_riscv_snitch_interpreter.py
@@ -1,5 +1,5 @@
 from xdsl.builder import Builder, ImplicitBuilder
-from xdsl.dialects import func, riscv, riscv_snitch, snitch
+from xdsl.dialects import func, riscv, riscv_snitch, rv32, snitch
 from xdsl.dialects.builtin import ModuleOp
 from xdsl.interpreter import Interpreter
 from xdsl.interpreters.func import FuncFunctions
@@ -67,7 +67,7 @@ def sum_to_for_op():
         with ImplicitBuilder(
             func.FuncOp("sum_to", ((float_register,), (float_register,))).body
         ) as (count,):
-            one = riscv.LiOp(1).rd
+            one = rv32.LiOp(1).rd
             initial = riscv.FCvtDWOp(one, rd=acc_reg_type).rd
 
             @Builder.implicit_region((float_register,))
diff --git a/tests/interpreters/test_snitch_stream_interpreter.py b/tests/interpreters/test_snitch_stream_interpreter.py
index 771e03bd9c..4614200efd 100644
--- a/tests/interpreters/test_snitch_stream_interpreter.py
+++ b/tests/interpreters/test_snitch_stream_interpreter.py
@@ -1,7 +1,7 @@
 import pytest
 
 from xdsl.builder import ImplicitBuilder
-from xdsl.dialects import riscv, riscv_snitch, snitch, snitch_stream
+from xdsl.dialects import riscv, riscv_snitch, rv32, snitch, snitch_stream
 from xdsl.dialects.builtin import ArrayAttr, ModuleOp
 from xdsl.interpreter import Interpreter
 from xdsl.interpreters.riscv import RiscvFunctions
@@ -79,7 +79,7 @@ def test_snitch_stream_interpreter():
     )
 
     with ImplicitBuilder(streaming_region_body) as (a_stream, b_stream, c_stream):
-        count_reg = riscv.LiOp(5).rd
+        count_reg = rv32.LiOp(5).rd
 
         frep_body = Region(Block())
 
diff --git a/xdsl/backend/riscv/lowering/convert_arith_to_riscv.py b/xdsl/backend/riscv/lowering/convert_arith_to_riscv.py
index 5b2480e8c8..045f9e4192 100644
--- a/xdsl/backend/riscv/lowering/convert_arith_to_riscv.py
+++ b/xdsl/backend/riscv/lowering/convert_arith_to_riscv.py
@@ -6,7 +6,7 @@
     cast_operands_to_regs,
 )
 from xdsl.context import Context
-from xdsl.dialects import arith, riscv
+from xdsl.dialects import arith, riscv, rv32
 from xdsl.dialects.builtin import (
     Float32Type,
     Float64Type,
@@ -47,7 +47,7 @@ def match_and_rewrite(
                 rewriter.replace_op(
                     op,
                     [
-                        constant := riscv.LiOp(op_val.value.data),
+                        constant := rv32.LiOp(op_val.value.data),
                         UnrealizedConversionCastOp.get(
                             constant.results, (op_result_type,)
                         ),
@@ -60,7 +60,7 @@ def match_and_rewrite(
                 rewriter.replace_op(
                     op,
                     [
-                        lui := riscv.LiOp(
+                        lui := rv32.LiOp(
                             convert_f32_to_u32(op_val.value.data),
                             rd=_INT_REGISTER_TYPE,
                         ),
@@ -80,7 +80,7 @@ def match_and_rewrite(
                     rewriter.replace_op(
                         op,
                         [
-                            lui := riscv.LiOp(
+                            lui := rv32.LiOp(
                                 int_val,
                                 rd=_INT_REGISTER_TYPE,
                             ),
@@ -105,9 +105,9 @@ def match_and_rewrite(
                         op,
                         [
                             sp := riscv.GetRegisterOp(riscv.Registers.SP),
-                            li_upper := riscv.LiOp(upper),
+                            li_upper := rv32.LiOp(upper),
                             riscv.SwOp(sp, li_upper, -4),
-                            li_lower := riscv.LiOp(lower),
+                            li_lower := rv32.LiOp(lower),
                             riscv.SwOp(sp, li_lower, -8),
                             fld := riscv.FLdOp(sp, -8, rd=_FLOAT_REGISTER_TYPE),
                             UnrealizedConversionCastOp.get(
@@ -123,7 +123,7 @@ def match_and_rewrite(
             rewriter.replace_op(
                 op,
                 [
-                    constant := riscv.LiOp(op_val.value.data),
+                    constant := rv32.LiOp(op_val.value.data),
                     UnrealizedConversionCastOp.get(constant.results, (op_result_type,)),
                 ],
             )
@@ -356,7 +356,7 @@ def match_and_rewrite(self, op: arith.CmpfOp, rewriter: PatternRewriter) -> None
         match op.predicate.value.data:
             # false
             case 0:
-                rewriter.replace_op(op, [riscv.LiOp(0)])
+                rewriter.replace_op(op, [rv32.LiOp(0)])
             # oeq
             case 1:
                 rewriter.replace_op(op, [riscv.FeqSOp(lhs, rhs, fastmath=fastmath)])
@@ -430,7 +430,7 @@ def match_and_rewrite(self, op: arith.CmpfOp, rewriter: PatternRewriter) -> None
                 rewriter.replace_op(op, [feq1, feq2, and_, riscv.XoriOp(and_, 1)])
             # true
             case 15:
-                rewriter.replace_op(op, [riscv.LiOp(1)])
+                rewriter.replace_op(op, [rv32.LiOp(1)])
             case _:
                 raise NotImplementedError("Cmpf predicate not supported")
 
diff --git a/xdsl/backend/riscv/lowering/convert_memref_to_riscv.py b/xdsl/backend/riscv/lowering/convert_memref_to_riscv.py
index d9340d2ed1..b3406aaa0b 100644
--- a/xdsl/backend/riscv/lowering/convert_memref_to_riscv.py
+++ b/xdsl/backend/riscv/lowering/convert_memref_to_riscv.py
@@ -9,7 +9,7 @@
 )
 from xdsl.builder import ImplicitBuilder
 from xdsl.context import Context
-from xdsl.dialects import memref, riscv, riscv_func
+from xdsl.dialects import memref, riscv, riscv_func, rv32
 from xdsl.dialects.builtin import (
     DYNAMIC_INDEX,
     AnyFloat,
@@ -51,7 +51,7 @@ def match_and_rewrite(self, op: memref.AllocOp, rewriter: PatternRewriter) -> No
         rewriter.replace_op(
             op,
             (
-                size_op := riscv.LiOp(size, comment="memref alloc size"),
+                size_op := rv32.LiOp(size, comment="memref alloc size"),
                 move_op := riscv.MVOp(size_op.rd, rd=riscv.Registers.A0),
                 call := riscv_func.CallOp(
                     SymbolRefAttr("malloc"),
@@ -127,7 +127,7 @@ def get_strided_pointer(
                 # elements required to be skipped when incrementing that dimension).
                 ops.extend(
                     (
-                        stride_op := riscv.LiOp(stride),
+                        stride_op := rv32.LiOp(stride),
                         offset_op := riscv.MulOp(increment, stride_op.rd),
                     )
                 )
@@ -150,7 +150,7 @@ def get_strided_pointer(
 
     ops.extend(
         [
-            bytes_per_element_op := riscv.LiOp(bytes_per_element),
+            bytes_per_element_op := rv32.LiOp(bytes_per_element),
             offset_bytes := riscv.MulOp(
                 head,
                 bytes_per_element_op.rd,
@@ -293,7 +293,7 @@ def match_and_rewrite(self, op: memref.GetGlobalOp, rewriter: PatternRewriter):
         rewriter.replace_op(
             op,
             [
-                ptr := riscv.LiOp(op.name_.string_value()),
+                ptr := rv32.LiOp(op.name_.string_value()),
                 UnrealizedConversionCastOp.get((ptr,), (op.memref.type,)),
             ],
         )
@@ -377,7 +377,7 @@ def match_and_rewrite(self, op: memref.SubviewOp, rewriter: PatternRewriter):
                     dynamic_offset_index += 1
                 else:
                     # No need to insert arithmetic ops that will be multiplied by zero
-                    index_ops.append(offset_op := riscv.LiOp(static_offset))
+                    index_ops.append(offset_op := rv32.LiOp(static_offset))
                     index_val = offset_op.rd
                 index_val.name_hint = "subview_dim_index"
                 indices.append(index_val)
diff --git a/xdsl/backend/riscv/lowering/convert_snitch_stream_to_snitch.py b/xdsl/backend/riscv/lowering/convert_snitch_stream_to_snitch.py
index 9dadd0346a..611b416f23 100644
--- a/xdsl/backend/riscv/lowering/convert_snitch_stream_to_snitch.py
+++ b/xdsl/backend/riscv/lowering/convert_snitch_stream_to_snitch.py
@@ -2,6 +2,7 @@
 from xdsl.dialects import (
     builtin,
     riscv,
+    rv32,
     snitch,
     snitch_stream,
 )
@@ -66,7 +67,7 @@ def insert_stride_pattern_ops(
 
     ints = tuple(builtin.IntAttr(i) for i in range(rank))
 
-    b_ops = tuple(riscv.LiOp(b.data) for b in reversed(ub.data))
+    b_ops = tuple(rv32.LiOp(b.data) for b in reversed(ub.data))
     new_b_ops = tuple(riscv.AddiOp(b_op.rd, -1) for b_op in b_ops)
     set_bound_ops = tuple(
         snitch.SsrSetDimensionBoundOp(new_b_op, dm, i)
@@ -75,14 +76,14 @@ def insert_stride_pattern_ops(
     interleaved_b_set_bound_ops = tuple(
         x for t in zip(new_b_ops, set_bound_ops) for x in t
     )
-    s_ops = tuple(riscv.LiOp(s.data) for s in reversed(strides.data))
+    s_ops = tuple(rv32.LiOp(s.data) for s in reversed(strides.data))
 
     new_ops: list[Operation] = [
         *b_ops,
         *interleaved_b_set_bound_ops,
         *s_ops,
         snitch.SsrSetDimensionStrideOp(s_ops[0], dm, ints[0]),
-        a_op := riscv.LiOp(0),
+        a_op := rv32.LiOp(0),
     ]
 
     for i in range(1, rank):
@@ -96,7 +97,7 @@ def insert_stride_pattern_ops(
     # Always reset the repetition count, even if it's the default
     new_ops.extend(
         (
-            repeat_op := riscv.LiOp(repeat.data - 1),
+            repeat_op := rv32.LiOp(repeat.data - 1),
             snitch.SsrSetStreamRepetitionOp(repeat_op.rd, dm),
         )
     )
diff --git a/xdsl/dialects/riscv/__init__.py b/xdsl/dialects/riscv/__init__.py
index 1d8e66a5ff..69b08a7948 100644
--- a/xdsl/dialects/riscv/__init__.py
+++ b/xdsl/dialects/riscv/__init__.py
@@ -151,7 +151,6 @@
     LbuOp,
     LhOp,
     LhuOp,
-    LiOp,
     LuiOp,
     LwOp,
     MaxOp,
@@ -299,7 +298,6 @@
         DivuOp,
         RemOp,
         RemuOp,
-        LiOp,
         RolOp,
         RorOp,
         RemuwOp,
diff --git a/xdsl/dialects/riscv/ops.py b/xdsl/dialects/riscv/ops.py
index 3019edbf63..4a8db5a5f0 100644
--- a/xdsl/dialects/riscv/ops.py
+++ b/xdsl/dialects/riscv/ops.py
@@ -16,7 +16,6 @@
     StringAttr,
     i32,
 )
-from xdsl.interfaces import ConstantLikeInterface
 from xdsl.ir import (
     Attribute,
     Block,
@@ -37,7 +36,6 @@
     opt_prop_def,
     prop_def,
     region_def,
-    result_def,
     traits_def,
     var_operand_def,
     var_result_def,
@@ -83,8 +81,6 @@
     RsRsImmIntegerOperation,
     RsRsOffIntegerOperation,
     assembly_arg_str,
-    parse_immediate_value,
-    print_immediate_value,
 )
 from .attrs import (
     SI20,
@@ -2127,75 +2123,6 @@ def get_canonicalization_patterns(cls) -> tuple[RewritePattern, ...]:
         return (LoadImmediate0(),)
 
 
-@irdl_op_definition
-class LiOp(RISCVCustomFormatOperation, RISCVInstruction, ConstantLikeInterface):
-    """
-    Loads a 32-bit immediate into rd.
-
-    This is an assembler pseudo-instruction.
-
-    See external [documentation](https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md#load-immediate).
-    """
-
-    name = "riscv.li"
-
-    rd = result_def(IntRegisterType)
-    immediate = attr_def(IntegerAttr[I32] | LabelAttr)
-
-    traits = traits_def(Pure(), LiOpHasCanonicalizationPatternTrait())
-
-    def __init__(
-        self,
-        immediate: int | IntegerAttr[I32] | str | LabelAttr,
-        *,
-        rd: IntRegisterType = Registers.UNALLOCATED_INT,
-        comment: str | StringAttr | None = None,
-    ):
-        if isinstance(immediate, int):
-            immediate = IntegerAttr(immediate, i32)
-        elif isinstance(immediate, str):
-            immediate = LabelAttr(immediate)
-        if isinstance(comment, str):
-            comment = StringAttr(comment)
-
-        super().__init__(
-            result_types=[rd],
-            attributes={
-                "immediate": immediate,
-                "comment": comment,
-            },
-        )
-
-    def assembly_line_args(self) -> tuple[AssemblyInstructionArg, ...]:
-        return self.rd, self.immediate
-
-    def get_constant_value(self):
-        return self.immediate
-
-    @classmethod
-    def custom_parse_attributes(cls, parser: Parser) -> dict[str, Attribute]:
-        attributes = dict[str, Attribute]()
-        attributes["immediate"] = parse_immediate_value(parser, i32)
-        return attributes
-
-    def custom_print_attributes(self, printer: Printer) -> AbstractSet[str]:
-        printer.print_string(" ")
-        print_immediate_value(printer, self.immediate)
-        return {"immediate", "fastmath"}
-
-    @classmethod
-    def parse_op_type(
-        cls, parser: Parser
-    ) -> tuple[Sequence[Attribute], Sequence[Attribute]]:
-        parser.parse_punctuation(":")
-        res_type = parser.parse_attribute()
-        return (), (res_type,)
-
-    def print_op_type(self, printer: Printer) -> None:
-        printer.print_string(" : ")
-        printer.print_attribute(self.rd.type)
-
-
 @irdl_op_definition
 class EcallOp(NullaryOperation):
     """
@@ -3390,7 +3317,6 @@ class VFMulSOp(RdRsRsFloatOperation[FloatRegisterType, FloatRegisterType]):
         DivuOp,
         RemOp,
         RemuOp,
-        LiOp,
         RolOp,
         RorOp,
         RemuwOp,
diff --git a/xdsl/dialects/rv32.py b/xdsl/dialects/rv32.py
index 9322f60034..c84e00b126 100644
--- a/xdsl/dialects/rv32.py
+++ b/xdsl/dialects/rv32.py
@@ -16,13 +16,13 @@
     AssemblyInstructionArg,
     IntRegisterType,
     LabelAttr,
-    LiOpHasCanonicalizationPatternTrait,
     Registers,
     RISCVCustomFormatOperation,
     RISCVInstruction,
     parse_immediate_value,
     print_immediate_value,
 )
+from xdsl.dialects.riscv.ops import LiOpHasCanonicalizationPatternTrait
 from xdsl.interfaces import ConstantLikeInterface
 from xdsl.ir import (
     Attribute,
diff --git a/xdsl/dialects/rv64.py b/xdsl/dialects/rv64.py
index 1ea5a3d1ad..d724106d63 100644
--- a/xdsl/dialects/rv64.py
+++ b/xdsl/dialects/rv64.py
@@ -16,13 +16,13 @@
     AssemblyInstructionArg,
     IntRegisterType,
     LabelAttr,
-    LiOpHasCanonicalizationPatternTrait,
     Registers,
     RISCVCustomFormatOperation,
     RISCVInstruction,
     parse_immediate_value,
     print_immediate_value,
 )
+from xdsl.dialects.riscv.ops import LiOpHasCanonicalizationPatternTrait
 from xdsl.interfaces import ConstantLikeInterface
 from xdsl.ir import (
     Attribute,
diff --git a/xdsl/interpreters/__init__.py b/xdsl/interpreters/__init__.py
index ad9080319a..39188adcd7 100644
--- a/xdsl/interpreters/__init__.py
+++ b/xdsl/interpreters/__init__.py
@@ -19,6 +19,8 @@
     riscv_libc,
     riscv_scf,
     riscv_snitch,
+    rv32,
+    rv64,
     scf,
     snitch_stream,
     tensor,
@@ -44,6 +46,8 @@ def register_implementations(interpreter: Interpreter, ctx: Context):
     interpreter.register_implementations(riscv_scf.RiscvScfFunctions())
     interpreter.register_implementations(riscv_snitch.RiscvSnitchFunctions())
     interpreter.register_implementations(riscv.RiscvFunctions())
+    interpreter.register_implementations(rv32.Rv32Functions())
+    interpreter.register_implementations(rv64.Rv64Functions())
     interpreter.register_implementations(scf.ScfFunctions())
     interpreter.register_implementations(snitch_stream.SnitchStreamFunctions())
     interpreter.register_implementations(tensor.TensorFunctions())
diff --git a/xdsl/interpreters/riscv.py b/xdsl/interpreters/riscv.py
index af694c0626..792249deca 100644
--- a/xdsl/interpreters/riscv.py
+++ b/xdsl/interpreters/riscv.py
@@ -229,16 +229,6 @@ def get_immediate_value(
                 data = RiscvFunctions.get_data_value(interpreter, imm.data)
                 return data
 
-    @impl(riscv.LiOp)
-    def run_li(
-        self,
-        interpreter: Interpreter,
-        op: riscv.LiOp,
-        args: tuple[Any, ...],
-    ):
-        results = (RiscvFunctions.get_immediate_value(interpreter, op.immediate),)
-        return RiscvFunctions.set_reg_values(interpreter, op.results, results)
-
     @impl(riscv.MVOp)
     def run_mv(
         self,
diff --git a/xdsl/interpreters/rv32.py b/xdsl/interpreters/rv32.py
new file mode 100644
index 0000000000..aee972b23d
--- /dev/null
+++ b/xdsl/interpreters/rv32.py
@@ -0,0 +1,25 @@
+from __future__ import annotations
+
+from typing import Any
+
+from xdsl.dialects import rv32
+from xdsl.interpreter import (
+    Interpreter,
+    InterpreterFunctions,
+    impl,
+    register_impls,
+)
+from xdsl.interpreters.riscv import RiscvFunctions
+
+
+@register_impls
+class Rv32Functions(InterpreterFunctions):
+    @impl(rv32.LiOp)
+    def run_li(
+        self,
+        interpreter: Interpreter,
+        op: rv32.LiOp,
+        args: tuple[Any, ...],
+    ):
+        results = (RiscvFunctions.get_immediate_value(interpreter, op.immediate),)
+        return RiscvFunctions.set_reg_values(interpreter, op.results, results)
diff --git a/xdsl/interpreters/rv64.py b/xdsl/interpreters/rv64.py
new file mode 100644
index 0000000000..8f6947b22f
--- /dev/null
+++ b/xdsl/interpreters/rv64.py
@@ -0,0 +1,25 @@
+from __future__ import annotations
+
+from typing import Any
+
+from xdsl.dialects import rv64
+from xdsl.interpreter import (
+    Interpreter,
+    InterpreterFunctions,
+    impl,
+    register_impls,
+)
+from xdsl.interpreters.riscv import RiscvFunctions
+
+
+@register_impls
+class Rv64Functions(InterpreterFunctions):
+    @impl(rv64.LiOp)
+    def run_li(
+        self,
+        interpreter: Interpreter,
+        op: rv64.LiOp,
+        args: tuple[Any, ...],
+    ):
+        results = (RiscvFunctions.get_immediate_value(interpreter, op.immediate),)
+        return RiscvFunctions.set_reg_values(interpreter, op.results, results)
diff --git a/xdsl/transforms/canonicalization_patterns/riscv.py b/xdsl/transforms/canonicalization_patterns/riscv.py
index 6bc1a56e43..f4a6c8cf10 100644
--- a/xdsl/transforms/canonicalization_patterns/riscv.py
+++ b/xdsl/transforms/canonicalization_patterns/riscv.py
@@ -1,4 +1,4 @@
-from xdsl.dialects import riscv, riscv_snitch
+from xdsl.dialects import riscv, riscv_snitch, rv32
 from xdsl.dialects.builtin import I32, IntegerAttr, i32
 from xdsl.dialects.utils import FastMathFlag
 from xdsl.ir import OpResult, SSAValue
@@ -63,7 +63,7 @@ def match_and_rewrite(self, op: riscv.MulOp, rewriter: PatternRewriter) -> None:
                 else:
                     return
             case int(), int():
-                rewriter.replace_op(op, riscv.LiOp(lhs * rhs, rd=rd))
+                rewriter.replace_op(op, rv32.LiOp(lhs * rhs, rd=rd))
             case _:
                 return
 
@@ -119,9 +119,7 @@ def match_and_rewrite(self, op: riscv.AddOp, rewriter: PatternRewriter) -> None:
                     ),
                 )
             case int(), int():
-                rewriter.replace_op(
-                    op, riscv.LiOp(lhs + rhs, rd=rd, comment=op.comment)
-                )
+                rewriter.replace_op(op, rv32.LiOp(lhs + rhs, rd=rd, comment=op.comment))
             case _:
                 pass
 
@@ -143,7 +141,7 @@ def match_and_rewrite(self, op: riscv.AddiOp, rewriter: PatternRewriter) -> None
             rd = op.rd.type
             rewriter.replace_op(
                 op,
-                riscv.LiOp(
+                rv32.LiOp(
                     rs1.value.data + op.immediate.value.data,
                     rd=rd,
                     comment=op.comment,
@@ -179,9 +177,7 @@ def match_and_rewrite(self, op: riscv.SubOp, rewriter: PatternRewriter) -> None:
                     ),
                 )
             case int(), int():
-                rewriter.replace_op(
-                    op, riscv.LiOp(lhs - rhs, rd=rd, comment=op.comment)
-                )
+                rewriter.replace_op(op, rv32.LiOp(lhs - rhs, rd=rd, comment=op.comment))
             case _:
                 pass
 
@@ -217,7 +213,7 @@ def match_and_rewrite(self, op: riscv.SubOp, rewriter: PatternRewriter) -> None:
             and op.rs2 == op.rs1.op.rs1
         ):
             rd = op.rd.type
-            rewriter.replace_op(op, riscv.LiOp(op.rs1.op.immediate.value.data, rd=rd))
+            rewriter.replace_op(op, rv32.LiOp(op.rs1.op.immediate.value.data, rd=rd))
 
 
 class AndiImmediate(RewritePattern):
@@ -225,13 +221,13 @@ class AndiImmediate(RewritePattern):
     def match_and_rewrite(self, op: riscv.AndiOp, rewriter: PatternRewriter) -> None:
         if (
             isinstance(op.rs1, OpResult)
-            and isinstance(op.rs1.op, riscv.LiOp)
+            and isinstance(op.rs1.op, rv32.LiOp)
             and isinstance(op.rs1.op.immediate, IntegerAttr)
             and isinstance(op.immediate, IntegerAttr)
         ):
             rd = op.rd.type
             rewriter.replace_matched_op(
-                riscv.LiOp(
+                rv32.LiOp(
                     op.rs1.op.immediate.value.data & op.immediate.value.data, rd=rd
                 )
             )
@@ -242,13 +238,13 @@ class OriImmediate(RewritePattern):
     def match_and_rewrite(self, op: riscv.OriOp, rewriter: PatternRewriter) -> None:
         if (
             isinstance(op.rs1, OpResult)
-            and isinstance(op.rs1.op, riscv.LiOp)
+            and isinstance(op.rs1.op, rv32.LiOp)
             and isinstance(op.rs1.op.immediate, IntegerAttr)
             and isinstance(op.immediate, IntegerAttr)
         ):
             rd = op.rd.type
             rewriter.replace_matched_op(
-                riscv.LiOp(
+                rv32.LiOp(
                     op.rs1.op.immediate.value.data | op.immediate.value.data, rd=rd
                 )
             )
@@ -259,13 +255,13 @@ class XoriImmediate(RewritePattern):
     def match_and_rewrite(self, op: riscv.XoriOp, rewriter: PatternRewriter) -> None:
         if (
             isinstance(op.rs1, OpResult)
-            and isinstance(op.rs1.op, riscv.LiOp)
+            and isinstance(op.rs1.op, rv32.LiOp)
             and isinstance(op.rs1.op.immediate, IntegerAttr)
             and isinstance(op.immediate, IntegerAttr)
         ):
             rd = op.rd.type
             rewriter.replace_matched_op(
-                riscv.LiOp(
+                rv32.LiOp(
                     op.rs1.op.immediate.value.data ^ op.immediate.value.data, rd=rd
                 )
             )
@@ -276,14 +272,14 @@ class ShiftLeftImmediate(RewritePattern):
     def match_and_rewrite(self, op: riscv.SlliOp, rewriter: PatternRewriter) -> None:
         if (
             isinstance(op.rs1, OpResult)
-            and isinstance(op.rs1.op, riscv.LiOp)
+            and isinstance(op.rs1.op, rv32.LiOp)
             and isinstance(op.rs1.op.immediate, IntegerAttr)
             and isinstance(op.immediate, IntegerAttr)
         ):
             rd = op.rd.type
             rewriter.replace_op(
                 op,
-                riscv.LiOp(
+                rv32.LiOp(
                     op.rs1.op.immediate.value.data << op.immediate.value.data, rd=rd
                 ),
             )
@@ -306,14 +302,14 @@ class ShiftRightImmediate(RewritePattern):
     def match_and_rewrite(self, op: riscv.SrliOp, rewriter: PatternRewriter) -> None:
         if (
             isinstance(op.rs1, OpResult)
-            and isinstance(op.rs1.op, riscv.LiOp)
+            and isinstance(op.rs1.op, rv32.LiOp)
             and isinstance(op.rs1.op.immediate, IntegerAttr)
             and isinstance(op.immediate, IntegerAttr)
         ):
             rd = op.rd.type
             rewriter.replace_op(
                 op,
-                riscv.LiOp(
+                rv32.LiOp(
                     op.rs1.op.immediate.value.data >> op.immediate.value.data, rd=rd
                 ),
             )
@@ -459,7 +455,7 @@ def match_and_rewrite(self, op: riscv.AddOp, rewriter: PatternRewriter) -> None:
             rewriter.replace_op(
                 op,
                 [
-                    li_op := riscv.LiOp(2),
+                    li_op := rv32.LiOp(2),
                     riscv.MulOp(
                         op.rs1,
                         li_op,
@@ -632,7 +628,7 @@ class LoadImmediate0(RewritePattern):
     """
 
     @op_type_rewrite_pattern
-    def match_and_rewrite(self, op: riscv.LiOp, rewriter: PatternRewriter) -> None:
+    def match_and_rewrite(self, op: rv32.LiOp, rewriter: PatternRewriter) -> None:
         if not (isinstance(op.immediate, IntegerAttr) and op.immediate.value.data == 0):
             return
 
@@ -659,5 +655,5 @@ def get_constant_value(value: SSAValue) -> IntegerAttr[I32] | None:
     if isinstance(value.op, riscv.MVOp):
         return get_constant_value(value.op.rs)
 
-    if isinstance(value.op, riscv.LiOp) and isinstance(value.op.immediate, IntegerAttr):
+    if isinstance(value.op, rv32.LiOp) and isinstance(value.op.immediate, IntegerAttr):
         return value.op.immediate
diff --git a/xdsl/transforms/convert_riscv_scf_for_to_frep.py b/xdsl/transforms/convert_riscv_scf_for_to_frep.py
index e3a547f270..a5a8afb935 100644
--- a/xdsl/transforms/convert_riscv_scf_for_to_frep.py
+++ b/xdsl/transforms/convert_riscv_scf_for_to_frep.py
@@ -1,7 +1,7 @@
 from itertools import chain
 
 from xdsl.context import Context
-from xdsl.dialects import builtin, riscv, riscv_scf, riscv_snitch, snitch
+from xdsl.dialects import builtin, riscv, riscv_scf, riscv_snitch, rv32, snitch
 from xdsl.passes import ModulePass
 from xdsl.pattern_rewriter import (
     GreedyRewritePatternApplier,
@@ -28,7 +28,7 @@ def match_and_rewrite(self, op: riscv_scf.ForOp, rewriter: PatternRewriter) -> N
             return
 
         if not (
-            isinstance(step_op := op.step.owner, riscv.LiOp)
+            isinstance(step_op := op.step.owner, rv32.LiOp)
             and isinstance(step_op.immediate, builtin.IntegerAttr)
             and step_op.immediate.value.data == 1
         ):
diff --git a/xdsl/transforms/lower_riscv_func.py b/xdsl/transforms/lower_riscv_func.py
index ef133f3ead..42a4d3045c 100644
--- a/xdsl/transforms/lower_riscv_func.py
+++ b/xdsl/transforms/lower_riscv_func.py
@@ -1,7 +1,7 @@
 from dataclasses import dataclass, field
 
 from xdsl.context import Context
-from xdsl.dialects import riscv, riscv_func
+from xdsl.dialects import riscv, riscv_func, rv32
 from xdsl.dialects.builtin import ModuleOp
 from xdsl.ir import Operation
 from xdsl.passes import ModulePass
@@ -40,7 +40,7 @@ def match_and_rewrite(self, op: riscv_func.SyscallOp, rewriter: PatternRewriter)
                 )
             )
 
-        ops.append(riscv.LiOp(immediate=op.syscall_num, rd=riscv.Registers.A7))
+        ops.append(rv32.LiOp(immediate=op.syscall_num, rd=riscv.Registers.A7))
 
         if op.result is None:
             ops.append(riscv.EcallOp())
diff --git a/xdsl/transforms/lower_snitch.py b/xdsl/transforms/lower_snitch.py
index e989389584..3b45d717db 100644
--- a/xdsl/transforms/lower_snitch.py
+++ b/xdsl/transforms/lower_snitch.py
@@ -6,7 +6,7 @@
 from dataclasses import dataclass
 
 from xdsl.context import Context
-from xdsl.dialects import builtin, riscv, riscv_snitch, snitch
+from xdsl.dialects import builtin, riscv, riscv_snitch, rv32, snitch
 from xdsl.dialects.builtin import IntegerAttr, i32
 from xdsl.ir import Operation
 from xdsl.irdl import Operand
@@ -121,7 +121,7 @@ def write_ssr_config_ops(
     ```
     """
     return [
-        address := riscv.LiOp(immediate=IntegerAttr(dm | reg << 5, i32)),
+        address := rv32.LiOp(immediate=IntegerAttr(dm | reg << 5, i32)),
         riscv_snitch.ScfgwOp(rs1=value, rs2=address, comment=comment),
     ]
 
diff --git a/xdsl/transforms/riscv_scf_loop_range_folding.py b/xdsl/transforms/riscv_scf_loop_range_folding.py
index 713d5b82a4..0795136f17 100644
--- a/xdsl/transforms/riscv_scf_loop_range_folding.py
+++ b/xdsl/transforms/riscv_scf_loop_range_folding.py
@@ -1,5 +1,5 @@
 from xdsl.context import Context
-from xdsl.dialects import builtin, riscv, riscv_scf
+from xdsl.dialects import builtin, riscv, riscv_scf, rv32
 from xdsl.passes import ModulePass
 from xdsl.pattern_rewriter import (
     PatternRewriter,
@@ -41,7 +41,7 @@ def match_and_rewrite(self, op: riscv_scf.ForOp, rewriter: PatternRewriter) -> N
                     # All the uses are multiplications by a constant, we can fold
                     rewriter.insert_op(
                         [
-                            shift := riscv.LiOp(constant),
+                            shift := rv32.LiOp(constant),
                             new_lb := riscv.AddOp(op.lb, shift),
                             new_ub := riscv.AddOp(op.ub, shift),
                         ]
@@ -50,7 +50,7 @@ def match_and_rewrite(self, op: riscv_scf.ForOp, rewriter: PatternRewriter) -> N
                     # All the uses are multiplications by a constant, we can fold
                     rewriter.insert_op(
                         [
-                            factor := riscv.LiOp(constant),
+                            factor := rv32.LiOp(constant),
                             new_lb := riscv.MulOp(op.lb, factor),
                             new_ub := riscv.MulOp(op.ub, factor),
                             new_step := riscv.MulOp(op.step, factor),

From adbebc45951aa61021a9250c9f9493d4352b87c2 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Fri, 6 Feb 2026 15:51:20 +0000
Subject: [PATCH 4/9] register implementation

---
 tests/interpreters/test_riscv_interpreter.py         | 3 +++
 tests/interpreters/test_riscv_scf_interpreter.py     | 2 ++
 tests/interpreters/test_riscv_snitch_interpreter.py  | 2 ++
 tests/interpreters/test_snitch_stream_interpreter.py | 2 ++
 4 files changed, 9 insertions(+)

diff --git a/tests/interpreters/test_riscv_interpreter.py b/tests/interpreters/test_riscv_interpreter.py
index 11e31e7916..e5b60a51e1 100644
--- a/tests/interpreters/test_riscv_interpreter.py
+++ b/tests/interpreters/test_riscv_interpreter.py
@@ -15,6 +15,7 @@
 )
 from xdsl.interpreter import Interpreter, PythonValues
 from xdsl.interpreters.riscv import RiscvFunctions
+from xdsl.interpreters.rv32 import Rv32Functions
 from xdsl.interpreters.utils.ptr import RawPtr, TypedPtr
 from xdsl.ir import Block, Region
 from xdsl.utils.bitwise_casts import convert_f32_to_u32
@@ -52,8 +53,10 @@ def my_custom_instruction(
     riscv_functions = RiscvFunctions(
         custom_instructions={"my_custom_instruction": my_custom_instruction},
     )
+    rv32_functions = Rv32Functions()
     interpreter = Interpreter(module_op)
     interpreter.register_implementations(riscv_functions)
+    interpreter.register_implementations(rv32_functions)
 
     assert interpreter.run_op(rv32.LiOp("label0"), ()) == (
         TypedPtr.new_int32((42,)).raw,
diff --git a/tests/interpreters/test_riscv_scf_interpreter.py b/tests/interpreters/test_riscv_scf_interpreter.py
index 915affb3eb..047d889c68 100644
--- a/tests/interpreters/test_riscv_scf_interpreter.py
+++ b/tests/interpreters/test_riscv_scf_interpreter.py
@@ -7,6 +7,7 @@
 from xdsl.interpreters.func import FuncFunctions
 from xdsl.interpreters.riscv import RiscvFunctions
 from xdsl.interpreters.riscv_scf import RiscvScfFunctions
+from xdsl.interpreters.rv32 import Rv32Functions
 from xdsl.ir import BlockArgument
 
 index = IndexType()
@@ -90,6 +91,7 @@ def interp(module_op: ModuleOp, func_name: str, n: int) -> int:
     interpreter = Interpreter(module_op)
     interpreter.register_implementations(RiscvScfFunctions())
     interpreter.register_implementations(RiscvFunctions())
+    interpreter.register_implementations(Rv32Functions())
     interpreter.register_implementations(FuncFunctions())
     (result,) = interpreter.call_op(func_name, (n,))
     return result
diff --git a/tests/interpreters/test_riscv_snitch_interpreter.py b/tests/interpreters/test_riscv_snitch_interpreter.py
index 3a325f639e..a63eb5f5e1 100644
--- a/tests/interpreters/test_riscv_snitch_interpreter.py
+++ b/tests/interpreters/test_riscv_snitch_interpreter.py
@@ -5,6 +5,7 @@
 from xdsl.interpreters.func import FuncFunctions
 from xdsl.interpreters.riscv import RiscvFunctions
 from xdsl.interpreters.riscv_snitch import RiscvSnitchFunctions
+from xdsl.interpreters.rv32 import Rv32Functions
 from xdsl.interpreters.utils.stream import Acc, Nats
 from xdsl.ir import BlockArgument
 from xdsl.utils.test_value import create_ssa_value
@@ -82,6 +83,7 @@ def for_loop_region(args: tuple[BlockArgument, ...]):
     interpreter = Interpreter(sum_to_for_op)
     interpreter.register_implementations(RiscvSnitchFunctions())
     interpreter.register_implementations(RiscvFunctions())
+    interpreter.register_implementations(Rv32Functions())
     interpreter.register_implementations(FuncFunctions())
 
     assert interpreter.call_op("sum_to", (5,)) == (64,)
diff --git a/tests/interpreters/test_snitch_stream_interpreter.py b/tests/interpreters/test_snitch_stream_interpreter.py
index 4614200efd..c8e8037742 100644
--- a/tests/interpreters/test_snitch_stream_interpreter.py
+++ b/tests/interpreters/test_snitch_stream_interpreter.py
@@ -6,6 +6,7 @@
 from xdsl.interpreter import Interpreter
 from xdsl.interpreters.riscv import RiscvFunctions
 from xdsl.interpreters.riscv_snitch import RiscvSnitchFunctions
+from xdsl.interpreters.rv32 import Rv32Functions
 from xdsl.interpreters.snitch_stream import SnitchStreamFunctions
 from xdsl.interpreters.utils.ptr import TypedPtr
 from xdsl.ir import Block, Region
@@ -61,6 +62,7 @@ def test_snitch_stream_interpreter():
 
     interpreter = Interpreter(ModuleOp([]))
     interpreter.register_implementations(RiscvFunctions())
+    interpreter.register_implementations(Rv32Functions())
     interpreter.register_implementations(SnitchStreamFunctions())
     interpreter.register_implementations(RiscvSnitchFunctions())
 

From b4c85f856eed57ba20be87114c8864e473eeffc4 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Fri, 6 Feb 2026 16:26:11 +0000
Subject: [PATCH 5/9] fix test

---
 tests/interactive/test_pass_metrics.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tests/interactive/test_pass_metrics.py b/tests/interactive/test_pass_metrics.py
index 9e80902072..79661ddb3d 100644
--- a/tests/interactive/test_pass_metrics.py
+++ b/tests/interactive/test_pass_metrics.py
@@ -108,8 +108,8 @@ def test_get_diff_operation_count():
         ("builtin.unrealized_conversion_cast", 4, "+4"),
         ("func.func", 1, "="),
         ("func.return", 1, "="),
-        ("rv32.li", 1, "+1"),
         ("riscv.mul", 1, "+1"),
+        ("rv32.li", 1, "+1"),
     )
 
     assert expected_diff_res == get_diff_operation_count(

From bea6a400d608510ed0a6720be60f2c456bb3d149 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Fri, 6 Feb 2026 16:32:36 +0000
Subject: [PATCH 6/9] fix toy

---
 docs/Toy/toy/__main__.py | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/docs/Toy/toy/__main__.py b/docs/Toy/toy/__main__.py
index 04bc574e06..f94a8db384 100644
--- a/docs/Toy/toy/__main__.py
+++ b/docs/Toy/toy/__main__.py
@@ -13,6 +13,7 @@
 from xdsl.interpreters.riscv_func import RiscvFuncFunctions
 from xdsl.interpreters.riscv_libc import RiscvLibcFunctions
 from xdsl.interpreters.riscv_scf import RiscvScfFunctions
+from xdsl.interpreters.rv32 import Rv32Functions
 from xdsl.interpreters.scf import ScfFunctions
 from xdsl.parser import Parser as IRParser
 from xdsl.printer import Printer
@@ -119,6 +120,7 @@ def main(path: Path, emit: str, ir: bool, print_generic: bool):
     ):
         interpreter.register_implementations(ToyAcceleratorInstructionFunctions())
         interpreter.register_implementations(RiscvFuncFunctions())
+        interpreter.register_implementations(Rv32Functions())
         interpreter.register_implementations(RiscvDebugFunctions())
         interpreter.register_implementations(RiscvLibcFunctions())
     if emit in ("riscv", "riscv-opt", "riscv-regalloc", "riscv-regalloc-opt"):

From 8261f071d9177b24cc60c58ed35f8a10b169db37 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Fri, 6 Feb 2026 18:44:40 +0000
Subject: [PATCH 7/9] add riscv_assembly_emission/rv{32|64}_ops tests

---
 .../riscv/riscv_assembly_emission.mlir        |   3 -
 tests/filecheck/dialects/riscv/riscv_ops.mlir |  24 -
 .../rv32/riscv_assembly_emission.mlir         | 368 ++++++++++
 tests/filecheck/dialects/rv32/rv32_ops.mlir   | 653 ++++++++++++++++++
 .../rv64/riscv_assembly_emission.mlir         | 368 ++++++++++
 tests/filecheck/dialects/rv64/rv64_ops.mlir   | 653 ++++++++++++++++++
 6 files changed, 2042 insertions(+), 27 deletions(-)
 create mode 100644 tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
 create mode 100644 tests/filecheck/dialects/rv32/rv32_ops.mlir
 create mode 100644 tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
 create mode 100644 tests/filecheck/dialects/rv64/rv64_ops.mlir

diff --git a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
index 8291489c86..58c08c2cfa 100644
--- a/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_assembly_emission.mlir
@@ -156,9 +156,6 @@
     %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
     // CHECK-NEXT: csrrwi zero, 1024, 8
 
-    // Assembler pseudo-instructions
-    %li = rv32.li 1: !riscv.reg<j_0>
-    // CHECK-NEXT: li j_0, 1
     // Environment Call and Breakpoints
     riscv.ecall
     // CHECK-NEXT: ecall
diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir
index 9ae2bbb3c8..8bd246af16 100644
--- a/tests/filecheck/dialects/riscv/riscv_ops.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_ops.mlir
@@ -271,10 +271,6 @@
     %czeronezop = riscv.czero.nez %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
     // CHECK-NEXT: %{{.*}} = riscv.czero.nez %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
 
-    // Assembler pseudo-instructions
-
-    %li = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
     // Environment Call and Breakpoints
     riscv.ecall
     // CHECK-NEXT: riscv.ecall
@@ -284,19 +280,6 @@
     // CHECK-NEXT: riscv.directive ".bss"
     riscv.directive ".align" "2"
     // CHECK-NEXT: riscv.directive ".align" "2"
-    riscv.assembly_section ".text" attributes {"foo" = i32} {
-      %nested_li = rv32.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
-    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
-
-    riscv.assembly_section ".text" {
-      %nested_li = rv32.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" {
-    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
 
     // Custom instruction
     %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
@@ -573,17 +556,10 @@
 // CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
 // CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
 // CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
 // CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
diff --git a/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
new file mode 100644
index 0000000000..fcf3e7b40f
--- /dev/null
+++ b/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
@@ -0,0 +1,368 @@
+// RUN: xdsl-opt -t riscv-asm %s | filecheck %s
+
+// TODO: Operations will be replaced with rv32 variant-specific counterparts
+
+"builtin.module"() ({
+  riscv_func.func @main() {
+    %0 = rv32.li 6 : !riscv.reg<zero>
+    // CHECK:      li zero, 6
+    %1 = rv32.li 5 : !riscv.reg<j_1>
+    // CHECK-NEXT: li j_1, 5
+    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, zero, j_1
+    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: mv j_2, zero
+    %seqz = riscv.seqz %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: seqz j_1, j_1
+    %snez = riscv.snez %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: snez j_1, j_1
+    %zextb = riscv.zext.b %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: zext.b j_1, j_1
+    %zextw = riscv.zext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: zext.w j_1, j_1
+    %sextw = riscv.sext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: sext.w j_1, j_1
+
+    // RV32I/RV64I: Integer Computational Instructions (Section 2.4)
+    // Integer Register-Immediate Instructions
+    %addi = riscv.addi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: addi j_1, j_1, 1
+    %slti = riscv.slti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slti j_1, j_1, 1
+    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: sltiu j_1, j_1, 1
+    %andi = riscv.andi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: andi j_1, j_1, 1
+    %ori = riscv.ori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: ori j_1, j_1, 1
+    %xori = riscv.xori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: xori j_1, j_1, 1
+    %slli = riscv.slli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slli j_1, j_1, 1
+    %srli = riscv.srli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srli j_1, j_1, 1
+    %srai = riscv.srai %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srai j_1, j_1, 1
+    %lui = riscv.lui 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: lui j_0, 1
+    %auipc = riscv.auipc 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: auipc j_0, 1
+
+    // Integer Register-Register Operations
+    %add = riscv.add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, j_2, j_1
+    %slt = riscv.slt %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: slt j_2, j_2, j_1
+    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sltu j_2, j_2, j_1
+    %and = riscv.and %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: and j_2, j_2, j_1
+    %or = riscv.or %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: or j_2, j_2, j_1
+    %xor = riscv.xor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: xor j_2, j_2, j_1
+    %sll = riscv.sll %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sll j_2, j_2, j_1
+    %srl = riscv.srl %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: srl j_2, j_2, j_1
+    %sub = riscv.sub %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sub j_2, j_2, j_1
+    %sra = riscv.sra %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sra j_2, j_2, j_1
+    riscv.nop
+    // CHECK-NEXT: nop
+
+    // RV32I/RV64I: 2.5 Control Transfer Instructions
+
+    // Unconditional Branch Instructions
+    riscv.jal 1
+    // CHECK-NEXT: jal 1
+    riscv.jal 1, !riscv.reg<s0>
+    // CHECK-NEXT: jal s0, 1
+    riscv.jal "label"
+    // CHECK-NEXT: jal label
+
+    riscv.j 1, !riscv.reg<zero>
+    // CHECK-NEXT: j 1
+    riscv.j "label", !riscv.reg<zero>
+    // CHECK-NEXT: j label
+
+    riscv.jalr %0, 1 : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr zero, 1
+    riscv.jalr %0 1, !riscv.reg<j_0> : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr j_0, zero, 1
+    riscv.jalr %0 "label" : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr zero, label
+
+    riscv.ret
+    // CHECK-NEXT: ret
+  ^bb0(%b00 : !riscv.reg, %b01 : !riscv.reg):
+
+
+    // Conditional Branch Instructions
+    riscv.beq %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: beq j_2, j_1, 1
+    riscv.bne %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bne j_2, j_1, 1
+    riscv.blt %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: blt j_2, j_1, 1
+    riscv.bge %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bge j_2, j_1, 1
+    riscv.bltu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bltu j_2, j_1, 1
+    riscv.bgeu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bgeu j_2, j_1, 1
+
+    // RV32I/RV64I: Load and Store Instructions (Section 2.6)
+    %lb = riscv.lb %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lb j_2, j_1, 1
+    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lbu j_2, j_1, 1
+    %lh = riscv.lh %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lh j_2, j_1, 1
+    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lhu j_2, j_1, 1
+    %lw = riscv.lw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lw j_2, 1(j_1)
+
+    riscv.sb %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sb j_2, j_1, 1
+    riscv.sh %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sh j_2, j_1, 1
+    riscv.sw %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sw j_1, 1(j_2)
+
+    // RV32I/RV64I: Control and Status Register Instructions (Section 2.8)
+    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrw j_1, 1024, j_2
+    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrw zero, 1024, j_2
+    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrs zero, 1024, j_2
+    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: csrrs j_2, 1024, zero
+    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, j_2
+    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, zero
+    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrsi j_1, 1024, 8
+    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrsi j_0, 1024, 0
+    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrci j_0, 1024, 8
+    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrci j_1, 1024, 0
+    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrwi j_0, 1024, 8
+    %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrwi zero, 1024, 8
+
+    // Assembler pseudo-instructions
+    %li = rv32.li 1: !riscv.reg<j_0>
+    // CHECK-NEXT: li j_0, 1
+    // Environment Call and Breakpoints
+    riscv.ecall
+    // CHECK-NEXT: ecall
+    riscv.ebreak
+    // CHECK-NEXT: ebreak
+    riscv.ret
+    // CHECK-NEXT: ret
+  ^bb1(%b10 : !riscv.reg, %b11 : !riscv.reg):
+
+    riscv.directive ".align" "2"
+    // CHECK-NEXT: .align 2
+    riscv.assembly_section ".text" {
+      %inner = rv32.li 5 : !riscv.reg<j_1>
+      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    }
+    // CHECK-NEXT:  li j_1, 5
+    // CHECK-NEXT:  addi j_1, j_1, 1
+    riscv.label "label0"
+    // CHECK-NEXT: label0:
+
+
+    // Custom instruction
+    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j_1>) -> (!riscv.reg<j_3>, !riscv.reg<j_4>)
+    // CHECK-NEXT:   hello j_3, j_4, zero, j_1
+
+
+    // RISC-V Extensions
+
+    riscv_snitch.frep_outer %0 {
+      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    }
+
+    // CHECK:          frep.o zero, 1, 0, 0
+    // CHECK-NEXT:     add  j_2, zero, j_1
+
+    riscv_snitch.frep_inner %0 {
+      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    }
+    // CHECK:          frep.i zero, 1, 0, 0
+    // CHECK-NEXT:     add  j_2, zero, j_1
+    
+    //RV32B/RV64B: "B" Extension for Bit Manipulation, Version 1.0.0
+    %rol = riscv.rol %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rol j_2, j_2, j_1
+    %ror = riscv.ror %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: ror j_2, j_2, j_1
+    %rolw = riscv.rolw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rolw j_2, j_2, j_1
+    %rorw = riscv.rorw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rorw j_2, j_2, j_1
+    %rori = riscv.rori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: rori j_1, j_1, 1
+    %roriw = riscv.roriw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: roriw j_1, j_1, 1
+    %bclr = riscv.bclr %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: bclr j_2, j_2, j_1
+    %bclri = riscv.bclri %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: bclri j_1, j_1, 1
+    %bseti = riscv.bseti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: bseti j_1, j_1, 1
+    %adduw = riscv.add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add.uw j_2, j_2, j_1
+    %sh1add = riscv.sh1add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh1add j_2, j_2, j_1
+    %sh2add = riscv.sh2add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh2add j_2, j_2, j_1
+    %sh3add = riscv.sh3add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh3add j_2, j_2, j_1
+    %sh1adduw = riscv.sh1add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh1add.uw j_2, j_2, j_1
+    %sh2adduw = riscv.sh2add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh2add.uw j_2, j_2, j_1
+    %sh3adduw = riscv.sh3add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh3add.uw j_2, j_2, j_1
+    %slliuw = riscv.slli.uw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slli.uw j_1, j_1, 1
+    %andn = riscv.andn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: andn j_2, j_2, j_1
+    %orn = riscv.orn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: orn j_2, j_2, j_1
+    %xnor = riscv.xnor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: xnor j_2, j_2, j_1
+    %max = riscv.max %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: max j_2, j_2, j_1
+    %maxu = riscv.maxu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: maxu j_2, j_2, j_1
+    %min = riscv.min %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: min j_2, j_2, j_1
+    %minu = riscv.minu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: minu j_2, j_2, j_1
+    
+    // "ZiCond" Conditional" operations extension
+    %czeroeqz = riscv.czero.eqz %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: czero.eqz j_2, j_2, j_1
+    %czeronez = riscv.czero.nez %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: czero.nez j_2, j_2, j_1
+
+    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
+
+    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.s.w fj_0, zero
+    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_1>
+    // CHECK-NEXT: fcvt.s.wu fj_1, j_1
+    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_2>
+    // CHECK-NEXT: fcvt.s.wu fj_2, j_1
+    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmadd.s fj_3, fj_0, fj_1, fj_2
+    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmsub.s fj_3, fj_0, fj_1, fj_2
+    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fnmsub.s fj_3, fj_0, fj_1, fj_2
+    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fnmadd.s fj_3, fj_0, fj_1, fj_2
+    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fadd.s fj_3, fj_0, fj_1
+    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsub.s fj_3, fj_0, fj_1
+    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmul.s fj_3, fj_0, fj_1
+    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fdiv.s fj_3, fj_0, fj_1
+    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<fj_0>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsqrt.s fj_3, fj_0
+    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnj.s fj_3, fj_0, fj_1
+    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnjn.s fj_3, fj_0, fj_1
+    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnjx.s fj_3, fj_0, fj_1
+    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmin.s fj_3, fj_0, fj_1
+    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmax.s fj_3, fj_0, fj_1
+    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fcvt.w.s j_3, fj_0
+    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fcvt.wu.s j_3, fj_0
+    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fmv.x.w j_3, fj_0
+    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: feq.s j_3, fj_0, fj_1
+    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: flt.s j_3, fj_0, fj_1
+    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fle.s j_3, fj_0, fj_1
+    %fclass = riscv.fclass.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fclass.s j_3, fj_0
+    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fcvt.s.w fj_3, zero
+    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fcvt.s.wu fj_3, zero
+    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmv.w.x fj_3, zero
+    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: flw fj_3, 1(zero)
+    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
+    // CHECK-NEXT: fsw fj_0, 1(zero)
+
+    // RV32F: 9 "D" Standard Extension for Double-Precision Floating-Point, Version 2.0
+
+    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fld fj_3, 1(zero)
+
+    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fld fj_3, hello, zero
+
+    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
+    // CHECK-NEXT: fsd fj_0, 1(zero)
+
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmadd.d fj_3, fj_0, fj_1, fj_2
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmsub.d fj_3, fj_0, fj_1, fj_2
+    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fadd.d fj_3, fj_0, fj_1
+    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsub.d fj_3, fj_0, fj_1
+    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmul.d fj_3, fj_0, fj_1
+    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fdiv.d fj_3, fj_0, fj_1
+    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmin.d fj_3, fj_0, fj_1
+    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmax.d fj_3, fj_0, fj_1
+
+    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.d.w fj_0, j_1
+    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.d.wu fj_0, j_1
+
+    // Vector Ops
+    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: vfadd.s fj_3, fj_0, fj_1
+    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: vfmul.s fj_3, fj_0, fj_1
+
+    // Terminate block
+    riscv_func.return
+    // CHECK-NEXT: ret
+  }
+// External
+riscv_func.func @external()
+// CHECK-NOT: external
+}) : () -> ()
diff --git a/tests/filecheck/dialects/rv32/rv32_ops.mlir b/tests/filecheck/dialects/rv32/rv32_ops.mlir
new file mode 100644
index 0000000000..5b0c844bdb
--- /dev/null
+++ b/tests/filecheck/dialects/rv32/rv32_ops.mlir
@@ -0,0 +1,653 @@
+// RUN: XDSL_ROUNDTRIP
+// RUN: XDSL_GENERIC_ROUNDTRIP
+
+// TODO: Operations will be replaced with rv32 variant-specific counterparts
+
+"builtin.module"() ({
+  riscv_func.func @main() {
+    %0 = riscv.get_register : !riscv.reg
+    %1 = riscv.get_register : !riscv.reg
+    // RV32I/RV64I: 2.4 Integer Computational Instructions
+
+    // Integer Register-Immediate Instructions
+    %addi = riscv.addi %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.addi %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %slti = riscv.slti %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slti %0, 1 : (!riscv.reg) -> !riscv.reg
+    %sltiu = riscv.sltiu %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sltiu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %andi = riscv.andi %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.andi %0, 1 : (!riscv.reg) -> !riscv.reg
+    %ori = riscv.ori %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.ori %0, 1 : (!riscv.reg) -> !riscv.reg
+    %xori = riscv.xori %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xori %0, 1 : (!riscv.reg) -> !riscv.reg
+    %slli = riscv.slli %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slli %0, 1 : (!riscv.reg) -> !riscv.reg
+    %srli = riscv.srli %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srli %0, 1 : (!riscv.reg) -> !riscv.reg
+    %srai = riscv.srai %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srai %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lui = riscv.lui 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lui 1 : () -> !riscv.reg
+    %auipc = riscv.auipc 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.auipc 1 : () -> !riscv.reg
+    %mv = riscv.mv %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.mv %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %seqz = riscv.seqz %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.seqz %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %snez = riscv.snez %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.snez %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zextb = riscv.zext.b %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.zext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zextw = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.zext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %sextw = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.sext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %srliw = riscv.srliw %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srliw %0, 1 : (!riscv.reg) -> !riscv.reg
+    %sraiw = riscv.sraiw %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sraiw %0, 1 : (!riscv.reg) -> !riscv.reg
+
+    // Integer Register-Register Operations
+    %add = riscv.add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %slt = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slt %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sltu = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sltu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %and = riscv.and %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.and %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %or = riscv.or %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.or %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %xor = riscv.xor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sll = riscv.sll %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sll %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %srl = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srl %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sub = riscv.sub %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sra = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sra %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %addw = riscv.addw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.addw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %subw = riscv.subw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.subw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sllw = riscv.sllw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sllw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %srlw = riscv.srlw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srlw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sraw = riscv.sraw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sraw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    riscv.nop
+    // CHECK-NEXT: riscv.nop
+
+    // RV32I/RV64I: 2.5 Control Transfer Instructions
+
+    // Unconditional Branch Instructions
+    riscv.jal 1
+    // CHECK-NEXT: riscv.jal 1
+    riscv.jal 1, !riscv.reg
+    // CHECK-NEXT: riscv.jal 1, !riscv.reg
+    riscv.jal "label"
+    // CHECK-NEXT: riscv.jal "label"
+
+    riscv.j 1
+    // CHECK-NEXT: riscv.j 1
+    riscv.j "label"
+    // CHECK-NEXT: riscv.j "label"
+
+    riscv.jalr %0, 1: (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, 1 : (!riscv.reg) -> ()
+    riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
+    riscv.jalr %0, "label" : (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, "label" : (!riscv.reg) -> ()
+
+    riscv.ret
+    // CHECK-NEXT: riscv.ret
+  ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+  // CHECK-NEXT: ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+
+    // Conditional Branch Instructions
+    riscv.beq %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.beq %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bne %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bne %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.blt %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.blt %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bge %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bge %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bltu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bltu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bgeu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bgeu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+
+    // RV32I/RV64I: 2.6 Load and Store Instructions
+
+    %lb = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lbu = riscv.lbu %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lbu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lh = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lhu = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lw = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
+    riscv.sb %0, %1, 1: (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sb %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+
+    // RV32I/RV64I: 2.8 Control and Status Register Instructions
+
+    %csrrw_rw = riscv.csrrw %0 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrw_w = riscv.csrrw %0 1024, "w" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024, "w" : (!riscv.reg) -> !riscv.reg
+    %csrrs_rw = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    %csrrc_rw = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrc_r = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 8 : () -> !riscv.reg
+    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 0 : () -> !riscv.reg
+    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 8 : () -> !riscv.reg
+    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 0 : () -> !riscv.reg
+    %csrrwi_rw = riscv.csrrwi 1024, 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1 : () -> !riscv.reg
+    %csrrwi_w = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
+
+    // Machine Mode Privileged Instructions
+    riscv.wfi
+    // CHECK-NEXT: riscv.wfi
+
+
+    // RV32M/RV64M: 7 “M” Standard Extension for Integer Multiplication and Division
+
+    // Multiplication Operations
+    %mul = riscv.mul %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulh = riscv.mulh %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulh %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulhsu = riscv.mulhsu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulhsu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulhu = riscv.mulhu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulhu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulw = riscv.mulw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+
+    // Division Operations
+    %div = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.div %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divu = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divw = riscv.divw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divuw = riscv.divuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rem = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rem %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remu = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remw = riscv.remw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remuw = riscv.remuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+    // RV32B/RV64B:  “B” Standard Extension for Bit Manipulation
+
+    %rol = riscv.rol %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rol %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %ror = riscv.ror %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.ror %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rori = riscv.rori %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rori %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %roriw = riscv.roriw %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.roriw %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %rolw = riscv.rolw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rolw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rorw = riscv.rorw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rorw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bclr = riscv.bclr %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bclr %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bext = riscv.bext %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bext %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bset = riscv.bset %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bset %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %binv = riscv.binv %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.binv %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %adduw = riscv.add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh1add = riscv.sh1add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh1add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh1adduw = riscv.sh1add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh1add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh2add = riscv.sh2add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh2add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh2adduw = riscv.sh2add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh2add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh3add = riscv.sh3add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh3add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh3adduw = riscv.sh3add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh3add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sextb = riscv.sext.b %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %sexth = riscv.sext.h %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zexth = riscv.zext.h %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.zext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %andn = riscv.andn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.andn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %xnor = riscv.xnor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xnor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %orn = riscv.orn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.orn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %max = riscv.max %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.max %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %maxu = riscv.maxu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.maxu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %min = riscv.min %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.min %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %minu = riscv.minu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.minu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+
+    // RV32/RV64 Zicond extension for conditional operations
+
+    %czeroeqzop = riscv.czero.eqz %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.czero.eqz %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %czeronezop = riscv.czero.nez %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.czero.nez %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+    // Assembler pseudo-instructions
+
+    %li = rv32.li 1 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
+    // Environment Call and Breakpoints
+    riscv.ecall
+    // CHECK-NEXT: riscv.ecall
+    riscv.ebreak
+    // CHECK-NEXT: riscv.ebreak
+    riscv.directive ".bss"
+    // CHECK-NEXT: riscv.directive ".bss"
+    riscv.directive ".align" "2"
+    // CHECK-NEXT: riscv.directive ".align" "2"
+    riscv.assembly_section ".text" attributes {"foo" = i32} {
+      %nested_li = rv32.li 1 : !riscv.reg
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
+    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
+    // CHECK-NEXT:  }
+
+    riscv.assembly_section ".text" {
+      %nested_li = rv32.li 1 : !riscv.reg
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" {
+    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
+    // CHECK-NEXT:  }
+
+    // Custom instruction
+    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+    // CHECK-NEXT:   %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+
+    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
+    %f0 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+    %f1 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+    %f2 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+
+    %fmv = riscv.fmv.s %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %fmadd_s = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmsub_s = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fnmsub_s = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fnmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fnmadd_s = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fnmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_s_fm = riscv.fadd.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_s_fm = riscv.fsub.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_s_fm = riscv.fmul.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_s_fm = riscv.fdiv.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fsqrt_s = riscv.fsqrt.s %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsqrt.s %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %fsgnj_s = riscv.fsgnj.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnj.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsgnjn_s = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnjn.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsgnjx_s = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnjx.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_s = riscv.fmin.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_s = riscv.fmax.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_s_fm = riscv.fmin.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_s_fm = riscv.fmax.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fcvt_w_s = riscv.fcvt.w.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.w.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fcvt_wu_s = riscv.fcvt.wu.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.wu.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fmv_x_w = riscv.fmv.x.w %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.x.w %{{.*}} : (!riscv.freg) -> !riscv.reg
+
+    %feq_s = riscv.feq.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %flt_s = riscv.flt.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fle_s = riscv.fle.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %feq_s_fm = riscv.feq.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %flt_s_fm = riscv.flt.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fle_s_fm = riscv.fle.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fclass_s = riscv.fclass.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fclass.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fcvt_s_w = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.w %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fcvt_s_wu = riscv.fcvt.s.wu %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fmv_w_x = riscv.fmv.w.x %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %{{.*}} : (!riscv.reg) -> !riscv.freg
+
+    %flw = riscv.flw %0, 1 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.flw %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
+    riscv.fsw %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
+    // CHECK-NEXT: riscv.fsw %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
+
+    // Vector Ops
+    %fld = riscv.fld %0, 1 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fld %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
+    riscv.fsd %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
+    // CHECK-NEXT: riscv.fsd %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
+
+    %fmv_d = riscv.fmv.d %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.d %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.vfadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.vfmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    // RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
+
+    %fadd_d = riscv.fadd.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_d_fm = riscv.fadd.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_d_fm = riscv.fsub.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_d_fm = riscv.fmul.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_d_fm = riscv.fdiv.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmadd.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmsub.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_d_fm = riscv.fmin.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_d_fm = riscv.fmax.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fcvt_d_w = riscv.fcvt.d.w %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fcvt_d_wu = riscv.fcvt.d.wu %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
+
+    %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+    // CHECK-NEXT: %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+
+    // Terminate block
+    riscv_func.return
+  }
+}) : () -> ()
+
+// CHECK-GENERIC:       "builtin.module"() ({
+// CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
+// CHECK-GENERIC-NEXT:      %0 = "riscv.get_register"() : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %1 = "riscv.get_register"() : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %addi = "riscv.addi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slti = "riscv.slti"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sltiu = "riscv.sltiu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %andi = "riscv.andi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %ori = "riscv.ori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xori = "riscv.xori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slli = "riscv.slli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srli = "riscv.srli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srai = "riscv.srai"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lui = "riscv.lui"() {immediate = 1 : i20} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %auipc = "riscv.auipc"() {immediate = 1 : i20} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mv = "riscv.mv"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %seqz = "riscv.seqz"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %snez = "riscv.snez"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zextb = "riscv.zext.b"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zextw = "riscv.zext.w"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sextw = "riscv.sext.w"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srliw = "riscv.srliw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sraiw = "riscv.sraiw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %add = "riscv.add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slt = "riscv.slt"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sltu = "riscv.sltu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %and = "riscv.and"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %or = "riscv.or"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xor = "riscv.xor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sll = "riscv.sll"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srl = "riscv.srl"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sub = "riscv.sub"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sra = "riscv.sra"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %addw = "riscv.addw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %subw = "riscv.subw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sllw = "riscv.sllw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srlw = "riscv.srlw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sraw = "riscv.sraw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.nop"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20, rd = !riscv.reg} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = #riscv.label<"label">} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = 1 : si20} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = #riscv.label<"label">} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12, rd = !riscv.reg} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = #riscv.label<"label">} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.ret"() : () -> ()
+// CHECK-GENERIC-NEXT:    ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+// CHECK-GENERIC-NEXT:      "riscv.beq"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bne"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.blt"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bge"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bltu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bgeu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      %lb = "riscv.lb"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lbu = "riscv.lbu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lh = "riscv.lh"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lhu = "riscv.lhu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lw = "riscv.lw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.sb"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.sh"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.sw"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      %csrrw_rw = "riscv.csrrw"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrw_w = "riscv.csrrw"(%0) {csr = 1024 : i32, writeonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrs_rw = "riscv.csrrs"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrs_r = "riscv.csrrs"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrc_rw = "riscv.csrrc"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrc_r = "riscv.csrrc"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrsi_rw = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrsi_r = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrci_rw = "riscv.csrrci"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrci_r = "riscv.csrrci"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrwi_rw = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrwi_w = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32, writeonly} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.wfi"() : () -> ()
+// CHECK-GENERIC-NEXT:      %mul = "riscv.mul"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulh = "riscv.mulh"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulhsu = "riscv.mulhsu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulhu = "riscv.mulhu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulw = "riscv.mulw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %div = "riscv.div"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divu = "riscv.divu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divw = "riscv.divw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divuw = "riscv.divuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rem = "riscv.rem"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remu = "riscv.remu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remw = "riscv.remw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remuw = "riscv.remuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rol = "riscv.rol"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %ror = "riscv.ror"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rori = "riscv.rori"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %roriw = "riscv.roriw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rolw = "riscv.rolw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rorw = "riscv.rorw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bclr = "riscv.bclr"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bext = "riscv.bext"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bset = "riscv.bset"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %binv = "riscv.binv"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %adduw = "riscv.add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh1add = "riscv.sh1add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh1adduw = "riscv.sh1add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh2add = "riscv.sh2add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh2adduw = "riscv.sh2add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh3add = "riscv.sh3add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh3adduw = "riscv.sh3add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sextb = "riscv.sext.b"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sexth = "riscv.sext.h"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zexth = "riscv.zext.h"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %andn = "riscv.andn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xnor = "riscv.xnor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %orn = "riscv.orn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %max = "riscv.max"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %maxu = "riscv.maxu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %min = "riscv.min"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
+// CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+// CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %f2 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmv = "riscv.fmv.s"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmadd_s = "riscv.fmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmsub_s = "riscv.fmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fnmsub_s = "riscv.fnmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fnmadd_s = "riscv.fnmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_s = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_s = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_s = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_s = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_s_fm = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_s_fm = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_s_fm = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_s_fm = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsqrt_s = "riscv.fsqrt.s"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnj_s = "riscv.fsgnj.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnjn_s = "riscv.fsgnjn.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnjx_s = "riscv.fsgnjx.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_s = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_s = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_s_fm = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_s_fm = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_w_s = "riscv.fcvt.w.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fcvt_wu_s = "riscv.fcvt.wu.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fmv_x_w = "riscv.fmv.x.w"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %feq_s = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %flt_s = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fle_s = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %feq_s_fm = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %flt_s_fm = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fle_s_fm = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fclass_s = "riscv.fclass.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %flw = "riscv.flw"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      "riscv.fsw"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
+// CHECK-GENERIC-NEXT:      %fld = "riscv.fld"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      "riscv.fsd"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
+// CHECK-GENERIC-NEXT:      %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_d = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_d = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_d = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_d = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_d_fm = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_d_fm = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_d_fm = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_d_fm = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmadd_d = "riscv.fmadd.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmsub_d = "riscv.fmsub.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_d = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_d = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_d_fm = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_d_fm = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_d_w = "riscv.fcvt.d.w"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_d_wu = "riscv.fcvt.d.wu"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = "riscv.parallel_mov"(%0, %1, %f0, %f1) <{input_widths = array<i32: 64, 32, 64, 32>}> : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+// CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
+// CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
+// CHECK-GENERIC-NEXT:  }) : () -> ()
diff --git a/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
new file mode 100644
index 0000000000..678b641701
--- /dev/null
+++ b/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
@@ -0,0 +1,368 @@
+// RUN: xdsl-opt -t riscv-asm %s | filecheck %s
+
+// TODO: Operations will be replaced with rv64 variant-specific counterparts
+
+"builtin.module"() ({
+  riscv_func.func @main() {
+    %0 = rv64.li 6 : !riscv.reg<zero>
+    // CHECK:      li zero, 6
+    %1 = rv64.li 5 : !riscv.reg<j_1>
+    // CHECK-NEXT: li j_1, 5
+    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, zero, j_1
+    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: mv j_2, zero
+    %seqz = riscv.seqz %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: seqz j_1, j_1
+    %snez = riscv.snez %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: snez j_1, j_1
+    %zextb = riscv.zext.b %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: zext.b j_1, j_1
+    %zextw = riscv.zext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: zext.w j_1, j_1
+    %sextw = riscv.sext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: sext.w j_1, j_1
+
+    // RV32I/RV64I: Integer Computational Instructions (Section 2.4)
+    // Integer Register-Immediate Instructions
+    %addi = riscv.addi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: addi j_1, j_1, 1
+    %slti = riscv.slti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slti j_1, j_1, 1
+    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: sltiu j_1, j_1, 1
+    %andi = riscv.andi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: andi j_1, j_1, 1
+    %ori = riscv.ori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: ori j_1, j_1, 1
+    %xori = riscv.xori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: xori j_1, j_1, 1
+    %slli = riscv.slli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slli j_1, j_1, 1
+    %srli = riscv.srli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srli j_1, j_1, 1
+    %srai = riscv.srai %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: srai j_1, j_1, 1
+    %lui = riscv.lui 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: lui j_0, 1
+    %auipc = riscv.auipc 1: () -> !riscv.reg<j_0>
+    // CHECK-NEXT: auipc j_0, 1
+
+    // Integer Register-Register Operations
+    %add = riscv.add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add j_2, j_2, j_1
+    %slt = riscv.slt %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: slt j_2, j_2, j_1
+    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sltu j_2, j_2, j_1
+    %and = riscv.and %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: and j_2, j_2, j_1
+    %or = riscv.or %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: or j_2, j_2, j_1
+    %xor = riscv.xor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: xor j_2, j_2, j_1
+    %sll = riscv.sll %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sll j_2, j_2, j_1
+    %srl = riscv.srl %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: srl j_2, j_2, j_1
+    %sub = riscv.sub %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sub j_2, j_2, j_1
+    %sra = riscv.sra %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sra j_2, j_2, j_1
+    riscv.nop
+    // CHECK-NEXT: nop
+
+    // RV32I/RV64I: 2.5 Control Transfer Instructions
+
+    // Unconditional Branch Instructions
+    riscv.jal 1
+    // CHECK-NEXT: jal 1
+    riscv.jal 1, !riscv.reg<s0>
+    // CHECK-NEXT: jal s0, 1
+    riscv.jal "label"
+    // CHECK-NEXT: jal label
+
+    riscv.j 1, !riscv.reg<zero>
+    // CHECK-NEXT: j 1
+    riscv.j "label", !riscv.reg<zero>
+    // CHECK-NEXT: j label
+
+    riscv.jalr %0, 1 : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr zero, 1
+    riscv.jalr %0 1, !riscv.reg<j_0> : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr j_0, zero, 1
+    riscv.jalr %0 "label" : (!riscv.reg<zero>) -> ()
+    // CHECK-NEXT: jalr zero, label
+
+    riscv.ret
+    // CHECK-NEXT: ret
+  ^bb0(%b00 : !riscv.reg, %b01 : !riscv.reg):
+
+
+    // Conditional Branch Instructions
+    riscv.beq %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: beq j_2, j_1, 1
+    riscv.bne %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bne j_2, j_1, 1
+    riscv.blt %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: blt j_2, j_1, 1
+    riscv.bge %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bge j_2, j_1, 1
+    riscv.bltu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bltu j_2, j_1, 1
+    riscv.bgeu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: bgeu j_2, j_1, 1
+
+    // RV32I/RV64I: Load and Store Instructions (Section 2.6)
+    %lb = riscv.lb %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lb j_2, j_1, 1
+    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lbu j_2, j_1, 1
+    %lh = riscv.lh %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lh j_2, j_1, 1
+    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lhu j_2, j_1, 1
+    %lw = riscv.lw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: lw j_2, 1(j_1)
+
+    riscv.sb %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sb j_2, j_1, 1
+    riscv.sh %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sh j_2, j_1, 1
+    riscv.sw %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
+    // CHECK-NEXT: sw j_1, 1(j_2)
+
+    // RV32I/RV64I: Control and Status Register Instructions (Section 2.8)
+    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrw j_1, 1024, j_2
+    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrw zero, 1024, j_2
+    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrs zero, 1024, j_2
+    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: csrrs j_2, 1024, zero
+    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, j_2
+    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrc j_0, 1024, zero
+    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrsi j_1, 1024, 8
+    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrsi j_0, 1024, 0
+    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrci j_0, 1024, 8
+    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j_1>
+    // CHECK-NEXT: csrrci j_1, 1024, 0
+    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j_0>
+    // CHECK-NEXT: csrrwi j_0, 1024, 8
+    %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
+    // CHECK-NEXT: csrrwi zero, 1024, 8
+
+    // Assembler pseudo-instructions
+    %li = rv64.li 1: !riscv.reg<j_0>
+    // CHECK-NEXT: li j_0, 1
+    // Environment Call and Breakpoints
+    riscv.ecall
+    // CHECK-NEXT: ecall
+    riscv.ebreak
+    // CHECK-NEXT: ebreak
+    riscv.ret
+    // CHECK-NEXT: ret
+  ^bb1(%b10 : !riscv.reg, %b11 : !riscv.reg):
+
+    riscv.directive ".align" "2"
+    // CHECK-NEXT: .align 2
+    riscv.assembly_section ".text" {
+      %inner = rv64.li 5 : !riscv.reg<j_1>
+      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    }
+    // CHECK-NEXT:  li j_1, 5
+    // CHECK-NEXT:  addi j_1, j_1, 1
+    riscv.label "label0"
+    // CHECK-NEXT: label0:
+
+
+    // Custom instruction
+    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j_1>) -> (!riscv.reg<j_3>, !riscv.reg<j_4>)
+    // CHECK-NEXT:   hello j_3, j_4, zero, j_1
+
+
+    // RISC-V Extensions
+
+    riscv_snitch.frep_outer %0 {
+      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    }
+
+    // CHECK:          frep.o zero, 1, 0, 0
+    // CHECK-NEXT:     add  j_2, zero, j_1
+
+    riscv_snitch.frep_inner %0 {
+      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    }
+    // CHECK:          frep.i zero, 1, 0, 0
+    // CHECK-NEXT:     add  j_2, zero, j_1
+    
+    //RV32B/RV64B: "B" Extension for Bit Manipulation, Version 1.0.0
+    %rol = riscv.rol %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rol j_2, j_2, j_1
+    %ror = riscv.ror %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: ror j_2, j_2, j_1
+    %rolw = riscv.rolw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rolw j_2, j_2, j_1
+    %rorw = riscv.rorw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: rorw j_2, j_2, j_1
+    %rori = riscv.rori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: rori j_1, j_1, 1
+    %roriw = riscv.roriw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: roriw j_1, j_1, 1
+    %bclr = riscv.bclr %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: bclr j_2, j_2, j_1
+    %bclri = riscv.bclri %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: bclri j_1, j_1, 1
+    %bseti = riscv.bseti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: bseti j_1, j_1, 1
+    %adduw = riscv.add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: add.uw j_2, j_2, j_1
+    %sh1add = riscv.sh1add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh1add j_2, j_2, j_1
+    %sh2add = riscv.sh2add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh2add j_2, j_2, j_1
+    %sh3add = riscv.sh3add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh3add j_2, j_2, j_1
+    %sh1adduw = riscv.sh1add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh1add.uw j_2, j_2, j_1
+    %sh2adduw = riscv.sh2add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh2add.uw j_2, j_2, j_1
+    %sh3adduw = riscv.sh3add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: sh3add.uw j_2, j_2, j_1
+    %slliuw = riscv.slli.uw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
+    // CHECK-NEXT: slli.uw j_1, j_1, 1
+    %andn = riscv.andn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: andn j_2, j_2, j_1
+    %orn = riscv.orn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: orn j_2, j_2, j_1
+    %xnor = riscv.xnor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: xnor j_2, j_2, j_1
+    %max = riscv.max %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: max j_2, j_2, j_1
+    %maxu = riscv.maxu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: maxu j_2, j_2, j_1
+    %min = riscv.min %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: min j_2, j_2, j_1
+    %minu = riscv.minu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: minu j_2, j_2, j_1
+    
+    // "ZiCond" Conditional" operations extension
+    %czeroeqz = riscv.czero.eqz %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: czero.eqz j_2, j_2, j_1
+    %czeronez = riscv.czero.nez %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
+    // CHECK-NEXT: czero.nez j_2, j_2, j_1
+
+    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
+
+    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.s.w fj_0, zero
+    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_1>
+    // CHECK-NEXT: fcvt.s.wu fj_1, j_1
+    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_2>
+    // CHECK-NEXT: fcvt.s.wu fj_2, j_1
+    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmadd.s fj_3, fj_0, fj_1, fj_2
+    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmsub.s fj_3, fj_0, fj_1, fj_2
+    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fnmsub.s fj_3, fj_0, fj_1, fj_2
+    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fnmadd.s fj_3, fj_0, fj_1, fj_2
+    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fadd.s fj_3, fj_0, fj_1
+    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsub.s fj_3, fj_0, fj_1
+    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmul.s fj_3, fj_0, fj_1
+    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fdiv.s fj_3, fj_0, fj_1
+    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<fj_0>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsqrt.s fj_3, fj_0
+    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnj.s fj_3, fj_0, fj_1
+    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnjn.s fj_3, fj_0, fj_1
+    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsgnjx.s fj_3, fj_0, fj_1
+    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmin.s fj_3, fj_0, fj_1
+    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmax.s fj_3, fj_0, fj_1
+    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fcvt.w.s j_3, fj_0
+    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fcvt.wu.s j_3, fj_0
+    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fmv.x.w j_3, fj_0
+    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: feq.s j_3, fj_0, fj_1
+    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: flt.s j_3, fj_0, fj_1
+    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fle.s j_3, fj_0, fj_1
+    %fclass = riscv.fclass.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
+    // CHECK-NEXT: fclass.s j_3, fj_0
+    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fcvt.s.w fj_3, zero
+    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fcvt.s.wu fj_3, zero
+    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmv.w.x fj_3, zero
+    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: flw fj_3, 1(zero)
+    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
+    // CHECK-NEXT: fsw fj_0, 1(zero)
+
+    // RV32F: 9 "D" Standard Extension for Double-Precision Floating-Point, Version 2.0
+
+    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fld fj_3, 1(zero)
+
+    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fld fj_3, hello, zero
+
+    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
+    // CHECK-NEXT: fsd fj_0, 1(zero)
+
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmadd.d fj_3, fj_0, fj_1, fj_2
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmsub.d fj_3, fj_0, fj_1, fj_2
+    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fadd.d fj_3, fj_0, fj_1
+    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fsub.d fj_3, fj_0, fj_1
+    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmul.d fj_3, fj_0, fj_1
+    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fdiv.d fj_3, fj_0, fj_1
+    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmin.d fj_3, fj_0, fj_1
+    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: fmax.d fj_3, fj_0, fj_1
+
+    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.d.w fj_0, j_1
+    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
+    // CHECK-NEXT: fcvt.d.wu fj_0, j_1
+
+    // Vector Ops
+    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: vfadd.s fj_3, fj_0, fj_1
+    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
+    // CHECK-NEXT: vfmul.s fj_3, fj_0, fj_1
+
+    // Terminate block
+    riscv_func.return
+    // CHECK-NEXT: ret
+  }
+// External
+riscv_func.func @external()
+// CHECK-NOT: external
+}) : () -> ()
diff --git a/tests/filecheck/dialects/rv64/rv64_ops.mlir b/tests/filecheck/dialects/rv64/rv64_ops.mlir
new file mode 100644
index 0000000000..1897676952
--- /dev/null
+++ b/tests/filecheck/dialects/rv64/rv64_ops.mlir
@@ -0,0 +1,653 @@
+// RUN: XDSL_ROUNDTRIP
+// RUN: XDSL_GENERIC_ROUNDTRIP
+ 
+// TODO: Operations will be replaced with rv64 variant-specific counterparts
+
+"builtin.module"() ({
+  riscv_func.func @main() {
+    %0 = riscv.get_register : !riscv.reg
+    %1 = riscv.get_register : !riscv.reg
+    // RV32I/RV64I: 2.4 Integer Computational Instructions
+
+    // Integer Register-Immediate Instructions
+    %addi = riscv.addi %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.addi %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %slti = riscv.slti %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slti %0, 1 : (!riscv.reg) -> !riscv.reg
+    %sltiu = riscv.sltiu %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sltiu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %andi = riscv.andi %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.andi %0, 1 : (!riscv.reg) -> !riscv.reg
+    %ori = riscv.ori %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.ori %0, 1 : (!riscv.reg) -> !riscv.reg
+    %xori = riscv.xori %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xori %0, 1 : (!riscv.reg) -> !riscv.reg
+    %slli = riscv.slli %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slli %0, 1 : (!riscv.reg) -> !riscv.reg
+    %srli = riscv.srli %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srli %0, 1 : (!riscv.reg) -> !riscv.reg
+    %srai = riscv.srai %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srai %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lui = riscv.lui 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lui 1 : () -> !riscv.reg
+    %auipc = riscv.auipc 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.auipc 1 : () -> !riscv.reg
+    %mv = riscv.mv %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.mv %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %seqz = riscv.seqz %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.seqz %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %snez = riscv.snez %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.snez %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zextb = riscv.zext.b %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.zext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zextw = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.zext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %sextw = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK: %{{.*}} = riscv.sext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %srliw = riscv.srliw %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srliw %0, 1 : (!riscv.reg) -> !riscv.reg
+    %sraiw = riscv.sraiw %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sraiw %0, 1 : (!riscv.reg) -> !riscv.reg
+
+    // Integer Register-Register Operations
+    %add = riscv.add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %slt = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.slt %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sltu = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sltu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %and = riscv.and %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.and %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %or = riscv.or %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.or %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %xor = riscv.xor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sll = riscv.sll %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sll %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %srl = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srl %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sub = riscv.sub %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sra = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sra %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %addw = riscv.addw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.addw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %subw = riscv.subw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.subw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sllw = riscv.sllw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sllw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %srlw = riscv.srlw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.srlw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sraw = riscv.sraw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sraw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    riscv.nop
+    // CHECK-NEXT: riscv.nop
+
+    // RV32I/RV64I: 2.5 Control Transfer Instructions
+
+    // Unconditional Branch Instructions
+    riscv.jal 1
+    // CHECK-NEXT: riscv.jal 1
+    riscv.jal 1, !riscv.reg
+    // CHECK-NEXT: riscv.jal 1, !riscv.reg
+    riscv.jal "label"
+    // CHECK-NEXT: riscv.jal "label"
+
+    riscv.j 1
+    // CHECK-NEXT: riscv.j 1
+    riscv.j "label"
+    // CHECK-NEXT: riscv.j "label"
+
+    riscv.jalr %0, 1: (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, 1 : (!riscv.reg) -> ()
+    riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
+    riscv.jalr %0, "label" : (!riscv.reg) -> ()
+    // CHECK-NEXT: riscv.jalr %0, "label" : (!riscv.reg) -> ()
+
+    riscv.ret
+    // CHECK-NEXT: riscv.ret
+  ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+  // CHECK-NEXT: ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+
+    // Conditional Branch Instructions
+    riscv.beq %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.beq %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bne %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bne %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.blt %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.blt %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bge %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bge %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bltu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bltu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.bgeu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.bgeu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
+
+    // RV32I/RV64I: 2.6 Load and Store Instructions
+
+    %lb = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lbu = riscv.lbu %0, 1: (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lbu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lh = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lhu = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
+    %lw = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
+    riscv.sb %0, %1, 1: (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sb %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+    // CHECK-NEXT: riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
+
+    // RV32I/RV64I: 2.8 Control and Status Register Instructions
+
+    %csrrw_rw = riscv.csrrw %0 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrw_w = riscv.csrrw %0 1024, "w" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024, "w" : (!riscv.reg) -> !riscv.reg
+    %csrrs_rw = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    %csrrc_rw = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
+    %csrrc_r = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
+    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 8 : () -> !riscv.reg
+    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 0 : () -> !riscv.reg
+    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 8 : () -> !riscv.reg
+    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 0 : () -> !riscv.reg
+    %csrrwi_rw = riscv.csrrwi 1024, 1 : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1 : () -> !riscv.reg
+    %csrrwi_w = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
+
+    // Machine Mode Privileged Instructions
+    riscv.wfi
+    // CHECK-NEXT: riscv.wfi
+
+
+    // RV32M/RV64M: 7 “M” Standard Extension for Integer Multiplication and Division
+
+    // Multiplication Operations
+    %mul = riscv.mul %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulh = riscv.mulh %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulh %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulhsu = riscv.mulhsu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulhsu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulhu = riscv.mulhu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulhu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %mulw = riscv.mulw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.mulw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+
+    // Division Operations
+    %div = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.div %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divu = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divw = riscv.divw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %divuw = riscv.divuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.divuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rem = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rem %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remu = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remw = riscv.remw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %remuw = riscv.remuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.remuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+    // RV32B/RV64B:  “B” Standard Extension for Bit Manipulation
+
+    %rol = riscv.rol %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rol %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %ror = riscv.ror %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.ror %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rori = riscv.rori %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rori %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %roriw = riscv.roriw %0, 1 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.roriw %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
+    %rolw = riscv.rolw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rolw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %rorw = riscv.rorw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.rorw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bclr = riscv.bclr %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bclr %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bext = riscv.bext %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bext %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %bset = riscv.bset %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.bset %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %binv = riscv.binv %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.binv %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %adduw = riscv.add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh1add = riscv.sh1add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh1add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh1adduw = riscv.sh1add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh1add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh2add = riscv.sh2add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh2add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh2adduw = riscv.sh2add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh2add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh3add = riscv.sh3add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh3add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sh3adduw = riscv.sh3add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sh3add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %sextb = riscv.sext.b %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %sexth = riscv.sext.h %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.sext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %zexth = riscv.zext.h %0 : (!riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.zext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
+    %andn = riscv.andn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.andn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %xnor = riscv.xnor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.xnor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %orn = riscv.orn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.orn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %max = riscv.max %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.max %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %maxu = riscv.maxu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.maxu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %min = riscv.min %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.min %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %minu = riscv.minu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.minu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+
+    // RV32/RV64 Zicond extension for conditional operations
+
+    %czeroeqzop = riscv.czero.eqz %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.czero.eqz %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    %czeronezop = riscv.czero.nez %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.czero.nez %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
+
+    // Assembler pseudo-instructions
+
+    %li = rv64.li 1 : !riscv.reg
+    // CHECK-NEXT: %{{.*}} = rv64.li 1 : !riscv.reg
+    // Environment Call and Breakpoints
+    riscv.ecall
+    // CHECK-NEXT: riscv.ecall
+    riscv.ebreak
+    // CHECK-NEXT: riscv.ebreak
+    riscv.directive ".bss"
+    // CHECK-NEXT: riscv.directive ".bss"
+    riscv.directive ".align" "2"
+    // CHECK-NEXT: riscv.directive ".align" "2"
+    riscv.assembly_section ".text" attributes {"foo" = i64} {
+      %nested_li = rv64.li 1 : !riscv.reg
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i64} {
+    // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
+    // CHECK-NEXT:  }
+
+    riscv.assembly_section ".text" {
+      %nested_li = rv64.li 1 : !riscv.reg
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" {
+    // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
+    // CHECK-NEXT:  }
+
+    // Custom instruction
+    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+    // CHECK-NEXT:   %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+
+    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
+    %f0 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+    %f1 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+    %f2 = riscv.get_float_register : !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
+
+    %fmv = riscv.fmv.s %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %fmadd_s = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmsub_s = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fnmsub_s = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fnmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fnmadd_s = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fnmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_s_fm = riscv.fadd.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_s_fm = riscv.fsub.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_s_fm = riscv.fmul.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_s_fm = riscv.fdiv.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fsqrt_s = riscv.fsqrt.s %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsqrt.s %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %fsgnj_s = riscv.fsgnj.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnj.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsgnjn_s = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnjn.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsgnjx_s = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsgnjx.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_s = riscv.fmin.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_s = riscv.fmax.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_s_fm = riscv.fmin.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_s_fm = riscv.fmax.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fcvt_w_s = riscv.fcvt.w.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.w.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fcvt_wu_s = riscv.fcvt.wu.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.wu.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fmv_x_w = riscv.fmv.x.w %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.x.w %{{.*}} : (!riscv.freg) -> !riscv.reg
+
+    %feq_s = riscv.feq.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %flt_s = riscv.flt.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fle_s = riscv.fle.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %feq_s_fm = riscv.feq.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %flt_s_fm = riscv.flt.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fle_s_fm = riscv.fle.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
+    %fclass_s = riscv.fclass.s %f0 : (!riscv.freg) -> !riscv.reg
+    // CHECK-NEXT: %{{.*}} = riscv.fclass.s %{{.*}} : (!riscv.freg) -> !riscv.reg
+    %fcvt_s_w = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.w %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fcvt_s_wu = riscv.fcvt.s.wu %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fmv_w_x = riscv.fmv.w.x %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %{{.*}} : (!riscv.reg) -> !riscv.freg
+
+    %flw = riscv.flw %0, 1 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.flw %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
+    riscv.fsw %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
+    // CHECK-NEXT: riscv.fsw %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
+
+    // Vector Ops
+    %fld = riscv.fld %0, 1 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fld %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
+    riscv.fsd %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
+    // CHECK-NEXT: riscv.fsd %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
+
+    %fmv_d = riscv.fmv.d %f0 : (!riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmv.d %{{.*}} : (!riscv.freg) -> !riscv.freg
+
+    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.vfadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.vfmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    // RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
+
+    %fadd_d = riscv.fadd.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fadd_d_fm = riscv.fadd.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fsub_d_fm = riscv.fsub.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmul_d_fm = riscv.fmul.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fdiv_d_fm = riscv.fdiv.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmadd.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmsub.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fmin_d_fm = riscv.fmin.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    %fmax_d_fm = riscv.fmax.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
+
+    %fcvt_d_w = riscv.fcvt.d.w %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %{{.*}} : (!riscv.reg) -> !riscv.freg
+    %fcvt_d_wu = riscv.fcvt.d.wu %0 : (!riscv.reg) -> !riscv.freg
+    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
+
+    %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+    // CHECK-NEXT: %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+
+    // Terminate block
+    riscv_func.return
+  }
+}) : () -> ()
+
+// CHECK-GENERIC:       "builtin.module"() ({
+// CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
+// CHECK-GENERIC-NEXT:      %0 = "riscv.get_register"() : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %1 = "riscv.get_register"() : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %addi = "riscv.addi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slti = "riscv.slti"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sltiu = "riscv.sltiu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %andi = "riscv.andi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %ori = "riscv.ori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xori = "riscv.xori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slli = "riscv.slli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srli = "riscv.srli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srai = "riscv.srai"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lui = "riscv.lui"() {immediate = 1 : i20} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %auipc = "riscv.auipc"() {immediate = 1 : i20} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mv = "riscv.mv"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %seqz = "riscv.seqz"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %snez = "riscv.snez"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zextb = "riscv.zext.b"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zextw = "riscv.zext.w"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sextw = "riscv.sext.w"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srliw = "riscv.srliw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sraiw = "riscv.sraiw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %add = "riscv.add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %slt = "riscv.slt"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sltu = "riscv.sltu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %and = "riscv.and"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %or = "riscv.or"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xor = "riscv.xor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sll = "riscv.sll"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srl = "riscv.srl"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sub = "riscv.sub"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sra = "riscv.sra"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %addw = "riscv.addw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %subw = "riscv.subw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sllw = "riscv.sllw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %srlw = "riscv.srlw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sraw = "riscv.sraw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.nop"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20, rd = !riscv.reg} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = #riscv.label<"label">} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = 1 : si20} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = #riscv.label<"label">} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12, rd = !riscv.reg} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = #riscv.label<"label">} : (!riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.ret"() : () -> ()
+// CHECK-GENERIC-NEXT:    ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
+// CHECK-GENERIC-NEXT:      "riscv.beq"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bne"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.blt"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bge"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bltu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.bgeu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      %lb = "riscv.lb"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lbu = "riscv.lbu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lh = "riscv.lh"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lhu = "riscv.lhu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %lw = "riscv.lw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.sb"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.sh"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      "riscv.sw"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
+// CHECK-GENERIC-NEXT:      %csrrw_rw = "riscv.csrrw"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrw_w = "riscv.csrrw"(%0) {csr = 1024 : i32, writeonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrs_rw = "riscv.csrrs"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrs_r = "riscv.csrrs"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrc_rw = "riscv.csrrc"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrc_r = "riscv.csrrc"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrsi_rw = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrsi_r = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrci_rw = "riscv.csrrci"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrci_r = "riscv.csrrci"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrwi_rw = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %csrrwi_w = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32, writeonly} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.wfi"() : () -> ()
+// CHECK-GENERIC-NEXT:      %mul = "riscv.mul"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulh = "riscv.mulh"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulhsu = "riscv.mulhsu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulhu = "riscv.mulhu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %mulw = "riscv.mulw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %div = "riscv.div"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divu = "riscv.divu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divw = "riscv.divw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %divuw = "riscv.divuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rem = "riscv.rem"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remu = "riscv.remu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remw = "riscv.remw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %remuw = "riscv.remuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rol = "riscv.rol"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %ror = "riscv.ror"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rori = "riscv.rori"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %roriw = "riscv.roriw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rolw = "riscv.rolw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %rorw = "riscv.rorw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bclr = "riscv.bclr"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bext = "riscv.bext"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %bset = "riscv.bset"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %binv = "riscv.binv"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %adduw = "riscv.add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh1add = "riscv.sh1add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh1adduw = "riscv.sh1add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh2add = "riscv.sh2add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh2adduw = "riscv.sh2add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh3add = "riscv.sh3add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sh3adduw = "riscv.sh3add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sextb = "riscv.sext.b"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %sexth = "riscv.sext.h"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %zexth = "riscv.zext.h"(%0) : (!riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %andn = "riscv.andn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %xnor = "riscv.xnor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %orn = "riscv.orn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %max = "riscv.max"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %maxu = "riscv.maxu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %min = "riscv.min"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i64} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
+// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
+// CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
+// CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %f2 = "riscv.get_float_register"() : () -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmv = "riscv.fmv.s"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmadd_s = "riscv.fmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmsub_s = "riscv.fmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fnmsub_s = "riscv.fnmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fnmadd_s = "riscv.fnmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_s = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_s = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_s = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_s = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_s_fm = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_s_fm = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_s_fm = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_s_fm = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsqrt_s = "riscv.fsqrt.s"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnj_s = "riscv.fsgnj.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnjn_s = "riscv.fsgnjn.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsgnjx_s = "riscv.fsgnjx.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_s = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_s = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_s_fm = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_s_fm = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_w_s = "riscv.fcvt.w.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fcvt_wu_s = "riscv.fcvt.wu.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fmv_x_w = "riscv.fmv.x.w"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %feq_s = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %flt_s = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fle_s = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %feq_s_fm = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %flt_s_fm = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fle_s_fm = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fclass_s = "riscv.fclass.s"(%f0) : (!riscv.freg) -> !riscv.reg
+// CHECK-GENERIC-NEXT:      %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %flw = "riscv.flw"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      "riscv.fsw"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
+// CHECK-GENERIC-NEXT:      %fld = "riscv.fld"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      "riscv.fsd"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
+// CHECK-GENERIC-NEXT:      %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_d = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_d = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_d = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_d = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fadd_d_fm = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fsub_d_fm = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmul_d_fm = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fdiv_d_fm = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmadd_d = "riscv.fmadd.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmsub_d = "riscv.fmsub.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_d = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_d = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmin_d_fm = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fmax_d_fm = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_d_w = "riscv.fcvt.d.w"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %fcvt_d_wu = "riscv.fcvt.d.wu"(%0) : (!riscv.reg) -> !riscv.freg
+// CHECK-GENERIC-NEXT:      %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = "riscv.parallel_mov"(%0, %1, %f0, %f1) <{input_widths = array<i32: 64, 32, 64, 32>}> : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+// CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
+// CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
+// CHECK-GENERIC-NEXT:  }) : () -> ()

From 469c732a93cf3a488dd9610fc3633fe40b2ef5d5 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Sat, 7 Feb 2026 19:27:45 +0000
Subject: [PATCH 8/9] modify test cases

---
 .../rv32/riscv_assembly_emission.mlir         | 380 +---------
 tests/filecheck/dialects/rv32/rv32_ops.mlir   | 652 +----------------
 .../rv64/riscv_assembly_emission.mlir         | 380 +---------
 tests/filecheck/dialects/rv64/rv64_ops.mlir   | 654 +-----------------
 4 files changed, 65 insertions(+), 2001 deletions(-)

diff --git a/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
index fcf3e7b40f..b21b82a2ba 100644
--- a/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
+++ b/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
@@ -1,368 +1,16 @@
 // RUN: xdsl-opt -t riscv-asm %s | filecheck %s
 
-// TODO: Operations will be replaced with rv32 variant-specific counterparts
-
-"builtin.module"() ({
-  riscv_func.func @main() {
-    %0 = rv32.li 6 : !riscv.reg<zero>
-    // CHECK:      li zero, 6
-    %1 = rv32.li 5 : !riscv.reg<j_1>
-    // CHECK-NEXT: li j_1, 5
-    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add j_2, zero, j_1
-    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: mv j_2, zero
-    %seqz = riscv.seqz %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: seqz j_1, j_1
-    %snez = riscv.snez %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: snez j_1, j_1
-    %zextb = riscv.zext.b %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: zext.b j_1, j_1
-    %zextw = riscv.zext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: zext.w j_1, j_1
-    %sextw = riscv.sext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: sext.w j_1, j_1
-
-    // RV32I/RV64I: Integer Computational Instructions (Section 2.4)
-    // Integer Register-Immediate Instructions
-    %addi = riscv.addi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: addi j_1, j_1, 1
-    %slti = riscv.slti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slti j_1, j_1, 1
-    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: sltiu j_1, j_1, 1
-    %andi = riscv.andi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: andi j_1, j_1, 1
-    %ori = riscv.ori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: ori j_1, j_1, 1
-    %xori = riscv.xori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: xori j_1, j_1, 1
-    %slli = riscv.slli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slli j_1, j_1, 1
-    %srli = riscv.srli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: srli j_1, j_1, 1
-    %srai = riscv.srai %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: srai j_1, j_1, 1
-    %lui = riscv.lui 1: () -> !riscv.reg<j_0>
-    // CHECK-NEXT: lui j_0, 1
-    %auipc = riscv.auipc 1: () -> !riscv.reg<j_0>
-    // CHECK-NEXT: auipc j_0, 1
-
-    // Integer Register-Register Operations
-    %add = riscv.add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add j_2, j_2, j_1
-    %slt = riscv.slt %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: slt j_2, j_2, j_1
-    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sltu j_2, j_2, j_1
-    %and = riscv.and %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: and j_2, j_2, j_1
-    %or = riscv.or %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: or j_2, j_2, j_1
-    %xor = riscv.xor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: xor j_2, j_2, j_1
-    %sll = riscv.sll %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sll j_2, j_2, j_1
-    %srl = riscv.srl %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: srl j_2, j_2, j_1
-    %sub = riscv.sub %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sub j_2, j_2, j_1
-    %sra = riscv.sra %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sra j_2, j_2, j_1
-    riscv.nop
-    // CHECK-NEXT: nop
-
-    // RV32I/RV64I: 2.5 Control Transfer Instructions
-
-    // Unconditional Branch Instructions
-    riscv.jal 1
-    // CHECK-NEXT: jal 1
-    riscv.jal 1, !riscv.reg<s0>
-    // CHECK-NEXT: jal s0, 1
-    riscv.jal "label"
-    // CHECK-NEXT: jal label
-
-    riscv.j 1, !riscv.reg<zero>
-    // CHECK-NEXT: j 1
-    riscv.j "label", !riscv.reg<zero>
-    // CHECK-NEXT: j label
-
-    riscv.jalr %0, 1 : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr zero, 1
-    riscv.jalr %0 1, !riscv.reg<j_0> : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr j_0, zero, 1
-    riscv.jalr %0 "label" : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr zero, label
-
-    riscv.ret
-    // CHECK-NEXT: ret
-  ^bb0(%b00 : !riscv.reg, %b01 : !riscv.reg):
-
-
-    // Conditional Branch Instructions
-    riscv.beq %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: beq j_2, j_1, 1
-    riscv.bne %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bne j_2, j_1, 1
-    riscv.blt %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: blt j_2, j_1, 1
-    riscv.bge %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bge j_2, j_1, 1
-    riscv.bltu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bltu j_2, j_1, 1
-    riscv.bgeu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bgeu j_2, j_1, 1
-
-    // RV32I/RV64I: Load and Store Instructions (Section 2.6)
-    %lb = riscv.lb %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lb j_2, j_1, 1
-    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lbu j_2, j_1, 1
-    %lh = riscv.lh %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lh j_2, j_1, 1
-    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lhu j_2, j_1, 1
-    %lw = riscv.lw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lw j_2, 1(j_1)
-
-    riscv.sb %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sb j_2, j_1, 1
-    riscv.sh %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sh j_2, j_1, 1
-    riscv.sw %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sw j_1, 1(j_2)
-
-    // RV32I/RV64I: Control and Status Register Instructions (Section 2.8)
-    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrw j_1, 1024, j_2
-    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j_2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrw zero, 1024, j_2
-    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrs zero, 1024, j_2
-    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: csrrs j_2, 1024, zero
-    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrc j_0, 1024, j_2
-    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrc j_0, 1024, zero
-    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrsi j_1, 1024, 8
-    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrsi j_0, 1024, 0
-    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrci j_0, 1024, 8
-    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrci j_1, 1024, 0
-    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrwi j_0, 1024, 8
-    %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrwi zero, 1024, 8
-
-    // Assembler pseudo-instructions
-    %li = rv32.li 1: !riscv.reg<j_0>
-    // CHECK-NEXT: li j_0, 1
-    // Environment Call and Breakpoints
-    riscv.ecall
-    // CHECK-NEXT: ecall
-    riscv.ebreak
-    // CHECK-NEXT: ebreak
-    riscv.ret
-    // CHECK-NEXT: ret
-  ^bb1(%b10 : !riscv.reg, %b11 : !riscv.reg):
-
-    riscv.directive ".align" "2"
-    // CHECK-NEXT: .align 2
-    riscv.assembly_section ".text" {
-      %inner = rv32.li 5 : !riscv.reg<j_1>
-      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    }
-    // CHECK-NEXT:  li j_1, 5
-    // CHECK-NEXT:  addi j_1, j_1, 1
-    riscv.label "label0"
-    // CHECK-NEXT: label0:
-
-
-    // Custom instruction
-    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j_1>) -> (!riscv.reg<j_3>, !riscv.reg<j_4>)
-    // CHECK-NEXT:   hello j_3, j_4, zero, j_1
-
-
-    // RISC-V Extensions
-
-    riscv_snitch.frep_outer %0 {
-      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    }
-
-    // CHECK:          frep.o zero, 1, 0, 0
-    // CHECK-NEXT:     add  j_2, zero, j_1
-
-    riscv_snitch.frep_inner %0 {
-      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    }
-    // CHECK:          frep.i zero, 1, 0, 0
-    // CHECK-NEXT:     add  j_2, zero, j_1
-    
-    //RV32B/RV64B: "B" Extension for Bit Manipulation, Version 1.0.0
-    %rol = riscv.rol %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rol j_2, j_2, j_1
-    %ror = riscv.ror %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: ror j_2, j_2, j_1
-    %rolw = riscv.rolw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rolw j_2, j_2, j_1
-    %rorw = riscv.rorw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rorw j_2, j_2, j_1
-    %rori = riscv.rori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: rori j_1, j_1, 1
-    %roriw = riscv.roriw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: roriw j_1, j_1, 1
-    %bclr = riscv.bclr %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: bclr j_2, j_2, j_1
-    %bclri = riscv.bclri %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: bclri j_1, j_1, 1
-    %bseti = riscv.bseti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: bseti j_1, j_1, 1
-    %adduw = riscv.add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add.uw j_2, j_2, j_1
-    %sh1add = riscv.sh1add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh1add j_2, j_2, j_1
-    %sh2add = riscv.sh2add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh2add j_2, j_2, j_1
-    %sh3add = riscv.sh3add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh3add j_2, j_2, j_1
-    %sh1adduw = riscv.sh1add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh1add.uw j_2, j_2, j_1
-    %sh2adduw = riscv.sh2add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh2add.uw j_2, j_2, j_1
-    %sh3adduw = riscv.sh3add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh3add.uw j_2, j_2, j_1
-    %slliuw = riscv.slli.uw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slli.uw j_1, j_1, 1
-    %andn = riscv.andn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: andn j_2, j_2, j_1
-    %orn = riscv.orn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: orn j_2, j_2, j_1
-    %xnor = riscv.xnor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: xnor j_2, j_2, j_1
-    %max = riscv.max %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: max j_2, j_2, j_1
-    %maxu = riscv.maxu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: maxu j_2, j_2, j_1
-    %min = riscv.min %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: min j_2, j_2, j_1
-    %minu = riscv.minu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: minu j_2, j_2, j_1
-    
-    // "ZiCond" Conditional" operations extension
-    %czeroeqz = riscv.czero.eqz %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: czero.eqz j_2, j_2, j_1
-    %czeronez = riscv.czero.nez %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: czero.nez j_2, j_2, j_1
-
-    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
-
-    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.s.w fj_0, zero
-    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_1>
-    // CHECK-NEXT: fcvt.s.wu fj_1, j_1
-    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_2>
-    // CHECK-NEXT: fcvt.s.wu fj_2, j_1
-    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmadd.s fj_3, fj_0, fj_1, fj_2
-    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmsub.s fj_3, fj_0, fj_1, fj_2
-    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fnmsub.s fj_3, fj_0, fj_1, fj_2
-    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fnmadd.s fj_3, fj_0, fj_1, fj_2
-    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fadd.s fj_3, fj_0, fj_1
-    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsub.s fj_3, fj_0, fj_1
-    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmul.s fj_3, fj_0, fj_1
-    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fdiv.s fj_3, fj_0, fj_1
-    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<fj_0>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsqrt.s fj_3, fj_0
-    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnj.s fj_3, fj_0, fj_1
-    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnjn.s fj_3, fj_0, fj_1
-    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnjx.s fj_3, fj_0, fj_1
-    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmin.s fj_3, fj_0, fj_1
-    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmax.s fj_3, fj_0, fj_1
-    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fcvt.w.s j_3, fj_0
-    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fcvt.wu.s j_3, fj_0
-    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fmv.x.w j_3, fj_0
-    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: feq.s j_3, fj_0, fj_1
-    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: flt.s j_3, fj_0, fj_1
-    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fle.s j_3, fj_0, fj_1
-    %fclass = riscv.fclass.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fclass.s j_3, fj_0
-    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fcvt.s.w fj_3, zero
-    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fcvt.s.wu fj_3, zero
-    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmv.w.x fj_3, zero
-    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: flw fj_3, 1(zero)
-    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
-    // CHECK-NEXT: fsw fj_0, 1(zero)
-
-    // RV32F: 9 "D" Standard Extension for Double-Precision Floating-Point, Version 2.0
-
-    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fld fj_3, 1(zero)
-
-    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fld fj_3, hello, zero
-
-    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
-    // CHECK-NEXT: fsd fj_0, 1(zero)
-
-    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmadd.d fj_3, fj_0, fj_1, fj_2
-    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmsub.d fj_3, fj_0, fj_1, fj_2
-    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fadd.d fj_3, fj_0, fj_1
-    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsub.d fj_3, fj_0, fj_1
-    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmul.d fj_3, fj_0, fj_1
-    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fdiv.d fj_3, fj_0, fj_1
-    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmin.d fj_3, fj_0, fj_1
-    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmax.d fj_3, fj_0, fj_1
-
-    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.d.w fj_0, j_1
-    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.d.wu fj_0, j_1
-
-    // Vector Ops
-    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: vfadd.s fj_3, fj_0, fj_1
-    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: vfmul.s fj_3, fj_0, fj_1
-
-    // Terminate block
-    riscv_func.return
-    // CHECK-NEXT: ret
-  }
-// External
-riscv_func.func @external()
-// CHECK-NOT: external
-}) : () -> ()
+riscv_func.func @main() {
+  %0 = rv32.li 6 : !riscv.reg<zero>
+  // CHECK:      li zero, 6
+  %1 = rv32.li 5 : !riscv.reg<j_1>
+  // CHECK-NEXT: li j_1, 5
+
+  // Assembler pseudo-instructions
+  %li = rv32.li 1 : !riscv.reg<j_0>
+  // CHECK-NEXT: li j_0, 1
+  
+  // Terminate block
+  riscv_func.return
+  // CHECK-NEXT: ret
+}
diff --git a/tests/filecheck/dialects/rv32/rv32_ops.mlir b/tests/filecheck/dialects/rv32/rv32_ops.mlir
index 5b0c844bdb..ce8316ec88 100644
--- a/tests/filecheck/dialects/rv32/rv32_ops.mlir
+++ b/tests/filecheck/dialects/rv32/rv32_ops.mlir
@@ -1,653 +1,37 @@
 // RUN: XDSL_ROUNDTRIP
 // RUN: XDSL_GENERIC_ROUNDTRIP
 
-// TODO: Operations will be replaced with rv32 variant-specific counterparts
+riscv_func.func @main() {
+  // Assembler pseudo-instructions
 
-"builtin.module"() ({
-  riscv_func.func @main() {
-    %0 = riscv.get_register : !riscv.reg
-    %1 = riscv.get_register : !riscv.reg
-    // RV32I/RV64I: 2.4 Integer Computational Instructions
-
-    // Integer Register-Immediate Instructions
-    %addi = riscv.addi %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.addi %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %slti = riscv.slti %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slti %0, 1 : (!riscv.reg) -> !riscv.reg
-    %sltiu = riscv.sltiu %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sltiu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %andi = riscv.andi %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.andi %0, 1 : (!riscv.reg) -> !riscv.reg
-    %ori = riscv.ori %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.ori %0, 1 : (!riscv.reg) -> !riscv.reg
-    %xori = riscv.xori %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xori %0, 1 : (!riscv.reg) -> !riscv.reg
-    %slli = riscv.slli %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slli %0, 1 : (!riscv.reg) -> !riscv.reg
-    %srli = riscv.srli %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srli %0, 1 : (!riscv.reg) -> !riscv.reg
-    %srai = riscv.srai %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srai %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lui = riscv.lui 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lui 1 : () -> !riscv.reg
-    %auipc = riscv.auipc 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.auipc 1 : () -> !riscv.reg
-    %mv = riscv.mv %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.mv %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %seqz = riscv.seqz %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.seqz %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %snez = riscv.snez %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.snez %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zextb = riscv.zext.b %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.zext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zextw = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.zext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %sextw = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.sext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %srliw = riscv.srliw %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srliw %0, 1 : (!riscv.reg) -> !riscv.reg
-    %sraiw = riscv.sraiw %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sraiw %0, 1 : (!riscv.reg) -> !riscv.reg
-
-    // Integer Register-Register Operations
-    %add = riscv.add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %slt = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slt %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sltu = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sltu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %and = riscv.and %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.and %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %or = riscv.or %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.or %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %xor = riscv.xor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sll = riscv.sll %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sll %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %srl = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srl %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sub = riscv.sub %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sra = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sra %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %addw = riscv.addw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.addw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %subw = riscv.subw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.subw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sllw = riscv.sllw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sllw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %srlw = riscv.srlw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srlw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sraw = riscv.sraw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sraw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    riscv.nop
-    // CHECK-NEXT: riscv.nop
-
-    // RV32I/RV64I: 2.5 Control Transfer Instructions
-
-    // Unconditional Branch Instructions
-    riscv.jal 1
-    // CHECK-NEXT: riscv.jal 1
-    riscv.jal 1, !riscv.reg
-    // CHECK-NEXT: riscv.jal 1, !riscv.reg
-    riscv.jal "label"
-    // CHECK-NEXT: riscv.jal "label"
-
-    riscv.j 1
-    // CHECK-NEXT: riscv.j 1
-    riscv.j "label"
-    // CHECK-NEXT: riscv.j "label"
-
-    riscv.jalr %0, 1: (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, 1 : (!riscv.reg) -> ()
-    riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
-    riscv.jalr %0, "label" : (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, "label" : (!riscv.reg) -> ()
-
-    riscv.ret
-    // CHECK-NEXT: riscv.ret
-  ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-  // CHECK-NEXT: ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-
-    // Conditional Branch Instructions
-    riscv.beq %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.beq %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bne %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bne %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.blt %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.blt %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bge %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bge %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bltu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bltu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bgeu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bgeu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-
-    // RV32I/RV64I: 2.6 Load and Store Instructions
-
-    %lb = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lbu = riscv.lbu %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lbu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lh = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lhu = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lw = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
-    riscv.sb %0, %1, 1: (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sb %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-
-    // RV32I/RV64I: 2.8 Control and Status Register Instructions
-
-    %csrrw_rw = riscv.csrrw %0 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrw_w = riscv.csrrw %0 1024, "w" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024, "w" : (!riscv.reg) -> !riscv.reg
-    %csrrs_rw = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    %csrrc_rw = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrc_r = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 8 : () -> !riscv.reg
-    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 0 : () -> !riscv.reg
-    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 8 : () -> !riscv.reg
-    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 0 : () -> !riscv.reg
-    %csrrwi_rw = riscv.csrrwi 1024, 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1 : () -> !riscv.reg
-    %csrrwi_w = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
-
-    // Machine Mode Privileged Instructions
-    riscv.wfi
-    // CHECK-NEXT: riscv.wfi
-
-
-    // RV32M/RV64M: 7 “M” Standard Extension for Integer Multiplication and Division
-
-    // Multiplication Operations
-    %mul = riscv.mul %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulh = riscv.mulh %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulh %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulhsu = riscv.mulhsu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulhsu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulhu = riscv.mulhu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulhu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulw = riscv.mulw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-
-    // Division Operations
-    %div = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.div %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divu = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divw = riscv.divw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divuw = riscv.divuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rem = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rem %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remu = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remw = riscv.remw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remuw = riscv.remuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-    // RV32B/RV64B:  “B” Standard Extension for Bit Manipulation
-
-    %rol = riscv.rol %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rol %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %ror = riscv.ror %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.ror %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rori = riscv.rori %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rori %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %roriw = riscv.roriw %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.roriw %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %rolw = riscv.rolw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rolw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rorw = riscv.rorw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rorw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bclr = riscv.bclr %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bclr %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bext = riscv.bext %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bext %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bset = riscv.bset %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bset %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %binv = riscv.binv %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.binv %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %adduw = riscv.add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh1add = riscv.sh1add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh1add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh1adduw = riscv.sh1add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh1add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh2add = riscv.sh2add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh2add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh2adduw = riscv.sh2add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh2add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh3add = riscv.sh3add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh3add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh3adduw = riscv.sh3add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh3add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sextb = riscv.sext.b %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %sexth = riscv.sext.h %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zexth = riscv.zext.h %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.zext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %andn = riscv.andn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.andn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %xnor = riscv.xnor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xnor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %orn = riscv.orn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.orn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %max = riscv.max %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.max %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %maxu = riscv.maxu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.maxu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %min = riscv.min %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.min %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %minu = riscv.minu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.minu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-
-    // RV32/RV64 Zicond extension for conditional operations
-
-    %czeroeqzop = riscv.czero.eqz %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.czero.eqz %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %czeronezop = riscv.czero.nez %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.czero.nez %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-    // Assembler pseudo-instructions
-
-    %li = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT: %{{.*}} = rv32.li 1 : !riscv.reg
-    // Environment Call and Breakpoints
-    riscv.ecall
-    // CHECK-NEXT: riscv.ecall
-    riscv.ebreak
-    // CHECK-NEXT: riscv.ebreak
-    riscv.directive ".bss"
-    // CHECK-NEXT: riscv.directive ".bss"
-    riscv.directive ".align" "2"
-    // CHECK-NEXT: riscv.directive ".align" "2"
-    riscv.assembly_section ".text" attributes {"foo" = i32} {
-      %nested_li = rv32.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
-    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
-
-    riscv.assembly_section ".text" {
-      %nested_li = rv32.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" {
-    // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
-
-    // Custom instruction
-    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-    // CHECK-NEXT:   %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-
-    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
-    %f0 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-    %f1 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-    %f2 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-
-    %fmv = riscv.fmv.s %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %fmadd_s = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmsub_s = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fnmsub_s = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fnmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fnmadd_s = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fnmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_s_fm = riscv.fadd.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_s_fm = riscv.fsub.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_s_fm = riscv.fmul.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_s_fm = riscv.fdiv.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fsqrt_s = riscv.fsqrt.s %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsqrt.s %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %fsgnj_s = riscv.fsgnj.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnj.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsgnjn_s = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnjn.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsgnjx_s = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnjx.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_s = riscv.fmin.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_s = riscv.fmax.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_s_fm = riscv.fmin.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_s_fm = riscv.fmax.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fcvt_w_s = riscv.fcvt.w.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.w.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fcvt_wu_s = riscv.fcvt.wu.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.wu.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fmv_x_w = riscv.fmv.x.w %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.x.w %{{.*}} : (!riscv.freg) -> !riscv.reg
-
-    %feq_s = riscv.feq.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %flt_s = riscv.flt.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fle_s = riscv.fle.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %feq_s_fm = riscv.feq.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %flt_s_fm = riscv.flt.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fle_s_fm = riscv.fle.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fclass_s = riscv.fclass.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fclass.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fcvt_s_w = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.w %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fcvt_s_wu = riscv.fcvt.s.wu %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fmv_w_x = riscv.fmv.w.x %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %{{.*}} : (!riscv.reg) -> !riscv.freg
-
-    %flw = riscv.flw %0, 1 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.flw %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
-    riscv.fsw %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
-    // CHECK-NEXT: riscv.fsw %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
-
-    // Vector Ops
-    %fld = riscv.fld %0, 1 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fld %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
-    riscv.fsd %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
-    // CHECK-NEXT: riscv.fsd %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
-
-    %fmv_d = riscv.fmv.d %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.d %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.vfadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.vfmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    // RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
-
-    %fadd_d = riscv.fadd.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_d_fm = riscv.fadd.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_d_fm = riscv.fsub.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_d_fm = riscv.fmul.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_d_fm = riscv.fdiv.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmadd.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmsub.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_d_fm = riscv.fmin.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_d_fm = riscv.fmax.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fcvt_d_w = riscv.fcvt.d.w %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fcvt_d_wu = riscv.fcvt.d.wu %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
-
-    %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
-    // CHECK-NEXT: %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+  %li = rv32.li 1 : !riscv.reg
+  // CHECK: %{{.*}} = rv32.li 1 : !riscv.reg
+  riscv.assembly_section ".text" attributes {"foo" = i32} {
+    %nested_li = rv32.li 1 : !riscv.reg
+  }
+  // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
+  // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
+  // CHECK-NEXT:  }
 
-    // Terminate block
-    riscv_func.return
+  riscv.assembly_section ".text" {
+    %nested_li = rv32.li 1 : !riscv.reg
   }
-}) : () -> ()
+  // CHECK-NEXT:  riscv.assembly_section ".text" {
+  // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
+  // CHECK-NEXT:  }
+
+  riscv_func.return
+}
 
 // CHECK-GENERIC:       "builtin.module"() ({
 // CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
-// CHECK-GENERIC-NEXT:      %0 = "riscv.get_register"() : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %1 = "riscv.get_register"() : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %addi = "riscv.addi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slti = "riscv.slti"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sltiu = "riscv.sltiu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %andi = "riscv.andi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %ori = "riscv.ori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xori = "riscv.xori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slli = "riscv.slli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srli = "riscv.srli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srai = "riscv.srai"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lui = "riscv.lui"() {immediate = 1 : i20} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %auipc = "riscv.auipc"() {immediate = 1 : i20} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mv = "riscv.mv"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %seqz = "riscv.seqz"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %snez = "riscv.snez"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zextb = "riscv.zext.b"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zextw = "riscv.zext.w"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sextw = "riscv.sext.w"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srliw = "riscv.srliw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sraiw = "riscv.sraiw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %add = "riscv.add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slt = "riscv.slt"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sltu = "riscv.sltu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %and = "riscv.and"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %or = "riscv.or"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xor = "riscv.xor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sll = "riscv.sll"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srl = "riscv.srl"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sub = "riscv.sub"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sra = "riscv.sra"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %addw = "riscv.addw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %subw = "riscv.subw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sllw = "riscv.sllw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srlw = "riscv.srlw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sraw = "riscv.sraw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.nop"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20, rd = !riscv.reg} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = #riscv.label<"label">} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = 1 : si20} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = #riscv.label<"label">} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12, rd = !riscv.reg} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = #riscv.label<"label">} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.ret"() : () -> ()
-// CHECK-GENERIC-NEXT:    ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-// CHECK-GENERIC-NEXT:      "riscv.beq"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bne"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.blt"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bge"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bltu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bgeu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      %lb = "riscv.lb"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lbu = "riscv.lbu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lh = "riscv.lh"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lhu = "riscv.lhu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lw = "riscv.lw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.sb"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.sh"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.sw"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      %csrrw_rw = "riscv.csrrw"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrw_w = "riscv.csrrw"(%0) {csr = 1024 : i32, writeonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrs_rw = "riscv.csrrs"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrs_r = "riscv.csrrs"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrc_rw = "riscv.csrrc"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrc_r = "riscv.csrrc"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrsi_rw = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrsi_r = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrci_rw = "riscv.csrrci"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrci_r = "riscv.csrrci"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrwi_rw = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrwi_w = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32, writeonly} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.wfi"() : () -> ()
-// CHECK-GENERIC-NEXT:      %mul = "riscv.mul"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulh = "riscv.mulh"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulhsu = "riscv.mulhsu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulhu = "riscv.mulhu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulw = "riscv.mulw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %div = "riscv.div"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divu = "riscv.divu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divw = "riscv.divw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divuw = "riscv.divuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rem = "riscv.rem"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remu = "riscv.remu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remw = "riscv.remw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remuw = "riscv.remuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rol = "riscv.rol"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %ror = "riscv.ror"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rori = "riscv.rori"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %roriw = "riscv.roriw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rolw = "riscv.rolw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rorw = "riscv.rorw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bclr = "riscv.bclr"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bext = "riscv.bext"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bset = "riscv.bset"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %binv = "riscv.binv"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %adduw = "riscv.add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh1add = "riscv.sh1add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh1adduw = "riscv.sh1add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh2add = "riscv.sh2add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh2adduw = "riscv.sh2add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh3add = "riscv.sh3add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh3adduw = "riscv.sh3add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sextb = "riscv.sext.b"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sexth = "riscv.sext.h"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zexth = "riscv.zext.h"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %andn = "riscv.andn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xnor = "riscv.xnor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %orn = "riscv.orn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %max = "riscv.max"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %maxu = "riscv.maxu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %min = "riscv.min"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
 // CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
 // CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
-// CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-// CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %f2 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmv = "riscv.fmv.s"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmadd_s = "riscv.fmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmsub_s = "riscv.fmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fnmsub_s = "riscv.fnmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fnmadd_s = "riscv.fnmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_s = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_s = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_s = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_s = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_s_fm = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_s_fm = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_s_fm = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_s_fm = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsqrt_s = "riscv.fsqrt.s"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnj_s = "riscv.fsgnj.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnjn_s = "riscv.fsgnjn.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnjx_s = "riscv.fsgnjx.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_s = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_s = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_s_fm = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_s_fm = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_w_s = "riscv.fcvt.w.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fcvt_wu_s = "riscv.fcvt.wu.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fmv_x_w = "riscv.fmv.x.w"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %feq_s = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %flt_s = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fle_s = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %feq_s_fm = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %flt_s_fm = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fle_s_fm = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fclass_s = "riscv.fclass.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %flw = "riscv.flw"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      "riscv.fsw"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
-// CHECK-GENERIC-NEXT:      %fld = "riscv.fld"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      "riscv.fsd"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
-// CHECK-GENERIC-NEXT:      %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_d = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_d = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_d = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_d = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_d_fm = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_d_fm = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_d_fm = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_d_fm = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmadd_d = "riscv.fmadd.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmsub_d = "riscv.fmsub.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_d = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_d = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_d_fm = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_d_fm = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_d_w = "riscv.fcvt.d.w"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_d_wu = "riscv.fcvt.d.wu"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = "riscv.parallel_mov"(%0, %1, %f0, %f1) <{input_widths = array<i32: 64, 32, 64, 32>}> : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
 // CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
 // CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
 // CHECK-GENERIC-NEXT:  }) : () -> ()
diff --git a/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
index 678b641701..f49d42da21 100644
--- a/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
+++ b/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
@@ -1,368 +1,16 @@
 // RUN: xdsl-opt -t riscv-asm %s | filecheck %s
 
-// TODO: Operations will be replaced with rv64 variant-specific counterparts
-
-"builtin.module"() ({
-  riscv_func.func @main() {
-    %0 = rv64.li 6 : !riscv.reg<zero>
-    // CHECK:      li zero, 6
-    %1 = rv64.li 5 : !riscv.reg<j_1>
-    // CHECK-NEXT: li j_1, 5
-    %2 = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add j_2, zero, j_1
-    %mv = riscv.mv %0 : (!riscv.reg<zero>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: mv j_2, zero
-    %seqz = riscv.seqz %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: seqz j_1, j_1
-    %snez = riscv.snez %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: snez j_1, j_1
-    %zextb = riscv.zext.b %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: zext.b j_1, j_1
-    %zextw = riscv.zext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: zext.w j_1, j_1
-    %sextw = riscv.sext.w %1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: sext.w j_1, j_1
-
-    // RV32I/RV64I: Integer Computational Instructions (Section 2.4)
-    // Integer Register-Immediate Instructions
-    %addi = riscv.addi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: addi j_1, j_1, 1
-    %slti = riscv.slti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slti j_1, j_1, 1
-    %sltiu = riscv.sltiu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: sltiu j_1, j_1, 1
-    %andi = riscv.andi %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: andi j_1, j_1, 1
-    %ori = riscv.ori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: ori j_1, j_1, 1
-    %xori = riscv.xori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: xori j_1, j_1, 1
-    %slli = riscv.slli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slli j_1, j_1, 1
-    %srli = riscv.srli %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: srli j_1, j_1, 1
-    %srai = riscv.srai %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: srai j_1, j_1, 1
-    %lui = riscv.lui 1: () -> !riscv.reg<j_0>
-    // CHECK-NEXT: lui j_0, 1
-    %auipc = riscv.auipc 1: () -> !riscv.reg<j_0>
-    // CHECK-NEXT: auipc j_0, 1
-
-    // Integer Register-Register Operations
-    %add = riscv.add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add j_2, j_2, j_1
-    %slt = riscv.slt %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: slt j_2, j_2, j_1
-    %sltu = riscv.sltu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sltu j_2, j_2, j_1
-    %and = riscv.and %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: and j_2, j_2, j_1
-    %or = riscv.or %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: or j_2, j_2, j_1
-    %xor = riscv.xor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: xor j_2, j_2, j_1
-    %sll = riscv.sll %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sll j_2, j_2, j_1
-    %srl = riscv.srl %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: srl j_2, j_2, j_1
-    %sub = riscv.sub %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sub j_2, j_2, j_1
-    %sra = riscv.sra %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sra j_2, j_2, j_1
-    riscv.nop
-    // CHECK-NEXT: nop
-
-    // RV32I/RV64I: 2.5 Control Transfer Instructions
-
-    // Unconditional Branch Instructions
-    riscv.jal 1
-    // CHECK-NEXT: jal 1
-    riscv.jal 1, !riscv.reg<s0>
-    // CHECK-NEXT: jal s0, 1
-    riscv.jal "label"
-    // CHECK-NEXT: jal label
-
-    riscv.j 1, !riscv.reg<zero>
-    // CHECK-NEXT: j 1
-    riscv.j "label", !riscv.reg<zero>
-    // CHECK-NEXT: j label
-
-    riscv.jalr %0, 1 : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr zero, 1
-    riscv.jalr %0 1, !riscv.reg<j_0> : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr j_0, zero, 1
-    riscv.jalr %0 "label" : (!riscv.reg<zero>) -> ()
-    // CHECK-NEXT: jalr zero, label
-
-    riscv.ret
-    // CHECK-NEXT: ret
-  ^bb0(%b00 : !riscv.reg, %b01 : !riscv.reg):
-
-
-    // Conditional Branch Instructions
-    riscv.beq %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: beq j_2, j_1, 1
-    riscv.bne %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bne j_2, j_1, 1
-    riscv.blt %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: blt j_2, j_1, 1
-    riscv.bge %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bge j_2, j_1, 1
-    riscv.bltu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bltu j_2, j_1, 1
-    riscv.bgeu %2, %1, 1: (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: bgeu j_2, j_1, 1
-
-    // RV32I/RV64I: Load and Store Instructions (Section 2.6)
-    %lb = riscv.lb %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lb j_2, j_1, 1
-    %lbu = riscv.lbu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lbu j_2, j_1, 1
-    %lh = riscv.lh %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lh j_2, j_1, 1
-    %lhu = riscv.lhu %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lhu j_2, j_1, 1
-    %lw = riscv.lw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: lw j_2, 1(j_1)
-
-    riscv.sb %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sb j_2, j_1, 1
-    riscv.sh %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sh j_2, j_1, 1
-    riscv.sw %2, %1, 1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> ()
-    // CHECK-NEXT: sw j_1, 1(j_2)
-
-    // RV32I/RV64I: Control and Status Register Instructions (Section 2.8)
-    %csrrw_rw = riscv.csrrw %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrw j_1, 1024, j_2
-    %csrrw_w = riscv.csrrw %2, 1024, "w" : (!riscv.reg<j_2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrw zero, 1024, j_2
-    %csrrs_rw = riscv.csrrs %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrs zero, 1024, j_2
-    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg<zero>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: csrrs j_2, 1024, zero
-    %csrrc_rw = riscv.csrrc %2, 1024 : (!riscv.reg<j_2>) -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrc j_0, 1024, j_2
-    %csrrc_r = riscv.csrrc %0, 1024, "r": (!riscv.reg<zero>) -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrc j_0, 1024, zero
-    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrsi j_1, 1024, 8
-    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrsi j_0, 1024, 0
-    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrci j_0, 1024, 8
-    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg<j_1>
-    // CHECK-NEXT: csrrci j_1, 1024, 0
-    %csrrwi_rw = riscv.csrrwi 1024, 8 : () -> !riscv.reg<j_0>
-    // CHECK-NEXT: csrrwi j_0, 1024, 8
-    %csrrwi_w = riscv.csrrwi 1024, 8, "w" : () -> !riscv.reg<zero>
-    // CHECK-NEXT: csrrwi zero, 1024, 8
-
-    // Assembler pseudo-instructions
-    %li = rv64.li 1: !riscv.reg<j_0>
-    // CHECK-NEXT: li j_0, 1
-    // Environment Call and Breakpoints
-    riscv.ecall
-    // CHECK-NEXT: ecall
-    riscv.ebreak
-    // CHECK-NEXT: ebreak
-    riscv.ret
-    // CHECK-NEXT: ret
-  ^bb1(%b10 : !riscv.reg, %b11 : !riscv.reg):
-
-    riscv.directive ".align" "2"
-    // CHECK-NEXT: .align 2
-    riscv.assembly_section ".text" {
-      %inner = rv64.li 5 : !riscv.reg<j_1>
-      %nested_addi = riscv.addi %inner, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    }
-    // CHECK-NEXT:  li j_1, 5
-    // CHECK-NEXT:  addi j_1, j_1, 1
-    riscv.label "label0"
-    // CHECK-NEXT: label0:
-
-
-    // Custom instruction
-    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg<zero>, !riscv.reg<j_1>) -> (!riscv.reg<j_3>, !riscv.reg<j_4>)
-    // CHECK-NEXT:   hello j_3, j_4, zero, j_1
-
-
-    // RISC-V Extensions
-
-    riscv_snitch.frep_outer %0 {
-      %add_o = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    }
-
-    // CHECK:          frep.o zero, 1, 0, 0
-    // CHECK-NEXT:     add  j_2, zero, j_1
-
-    riscv_snitch.frep_inner %0 {
-      %add_i = riscv.add %0, %1 : (!riscv.reg<zero>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    }
-    // CHECK:          frep.i zero, 1, 0, 0
-    // CHECK-NEXT:     add  j_2, zero, j_1
-    
-    //RV32B/RV64B: "B" Extension for Bit Manipulation, Version 1.0.0
-    %rol = riscv.rol %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rol j_2, j_2, j_1
-    %ror = riscv.ror %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: ror j_2, j_2, j_1
-    %rolw = riscv.rolw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rolw j_2, j_2, j_1
-    %rorw = riscv.rorw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: rorw j_2, j_2, j_1
-    %rori = riscv.rori %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: rori j_1, j_1, 1
-    %roriw = riscv.roriw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: roriw j_1, j_1, 1
-    %bclr = riscv.bclr %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: bclr j_2, j_2, j_1
-    %bclri = riscv.bclri %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: bclri j_1, j_1, 1
-    %bseti = riscv.bseti %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: bseti j_1, j_1, 1
-    %adduw = riscv.add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: add.uw j_2, j_2, j_1
-    %sh1add = riscv.sh1add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh1add j_2, j_2, j_1
-    %sh2add = riscv.sh2add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh2add j_2, j_2, j_1
-    %sh3add = riscv.sh3add %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh3add j_2, j_2, j_1
-    %sh1adduw = riscv.sh1add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh1add.uw j_2, j_2, j_1
-    %sh2adduw = riscv.sh2add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh2add.uw j_2, j_2, j_1
-    %sh3adduw = riscv.sh3add.uw %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: sh3add.uw j_2, j_2, j_1
-    %slliuw = riscv.slli.uw %1, 1 : (!riscv.reg<j_1>) -> !riscv.reg<j_1>
-    // CHECK-NEXT: slli.uw j_1, j_1, 1
-    %andn = riscv.andn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: andn j_2, j_2, j_1
-    %orn = riscv.orn %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: orn j_2, j_2, j_1
-    %xnor = riscv.xnor %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: xnor j_2, j_2, j_1
-    %max = riscv.max %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: max j_2, j_2, j_1
-    %maxu = riscv.maxu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: maxu j_2, j_2, j_1
-    %min = riscv.min %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: min j_2, j_2, j_1
-    %minu = riscv.minu %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: minu j_2, j_2, j_1
-    
-    // "ZiCond" Conditional" operations extension
-    %czeroeqz = riscv.czero.eqz %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: czero.eqz j_2, j_2, j_1
-    %czeronez = riscv.czero.nez %2, %1 : (!riscv.reg<j_2>, !riscv.reg<j_1>) -> !riscv.reg<j_2>
-    // CHECK-NEXT: czero.nez j_2, j_2, j_1
-
-    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
-
-    %f0 = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.s.w fj_0, zero
-    %f1 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_1>
-    // CHECK-NEXT: fcvt.s.wu fj_1, j_1
-    %f2 = riscv.fcvt.s.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_2>
-    // CHECK-NEXT: fcvt.s.wu fj_2, j_1
-    %fmadd = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmadd.s fj_3, fj_0, fj_1, fj_2
-    %fmsub = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmsub.s fj_3, fj_0, fj_1, fj_2
-    %fnmsub = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fnmsub.s fj_3, fj_0, fj_1, fj_2
-    %fnmadd = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fnmadd.s fj_3, fj_0, fj_1, fj_2
-    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fadd.s fj_3, fj_0, fj_1
-    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsub.s fj_3, fj_0, fj_1
-    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmul.s fj_3, fj_0, fj_1
-    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fdiv.s fj_3, fj_0, fj_1
-    %fsqrt = riscv.fsqrt.s %f0 : (!riscv.freg<fj_0>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsqrt.s fj_3, fj_0
-    %fsgnj = riscv.fsgnj.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnj.s fj_3, fj_0, fj_1
-    %fsgnjn = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnjn.s fj_3, fj_0, fj_1
-    %fsgnjx = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsgnjx.s fj_3, fj_0, fj_1
-    %fmin = riscv.fmin.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmin.s fj_3, fj_0, fj_1
-    %fmax = riscv.fmax.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmax.s fj_3, fj_0, fj_1
-    %fcvtws = riscv.fcvt.w.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fcvt.w.s j_3, fj_0
-    %fcvtwus = riscv.fcvt.wu.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fcvt.wu.s j_3, fj_0
-    %fmvxw = riscv.fmv.x.w %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fmv.x.w j_3, fj_0
-    %feq = riscv.feq.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: feq.s j_3, fj_0, fj_1
-    %flt = riscv.flt.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: flt.s j_3, fj_0, fj_1
-    %fle = riscv.fle.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fle.s j_3, fj_0, fj_1
-    %fclass = riscv.fclass.s %f0 : (!riscv.freg<fj_0>) -> !riscv.reg<j_3>
-    // CHECK-NEXT: fclass.s j_3, fj_0
-    %fcvtsw = riscv.fcvt.s.w %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fcvt.s.w fj_3, zero
-    %fcvtswu = riscv.fcvt.s.wu %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fcvt.s.wu fj_3, zero
-    %fmvwx = riscv.fmv.w.x %0 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmv.w.x fj_3, zero
-    %flw = riscv.flw %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: flw fj_3, 1(zero)
-    riscv.fsw %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
-    // CHECK-NEXT: fsw fj_0, 1(zero)
-
-    // RV32F: 9 "D" Standard Extension for Double-Precision Floating-Point, Version 2.0
-
-    %fld = riscv.fld %0, 1 : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fld fj_3, 1(zero)
-
-    %min_val = riscv.fld %0, "hello" : (!riscv.reg<zero>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fld fj_3, hello, zero
-
-    riscv.fsd %0, %f0, 1  : (!riscv.reg<zero>, !riscv.freg<fj_0>) -> ()
-    // CHECK-NEXT: fsd fj_0, 1(zero)
-
-    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmadd.d fj_3, fj_0, fj_1, fj_2
-    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>, !riscv.freg<fj_2>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmsub.d fj_3, fj_0, fj_1, fj_2
-    %fadd_d= riscv.fadd.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fadd.d fj_3, fj_0, fj_1
-    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fsub.d fj_3, fj_0, fj_1
-    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmul.d fj_3, fj_0, fj_1
-    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fdiv.d fj_3, fj_0, fj_1
-    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmin.d fj_3, fj_0, fj_1
-    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: fmax.d fj_3, fj_0, fj_1
-
-    %fcvt_d_w = riscv.fcvt.d.w %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.d.w fj_0, j_1
-    %fcvt_d_wu = riscv.fcvt.d.wu %1 : (!riscv.reg<j_1>) -> !riscv.freg<fj_0>
-    // CHECK-NEXT: fcvt.d.wu fj_0, j_1
-
-    // Vector Ops
-    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: vfadd.s fj_3, fj_0, fj_1
-    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg<fj_0>, !riscv.freg<fj_1>) -> !riscv.freg<fj_3>
-    // CHECK-NEXT: vfmul.s fj_3, fj_0, fj_1
-
-    // Terminate block
-    riscv_func.return
-    // CHECK-NEXT: ret
-  }
-// External
-riscv_func.func @external()
-// CHECK-NOT: external
-}) : () -> ()
+riscv_func.func @main() {
+  %0 = rv64.li 6 : !riscv.reg<zero>
+  // CHECK:      li zero, 6
+  %1 = rv64.li 5 : !riscv.reg<j_1>
+  // CHECK-NEXT: li j_1, 5
+
+  // Assembler pseudo-instructions
+  %li = rv64.li 1 : !riscv.reg<j_0>
+  // CHECK-NEXT: li j_0, 1
+  
+  // Terminate block
+  riscv_func.return
+  // CHECK-NEXT: ret
+}
diff --git a/tests/filecheck/dialects/rv64/rv64_ops.mlir b/tests/filecheck/dialects/rv64/rv64_ops.mlir
index 1897676952..b362d72a93 100644
--- a/tests/filecheck/dialects/rv64/rv64_ops.mlir
+++ b/tests/filecheck/dialects/rv64/rv64_ops.mlir
@@ -1,653 +1,37 @@
 // RUN: XDSL_ROUNDTRIP
 // RUN: XDSL_GENERIC_ROUNDTRIP
- 
-// TODO: Operations will be replaced with rv64 variant-specific counterparts
 
-"builtin.module"() ({
-  riscv_func.func @main() {
-    %0 = riscv.get_register : !riscv.reg
-    %1 = riscv.get_register : !riscv.reg
-    // RV32I/RV64I: 2.4 Integer Computational Instructions
+riscv_func.func @main() {
+  // Assembler pseudo-instructions
 
-    // Integer Register-Immediate Instructions
-    %addi = riscv.addi %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.addi %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %slti = riscv.slti %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slti %0, 1 : (!riscv.reg) -> !riscv.reg
-    %sltiu = riscv.sltiu %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sltiu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %andi = riscv.andi %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.andi %0, 1 : (!riscv.reg) -> !riscv.reg
-    %ori = riscv.ori %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.ori %0, 1 : (!riscv.reg) -> !riscv.reg
-    %xori = riscv.xori %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xori %0, 1 : (!riscv.reg) -> !riscv.reg
-    %slli = riscv.slli %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slli %0, 1 : (!riscv.reg) -> !riscv.reg
-    %srli = riscv.srli %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srli %0, 1 : (!riscv.reg) -> !riscv.reg
-    %srai = riscv.srai %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srai %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lui = riscv.lui 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lui 1 : () -> !riscv.reg
-    %auipc = riscv.auipc 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.auipc 1 : () -> !riscv.reg
-    %mv = riscv.mv %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.mv %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %seqz = riscv.seqz %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.seqz %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %snez = riscv.snez %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.snez %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zextb = riscv.zext.b %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.zext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zextw = riscv.zext.w %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.zext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %sextw = riscv.sext.w %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK: %{{.*}} = riscv.sext.w %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %srliw = riscv.srliw %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srliw %0, 1 : (!riscv.reg) -> !riscv.reg
-    %sraiw = riscv.sraiw %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sraiw %0, 1 : (!riscv.reg) -> !riscv.reg
-
-    // Integer Register-Register Operations
-    %add = riscv.add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %slt = riscv.slt %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.slt %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sltu = riscv.sltu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sltu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %and = riscv.and %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.and %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %or = riscv.or %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.or %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %xor = riscv.xor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sll = riscv.sll %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sll %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %srl = riscv.srl %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srl %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sub = riscv.sub %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sub %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sra = riscv.sra %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sra %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %addw = riscv.addw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.addw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %subw = riscv.subw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.subw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sllw = riscv.sllw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sllw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %srlw = riscv.srlw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.srlw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sraw = riscv.sraw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sraw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    riscv.nop
-    // CHECK-NEXT: riscv.nop
-
-    // RV32I/RV64I: 2.5 Control Transfer Instructions
-
-    // Unconditional Branch Instructions
-    riscv.jal 1
-    // CHECK-NEXT: riscv.jal 1
-    riscv.jal 1, !riscv.reg
-    // CHECK-NEXT: riscv.jal 1, !riscv.reg
-    riscv.jal "label"
-    // CHECK-NEXT: riscv.jal "label"
-
-    riscv.j 1
-    // CHECK-NEXT: riscv.j 1
-    riscv.j "label"
-    // CHECK-NEXT: riscv.j "label"
-
-    riscv.jalr %0, 1: (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, 1 : (!riscv.reg) -> ()
-    riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, 1, !riscv.reg : (!riscv.reg) -> ()
-    riscv.jalr %0, "label" : (!riscv.reg) -> ()
-    // CHECK-NEXT: riscv.jalr %0, "label" : (!riscv.reg) -> ()
-
-    riscv.ret
-    // CHECK-NEXT: riscv.ret
-  ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-  // CHECK-NEXT: ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-
-    // Conditional Branch Instructions
-    riscv.beq %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.beq %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bne %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bne %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.blt %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.blt %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bge %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bge %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bltu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bltu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.bgeu %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.bgeu %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.reg) -> ()
-
-    // RV32I/RV64I: 2.6 Load and Store Instructions
-
-    %lb = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lb %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lbu = riscv.lbu %0, 1: (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lbu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lh = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lh %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lhu = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lhu %0, 1 : (!riscv.reg) -> !riscv.reg
-    %lw = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.lw %0, 1 : (!riscv.reg) -> !riscv.reg
-    riscv.sb %0, %1, 1: (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sb %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sh %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-    // CHECK-NEXT: riscv.sw %0, %1, 1 : (!riscv.reg, !riscv.reg) -> ()
-
-    // RV32I/RV64I: 2.8 Control and Status Register Instructions
-
-    %csrrw_rw = riscv.csrrw %0 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrw_w = riscv.csrrw %0 1024, "w" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrw %0, 1024, "w" : (!riscv.reg) -> !riscv.reg
-    %csrrs_rw = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrs_r = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrs %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    %csrrc_rw = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024 : (!riscv.reg) -> !riscv.reg
-    %csrrc_r = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrc %0, 1024, "r" : (!riscv.reg) -> !riscv.reg
-    %csrrsi_rw = riscv.csrrsi 1024, 8 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 8 : () -> !riscv.reg
-    %csrrsi_r = riscv.csrrsi 1024, 0 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrsi 1024, 0 : () -> !riscv.reg
-    %csrrci_rw = riscv.csrrci 1024, 8 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 8 : () -> !riscv.reg
-    %csrrci_r = riscv.csrrci 1024, 0 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrci 1024, 0 : () -> !riscv.reg
-    %csrrwi_rw = riscv.csrrwi 1024, 1 : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1 : () -> !riscv.reg
-    %csrrwi_w = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.csrrwi 1024, 1, "w" : () -> !riscv.reg
-
-    // Machine Mode Privileged Instructions
-    riscv.wfi
-    // CHECK-NEXT: riscv.wfi
-
-
-    // RV32M/RV64M: 7 “M” Standard Extension for Integer Multiplication and Division
-
-    // Multiplication Operations
-    %mul = riscv.mul %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mul %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulh = riscv.mulh %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulh %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulhsu = riscv.mulhsu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulhsu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulhu = riscv.mulhu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulhu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %mulw = riscv.mulw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.mulw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-
-    // Division Operations
-    %div = riscv.div %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.div %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divu = riscv.divu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divw = riscv.divw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %divuw = riscv.divuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.divuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rem = riscv.rem %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rem %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remu = riscv.remu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remw = riscv.remw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %remuw = riscv.remuw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.remuw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-    // RV32B/RV64B:  “B” Standard Extension for Bit Manipulation
-
-    %rol = riscv.rol %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rol %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %ror = riscv.ror %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.ror %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rori = riscv.rori %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rori %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %roriw = riscv.roriw %0, 1 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.roriw %{{.*}}, 1 : (!riscv.reg) -> !riscv.reg
-    %rolw = riscv.rolw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rolw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %rorw = riscv.rorw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.rorw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bclr = riscv.bclr %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bclr %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bext = riscv.bext %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bext %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %bset = riscv.bset %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.bset %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %binv = riscv.binv %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.binv %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %adduw = riscv.add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh1add = riscv.sh1add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh1add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh1adduw = riscv.sh1add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh1add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh2add = riscv.sh2add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh2add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh2adduw = riscv.sh2add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh2add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh3add = riscv.sh3add %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh3add %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sh3adduw = riscv.sh3add.uw %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sh3add.uw %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %sextb = riscv.sext.b %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sext.b %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %sexth = riscv.sext.h %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.sext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %zexth = riscv.zext.h %0 : (!riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.zext.h %{{.*}} : (!riscv.reg) -> !riscv.reg
-    %andn = riscv.andn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.andn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %xnor = riscv.xnor %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.xnor %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %orn = riscv.orn %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.orn %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %max = riscv.max %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.max %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %maxu = riscv.maxu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.maxu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %min = riscv.min %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.min %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %minu = riscv.minu %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.minu %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-
-    // RV32/RV64 Zicond extension for conditional operations
-
-    %czeroeqzop = riscv.czero.eqz %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.czero.eqz %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    %czeronezop = riscv.czero.nez %0, %1 : (!riscv.reg, !riscv.reg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.czero.nez %{{.*}}, %{{.*}} : (!riscv.reg, !riscv.reg) -> !riscv.reg
-
-    // Assembler pseudo-instructions
-
-    %li = rv64.li 1 : !riscv.reg
-    // CHECK-NEXT: %{{.*}} = rv64.li 1 : !riscv.reg
-    // Environment Call and Breakpoints
-    riscv.ecall
-    // CHECK-NEXT: riscv.ecall
-    riscv.ebreak
-    // CHECK-NEXT: riscv.ebreak
-    riscv.directive ".bss"
-    // CHECK-NEXT: riscv.directive ".bss"
-    riscv.directive ".align" "2"
-    // CHECK-NEXT: riscv.directive ".align" "2"
-    riscv.assembly_section ".text" attributes {"foo" = i64} {
-      %nested_li = rv64.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i64} {
-    // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
-
-    riscv.assembly_section ".text" {
-      %nested_li = rv64.li 1 : !riscv.reg
-    }
-    // CHECK-NEXT:  riscv.assembly_section ".text" {
-    // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
-    // CHECK-NEXT:  }
-
-    // Custom instruction
-    %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-    // CHECK-NEXT:   %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-
-    // RV32F: 8 “F” Standard Extension for Single-Precision Floating-Point, Version 2.0
-    %f0 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-    %f1 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-    %f2 = riscv.get_float_register : !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.get_float_register : !riscv.freg
-
-    %fmv = riscv.fmv.s %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.s %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %fmadd_s = riscv.fmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmsub_s = riscv.fmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fnmsub_s = riscv.fnmsub.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fnmsub.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fnmadd_s = riscv.fnmadd.s %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fnmadd.s %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_s = riscv.fadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_s = riscv.fsub.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_s = riscv.fmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_s = riscv.fdiv.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_s_fm = riscv.fadd.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_s_fm = riscv.fsub.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_s_fm = riscv.fmul.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_s_fm = riscv.fdiv.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fsqrt_s = riscv.fsqrt.s %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsqrt.s %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %fsgnj_s = riscv.fsgnj.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnj.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsgnjn_s = riscv.fsgnjn.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnjn.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsgnjx_s = riscv.fsgnjx.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsgnjx.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_s = riscv.fmin.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_s = riscv.fmax.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_s_fm = riscv.fmin.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_s_fm = riscv.fmax.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fcvt_w_s = riscv.fcvt.w.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.w.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fcvt_wu_s = riscv.fcvt.wu.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.wu.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fmv_x_w = riscv.fmv.x.w %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.x.w %{{.*}} : (!riscv.freg) -> !riscv.reg
-
-    %feq_s = riscv.feq.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %flt_s = riscv.flt.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fle_s = riscv.fle.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %feq_s_fm = riscv.feq.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.feq.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %flt_s_fm = riscv.flt.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.flt.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fle_s_fm = riscv.fle.s %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fle.s %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.reg
-    %fclass_s = riscv.fclass.s %f0 : (!riscv.freg) -> !riscv.reg
-    // CHECK-NEXT: %{{.*}} = riscv.fclass.s %{{.*}} : (!riscv.freg) -> !riscv.reg
-    %fcvt_s_w = riscv.fcvt.s.w %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.w %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fcvt_s_wu = riscv.fcvt.s.wu %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.s.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fmv_w_x = riscv.fmv.w.x %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.w.x %{{.*}} : (!riscv.reg) -> !riscv.freg
-
-    %flw = riscv.flw %0, 1 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.flw %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
-    riscv.fsw %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
-    // CHECK-NEXT: riscv.fsw %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
-
-    // Vector Ops
-    %fld = riscv.fld %0, 1 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fld %{{.*}}, 1 : (!riscv.reg) -> !riscv.freg
-    riscv.fsd %0, %f0, 1 : (!riscv.reg, !riscv.freg) -> ()
-    // CHECK-NEXT: riscv.fsd %{{.*}}, %{{.*}}, 1 : (!riscv.reg, !riscv.freg) -> ()
-
-    %fmv_d = riscv.fmv.d %f0 : (!riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmv.d %{{.*}} : (!riscv.freg) -> !riscv.freg
-
-    %vfadd_s = riscv.vfadd.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.vfadd.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %vfmul_s = riscv.vfmul.s %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.vfmul.s %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    // RV32F: 9 “D” Standard Extension for Double-Precision Floating-Point, Version 2.0
-
-    %fadd_d = riscv.fadd.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_d = riscv.fsub.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_d = riscv.fmul.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_d = riscv.fdiv.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fadd_d_fm = riscv.fadd.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fadd.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fsub_d_fm = riscv.fsub.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fsub.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmul_d_fm = riscv.fmul.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmul.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fdiv_d_fm = riscv.fdiv.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fdiv.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmadd_d = riscv.fmadd.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmadd.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmsub_d = riscv.fmsub.d %f0, %f1, %f2 : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmsub.d %{{.*}}, %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_d = riscv.fmin.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_d = riscv.fmax.d %f0, %f1 : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fmin_d_fm = riscv.fmin.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmin.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    %fmax_d_fm = riscv.fmax.d %f0, %f1 fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fmax.d %{{.*}}, %{{.*}} fastmath<fast> : (!riscv.freg, !riscv.freg) -> !riscv.freg
-
-    %fcvt_d_w = riscv.fcvt.d.w %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.w %{{.*}} : (!riscv.reg) -> !riscv.freg
-    %fcvt_d_wu = riscv.fcvt.d.wu %0 : (!riscv.reg) -> !riscv.freg
-    // CHECK-NEXT: %{{.*}} = riscv.fcvt.d.wu %{{.*}} : (!riscv.reg) -> !riscv.freg
-
-    %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
-    // CHECK-NEXT: %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = riscv.parallel_mov %0, %1, %f0, %f1 [64, 32, 64, 32] : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
+  %li = rv64.li 1 : !riscv.reg
+  // CHECK: %{{.*}} = rv64.li 1 : !riscv.reg
+  riscv.assembly_section ".text" attributes {"foo" = i32} {
+    %nested_li = rv64.li 1 : !riscv.reg
+  }
+  // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
+  // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
+  // CHECK-NEXT:  }
 
-    // Terminate block
-    riscv_func.return
+  riscv.assembly_section ".text" {
+    %nested_li = rv64.li 1 : !riscv.reg
   }
-}) : () -> ()
+  // CHECK-NEXT:  riscv.assembly_section ".text" {
+  // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
+  // CHECK-NEXT:  }
+
+  riscv_func.return
+}
 
 // CHECK-GENERIC:       "builtin.module"() ({
 // CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
-// CHECK-GENERIC-NEXT:      %0 = "riscv.get_register"() : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %1 = "riscv.get_register"() : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %addi = "riscv.addi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slti = "riscv.slti"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sltiu = "riscv.sltiu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %andi = "riscv.andi"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %ori = "riscv.ori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xori = "riscv.xori"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slli = "riscv.slli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srli = "riscv.srli"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srai = "riscv.srai"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lui = "riscv.lui"() {immediate = 1 : i20} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %auipc = "riscv.auipc"() {immediate = 1 : i20} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mv = "riscv.mv"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %seqz = "riscv.seqz"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %snez = "riscv.snez"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zextb = "riscv.zext.b"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zextw = "riscv.zext.w"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sextw = "riscv.sext.w"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srliw = "riscv.srliw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sraiw = "riscv.sraiw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %add = "riscv.add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %slt = "riscv.slt"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sltu = "riscv.sltu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %and = "riscv.and"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %or = "riscv.or"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xor = "riscv.xor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sll = "riscv.sll"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srl = "riscv.srl"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sub = "riscv.sub"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sra = "riscv.sra"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %addw = "riscv.addw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %subw = "riscv.subw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sllw = "riscv.sllw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %srlw = "riscv.srlw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sraw = "riscv.sraw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.nop"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = 1 : si20, rd = !riscv.reg} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jal"() {immediate = #riscv.label<"label">} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = 1 : si20} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.j"() {immediate = #riscv.label<"label">} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = 1 : si12, rd = !riscv.reg} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.jalr"(%0) {immediate = #riscv.label<"label">} : (!riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.ret"() : () -> ()
-// CHECK-GENERIC-NEXT:    ^bb0(%2 : !riscv.reg, %3 : !riscv.reg):
-// CHECK-GENERIC-NEXT:      "riscv.beq"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bne"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.blt"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bge"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bltu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.bgeu"(%0, %1) {offset = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      %lb = "riscv.lb"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lbu = "riscv.lbu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lh = "riscv.lh"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lhu = "riscv.lhu"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %lw = "riscv.lw"(%0) {immediate = 1 : si12} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.sb"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.sh"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      "riscv.sw"(%0, %1) {immediate = 1 : si12} : (!riscv.reg, !riscv.reg) -> ()
-// CHECK-GENERIC-NEXT:      %csrrw_rw = "riscv.csrrw"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrw_w = "riscv.csrrw"(%0) {csr = 1024 : i32, writeonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrs_rw = "riscv.csrrs"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrs_r = "riscv.csrrs"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrc_rw = "riscv.csrrc"(%0) {csr = 1024 : i32} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrc_r = "riscv.csrrc"(%0) {csr = 1024 : i32, readonly} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrsi_rw = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrsi_r = "riscv.csrrsi"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrci_rw = "riscv.csrrci"() {csr = 1024 : i32, immediate = 8 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrci_r = "riscv.csrrci"() {csr = 1024 : i32, immediate = 0 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrwi_rw = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %csrrwi_w = "riscv.csrrwi"() {csr = 1024 : i32, immediate = 1 : i32, writeonly} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.wfi"() : () -> ()
-// CHECK-GENERIC-NEXT:      %mul = "riscv.mul"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulh = "riscv.mulh"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulhsu = "riscv.mulhsu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulhu = "riscv.mulhu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %mulw = "riscv.mulw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %div = "riscv.div"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divu = "riscv.divu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divw = "riscv.divw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %divuw = "riscv.divuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rem = "riscv.rem"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remu = "riscv.remu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remw = "riscv.remw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %remuw = "riscv.remuw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rol = "riscv.rol"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %ror = "riscv.ror"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rori = "riscv.rori"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %roriw = "riscv.roriw"(%0) {immediate = 1 : ui5} : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rolw = "riscv.rolw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %rorw = "riscv.rorw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bclr = "riscv.bclr"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bext = "riscv.bext"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %bset = "riscv.bset"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %binv = "riscv.binv"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %adduw = "riscv.add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh1add = "riscv.sh1add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh1adduw = "riscv.sh1add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh2add = "riscv.sh2add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh2adduw = "riscv.sh2add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh3add = "riscv.sh3add"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sh3adduw = "riscv.sh3add.uw"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sextb = "riscv.sext.b"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %sexth = "riscv.sext.h"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %zexth = "riscv.zext.h"(%0) : (!riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %andn = "riscv.andn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %xnor = "riscv.xnor"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %orn = "riscv.orn"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %max = "riscv.max"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %maxu = "riscv.maxu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %min = "riscv.min"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %minu = "riscv.minu"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %czeroeqzop = "riscv.czero.eqz"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %czeronezop = "riscv.czero.nez"(%0, %1) : (!riscv.reg, !riscv.reg) -> !riscv.reg
 // CHECK-GENERIC-NEXT:      %li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.ecall"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
 // CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i64} : () -> ()
+// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
 // CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
 // CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
-// CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
-// CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %f2 = "riscv.get_float_register"() : () -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmv = "riscv.fmv.s"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmadd_s = "riscv.fmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmsub_s = "riscv.fmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fnmsub_s = "riscv.fnmsub.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fnmadd_s = "riscv.fnmadd.s"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_s = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_s = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_s = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_s = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_s_fm = "riscv.fadd.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_s_fm = "riscv.fsub.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_s_fm = "riscv.fmul.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_s_fm = "riscv.fdiv.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsqrt_s = "riscv.fsqrt.s"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnj_s = "riscv.fsgnj.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnjn_s = "riscv.fsgnjn.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsgnjx_s = "riscv.fsgnjx.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_s = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_s = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_s_fm = "riscv.fmin.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_s_fm = "riscv.fmax.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_w_s = "riscv.fcvt.w.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fcvt_wu_s = "riscv.fcvt.wu.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fmv_x_w = "riscv.fmv.x.w"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %feq_s = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %flt_s = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fle_s = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %feq_s_fm = "riscv.feq.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %flt_s_fm = "riscv.flt.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fle_s_fm = "riscv.fle.s"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fclass_s = "riscv.fclass.s"(%f0) : (!riscv.freg) -> !riscv.reg
-// CHECK-GENERIC-NEXT:      %fcvt_s_w = "riscv.fcvt.s.w"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_s_wu = "riscv.fcvt.s.wu"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmv_w_x = "riscv.fmv.w.x"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %flw = "riscv.flw"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      "riscv.fsw"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
-// CHECK-GENERIC-NEXT:      %fld = "riscv.fld"(%0) {immediate = 1 : i12} : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      "riscv.fsd"(%0, %f0) {immediate = 1 : i12} : (!riscv.reg, !riscv.freg) -> ()
-// CHECK-GENERIC-NEXT:      %fmv_d = "riscv.fmv.d"(%f0) : (!riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %vfadd_s = "riscv.vfadd.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %vfmul_s = "riscv.vfmul.s"(%f0, %f1) : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_d = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_d = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_d = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_d = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fadd_d_fm = "riscv.fadd.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fsub_d_fm = "riscv.fsub.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmul_d_fm = "riscv.fmul.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fdiv_d_fm = "riscv.fdiv.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmadd_d = "riscv.fmadd.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmsub_d = "riscv.fmsub.d"(%f0, %f1, %f2) : (!riscv.freg, !riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_d = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_d = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<none>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmin_d_fm = "riscv.fmin.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fmax_d_fm = "riscv.fmax.d"(%f0, %f1) {fastmath = #riscv.fastmath<fast>} : (!riscv.freg, !riscv.freg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_d_w = "riscv.fcvt.d.w"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %fcvt_d_wu = "riscv.fcvt.d.wu"(%0) : (!riscv.reg) -> !riscv.freg
-// CHECK-GENERIC-NEXT:      %mov_int_a, %mov_int_b, %mov_f_a, %mov_f_b = "riscv.parallel_mov"(%0, %1, %f0, %f1) <{input_widths = array<i32: 64, 32, 64, 32>}> : (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg) -> (!riscv.reg, !riscv.reg, !riscv.freg, !riscv.freg)
 // CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
 // CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
 // CHECK-GENERIC-NEXT:  }) : () -> ()

From 8a4144c3d6faf2615dc5504f16b44fe8368a1332 Mon Sep 17 00:00:00 2001
From: osmanyasar05 <osmanyas05@gmail.com>
Date: Sun, 8 Feb 2026 12:37:51 +0000
Subject: [PATCH 9/9] remove assembly section tests

---
 tests/filecheck/dialects/riscv/riscv_ops.mlir | 19 +++++++++++++++++++
 ...ssion.mlir => rv32_assembly_emission.mlir} |  0
 tests/filecheck/dialects/rv32/rv32_ops.mlir   | 19 -------------------
 ...ssion.mlir => rv64_assembly_emission.mlir} |  0
 tests/filecheck/dialects/rv64/rv64_ops.mlir   | 19 -------------------
 5 files changed, 19 insertions(+), 38 deletions(-)
 rename tests/filecheck/dialects/rv32/{riscv_assembly_emission.mlir => rv32_assembly_emission.mlir} (100%)
 rename tests/filecheck/dialects/rv64/{riscv_assembly_emission.mlir => rv64_assembly_emission.mlir} (100%)

diff --git a/tests/filecheck/dialects/riscv/riscv_ops.mlir b/tests/filecheck/dialects/riscv/riscv_ops.mlir
index 8bd246af16..443cbdf972 100644
--- a/tests/filecheck/dialects/riscv/riscv_ops.mlir
+++ b/tests/filecheck/dialects/riscv/riscv_ops.mlir
@@ -280,6 +280,19 @@
     // CHECK-NEXT: riscv.directive ".bss"
     riscv.directive ".align" "2"
     // CHECK-NEXT: riscv.directive ".align" "2"
+    riscv.assembly_section ".text" attributes {"foo" = i32} {
+      riscv.nop
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
+    // CHECK-NEXT:    riscv.nop
+    // CHECK-NEXT:  }
+
+    riscv.assembly_section ".text" {
+      riscv.nop
+    }
+    // CHECK-NEXT:  riscv.assembly_section ".text" {
+    // CHECK-NEXT:    riscv.nop
+    // CHECK-NEXT:  }
 
     // Custom instruction
     %custom0, %custom1 = riscv.custom_assembly_instruction %0, %1 {"instruction_name" = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
@@ -560,6 +573,12 @@
 // CHECK-GENERIC-NEXT:      "riscv.ebreak"() : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".bss"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv.directive"() {directive = ".align", value = "2"} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        "riscv.nop"() : () -> ()
+// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
+// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
+// CHECK-GENERIC-NEXT:        "riscv.nop"() : () -> ()
+// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
 // CHECK-GENERIC-NEXT:      %custom0, %custom1 = "riscv.custom_assembly_instruction"(%0, %1) {instruction_name = "hello"} : (!riscv.reg, !riscv.reg) -> (!riscv.reg, !riscv.reg)
 // CHECK-GENERIC-NEXT:      %f0 = "riscv.get_float_register"() : () -> !riscv.freg
 // CHECK-GENERIC-NEXT:      %f1 = "riscv.get_float_register"() : () -> !riscv.freg
diff --git a/tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv32/rv32_assembly_emission.mlir
similarity index 100%
rename from tests/filecheck/dialects/rv32/riscv_assembly_emission.mlir
rename to tests/filecheck/dialects/rv32/rv32_assembly_emission.mlir
diff --git a/tests/filecheck/dialects/rv32/rv32_ops.mlir b/tests/filecheck/dialects/rv32/rv32_ops.mlir
index ce8316ec88..557c7412a5 100644
--- a/tests/filecheck/dialects/rv32/rv32_ops.mlir
+++ b/tests/filecheck/dialects/rv32/rv32_ops.mlir
@@ -6,19 +6,6 @@ riscv_func.func @main() {
 
   %li = rv32.li 1 : !riscv.reg
   // CHECK: %{{.*}} = rv32.li 1 : !riscv.reg
-  riscv.assembly_section ".text" attributes {"foo" = i32} {
-    %nested_li = rv32.li 1 : !riscv.reg
-  }
-  // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
-  // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-  // CHECK-NEXT:  }
-
-  riscv.assembly_section ".text" {
-    %nested_li = rv32.li 1 : !riscv.reg
-  }
-  // CHECK-NEXT:  riscv.assembly_section ".text" {
-  // CHECK-NEXT:    %{{.*}} = rv32.li 1 : !riscv.reg
-  // CHECK-NEXT:  }
 
   riscv_func.return
 }
@@ -26,12 +13,6 @@ riscv_func.func @main() {
 // CHECK-GENERIC:       "builtin.module"() ({
 // CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
 // CHECK-GENERIC-NEXT:      %li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv32.li"() {immediate = 1 : i32} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
 // CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
 // CHECK-GENERIC-NEXT:  }) : () -> ()
diff --git a/tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir b/tests/filecheck/dialects/rv64/rv64_assembly_emission.mlir
similarity index 100%
rename from tests/filecheck/dialects/rv64/riscv_assembly_emission.mlir
rename to tests/filecheck/dialects/rv64/rv64_assembly_emission.mlir
diff --git a/tests/filecheck/dialects/rv64/rv64_ops.mlir b/tests/filecheck/dialects/rv64/rv64_ops.mlir
index b362d72a93..5a0a81649d 100644
--- a/tests/filecheck/dialects/rv64/rv64_ops.mlir
+++ b/tests/filecheck/dialects/rv64/rv64_ops.mlir
@@ -6,19 +6,6 @@ riscv_func.func @main() {
 
   %li = rv64.li 1 : !riscv.reg
   // CHECK: %{{.*}} = rv64.li 1 : !riscv.reg
-  riscv.assembly_section ".text" attributes {"foo" = i32} {
-    %nested_li = rv64.li 1 : !riscv.reg
-  }
-  // CHECK-NEXT:  riscv.assembly_section ".text" attributes {foo = i32} {
-  // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
-  // CHECK-NEXT:  }
-
-  riscv.assembly_section ".text" {
-    %nested_li = rv64.li 1 : !riscv.reg
-  }
-  // CHECK-NEXT:  riscv.assembly_section ".text" {
-  // CHECK-NEXT:    %{{.*}} = rv64.li 1 : !riscv.reg
-  // CHECK-NEXT:  }
 
   riscv_func.return
 }
@@ -26,12 +13,6 @@ riscv_func.func @main() {
 // CHECK-GENERIC:       "builtin.module"() ({
 // CHECK-GENERIC-NEXT:    "riscv_func.func"() ({
 // CHECK-GENERIC-NEXT:      %li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text", foo = i32} : () -> ()
-// CHECK-GENERIC-NEXT:      "riscv.assembly_section"() ({
-// CHECK-GENERIC-NEXT:        %nested_li = "rv64.li"() {immediate = 1 : i64} : () -> !riscv.reg
-// CHECK-GENERIC-NEXT:      }) {directive = ".text"} : () -> ()
 // CHECK-GENERIC-NEXT:      "riscv_func.return"() : () -> ()
 // CHECK-GENERIC-NEXT:    }) {sym_name = "main", function_type = () -> ()} : () -> ()
 // CHECK-GENERIC-NEXT:  }) : () -> ()