Skip to content

Commit c6d36df

Browse files
yvesllmmahadevan108
yvesll
authored and
mmahadevan108
committed
devices: MCXE24x: Add EIM and ERM clock ip name array
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
1 parent ee56cb7 commit c6d36df

File tree

3 files changed

+60
-15
lines changed

3 files changed

+60
-15
lines changed

‎mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE245/drivers/fsl_clock.h‎

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,18 @@ extern volatile uint32_t g_xtal0Freq;
183183
kCLOCK_Mpu \
184184
}
185185

186+
/*! @brief Clock ip name array for EIM. */
187+
#define EIM_CLOCKS \
188+
{ \
189+
kCLOCK_Eim \
190+
}
191+
192+
/*! @brief Clock ip name array for ERM. */
193+
#define ERM_CLOCKS \
194+
{ \
195+
kCLOCK_Erm \
196+
}
197+
186198
/*!
187199
* @brief LPO clock frequency.
188200
*/
@@ -730,13 +742,14 @@ uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type);
730742
*/
731743
static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *config)
732744
{
733-
assert(config);
734745
union
735746
{
736747
const uint32_t *configInt;
737748
const scg_sys_clk_config_t *configPtr;
738749
} Config;
739750

751+
assert(config);
752+
740753
Config.configPtr = config;
741754
SCG->VCCR = *(Config.configInt);
742755
}
@@ -750,13 +763,14 @@ static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *con
750763
*/
751764
static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *config)
752765
{
753-
assert(config);
754766
union
755767
{
756768
const uint32_t *configInt;
757769
const scg_sys_clk_config_t *configPtr;
758770
} Config;
759771

772+
assert(config);
773+
760774
Config.configPtr = config;
761775
SCG->RCCR = *(Config.configInt);
762776
}
@@ -770,13 +784,14 @@ static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *conf
770784
*/
771785
static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *config)
772786
{
773-
assert(config);
774787
union
775788
{
776789
const uint32_t *configInt;
777790
const scg_sys_clk_config_t *configPtr;
778791
} Config;
779792

793+
assert(config);
794+
780795
Config.configPtr = config;
781796
SCG->HCCR = *(Config.configInt);
782797
}
@@ -790,8 +805,6 @@ static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *co
790805
*/
791806
static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
792807
{
793-
assert(config);
794-
795808
uint32_t tempCsr;
796809

797810
union
@@ -800,6 +813,8 @@ static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
800813
scg_sys_clk_config_t *configPtr;
801814
} Config;
802815

816+
assert(config);
817+
803818
Config.configPtr = config;
804819

805820
/*

‎mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE246/drivers/fsl_clock.h‎

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,18 @@ extern volatile uint32_t g_xtal0Freq;
183183
kCLOCK_Mpu \
184184
}
185185

186+
/*! @brief Clock ip name array for EIM. */
187+
#define EIM_CLOCKS \
188+
{ \
189+
kCLOCK_Eim \
190+
}
191+
192+
/*! @brief Clock ip name array for ERM. */
193+
#define ERM_CLOCKS \
194+
{ \
195+
kCLOCK_Erm \
196+
}
197+
186198
/*!
187199
* @brief LPO clock frequency.
188200
*/
@@ -730,13 +742,14 @@ uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type);
730742
*/
731743
static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *config)
732744
{
733-
assert(config);
734745
union
735746
{
736747
const uint32_t *configInt;
737748
const scg_sys_clk_config_t *configPtr;
738749
} Config;
739750

751+
assert(config);
752+
740753
Config.configPtr = config;
741754
SCG->VCCR = *(Config.configInt);
742755
}
@@ -750,13 +763,14 @@ static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *con
750763
*/
751764
static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *config)
752765
{
753-
assert(config);
754766
union
755767
{
756768
const uint32_t *configInt;
757769
const scg_sys_clk_config_t *configPtr;
758770
} Config;
759771

772+
assert(config);
773+
760774
Config.configPtr = config;
761775
SCG->RCCR = *(Config.configInt);
762776
}
@@ -770,13 +784,14 @@ static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *conf
770784
*/
771785
static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *config)
772786
{
773-
assert(config);
774787
union
775788
{
776789
const uint32_t *configInt;
777790
const scg_sys_clk_config_t *configPtr;
778791
} Config;
779792

793+
assert(config);
794+
780795
Config.configPtr = config;
781796
SCG->HCCR = *(Config.configInt);
782797
}
@@ -790,8 +805,6 @@ static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *co
790805
*/
791806
static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
792807
{
793-
assert(config);
794-
795808
uint32_t tempCsr;
796809

797810
union
@@ -800,6 +813,8 @@ static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
800813
scg_sys_clk_config_t *configPtr;
801814
} Config;
802815

816+
assert(config);
817+
803818
Config.configPtr = config;
804819

805820
/*

‎mcux/mcux-sdk-ng/devices/MCX/MCXE/MCXE247/drivers/fsl_clock.h‎

Lines changed: 20 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,18 @@ extern volatile uint32_t g_xtal0Freq;
201201
kCLOCK_Mpu \
202202
}
203203

204+
/*! @brief Clock ip name array for EIM. */
205+
#define EIM_CLOCKS \
206+
{ \
207+
kCLOCK_Eim \
208+
}
209+
210+
/*! @brief Clock ip name array for ERM. */
211+
#define ERM_CLOCKS \
212+
{ \
213+
kCLOCK_Erm \
214+
}
215+
204216
/*!
205217
* @brief LPO clock frequency.
206218
*/
@@ -755,13 +767,14 @@ uint32_t CLOCK_GetSysClkFreq(scg_sys_clk_t type);
755767
*/
756768
static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *config)
757769
{
758-
assert(config);
759770
union
760771
{
761772
const uint32_t *configInt;
762773
const scg_sys_clk_config_t *configPtr;
763774
} Config;
764775

776+
assert(config);
777+
765778
Config.configPtr = config;
766779
SCG->VCCR = *(Config.configInt);
767780
}
@@ -775,13 +788,14 @@ static inline void CLOCK_SetVlprModeSysClkConfig(const scg_sys_clk_config_t *con
775788
*/
776789
static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *config)
777790
{
778-
assert(config);
779791
union
780792
{
781793
const uint32_t *configInt;
782794
const scg_sys_clk_config_t *configPtr;
783795
} Config;
784796

797+
assert(config);
798+
785799
Config.configPtr = config;
786800
SCG->RCCR = *(Config.configInt);
787801
}
@@ -795,13 +809,14 @@ static inline void CLOCK_SetRunModeSysClkConfig(const scg_sys_clk_config_t *conf
795809
*/
796810
static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *config)
797811
{
798-
assert(config);
799812
union
800813
{
801814
const uint32_t *configInt;
802815
const scg_sys_clk_config_t *configPtr;
803816
} Config;
804817

818+
assert(config);
819+
805820
Config.configPtr = config;
806821
SCG->HCCR = *(Config.configInt);
807822
}
@@ -815,14 +830,14 @@ static inline void CLOCK_SetHsrunModeSysClkConfig(const scg_sys_clk_config_t *co
815830
*/
816831
static inline void CLOCK_GetCurSysClkConfig(scg_sys_clk_config_t *config)
817832
{
818-
assert(config);
819-
820833
union
821834
{
822835
uint32_t *configInt;
823836
scg_sys_clk_config_t *configPtr;
824837
} Config;
825838

839+
assert(config);
840+
826841
Config.configPtr = config;
827842
*(Config.configInt) = SCG->CSR;
828843
}

0 commit comments

Comments
 (0)