drivers: can: mcux: flexcan: support Enhanced CAN Bit Timing registers

Some FlexCAN devices have enhanced bit timing registers (EPRS ENCBT EDCBT)
with extended timing configuration ranges and different behavior compared
to standard bit timing registers.

This change adds proper support for these enhanced registers, utilize full
bit timing capabilities.

Key differences for enhanced bit timing registers:
- Extended timing ranges with larger maximum values for sjw, phase_seg1,
  phase_seg2, and prescaler fields
- No propagation segment configuration support, so prop_seg must be 0
- prop_seg value is used directly without the typical 'minus 1' adjustment

The implementation adds conditional compilation based on the
`FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG` feature flag.
For Enhanced registers, use extended timing limits and prop_seg directly.

Test this commit on mimxrt1180_evk/mimxrt1189/cm33 drivers.can.timing
test case, and enable `TEST_ALL_BITRATES` Kconfig symbol.

Signed-off-by: William Tang <william.tang@nxp.com>

Author: william-tang914

drivers/can/can_mcux_flexcan.c

@@ -309,7 +309,13 @@ static int mcux_flexcan_start(const struct device *dev)
 	timing.rJumpwidth = data->timing.sjw - 1U;
 	timing.phaseSeg1 = data->timing.phase_seg1 - 1U;
 	timing.phaseSeg2 = data->timing.phase_seg2 - 1U;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && \
+	     FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
+	/* No propagation segment configuration, so prop_seg must be 0 */
+	timing.propSeg = data->timing.prop_seg;
+#else
 	timing.propSeg = data->timing.prop_seg - 1U;
+#endif
 	FLEXCAN_SetTimingConfig(base, &timing);
 
 #ifdef CONFIG_CAN_MCUX_FLEXCAN_FD
@@ -1256,7 +1262,13 @@ static int mcux_flexcan_init(const struct device *dev)
 	flexcan_config.enableListenOnlyMode = true;
 
 	flexcan_config.timingConfig.rJumpwidth = data->timing.sjw - 1U;
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && \
+	     FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
+	/* No propagation segment configuration, so prop_seg must be 0 */
+	flexcan_config.timingConfig.propSeg = data->timing.prop_seg;
+#else
 	flexcan_config.timingConfig.propSeg = data->timing.prop_seg - 1U;
+#endif
 	flexcan_config.timingConfig.phaseSeg1 = data->timing.phase_seg1 - 1U;
 	flexcan_config.timingConfig.phaseSeg2 = data->timing.phase_seg2 - 1U;
 
@@ -1358,13 +1370,46 @@ static DEVICE_API(can, mcux_flexcan_fd_driver_api) = {
 	 * FlexCAN FD timing limits are specified in the "CAN Bit Timing
 	 * Register (CBT)" and "CAN FD Bit Timing Register" field description
 	 * tables in the SoC reference manual.
+	 * Some devices have enhanced bit timing registers (EPRS ENCBT EDCBT)
+	 * with different limits and do not have propagation segment configuration.
 	 *
 	 * Note that the values here are the "physical" timing limits, whereas
 	 * the register field limits are physical values minus 1 (which is
 	 * handled by the flexcan_timing_config_t field assignments elsewhere
 	 * in this driver). The exception to this are the prop_seg values for
 	 * the data phase, which correspond to the allowed register values.
 	 */
+#if (defined(FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG) && \
+	     FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG)
+	.timing_min = {
+		.sjw = 0x01,
+		.prop_seg = 0,
+		.phase_seg1 = 0x02,
+		.phase_seg2 = 0x02,
+		.prescaler = 0x01
+	},
+	.timing_max = {
+		.sjw = 0x80,
+		.prop_seg = 0,
+		.phase_seg1 = 0x100,
+		.phase_seg2 = 0x80,
+		.prescaler = 0x400
+	},
+	.timing_data_min = {
+		.sjw = 0x01,
+		.prop_seg = 0,
+		.phase_seg1 = 0x02,
+		.phase_seg2 = 0x02,
+		.prescaler = 0x01
+	},
+	.timing_data_max = {
+		.sjw = 0x10,
+		.prop_seg = 0,
+		.phase_seg1 = 0x20,
+		.phase_seg2 = 0x10,
+		.prescaler = 0x400
+	},
+#else
 	.timing_min = {
 		.sjw = 0x01,
 		.prop_seg = 0x01,
@@ -1393,6 +1438,7 @@ static DEVICE_API(can, mcux_flexcan_fd_driver_api) = {
 		.phase_seg2 = 0x08,
 		.prescaler = 0x400
 	},
+#endif /* FSL_FEATURE_FLEXCAN_HAS_ENHANCED_BIT_TIMING_REG */
 };
 #endif /* CONFIG_CAN_MCUX_FLEXCAN_FD */