boards: enables support for s32z270 hse crypto

haduongquang · haduongquang · commit 1f24a4b782d0 · 2025-04-28T15:00:00.000+07:00
Enable test for s32z270 hash crypto.

Enable samples for cipher cryptoEndable samples for EBC, CBC,
CTR mode of cipher crypto.

Signed-off-by: Ha Duong Quang &lt;ha.duongquang@nxp.com&gt;
diff --git a/boards/nxp/s32z2xxdc2/doc/index.rst b/boards/nxp/s32z2xxdc2/doc/index.rst
@@ -136,6 +136,19 @@ External Flash
 The on-board S26HS512T 512M-bit HyperFlash memory is connected to the QSPI controller
 port A1. This board configuration selects it as the default flash controller.
 
+CRYPTO
+======
+
+The Hardware Security Engine (HSE) supports cryptographic operations, including hashing and
+symmetric ciphers, with capabilities for ECB, CBC, and CTR modes using RAM-based key catalogs
+with 128-bit or 256-bit key lengths.
+
+.. note::
+   The driver assumes that the HSE Firmware has been installed and configured (i.e the key catalogs
+   has been formatted, used MU instances has been activated, etc). HSE Firmware installation and
+   configuration phase documented in HSE Firmware User Manual. Please contact NXP sales person or
+   NXP distributor in order to have access to that document.
+
 Programming and Debugging
 *************************
 
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu0_D.yaml
@@ -1,4 +1,4 @@
-# Copyright 2023-2024 NXP
+# Copyright 2023-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu0
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - crypto
 vendor: nxp
diff --git a/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml b/boards/nxp/s32z2xxdc2/s32z2xxdc2_s32z270_rtu1_D.yaml
@@ -1,4 +1,4 @@
-# Copyright 2022-2024 NXP
+# Copyright 2022-2025 NXP
 # SPDX-License-Identifier: Apache-2.0
 
 identifier: s32z2xxdc2@D/s32z270/rtu1
@@ -20,4 +20,5 @@ supported:
   - i2c
   - dma
   - pwm
+  - crypto
 vendor: nxp
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay b/samples/drivers/crypto/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub2 {
+	status = "okay";
+};
diff --git a/samples/drivers/crypto/src/main.c b/samples/drivers/crypto/src/main.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2016 Intel Corporation.
+ * Copyright 2025 NXP
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -27,6 +28,8 @@ LOG_MODULE_REGISTER(main);
 #define CRYPTO_DEV_COMPAT st_stm32_aes
 #elif DT_HAS_COMPAT_STATUS_OKAY(nxp_mcux_dcp)
 #define CRYPTO_DEV_COMPAT nxp_mcux_dcp
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #elif CONFIG_CRYPTO_NRF_ECB
 #define CRYPTO_DEV_COMPAT nordic_nrf_ecb
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu0.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub0 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay b/tests/crypto/crypto_hash/boards/s32z2xxdc2_s32z270_rtu1.overlay
@@ -0,0 +1,9 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&mub2 {
+	status = "okay";
+};
diff --git a/tests/crypto/crypto_hash/src/main.c b/tests/crypto/crypto_hash/src/main.c
@@ -13,6 +13,8 @@
 #define CRYPTO_DRV_NAME CONFIG_CRYPTO_MBEDTLS_SHIM_DRV_NAME
 #elif DT_HAS_COMPAT_STATUS_OKAY(renesas_smartbond_crypto)
 #define CRYPTO_DEV_COMPAT renesas_smartbond_crypto
+#elif DT_HAS_COMPAT_STATUS_OKAY(nxp_s32_crypto_hse_mu)
+#define CRYPTO_DEV_COMPAT nxp_s32_crypto_hse_mu
 #else
 #error "You need to enable one crypto device"
 #endif
