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henrikbrixandersenkartben
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drivers: counter: add NEORV32 GPTMR driver
Add counter driver for the NEORV32 General Purpose Timer (GPTMR). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
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‎drivers/counter/CMakeLists.txt‎

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@@ -57,3 +57,4 @@ zephyr_library_sources_ifdef(CONFIG_COUNTER_RA_AGT counter_renesas_
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zephyr_library_sources_ifdef(CONFIG_COUNTER_RENESAS_RZ_GTM counter_renesas_rz_gtm.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912_SLWTMR counter_realtek_rts5912_slwtmr.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_REALTEK_RTS5912 counter_realtek_rts5912.c)
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zephyr_library_sources_ifdef(CONFIG_COUNTER_NEORV32_GPTMR counter_neorv32_gptmr.c)

‎drivers/counter/Kconfig‎

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@@ -112,4 +112,6 @@ source "drivers/counter/Kconfig.rts5912_slwtmr"
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source "drivers/counter/Kconfig.rts5912"
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source "drivers/counter/Kconfig.neorv32"
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endif # COUNTER

‎drivers/counter/Kconfig.neorv32‎

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# NEORV32 General Purpose Timer (GPTMR)
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#
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# Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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# SPDX-License-Identifier: Apache-2.0
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config COUNTER_NEORV32_GPTMR
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bool "NEORV32 GPTMR driver"
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default y
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depends on DT_HAS_NEORV32_GPTMR_ENABLED
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depends on SYSCON
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help
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Enable NEORV32 General Purpose Timer (GPTMR) driver.

‎drivers/counter/counter_neorv32_gptmr.c‎

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/*
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* Copyright (c) 2025 Henrik Brix Andersen <henrik@brixandersen.dk>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT neorv32_gptmr
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#include <zephyr/drivers/counter.h>
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#include <zephyr/drivers/syscon.h>
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#include <zephyr/irq.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/logging/log.h>
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#include <soc.h>
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LOG_MODULE_REGISTER(neorv32_gptmr, CONFIG_COUNTER_LOG_LEVEL);
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/* Registers */
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#define NEORV32_GPTMR_CTRL 0x00
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#define NEORV32_GPTMR_CTRL_EN BIT(0)
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#define NEORV32_GPTMR_CTRL_PRSC GENMASK(3, 1)
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#define NEORV32_GPTMR_CTRL_IRQ_CLR BIT(30)
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#define NEORV32_GPTMR_CTRL_IRQ_PND BIT(31)
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#define NEORV32_GPTMR_THRES 0x04
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#define NEORV32_GPTMR_COUNT 0x08
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struct neorv32_gptmr_config {
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struct counter_config_info info;
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const struct device *syscon;
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mm_reg_t base;
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uint8_t prescaler;
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void (*irq_config_func)(void);
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};
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struct neorv32_gptmr_data {
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struct k_spinlock lock;
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counter_top_callback_t top_callback;
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void *top_user_data;
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};
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static inline uint32_t neorv32_gptmr_read(const struct device *dev, uint16_t reg)
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{
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const struct neorv32_gptmr_config *config = dev->config;
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return sys_read32(config->base + reg);
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}
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static inline void neorv32_gptmr_write(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct neorv32_gptmr_config *config = dev->config;
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sys_write32(val, config->base + reg);
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}
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static int neorv32_gptmr_start(const struct device *dev)
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{
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struct neorv32_gptmr_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t ctrl;
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key = k_spin_lock(&data->lock);
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ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL);
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ctrl |= NEORV32_GPTMR_CTRL_EN;
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int neorv32_gptmr_stop(const struct device *dev)
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{
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struct neorv32_gptmr_data *data = dev->data;
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k_spinlock_key_t key;
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uint32_t ctrl;
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key = k_spin_lock(&data->lock);
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ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL);
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ctrl &= ~NEORV32_GPTMR_CTRL_EN;
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl);
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k_spin_unlock(&data->lock, key);
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return 0;
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}
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static int neorv32_gptmr_get_value(const struct device *dev, uint32_t *ticks)
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{
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*ticks = neorv32_gptmr_read(dev, NEORV32_GPTMR_COUNT);
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return 0;
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}
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static int neorv32_gptmr_set_top_value(const struct device *dev, const struct counter_top_cfg *cfg)
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{
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struct neorv32_gptmr_data *data = dev->data;
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k_spinlock_key_t key;
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bool restart = false;
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uint32_t count;
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uint32_t ctrl;
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int err = 0;
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__ASSERT_NO_MSG(cfg != NULL);
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if (cfg->ticks == 0) {
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return -EINVAL;
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}
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if ((cfg->flags & ~(COUNTER_TOP_CFG_DONT_RESET | COUNTER_TOP_CFG_RESET_WHEN_LATE)) != 0U) {
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LOG_ERR("unsupported flags 0x%08x", cfg->flags);
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return -ENOTSUP;
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}
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key = k_spin_lock(&data->lock);
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data->top_callback = cfg->callback;
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data->top_user_data = cfg->user_data;
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ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL);
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count = neorv32_gptmr_read(dev, NEORV32_GPTMR_COUNT);
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if ((ctrl & NEORV32_GPTMR_CTRL_EN) != 0U) {
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if ((cfg->flags & COUNTER_TOP_CFG_DONT_RESET) == 0U) {
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl & ~NEORV32_GPTMR_CTRL_EN);
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restart = true;
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} else if (count >= cfg->ticks) {
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if ((cfg->flags & COUNTER_TOP_CFG_RESET_WHEN_LATE) != 0U) {
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL,
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ctrl & ~NEORV32_GPTMR_CTRL_EN);
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restart = true;
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}
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err = -ETIME;
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}
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}
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neorv32_gptmr_write(dev, NEORV32_GPTMR_THRES, cfg->ticks);
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if (restart) {
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl);
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}
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k_spin_unlock(&data->lock, key);
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return err;
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}
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static uint32_t neorv32_gptmr_get_pending_int(const struct device *dev)
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{
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uint32_t ctrl;
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ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL);
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return (ctrl & NEORV32_GPTMR_CTRL_IRQ_PND) != 0 ? 1 : 0;
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}
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static uint32_t neorv32_gptmr_get_top_value(const struct device *dev)
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{
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return neorv32_gptmr_read(dev, NEORV32_GPTMR_THRES);
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}
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static uint32_t neorv32_gptmr_get_freq(const struct device *dev)
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{
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static const uint16_t prescalers[] = { 2U, 4U, 8U, 64U, 128U, 1024U, 2048U, 4096U };
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const struct neorv32_gptmr_config *config = dev->config;
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uint32_t clk;
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int err;
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err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_CLK, &clk);
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if (err < 0) {
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LOG_ERR("failed to determine clock rate (err %d)", err);
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return 0U;
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}
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return clk / prescalers[config->prescaler];
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}
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static void neorv32_gptmr_isr(const struct device *dev)
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{
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struct neorv32_gptmr_data *data = dev->data;
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counter_top_callback_t top_callback;
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void *top_user_data;
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k_spinlock_key_t key;
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uint32_t ctrl;
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key = k_spin_lock(&data->lock);
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ctrl = neorv32_gptmr_read(dev, NEORV32_GPTMR_CTRL);
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ctrl |= NEORV32_GPTMR_CTRL_IRQ_CLR;
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl);
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top_callback = data->top_callback;
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top_user_data = data->top_user_data;
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k_spin_unlock(&data->lock, key);
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if (top_callback != NULL) {
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top_callback(dev, top_user_data);
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}
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}
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static int neorv32_gptmr_init(const struct device *dev)
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{
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const struct neorv32_gptmr_config *config = dev->config;
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uint32_t features;
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uint32_t ctrl;
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int err;
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if (!device_is_ready(config->syscon)) {
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LOG_ERR("syscon device not ready");
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return -EINVAL;
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}
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err = syscon_read_reg(config->syscon, NEORV32_SYSINFO_SOC, &features);
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if (err < 0) {
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LOG_ERR("failed to determine implemented features (err %d)", err);
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return -EIO;
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}
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if ((features & NEORV32_SYSINFO_SOC_IO_GPTMR) == 0) {
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LOG_ERR("neorv32 gptmr not supported");
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return -ENODEV;
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}
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/* Stop timer, set prescaler, clear any pending interrupt */
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ctrl = FIELD_PREP(NEORV32_GPTMR_CTRL_PRSC, config->prescaler) | NEORV32_GPTMR_CTRL_IRQ_CLR;
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neorv32_gptmr_write(dev, NEORV32_GPTMR_CTRL, ctrl);
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config->irq_config_func();
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return 0;
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}
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static DEVICE_API(counter, neorv32_gptmr_driver_api) = {
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.start = neorv32_gptmr_start,
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.stop = neorv32_gptmr_stop,
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.get_value = neorv32_gptmr_get_value,
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.set_top_value = neorv32_gptmr_set_top_value,
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.get_pending_int = neorv32_gptmr_get_pending_int,
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.get_top_value = neorv32_gptmr_get_top_value,
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.get_freq = neorv32_gptmr_get_freq,
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};
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#define COUNTER_NEORV32_GPTMR_INIT(n) \
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static void neorv32_gptmr_config_func_##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), neorv32_gptmr_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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} \
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\
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static struct neorv32_gptmr_data neorv32_gptmr_data_##n; \
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\
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static struct neorv32_gptmr_config neorv32_gptmr_config_##n = { \
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.info = { \
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.max_top_value = UINT32_MAX, \
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.freq = 0U, \
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.flags = COUNTER_CONFIG_INFO_COUNT_UP, \
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.channels = 0, \
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}, \
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.syscon = DEVICE_DT_GET(DT_INST_PHANDLE(n, syscon)), \
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.base = DT_INST_REG_ADDR(n), \
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.prescaler = DT_INST_ENUM_IDX(n, prescaler), \
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.irq_config_func = neorv32_gptmr_config_func_##n, \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &neorv32_gptmr_init, NULL, &neorv32_gptmr_data_##n, \
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&neorv32_gptmr_config_##n, POST_KERNEL, \
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CONFIG_COUNTER_INIT_PRIORITY, &neorv32_gptmr_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(COUNTER_NEORV32_GPTMR_INIT)

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