tests: drivers: can: api: support nuvoton numaker_m3334ki

Add support for Nuvoton NuMaker-M3334KI board

This target has only 4 MPU regions, so disable userspace test.

Signed-off-by: Chun-Chieh Li <ccli8@nuvoton.com>

Author: ccli8

drivers/can/can_numaker.c

@@ -49,7 +49,7 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
 	clkdiv_divider = CLK_GetModuleClockDivider(config->clk_modidx) + 1;
 
 	switch (clksrc_rate_idx) {
-#if defined(CONFIG_SOC_SERIES_M46X)
+#if defined(CONFIG_SOC_SERIES_M46X) || defined(CONFIG_SOC_SERIES_M333X)
 	case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
 		*rate = __HXT / clkdiv_divider;
 		break;
@@ -91,19 +91,6 @@ static int can_numaker_get_core_clock(const struct device *dev, uint32_t *rate)
 	case (CLK_CANFDSEL_CANFD0SEL_HIRC48M_DIV4 >> CLK_CANFDSEL_CANFD0SEL_Pos):
 		*rate = (__HIRC48M / 4) / clkdiv_divider;
 		break;
-#elif defined(CONFIG_SOC_SERIES_M333X)
-	case (CLK_CLKSEL0_CANFD0SEL_HXT >> CLK_CLKSEL0_CANFD0SEL_Pos):
-		*rate = __HXT / clkdiv_divider;
-		break;
-	case (CLK_CLKSEL0_CANFD0SEL_PLL_DIV2 >> CLK_CLKSEL0_CANFD0SEL_Pos):
-		*rate = (CLK_GetPLLClockFreq() / 2) / clkdiv_divider;
-		break;
-	case (CLK_CLKSEL0_CANFD0SEL_HCLK >> CLK_CLKSEL0_CANFD0SEL_Pos):
-		*rate = CLK_GetHCLKFreq() / clkdiv_divider;
-		break;
-	case (CLK_CLKSEL0_CANFD0SEL_HIRC >> CLK_CLKSEL0_CANFD0SEL_Pos):
-		*rate = __HIRC / clkdiv_divider;
-		break;
 #endif
 	default:
 		LOG_ERR("Invalid clock source rate index");

tests/drivers/can/api/boards/numaker_m3334ki.conf

@@ -0,0 +1 @@
+CONFIG_TEST_USERSPACE=n

tests/drivers/can/api/boards/numaker_m3334ki.overlay

@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: Apache-2.0 */
+
+/ {
+	chosen {
+		zephyr,canbus = &canfd0;
+	};
+};
+
+&pinctrl {
+	/* CAN TX/RX --> UNO D8/D9 */
+	canfd0_default: canfd0_default {
+		group0 {
+			pinmux = <PA5MFP_CANFD0_TXD>,
+				 <PA4MFP_CANFD0_RXD>;
+		};
+	};
+};
+
+&canfd0 {
+	pinctrl-0 = <&canfd0_default>;
+	pinctrl-names = "default";
+	status = "okay";
+};