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style: soc: apply coding style on CMakeLists.txt files
Apply the CMake style guidelines to CMakeList.txt files in soc/. Signed-off-by: Josuah Demangeon <me@josuah.net>
1 parent e24c4ec commit 79b5790

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12 files changed

+56
-65
lines changed

12 files changed

+56
-65
lines changed

‎soc/intel/intel_adsp/CMakeLists.txt‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -7,11 +7,11 @@ zephyr_include_directories(common)
77

88
add_subdirectory(common)
99
if(CONFIG_SOC_SERIES_INTEL_ADSP_ACE)
10-
zephyr_include_directories(ace)
11-
add_subdirectory(ace)
10+
zephyr_include_directories(ace)
11+
add_subdirectory(ace)
1212
endif()
1313
if(CONFIG_INTEL_ADSP_CAVS)
14-
zephyr_include_directories(cavs)
15-
add_subdirectory(cavs)
14+
zephyr_include_directories(cavs)
15+
add_subdirectory(cavs)
1616
endif()
1717
zephyr_include_directories(common/include)

‎soc/mediatek/mt8xxx/CMakeLists.txt‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -9,10 +9,11 @@ zephyr_library_sources_ifdef(CONFIG_SOC_MT8188 ${CONFIG_SOC}/cpuclk.c)
99
set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/${CONFIG_SOC}/linker.ld CACHE INTERNAL "")
1010

1111
add_custom_target(dsp_img ALL
12-
DEPENDS ${ZEPHYR_FINAL_EXECUTABLE}
13-
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_img.py
14-
${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME}
15-
${CMAKE_BINARY_DIR}/zephyr/zephyr.img)
12+
DEPENDS ${ZEPHYR_FINAL_EXECUTABLE}
13+
COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/gen_img.py
14+
${ZEPHYR_BINARY_DIR}/${KERNEL_ELF_NAME}
15+
${CMAKE_BINARY_DIR}/zephyr/zephyr.img
16+
)
1617

1718
# Sign zephyr.ri using west (if the underlying rimage tool is
1819
# available; generally it isn't except in SOF builds). Note that the
@@ -37,9 +38,9 @@ board_set_rimage_target(${CONFIG_SOC})
3738
set(RIMAGE_SIGN_KEY "otc_private_key_3k.pem" CACHE STRING "default rimage key")
3839
add_custom_target(zephyr.ri ALL DEPENDS ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri)
3940
add_custom_command(
40-
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
41-
COMMENT "Sign with rimage..."
42-
COMMAND west $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose> sign
43-
--if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR}
44-
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
41+
OUTPUT ${CMAKE_BINARY_DIR}/zephyr/zephyr.ri
42+
COMMENT "Sign with rimage..."
43+
COMMAND west $<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose> sign
44+
--if-tool-available --tool rimage --build-dir ${CMAKE_BINARY_DIR}
45+
DEPENDS ${CMAKE_BINARY_DIR}/zephyr/${KERNEL_ELF_NAME}
4546
)

‎soc/native/inf_clock/CMakeLists.txt‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,15 @@ zephyr_library()
66
zephyr_library_compile_definitions(NO_POSIX_CHEATS)
77

88
zephyr_library_sources(
9-
soc.c
10-
native_tasks.c
11-
native_remap.c
12-
)
9+
soc.c
10+
native_tasks.c
11+
native_remap.c
12+
)
1313

1414
zephyr_library_include_directories(
1515
${ZEPHYR_BASE}/kernel/include
1616
${ZEPHYR_BASE}/arch/posix/include
17-
)
17+
)
1818

1919
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/posix/linker.ld CACHE INTERNAL "")
2020

‎soc/raspberrypi/rpi_pico/common/CMakeLists.txt‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,7 +4,7 @@
44
zephyr_include_directories(.)
55

66
zephyr_sources(
7-
soc.c
7+
soc.c
88
)
99

1010
zephyr_sources_ifdef(CONFIG_RPI_PICO_ROM_BOOTLOADER rom_bootloader.c)

‎soc/snps/hsdk/CMakeLists.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@ if(COMPILER STREQUAL gcc)
1212
else()
1313
# MWDT compiler options
1414
zephyr_compile_options(-arcv2hs -core2 -Xatomic -Xll64 -Xunaligned -Xcode_density
15-
-Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
16-
-Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc)
15+
-Xdiv_rem=radix4 -Xswap -Xbitscan -Xmpy_option=qmpyh
16+
-Xshift_assist -Xbarrel_shifter -Xtimer0 -Xtimer1 -Xrtc)
1717
zephyr_compile_options_ifdef(CONFIG_FPU -Xfpu_mac -Xfpud_div)
1818

1919
zephyr_ld_options(-Hlib=hs38_full)

‎soc/snps/nsim/arc_classic/em/CMakeLists.txt‎

Lines changed: 8 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -11,22 +11,20 @@ if(COMPILER STREQUAL gcc)
1111
else()
1212
# MWDT compiler options
1313
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM -arcv2em -core3 -Xdiv_rem=radix2
14-
-Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
15-
-Xshift_assist -Xdsp2 -Xdsp_complex
16-
-Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
17-
-Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
18-
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
14+
-Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter -Xshift_assist -Xdsp2 -Xdsp_complex
15+
-Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
16+
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
1917

2018
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
21-
-Xbitscan -Xswap -Xbarrel_shifter
22-
-Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
23-
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
19+
-Xbitscan -Xswap -Xbarrel_shifter
20+
-Xshift_assist -Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
21+
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
2422

2523
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_EM11D -Hlib=em9d_nrg_fpusp -Hdsplib)
2624

2725
if(CONFIG_SOC_NSIM_EM11D)
2826
set_property(GLOBAL PROPERTY z_arc_dsp_options -Xxy -Xagu_large -Hfxapi -Xdsp2
29-
-Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
30-
-Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
27+
-Xdsp_accshift=full -Xdsp_divsqrt=radix2 -Xdsp_complex -Xdsp_itu
28+
-Xdsp_ctrl=postshift,noguard,convergent -Xmpy_option=mpyd)
3129
endif()
3230
endif()

‎soc/snps/nsim/arc_classic/hs/CMakeLists.txt‎

Lines changed: 12 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -14,48 +14,42 @@ else()
1414
# MWDT compiler options
1515

1616
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS -arcv2hs -core2 -Xatomic
17-
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
18-
-Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
19-
-Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
20-
-Xtimer0 -Xtimer1)
17+
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
18+
-Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)
2119

2220
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS -Hlib=hs38_full)
2321

2422
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_SMP -arcv2hs -core2 -Xatomic
25-
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
26-
-Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
27-
-Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
28-
-Xtimer0 -Xtimer1)
23+
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
24+
-Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)
2925

3026
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_SMP -Hlib=hs38_full)
3127

3228
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -arcv2hs -core2 -Xatomic
33-
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density
34-
-Xswap -Xbitscan -Xmpy_option=qmpyh -Xshift_assist
35-
-Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc
36-
-Xtimer0 -Xtimer1)
29+
-Xll64 -Xdiv_rem=radix4 -Xunaligned -Xcode_density -Xswap -Xbitscan -Xmpy_option=qmpyh
30+
-Xshift_assist -Xbarrel_shifter -Xfpud_div -Xfpu_mac -Xrtc -Xtimer0 -Xtimer1)
3731

3832
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS_MPUV6 -Hlib=hs38_full)
3933

4034
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
41-
-HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
42-
-Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
35+
-HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
36+
-Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
4337

4438
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X -Hlib=hs58_full)
4539

4640
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -arcv3hs -core0 -Xdual_issue -uarch_rev=0:0
47-
-HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh
48-
-Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
41+
-HL -Hlpc_width=0 -Xatomic=2 -Xll64 -Xunaligned -Xdiv_rem=radix4 -Xmpy_option=qmpyh -Xtimer0
42+
-Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
4943

5044
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS5X_SMP -Hlib=hs58_full)
5145

5246
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
53-
-Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
47+
-Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
5448

5549
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X -Hlib=hs68_full_zephyr)
5650

5751
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -arc64 -core0 -uarch_rev=0:0 -HL -Xatomic=2
58-
-Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
52+
-Xunaligned -Xmpy_cycles=3 -Xtimer0 -Xtimer1 -Xrtc -dcache=32768,64,2,a -Hld_cycles=1)
5953

6054
zephyr_ld_option_ifdef(CONFIG_SOC_NSIM_HS6X_SMP -Hlib=hs68_full_zephyr)
6155
endif()

‎soc/snps/nsim/arc_classic/sem/CMakeLists.txt‎

Lines changed: 3 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -12,10 +12,8 @@ else()
1212
# MWDT compiler options
1313

1414
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
15-
-Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
16-
-Xshift_assist -Xbarrel_shifter -Xdsp2
17-
-Xdsp_complex -Xdsp_divsqrt=radix2
18-
-Xdsp_accshift=limited -Xtimer0 -Xtimer1
19-
-Xsec_timer0 -Xstack_check -Xsec_modes -Xdmac)
15+
-Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd -Xshift_assist -Xbarrel_shifter -Xdsp2
16+
-Xdsp_complex -Xdsp_divsqrt=radix2 -Xdsp_accshift=limited -Xtimer0 -Xtimer1 -Xsec_timer0
17+
-Xstack_check -Xsec_modes -Xdmac)
2018

2119
endif()

‎soc/st/stm32/CMakeLists.txt‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2,10 +2,10 @@
22
# SPDX-License-Identifier: Apache-2.0
33

44
if(CONFIG_BUILD_WITH_TFM)
5-
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
6-
#Execute post build script postbuild.sh
7-
COMMAND $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/postbuild.sh ${CROSS_COMPILE}${CC}
8-
)
5+
set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
6+
# Execute post build script postbuild.sh
7+
COMMAND $<TARGET_PROPERTY:tfm,TFM_BINARY_DIR>/api_ns/postbuild.sh ${CROSS_COMPILE}${CC}
8+
)
99
endif()
1010

1111
add_subdirectory(common)

‎soc/st/stm32/common/CMakeLists.txt‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33
zephyr_include_directories(.)
44

55
zephyr_sources(
6-
stm32cube_hal.c
7-
soc_config.c
6+
stm32cube_hal.c
7+
soc_config.c
88
)
99

1010
if(DEFINED CONFIG_STM32_CCM)

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