drivers: mspi: Adding SPI transceive with polling.

Implemented SPI transmit and receive functionality
in polling manner for the QSPI module of SAMD5x/SAME5x.

Signed-off-by: Shikhar Tandon <Shikhar.Tandon@microchip.com>

Author: shikhartandonmicrochip

drivers/mspi/mspi_mchp_qspi_g1.c

@@ -847,6 +847,13 @@ static int mspi_mchp_dev_config(const struct device *controller,
 		set_serial_memory_mode(q);
 		LOG_INF("Serial memory mode enabled\n");
 	}
+	/*if communicating with SPI device(not serial memory)
+	1 - set to SPI mode
+	2 - set CSMODE to 1 to foolproof any CS de-asserts when next byte transfer begins*/
+	else
+	{
+		q->QSPI_CTRLB = (q->QSPI_CTRLB & ~((QSPI_CTRLB_CSMODE_Msk) | (QSPI_CTRLB_MODE_Msk))) | (QSPI_CTRLB_MODE(0) | QSPI_CTRLB_CSMODE(1));
+	}
 	/*CTRLB register*/
 	//DLYCS and DLYBCT to be set by mspi_timing_config() API -current default 0
 	//DATALEN default to 0 -- 8 bits(1 byte)
@@ -1736,16 +1743,195 @@ static int mspi_pio_serial_transceive(const struct device *controller,
 }
 
 
+static bool spi_transceive(const struct device *controller,
+						   const struct mspi_xfer_packet *packet,
+						   const struct mspi_xfer *xfer)
+{
+	bool isRequestAccepted = false;
+	bool cmdwriteonly = false;
+
+	const mspi_sam_qspi_cfg_t *cfg = controller->config;
+	mspi_sam_qspi_data_t *data	  = controller->data;
+	qspi_registers_t *q = cfg->reg_cfg.regs;
+
+	mspi_context_t *ctx = &data->ctx;
+	uint32_t dummyData;
+	uint16_t dummyLen = packet->num_bytes;
+	uint16_t pre_dummy_bytes = 0;
+	uint16_t pre_dummy_bytes_tmp = 0;
+
+	uint32_t rx_drop  = 0;
+	uint8_t addressLen = xfer->addr_length;
+
+	uint32_t receivedData;
+	uint32_t packets = packet->num_bytes;
+	uint32_t blocks = 0;
+
+	uint32_t index = 0;
+	
+	if(packet->dir == MSPI_RX)
+	{
+		pre_dummy_bytes = (xfer->rx_dummy + 7) / 8;
+	}
+	else
+	{
+		pre_dummy_bytes = (xfer->tx_dummy + 7) / 8;
+	}
+	pre_dummy_bytes_tmp = pre_dummy_bytes;
+	rx_drop = xfer->cmd_length + xfer->addr_length + pre_dummy_bytes;
+	
+
+	//take a semaphore(TBD:do the dev_id check later)
+	if ((k_sem_count_get(&ctx->lock) != 0) && (k_sem_take(&ctx->lock, K_FOREVER) == 0))
+	{
+		isRequestAccepted = true;
+
+		/* Flush out any unread data in SPI read buffer */
+		dummyData = (q->QSPI_RXDATA & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos;
+
+		if(xfer->cmd_length != 0)
+		{
+			/*command write only , just break out of loop*/
+			if((packet->dir == MSPI_TX) && (xfer->addr_length == 0) && (packet->num_bytes == 0) && (packet->data_buf == NULL))
+			{
+				LOG_INF("Command write only");
+				cmdwriteonly = true;
+			}
+			LOG_INF("packet cmd = 0x%X",packet->cmd);
+			//initiate the transfer
+			q->QSPI_TXDATA = (uint8_t)packet->cmd;
+		}
+
+		//TBD:when command is more than 1 byte
+		while(blocks < (xfer->cmd_length + xfer->addr_length + packet->num_bytes + pre_dummy_bytes))
+		{
+			blocks++;
+			//wait for received data to come in RXDATA from shifter
+			while((q->QSPI_INTFLAG & QSPI_INTFLAG_RXC_Msk) != QSPI_INTFLAG_RXC_Msk)
+			{
+			}
+
+			{
+				//reading RXDATA clears RXC flag
+				receivedData = ((q->QSPI_RXDATA & QSPI_RXDATA_DATA_Msk) >> QSPI_RXDATA_DATA_Pos);
+				/*drop cmd,address,pre-dummy cycles*/
+				if(rx_drop != 0)
+				{
+					rx_drop--;
+					LOG_INF("rx_drop = %u",rx_drop);
+					if(cmdwriteonly == true)
+					{
+						QSPI_EndTransfer(q);
+						goto out;
+					}
+				}
+				else
+				{
+					if(packet->dir == MSPI_RX)
+					{
+						packet->data_buf[index++] = receivedData;
+						LOG_INF("receivedData = %u",receivedData);
+						if((blocks == (xfer->cmd_length + xfer->addr_length + packet->num_bytes + pre_dummy_bytes)) || (dummyLen == 0))
+						{
+							QSPI_EndTransfer(q);
+							LOG_INF("break out");
+							break;
+						}
+					}
+					/*for MSPI_TX if addresses and data has been sent , end and exit*/
+					else if((addressLen == 0) && (packets == 0))
+					{
+						/*dont go in DRE check if adress byte and data bytes are 0*/
+						QSPI_EndTransfer(q);
+						LOG_INF("All address and data packets sent.");
+						break;
+					}
+				}
+			}
+			
+
+			//wait for data to move from TXDATA to shifter
+			while((q->QSPI_INTFLAG & QSPI_INTFLAG_DRE_Msk) != QSPI_INTFLAG_DRE_Msk)
+			{
+			}
+			
+			{
+				/*set LASTXFER before sending out last byte in TXDATA(compare blocks or dummylen(if address bytes have been sent and last dummy byte remains))*/
+				if((blocks == (xfer->cmd_length + xfer->addr_length + packet->num_bytes + pre_dummy_bytes)) && (packet->dir == MSPI_TX))
+				{
+					LOG_INF("here!!!!");
+					QSPI_EndTransfer(q);
+					goto out;
+				}
+
+				if(addressLen > 0)
+				{
+					q->QSPI_TXDATA = (uint8_t)(((packet->address & (0x000000FF << (8*(addressLen - 1))))) >> (8*(addressLen - 1)));
+					addressLen--;
+				}
+				/*for dummy cycles if needed before transmitting bogus 0xFF to read in or clock in data*/
+				else if(pre_dummy_bytes_tmp > 0)
+				{
+					q->QSPI_TXDATA = (uint8_t)0xFF;
+					pre_dummy_bytes_tmp--;
+				}
+				else if(dummyLen > 0 && packet->dir == MSPI_RX)
+				{
+					if(dummyLen == 1)
+					{
+						//QSPI_EndTransfer(q);
+						LOG_INF("last dummy");
+					}
+					q->QSPI_TXDATA = (uint8_t)0xFF;
+					dummyLen--;
+				}
+				else 
+				{
+					q->QSPI_TXDATA = packet->data_buf[index++];
+					packets--;
+					LOG_INF("packets = %u,addressLen = %u,rx_drop = %u,blocks = %u",packets,addressLen,rx_drop,blocks);
+				}
+				
+			}
+			
+		}
+	}
+	else
+	{
+		LOG_INF("semaphore not init");
+		return false;
+	}
+
+out:
+	//semaphore be released
+	k_sem_give(&ctx->lock);
+	LOG_INF("Write Read Completed!");
+	//check for txdummy in writeread if it matches num_bytes - (opcode+address)
+	return isRequestAccepted;
+}
+
 static int mspi_pio_spi_transceive(const struct device *controller,
 			       				   const struct mspi_xfer *xfer)
 {
 
 	const struct mspi_xfer_packet *packet = NULL;
+	const mspi_sam_qspi_cfg_t *cfg = controller->config;
+	qspi_registers_t *q = cfg->reg_cfg.regs;
 
 	uint32_t num_packets = xfer->num_packet;
+	LOG_INF("num of packets = %u",num_packets);
 	uint32_t packets_done = 0;
 	int ret = 0;
 
+	
+	while(packets_done < num_packets)
+	{
+		packet = &xfer->packets[packets_done];
+		spi_transceive(controller,packet,xfer);
+		packets_done++;
+	}
+	
+
 out:
 	return ret;
 
@@ -1801,7 +1987,6 @@ static int mspi_mchp_transceive(const struct device *controller,
 	if(((q->QSPI_STATUS & QSPI_STATUS_CSSTATUS_Msk) == 0) || ((q->QSPI_STATUS & QSPI_STATUS_ENABLE_Msk) == 0)) 
 	{
 		LOG_ERR("QSPI module not enabled or CS line not de-asserted");
-		//return -EIO;
 		ret = -EIO;
 		goto out;
 	}
@@ -1817,7 +2002,12 @@ static int mspi_mchp_transceive(const struct device *controller,
 		if(find_serial_mode_of_child(cfg->child_desc,dev_id->dev_idx,cfg->num_children) == false)
 		{
 			/*SPI mode implementation*/
-			q->QSPI_CTRLB |= QSPI_CTRLB_MODE(0);
+
+			/*re-doing mode 0(SPI mode) and phase=0 polarity=0 for now*/
+			// q->QSPI_CTRLB |= QSPI_CTRLB_MODE(0);
+			// q->QSPI_BAUD |= (q->QSPI_BAUD & ~(QSPI_BAUD_CPOL_Msk | QSPI_BAUD_CPHA_Msk)) | 
+			// 					(QSPI_BAUD_CPOL(0) | QSPI_BAUD_CPHA(0));
+
 			LOG_INF("Implementing in SPI mode");
 			mspi_pio_spi_transceive(controller,xfer);
 		}

drivers/mspi/mspi_mchp_qspi_g1.h

@@ -219,7 +219,7 @@ static inline void set_address_len(qspi_registers_t *q, uint32_t addr_len)
  */
 static inline void set_serial_memory_mode(qspi_registers_t *q)
 {
-	q->QSPI_CTRLB |= QSPI_CTRLB_MODE(1);
+	q->QSPI_CTRLB = (q->QSPI_CTRLB & ~((QSPI_CTRLB_CSMODE_Msk) | (QSPI_CTRLB_MODE_Msk))) | (QSPI_CTRLB_MODE(1) | QSPI_CTRLB_CSMODE(0));
 }
 
 /**