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boards: intel: wcl: Add board definition
This commit introduces board defintion for Wildcat Lake. Signed-off-by: S Swetha <s.swetha@intel.com>
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‎boards/intel/wcl/CMakeLists.txt‎

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# SPDX-License-Identifier: Apache-2.0
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# Create an EFI image
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if(CONFIG_BUILD_OUTPUT_EFI)
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set_property(
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GLOBAL
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APPEND PROPERTY
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extra_post_build_commands
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COMMAND
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${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py
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-c ${CMAKE_C_COMPILER}
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-o ${CMAKE_OBJCOPY}
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-i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated
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-f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf
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$<$<BOOL:${CMAKE_VERBOSE_MAKEFILE}>:--verbose>
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WORKING_DIRECTORY
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${PROJECT_BINARY_DIR}
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)
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endif()

‎boards/intel/wcl/Kconfig.defconfig‎

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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BUILD_OUTPUT_STRIPPED
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default y
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config MP_MAX_NUM_CPUS
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default 2
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# The APIC TSC deadline and one-shot timers on this board run at 2 GHz; the HPET runs at 19.2 MHz.
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TSC_DEADLINE_TIMER
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TIMER_TSC
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default $(dt_node_int_prop_int,/soc/hpet@fed00000,clock-frequency)
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if APIC_TIMER
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config APIC_TIMER_IRQ
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default 24
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endif
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if APIC_TIMER_TSC
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config APIC_TIMER_TSC_M
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default 2
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config APIC_TIMER_TSC_N
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default 68
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endif
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config ACPI
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default y
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if ACPI
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config HEAP_MEM_POOL_ADD_SIZE_ACPI
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default 64000000
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config MAIN_STACK_SIZE
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default 320000
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if SHELL
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config SHELL_STACK_SIZE
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default 320000
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endif # SHELL
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endif # ACPI
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if DMA
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config DMA_64BIT
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default y
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config DMA_DW_HW_LLI
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default n
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config DMA_DW_CHANNEL_COUNT
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default 2
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endif
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config UART_NS16550_INTEL_LPSS_DMA
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default y if $(dt_nodelabel_enabled,uart0_dma) || $(dt_nodelabel_enabled,uart1_dma)
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config HAS_COVERAGE_SUPPORT
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default y

‎boards/intel/wcl/Kconfig.intel_wcl_crb‎

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# Copyright (c) 2025 Intel Corporation
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_INTEL_WCL_CRB
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select SOC_WILDCAT_LAKE

‎boards/intel/wcl/board.cmake‎

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# SPDX-License-Identifier: Apache-2.0
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board_set_flasher_ifnset(misc-flasher)
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board_finalize_runner_args(misc-flasher)

‎boards/intel/wcl/board.yml‎

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boards:
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- name: intel_wcl_crb
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vendor: intel
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socs:
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- name: wildcat_lake

‎boards/intel/wcl/doc/index.rst‎

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.. zephyr:board:: intel_wcl_crb
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Overview
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********
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Wildcat lake processor is a 64-bit multi-core processor.
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Wildcat Lake is based on a Hybrid architecture, utilizing P-cores E-cores Xe3 cores
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for performance and efficiency.
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For more information about Wildcat Lake Processor lines, P-cores, and E-cores
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please refer to `INTEL_WCL`_.
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This board configuration enables kernel support for the Wildcat Lake boards.
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Hardware
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********
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.. zephyr:board-supported-hw::
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General information about the board can be found at the `INTEL_WCL`_. website.
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Connections and IOs
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===================
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Refer to the `INTEL_WCL`_. website for more information.
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Programming and Debugging
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*************************
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Use the following procedures for booting an image for an Wildcat Lake RVP board.
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.. contents::
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:depth: 1
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:local:
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:backlinks: top
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Build Zephyr application
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========================
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#. Build a Zephyr application; for instance, to build the ``hello_world``
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application for Wildcat Lake RVP:
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.. zephyr-app-commands::
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:zephyr-app: samples/hello_world
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:board: intel_wcl_crb
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:goals: build
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.. note::
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A Zephyr EFI image file named :file:`zephyr.efi` is automatically
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created in the build directory after the application is built.
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.. include:: ../../../intel/common/efi_boot.rst
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:start-after: start_include_here
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.. _INTEL_WCL: https://edc.intel.com/content/www/us/en/secure/design/confidential/products/platforms/details/wildcat-lake-processor-external-design-specification-volume-1-of-2/

‎boards/intel/wcl/intel_wcl_crb.dts‎

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/*
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* Copyright (c) 2025 Intel Corporation
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#define DT_DRAM_SIZE DT_SIZE_M(2048)
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#include <intel/wildcat_lake.dtsi>
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/ {
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model = "intel_wcl_crb";
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compatible = "intel,wildcat-lake-crb";
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chosen {
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zephyr,sram = &dram0;
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zephyr,console = &uart_legacy;
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zephyr,shell-uart = &uart_legacy;
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};
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aliases {
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watchdog0 = &tco_wdt;
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rtc = &rtc;
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i2c-0 = &i2c0;
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pwm-test = &pwm0;
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};
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};
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&uart_legacy {
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status = "okay";
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};
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&rtc {
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status = "okay";
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};
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&smbus0 {
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status = "okay";
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};
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&tco_wdt {
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status = "okay";
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};
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&pwm0 {
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status = "okay";
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};
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&hpet {
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status = "okay";
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};
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&tgpio {
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status = "okay";
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};

‎boards/intel/wcl/intel_wcl_crb.yaml‎

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identifier: intel_wcl_crb
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name: Wildcat Lake CRB
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type: mcu
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arch: x86
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toolchain:
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- zephyr
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ram: 2048
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supported:
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- acpi
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- smp
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- smbus
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- watchdog
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- rtc
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- gpio
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- pwm
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testing:
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ignore_tags:
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- net
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- bluetooth
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vendor: intel

‎boards/intel/wcl/intel_wcl_crb_defconfig‎

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# SPDX-License-Identifier: Apache-2.0
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CONFIG_PIC_DISABLE=y
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CONFIG_LOAPIC=y
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CONFIG_CONSOLE=y
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CONFIG_SERIAL=y
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CONFIG_UART_NS16550=y
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CONFIG_UART_NS16550_VARIANT_NS16750=y
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CONFIG_UART_CONSOLE=y
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CONFIG_X2APIC=y
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CONFIG_SMP=y
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CONFIG_BUILD_OUTPUT_EFI=y

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