dts: nxp: Add binding for C40 flash and flash controller

Introduce DT bindings for on-chip C40 flash and its controller
and describe their corresponding nodes in nxp_s32k344_m7.dtsi.

- Binding: dts/bindings/mtd/nxp,c40-flash.yaml
Erase/write block sizes.

- Binding: dts/bindings/flash_controller/nxp,c40-flash-controller.yaml
Describe flash device (child) ranges

- SoC nodes:  With the new compatible and geometry
properties. Keep status = "disabled" at the SoC level
so boards opt-in.

This prepares the platform for using Zephyr’s flash API / FLASH_MAP /
MCUboot with internal code flash.

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>

Author: sumitbatra-nxp

dts/arm/nxp/nxp_s32k344_m7.dtsi

@@ -62,16 +62,23 @@
 			reg = <0x20400000 DT_SIZE_K(320)>;
 		};
 
-		/*
-		 * Last 48Kb is reserved by Secure BAF, application core cannot access it.
-		 *
-		 * Do not assign the compatible for this now, when Flash API is implemented,
-		 * need to check if "soc-nv-flash" can be used or a new binding need to be
-		 * created, based on it.
-		 */
-		flash0: flash@400000 {
-			reg = <0x00400000 DT_SIZE_K(4048)>;
-			status = "disabled";
+		c40fc: flash-controller@40268000 {
+			compatible = "nxp,c40-flash-controller";
+			reg = <0x40268000 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			/* Map child address 0x0..size onto CPU 0x0040_0000.. */
+			/* Last 48Kb is reserved by Secure BAF, app core cannot access it.*/
+			ranges = <0x0 0x00400000 DT_SIZE_K(4048)>; /* 4048 KiB Flash window */
+
+			flash0: flash@0 {
+				compatible = "nxp,c40-flash";
+				reg = <0x0 DT_SIZE_K(4048)>;
+				erase-block-size = <DT_SIZE_K(8)>;  /* 8 KiB sectors */
+				write-block-size = <8>;             /* 8-byte min program unit */
+				status = "disabled";
+			};
 		};
 
 		clock: clock-controller@402c8000 {

dts/bindings/flash_controller/nxp,c40-flash-controller.yaml

@@ -0,0 +1,19 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+title: NXP C40 Flash Controller
+
+description: |
+  Controller for the on-chip NXP C40 flash array.
+
+compatible: "nxp,c40-flash-controller"
+
+include: base.yaml
+
+properties:
+  "#address-cells":
+    const: 1
+    description: Number of address cells for child flash nodes.
+
+  "#size-cells":
+    const: 1
+    description: Number of size cells for child flash nodes.

dts/bindings/mtd/nxp,c40-flash.yaml

@@ -0,0 +1,19 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+title: NXP C40 Internal Flash
+
+description: |
+  On-chip C40 flash array used with NXP C40 flash controller.
+
+compatible: "nxp,c40-flash"
+
+include: soc-nv-flash.yaml
+
+properties:
+  erase-block-size:
+    const: 8192
+    description: Minimum erase size for C40 is 8 KiB.
+
+  write-block-size:
+    const: 8
+    description: Smallest programmable unit is 8 bytes.