diff --git a/boards/intel/wcl/CMakeLists.txt b/boards/intel/wcl/CMakeLists.txt new file mode 100644 index 0000000000000..8ea6bcd46e125 --- /dev/null +++ b/boards/intel/wcl/CMakeLists.txt @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: Apache-2.0 + +# Create an EFI image +if(CONFIG_BUILD_OUTPUT_EFI) + set_property( + GLOBAL + APPEND PROPERTY + extra_post_build_commands + COMMAND + ${PYTHON_EXECUTABLE} ${PROJECT_SOURCE_DIR}/arch/x86/zefi/zefi.py + -c ${CMAKE_C_COMPILER} + -o ${CMAKE_OBJCOPY} + -i ${ZEPHYR_BASE}/include ${PROJECT_BINARY_DIR}/include/generated + -f ${PROJECT_BINARY_DIR}/${CONFIG_KERNEL_BIN_NAME}.elf + $<$:--verbose> + WORKING_DIRECTORY + ${PROJECT_BINARY_DIR} +) +endif() diff --git a/boards/intel/wcl/Kconfig.defconfig b/boards/intel/wcl/Kconfig.defconfig new file mode 100644 index 0000000000000..7c29b0f6d983a --- /dev/null +++ b/boards/intel/wcl/Kconfig.defconfig @@ -0,0 +1,70 @@ +# Copyright (c) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BUILD_OUTPUT_STRIPPED + default y + +config MP_MAX_NUM_CPUS + default 2 + +# The APIC TSC deadline and one-shot timers on this board run at 2 GHz; the HPET runs at 19.2 MHz. +config SYS_CLOCK_HW_CYCLES_PER_SEC + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TSC_DEADLINE_TIMER + default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency) if APIC_TIMER_TSC + default $(dt_node_int_prop_int,/soc/hpet@fed00000,clock-frequency) + +if APIC_TIMER + +config APIC_TIMER_IRQ + default 24 + +endif + +if APIC_TIMER_TSC + +config APIC_TIMER_TSC_M + default 2 + +config APIC_TIMER_TSC_N + default 68 + +endif + +config ACPI + default y + +if ACPI + +config HEAP_MEM_POOL_ADD_SIZE_ACPI + default 64000000 + +config MAIN_STACK_SIZE + default 320000 + +if SHELL + +config SHELL_STACK_SIZE + default 320000 + +endif # SHELL + +endif # ACPI + +if DMA + +config DMA_64BIT + default y + +config DMA_DW_HW_LLI + default n + +config DMA_DW_CHANNEL_COUNT + default 2 + +endif + +config UART_NS16550_INTEL_LPSS_DMA + default y if $(dt_nodelabel_enabled,uart0_dma) || $(dt_nodelabel_enabled,uart1_dma) + +config HAS_COVERAGE_SUPPORT + default y diff --git a/boards/intel/wcl/Kconfig.intel_wcl_crb b/boards/intel/wcl/Kconfig.intel_wcl_crb new file mode 100644 index 0000000000000..50e84ecfadc2d --- /dev/null +++ b/boards/intel/wcl/Kconfig.intel_wcl_crb @@ -0,0 +1,5 @@ +# Copyright (c) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +config BOARD_INTEL_WCL_CRB + select SOC_WILDCAT_LAKE diff --git a/boards/intel/wcl/board.cmake b/boards/intel/wcl/board.cmake new file mode 100644 index 0000000000000..6b01bab2aeea8 --- /dev/null +++ b/boards/intel/wcl/board.cmake @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: Apache-2.0 + +board_set_flasher_ifnset(misc-flasher) +board_finalize_runner_args(misc-flasher) diff --git a/boards/intel/wcl/board.yml b/boards/intel/wcl/board.yml new file mode 100644 index 0000000000000..c7fc9d37506f6 --- /dev/null +++ b/boards/intel/wcl/board.yml @@ -0,0 +1,5 @@ +boards: + - name: intel_wcl_crb + vendor: intel + socs: + - name: wildcat_lake diff --git a/boards/intel/wcl/doc/index.rst b/boards/intel/wcl/doc/index.rst new file mode 100644 index 0000000000000..c87bb8d37b847 --- /dev/null +++ b/boards/intel/wcl/doc/index.rst @@ -0,0 +1,55 @@ +.. zephyr:board:: intel_wcl_crb + +Overview +******** +Wildcat lake processor is a 64-bit multi-core processor. + +Wildcat Lake is based on a Hybrid architecture, utilizing P-cores E-cores Xe3 cores +for performance and efficiency. + +For more information about Wildcat Lake Processor lines, P-cores, and E-cores +please refer to `INTEL_WCL`_. + +This board configuration enables kernel support for the Wildcat Lake boards. + +Hardware +******** + +.. zephyr:board-supported-hw:: + +General information about the board can be found at the `INTEL_WCL`_. website. + +Connections and IOs +=================== + +Refer to the `INTEL_WCL`_. website for more information. + +Programming and Debugging +************************* +Use the following procedures for booting an image for an Wildcat Lake RVP board. + +.. contents:: + :depth: 1 + :local: + :backlinks: top + +Build Zephyr application +======================== + +#. Build a Zephyr application; for instance, to build the ``hello_world`` + application for Wildcat Lake RVP: + + .. zephyr-app-commands:: + :zephyr-app: samples/hello_world + :board: intel_wcl_crb + :goals: build + + .. note:: + + A Zephyr EFI image file named :file:`zephyr.efi` is automatically + created in the build directory after the application is built. + +.. include:: ../../../intel/common/efi_boot.rst + :start-after: start_include_here + +.. _INTEL_WCL: https://edc.intel.com/content/www/us/en/secure/design/confidential/products/platforms/details/wildcat-lake-processor-external-design-specification-volume-1-of-2/ diff --git a/boards/intel/wcl/intel_wcl_crb.dts b/boards/intel/wcl/intel_wcl_crb.dts new file mode 100644 index 0000000000000..3b90fc2f371d2 --- /dev/null +++ b/boards/intel/wcl/intel_wcl_crb.dts @@ -0,0 +1,58 @@ +/* + * Copyright (c) 2025 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/dts-v1/; + +#include + +#define DT_DRAM_SIZE DT_SIZE_M(2048) + +#include + +/ { + model = "intel_wcl_crb"; + compatible = "intel,wildcat-lake-crb"; + + chosen { + zephyr,sram = &dram0; + zephyr,console = &uart_legacy; + zephyr,shell-uart = &uart_legacy; + }; + + aliases { + watchdog0 = &tco_wdt; + rtc = &rtc; + i2c-0 = &i2c0; + pwm-test = &pwm0; + }; +}; + +&uart_legacy { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&smbus0 { + status = "okay"; +}; + +&tco_wdt { + status = "okay"; +}; + +&pwm0 { + status = "okay"; +}; + +&hpet { + status = "okay"; +}; + +&tgpio { + status = "okay"; +}; diff --git a/boards/intel/wcl/intel_wcl_crb.yaml b/boards/intel/wcl/intel_wcl_crb.yaml new file mode 100644 index 0000000000000..f560468659d31 --- /dev/null +++ b/boards/intel/wcl/intel_wcl_crb.yaml @@ -0,0 +1,20 @@ +identifier: intel_wcl_crb +name: Wildcat Lake CRB +type: mcu +arch: x86 +toolchain: + - zephyr +ram: 2048 +supported: + - acpi + - smp + - smbus + - watchdog + - rtc + - gpio + - pwm +testing: + ignore_tags: + - net + - bluetooth +vendor: intel diff --git a/boards/intel/wcl/intel_wcl_crb_defconfig b/boards/intel/wcl/intel_wcl_crb_defconfig new file mode 100644 index 0000000000000..853850deb12c5 --- /dev/null +++ b/boards/intel/wcl/intel_wcl_crb_defconfig @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: Apache-2.0 + +CONFIG_PIC_DISABLE=y +CONFIG_LOAPIC=y +CONFIG_CONSOLE=y +CONFIG_SERIAL=y +CONFIG_UART_NS16550=y +CONFIG_UART_NS16550_VARIANT_NS16750=y +CONFIG_UART_CONSOLE=y +CONFIG_X2APIC=y +CONFIG_SMP=y +CONFIG_BUILD_OUTPUT_EFI=y diff --git a/drivers/gpio/gpio_intel.c b/drivers/gpio/gpio_intel.c index 7d59b1b8f08d2..f6b18390340be 100644 --- a/drivers/gpio/gpio_intel.c +++ b/drivers/gpio/gpio_intel.c @@ -68,8 +68,8 @@ #define PAD_CFG1_IOSTERM_MASK (0x03 << PAD_CFG1_IOSTERM_POS) #define PAD_CFG1_IOSTERM_FUNC (0 << PAD_CFG1_IOSTERM_POS) #define PAD_CFG1_IOSTERM_DISPUD (1 << PAD_CFG1_IOSTERM_POS) -#define PAD_CFG1_IOSTERM_PU (2 << PAD_CFG1_IOSTERM_POS) -#define PAD_CFG1_IOSTERM_PD (3 << PAD_CFG1_IOSTERM_POS) +#define PAD_CFG1_IOSTERM_PD (2 << PAD_CFG1_IOSTERM_POS) +#define PAD_CFG1_IOSTERM_PU (3 << PAD_CFG1_IOSTERM_POS) #define PAD_CFG1_TERM_POS 10 #define PAD_CFG1_TERM_MASK (0x0F << PAD_CFG1_TERM_POS) diff --git a/dts/bindings/cpu/intel,wildcat-lake.yaml b/dts/bindings/cpu/intel,wildcat-lake.yaml new file mode 100644 index 0000000000000..cd9eff03448f1 --- /dev/null +++ b/dts/bindings/cpu/intel,wildcat-lake.yaml @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Intel Corp. +# SPDX-License-Identifier: Apache-2.0 + +description: Intel Wildcat Lake CPU + +compatible: "intel,wildcat-lake" + +include: cpu.yaml diff --git a/dts/bindings/timer/intel,hpet.yaml b/dts/bindings/timer/intel,hpet.yaml index b293f2e7e482a..55a29e092a5fe 100644 --- a/dts/bindings/timer/intel,hpet.yaml +++ b/dts/bindings/timer/intel,hpet.yaml @@ -14,6 +14,10 @@ properties: interrupts: required: true + clock-frequency: + type: int + description: HPET timer clock frequency in Hz + no-legacy-irq: type: boolean description: Do not set legacy IRQ bit diff --git a/dts/x86/intel/wildcat_lake.dtsi b/dts/x86/intel/wildcat_lake.dtsi new file mode 100644 index 0000000000000..37125b5ce8c54 --- /dev/null +++ b/dts/x86/intel/wildcat_lake.dtsi @@ -0,0 +1,445 @@ +/* + * Copyright (c) 2025 Intel Corporation. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include "skeleton.dtsi" +#include +#include +#include +#include +#include "gpio_common.dtsi" + +/ { + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu: cpu@0 { + device_type = "cpu"; + compatible = "intel,wildcat-lake"; + d-cache-line-size = <64>; + reg = <0>; + clock-frequency = <2000000000>; + }; + + cpu@1 { + device_type = "cpu"; + compatible = "intel,wildcat-lake"; + d-cache-line-size = <64>; + reg = <1>; + }; + }; + + dram0: memory@0 { + device_type = "memory"; + reg = <0x0 DT_DRAM_SIZE>; + }; + + intc: ioapic@fec00000 { + compatible = "intel,ioapic"; + #address-cells = <1>; + #interrupt-cells = <3>; + reg = <0xfec00000 0x1000>; + interrupt-controller; + }; + + intc_loapic: loapic@fee00000 { + compatible = "intel,loapic"; + reg = <0xfee00000 0x1000>; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + }; + + acpi { + gpio_a: gpio_a { + acpi-hid = "INTC10EC"; + acpi-uid = "3"; + group-index = <0x02>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_b: gpio_b { + acpi-hid = "INTC10EC"; + acpi-uid = "5"; + group-index = <0x0>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_c: gpio_c { + acpi-hid = "INTC10EC"; + acpi-uid = "0"; + group-index = <0x01>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_d: gpio_d { + acpi-hid = "INTC10EC"; + acpi-uid = "5"; + group-index = <0x01>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_e: gpio_e { + acpi-hid = "INTC10EC"; + acpi-uid = "1"; + group-index = <0x01>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_f: gpio_f { + acpi-hid = "INTC10EC"; + acpi-uid = "1"; + group-index = <0x0>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_h: gpio_h { + acpi-hid = "INTC10EC"; + acpi-uid = "3"; + group-index = <0x01>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_s: gpio_s { + acpi-hid = "INTC10EC"; + acpi-uid = "4"; + group-index = <0x0>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + + gpio_v: gpio_v { + acpi-hid = "INTC10EC"; + acpi-uid = "0"; + group-index = <0x0>; + acpi-ginf-3-param; + int-stat-offset = <0x20>; + int-en-offset = <0x10>; + status = "disabled"; + }; + }; + + pcie0: pcie0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "pcie-controller"; + acpi-hid = "PNP0A08"; + ranges; + + smbus0: smbus0 { + compatible = "intel,pch-smbus"; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d22>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + uart0_dma: uart0_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + uart0: uart0 { + compatible = "ns16550"; + vendor-id = <0x8086>; + device-id = <0x4d25>; + clock-frequency = <1843200>; + current-speed = <115200>; + reg-shift = <2>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&uart0_dma 0>, <&uart0_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1_dma: uart1_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + uart1: uart1 { + compatible = "ns16550"; + vendor-id = <0x8086>; + device-id = <0x4d26>; + clock-frequency = <1843200>; + current-speed = <1152000>; + reg-shift = <2>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&uart1_dma 0>, <&uart1_dma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: uart2 { + compatible = "ns16550"; + vendor-id = <0x8086>; + device-id = <0x4d52>; + clock-frequency = <1843200>; + current-speed = <115200>; + reg-shift = <2>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + i2c0_dma: i2c0_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + i2c0: i2c0 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d78>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&i2c0_dma 0>; + status = "disabled"; + }; + + i2c1_dma: i2c1_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + i2c1: i2c1 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d79>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&i2c1_dma 0>; + status = "disabled"; + }; + + i2c2_dma: i2c2_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + i2c2: i2c2 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d7a>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&i2c2_dma 0>; + status = "disabled"; + }; + + i2c3_dma: i2c3_dma { + compatible = "intel,lpss"; + #dma-cells = <1>; + status = "disabled"; + }; + + i2c3: i2c3 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d7b>; + interrupts = ; + interrupt-parent = <&intc>; + dmas = <&i2c3_dma 0>; + status = "disabled"; + }; + + i2c4: i2c4 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d50>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + i2c5: i2c5 { + compatible = "snps,designware-i2c"; + clock-frequency = ; + #address-cells = <1>; + #size-cells = <0>; + vendor-id = <0x8086>; + device-id = <0x4d51>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + spi0: spi0 { + compatible = "intel,penwell-spi"; + vendor-id = <0x8086>; + device-id = <0x4d27>; + #address-cells = <1>; + #size-cells = <0>; + pw,cs-mode = <0>; + pw,cs-output = <0>; + pw,fifo-depth = <64>; + cs-gpios = <&gpio_e 17 GPIO_ACTIVE_LOW>; + clock-frequency = <100000000>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + spi1: spi1 { + compatible = "intel,penwell-spi"; + vendor-id = <0x8086>; + device-id = <0x4d30>; + #address-cells = <1>; + #size-cells = <0>; + pw,cs-mode = <0>; + pw,cs-output = <0>; + pw,fifo-depth = <64>; + cs-gpios = <&gpio_f 17 GPIO_ACTIVE_LOW>; + clock-frequency = <100000000>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + + spi2: spi2 { + compatible = "intel,penwell-spi"; + vendor-id = <0x8086>; + device-id = <0x4d46>; + #address-cells = <1>; + #size-cells = <0>; + pw,cs-mode = <0>; + pw,cs-output = <0>; + pw,fifo-depth = <64>; + cs-gpios = <&gpio_f 18 GPIO_ACTIVE_LOW>; + clock-frequency = <100000000>; + interrupts = ; + interrupt-parent = <&intc>; + status = "disabled"; + }; + }; + + soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges; + + vtd: vtd@fed91000 { + compatible = "intel,vt-d"; + reg = <0xfed91000 0x1000>; + status = "okay"; + }; + + uart_legacy: uart@3f8 { + compatible = "ns16550"; + reg = <0x000003f8 0x100>; + io-mapped; + clock-frequency = <1843200>; + interrupts = <4 IRQ_TYPE_LOWEST_EDGE_RISING 3>; + interrupt-parent = <&intc>; + reg-shift = <0>; + status = "disabled"; + }; + + tgpio: tgpio@fe001210 { + compatible = "intel,timeaware-gpio"; + reg = <0xfe001210 0x100>; + timer-clock = <19200000>; + max-pins = <2>; + status = "disabled"; + }; + + hpet: hpet@fed00000 { + compatible = "intel,hpet"; + reg = <0xfed00000 0x400>; + interrupts = <2 IRQ_TYPE_FIXED_EDGE_RISING 4>; + interrupt-parent = <&intc>; + clock-frequency = <19200000>; + status = "disabled"; + }; + + mfd: mfd@70 { + compatible = "motorola,mc146818-mfd"; + reg = <0x70 0x01 0x71 0x01 0x72 0x01 0x73 0x01>; + + rtc: counter: rtc { + compatible = "motorola,mc146818"; + interrupts = <8 IRQ_TYPE_LOWEST_EDGE_RISING 3>; + interrupt-parent = <&intc>; + alarms-count = <1>; + + status = "okay"; + }; + + bbram: bbram { + compatible = "motorola,mc146818-bbram"; + size = <241>; + status = "okay"; + }; + + status = "okay"; + }; + + tco_wdt: tco_wdt@400 { + compatible = "intel,tco-wdt"; + reg = <0x0400 0x20>; + status = "disabled"; + }; + + pwm0: pwm0@5d0000 { + compatible = "intel,blinky-pwm"; + reg = <0x5d0000 0x500>; + reg-upper32 = <0x40>; + reg-offset = <0x430>; + clock-frequency = <32768>; + max-pins = <1>; + #pwm-cells = <2>; + status = "disabled"; + }; + }; +}; diff --git a/soc/intel/wildcat_lake/CMakeLists.txt b/soc/intel/wildcat_lake/CMakeLists.txt new file mode 100644 index 0000000000000..a5996d4e90431 --- /dev/null +++ b/soc/intel/wildcat_lake/CMakeLists.txt @@ -0,0 +1,8 @@ +# SPDX-License-Identifier: Apache-2.0 + +zephyr_include_directories(.) + +zephyr_cc_option(-march=goldmont) +zephyr_library_sources_ifdef(CONFIG_GPIO ../common/soc_gpio.c) + +set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "") diff --git a/soc/intel/wildcat_lake/Kconfig b/soc/intel/wildcat_lake/Kconfig new file mode 100644 index 0000000000000..54b69e1004d4c --- /dev/null +++ b/soc/intel/wildcat_lake/Kconfig @@ -0,0 +1,11 @@ +# Copyright (c) 2025 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_WILDCAT_LAKE + select X86 + select X86_64 + select CPU_ATOM + select PCIE + select PCIE_MSI + select DYNAMIC_INTERRUPTS + select X86_MMU diff --git a/soc/intel/wildcat_lake/Kconfig.defconfig b/soc/intel/wildcat_lake/Kconfig.defconfig new file mode 100644 index 0000000000000..64f352013a49f --- /dev/null +++ b/soc/intel/wildcat_lake/Kconfig.defconfig @@ -0,0 +1,15 @@ +# Wildcat Lake SoC configuration options + +# Copyright (c) 2025 Intel Corporation +# SPDX-License-Identifier: Apache-2.0 + +if SOC_WILDCAT_LAKE + +config PCIE_MMIO_CFG + default y + +config X86_DYNAMIC_IRQ_STUBS + default 16 + depends on DYNAMIC_INTERRUPTS + +endif # SOC_WILDCAT_LAKE diff --git a/soc/intel/wildcat_lake/Kconfig.soc b/soc/intel/wildcat_lake/Kconfig.soc new file mode 100644 index 0000000000000..40f316dd70022 --- /dev/null +++ b/soc/intel/wildcat_lake/Kconfig.soc @@ -0,0 +1,8 @@ +# Copyright (c) 2025 Intel Corporation Inc. +# SPDX-License-Identifier: Apache-2.0 + +config SOC_WILDCAT_LAKE + bool + +config SOC + default "wildcat_lake" if SOC_WILDCAT_LAKE diff --git a/soc/intel/wildcat_lake/linker.ld b/soc/intel/wildcat_lake/linker.ld new file mode 100644 index 0000000000000..c1d3990d69230 --- /dev/null +++ b/soc/intel/wildcat_lake/linker.ld @@ -0,0 +1,12 @@ +/* + * Copyright (c) 2025 Intel Corp. + * SPDX-License-Identifier: Apache-2.0 + */ + +#include + +#ifdef CONFIG_X86_64 +#include +#else +#include +#endif /* CONFIG_X86_64 */ diff --git a/soc/intel/wildcat_lake/soc.h b/soc/intel/wildcat_lake/soc.h new file mode 100644 index 0000000000000..53de98f49d0cd --- /dev/null +++ b/soc/intel/wildcat_lake/soc.h @@ -0,0 +1,39 @@ +/* + * Copyright (c) 2025 Intel Corporation + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief Board configuration macros for the Wildcat Lake SoC + * + * This header file is used to specify and describe soc-level aspects for + * the 'Wildcat Lake' SoC. + */ + +#ifndef __SOC_H_ +#define __SOC_H_ + +#include + +#ifndef _ASMLANGUAGE +#include +#include +#endif + +#if DT_ANY_INST_HAS_PROP_STATUS_OKAY(acpi_hid) +#include "../common/soc_gpio.h" +#endif + +#ifdef CONFIG_GPIO_INTEL +#include "soc_gpio.h" +#endif + +#if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie) +#include +#define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console)) +#else +#define X86_SOC_EARLY_SERIAL_MMIO8_ADDR DT_REG_ADDR(DT_CHOSEN(zephyr_console)) +#endif + +#endif /* __SOC_H_ */ diff --git a/soc/intel/wildcat_lake/soc.yml b/soc/intel/wildcat_lake/soc.yml new file mode 100644 index 0000000000000..c2c892d1c58f4 --- /dev/null +++ b/soc/intel/wildcat_lake/soc.yml @@ -0,0 +1,4 @@ +vendor: intel +comment: "Intel Wildcat Lake SoC" +socs: +- name: wildcat_lake diff --git a/soc/intel/wildcat_lake/soc_gpio.h b/soc/intel/wildcat_lake/soc_gpio.h new file mode 100644 index 0000000000000..afa9a6c6f85bb --- /dev/null +++ b/soc/intel/wildcat_lake/soc_gpio.h @@ -0,0 +1,23 @@ +/* + * Copyright (c) 2025, Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/** + * @file + * @brief GPIO macros for the Wildcat Lake SoC + * + * This header file is used to specify the GPIO macros for + * the Wildcat Lake SoC. + */ + +#ifndef __SOC_GPIO_H_ +#define __SOC_GPIO_H_ + +#define GPIO_OWNERSHIP_BIT(raw_pin) (0x0) +#define GPIO_RAW_PIN(pin, pin_offset) pin +#define PAD_CFG0_PMODE_MASK (0x07 << 10) +#define PIN_OFFSET (0x10) + +#endif /* __SOC_GPIO_H_ */ diff --git a/tests/drivers/disk/disk_access/boards/intel_wcl_crb.conf b/tests/drivers/disk/disk_access/boards/intel_wcl_crb.conf new file mode 100644 index 0000000000000..109b049bcb4c7 --- /dev/null +++ b/tests/drivers/disk/disk_access/boards/intel_wcl_crb.conf @@ -0,0 +1,4 @@ +CONFIG_NVME=y +CONFIG_PCIE_MSI=y +CONFIG_PCIE_MSI_X=y +CONFIG_PCIE_MSI_MULTI_VECTOR=y diff --git a/tests/drivers/disk/disk_access/boards/intel_wcl_crb.overlay b/tests/drivers/disk/disk_access/boards/intel_wcl_crb.overlay new file mode 100644 index 0000000000000..decdd129cf054 --- /dev/null +++ b/tests/drivers/disk/disk_access/boards/intel_wcl_crb.overlay @@ -0,0 +1,25 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +/ { + pcie0 { + nvme0: nvme0 { + compatible = "nvme-controller"; + + vendor-id = <0x1344>; /* Subjected to change base on Hardware used */ + device-id = <0x5415>; /* Subjected to change base on Hardware used */ + + status = "okay"; + }; + }; + + ramdisk0 { + compatible = "zephyr,ram-disk"; + disk-name = "RAM"; + sector-size = <512>; + sector-count = <192>; + }; +}; diff --git a/tests/drivers/gpio/gpio_basic_api/boards/intel_wcl_crb.overlay b/tests/drivers/gpio/gpio_basic_api/boards/intel_wcl_crb.overlay new file mode 100644 index 0000000000000..b33707590b654 --- /dev/null +++ b/tests/drivers/gpio/gpio_basic_api/boards/intel_wcl_crb.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ +/* + * Connect loopback between GPP_B_22 and GPP_B_23. + * BIOS settings to mark these two pins as GPIO + * Under Intel Advanced Menu > PCH-IO Configuration + * Enable Timed GPIO0 > Disable + * Enable Timed GPIO1 > Disable + * ISH Configuration > GP_5 > Unchecked [ ] + * ISH Configuration > GP_6 > Unchecked [ ] + */ + +&gpio_b { + status = "okay"; +}; + +/ { + resources { + compatible = "test-gpio-basic-api"; + + out-gpios = <&gpio_b 22 0>; + in-gpios = <&gpio_b 23 0>; + }; +}; diff --git a/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.conf b/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.conf new file mode 100644 index 0000000000000..469a8f7c4451a --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.conf @@ -0,0 +1,4 @@ +CONFIG_SPI=y +CONFIG_SPI_ASYNC=n +CONFIG_GPIO=y +CONFIG_SPI_LOOPBACK_MODE_LOOP=y diff --git a/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.overlay b/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.overlay new file mode 100644 index 0000000000000..9069280f04581 --- /dev/null +++ b/tests/drivers/spi/spi_loopback/boards/intel_wcl_crb.overlay @@ -0,0 +1,27 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +&spi0 { + pw,cs-mode = <0>; + pw,cs-output = <0>; + status = "okay"; + + slow@0 { + compatible = "test-spi-loopback-slow"; + reg = <0>; + spi-max-frequency = <500000>; + }; + + fast@0 { + compatible = "test-spi-loopback-fast"; + reg = <0>; + spi-max-frequency = <16000000>; + }; +}; + +&gpio_e { + status = "okay"; +}; diff --git a/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.conf b/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.conf new file mode 100644 index 0000000000000..1104c4d739194 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.conf @@ -0,0 +1,2 @@ +CONFIG_UART_INTERRUPT_DRIVEN=y +CONFIG_TEST_USERSPACE=n diff --git a/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.overlay b/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.overlay new file mode 100644 index 0000000000000..d36db80aa1fc4 --- /dev/null +++ b/tests/drivers/uart/uart_async_api/boards/intel_wcl_crb.overlay @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2025 Intel Corporation + * + * SPDX-License-Identifier: Apache-2.0 + */ + +dut: &uart1 { + status = "okay"; +}; + +&uart1_dma { + status = "okay"; +};