From 4f3943d6246e3c80610591f922008f11bb208678 Mon Sep 17 00:00:00 2001 From: Luis Martinez Date: Tue, 2 Sep 2025 16:43:12 +0000 Subject: [PATCH] [topgen] Removing alert and cpu crashdumps and CSRs from rstmgr Removing the `alert_handler` and/or the `rv_core_ibex` from the top config should remove the corresponding crashdumps and CSRs. Signed-off-by: Luis Martinez --- hw/ip/sfi_ctrl/data/sfi_ctrl.hjson | 92 ++++++ hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl | 11 + .../rstmgr/data/rstmgr.tpldesc.hjson | 11 +- .../rstmgr/doc/theory_of_operation.md.tpl | 2 - hw/ip_templates/rstmgr/rstmgr.core.tpl | 4 +- hw/top_darjeeling/data/top_darjeeling.hjson | 3 +- .../ip_autogen/rstmgr/data/rstmgr.hjson | 1 + .../data/top_darjeeling_rstmgr.ipconfig.hjson | 3 +- .../ip_autogen/rstmgr/data/rstmgr.hjson | 1 + .../data/top_earlgrey_rstmgr.ipconfig.hjson | 3 +- .../autogen/top_englishbreakfast.gen.hjson | 24 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../dv/autogen/xbar_tgl_excl.cfg | 2 +- .../data/autogen/xbar_peri.gen.hjson | 2 +- .../ip/xbar_peri/dv/autogen/xbar_cover.cfg | 2 +- .../dv/autogen/xbar_env_pkg__params.sv | 2 +- .../ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv | 2 +- .../ip_autogen/rstmgr/data/rstmgr.hjson | 105 +------ ...top_englishbreakfast_rstmgr.ipconfig.hjson | 3 +- .../ip_autogen/rstmgr/doc/interfaces.md | 19 +- .../ip_autogen/rstmgr/doc/registers.md | 129 ++------- .../ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv | 110 +++----- .../ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv | 262 +++--------------- .../rtl/autogen/top_englishbreakfast.sv | 1 - .../rtl/autogen/top_englishbreakfast_pkg.sv | 2 +- .../sw/autogen/chip/top_englishbreakfast.rs | 2 +- .../sw/autogen/top_englishbreakfast.h | 2 +- .../sw/autogen/top_englishbreakfast_memory.h | 2 +- util/topgen.py | 9 +- 29 files changed, 257 insertions(+), 556 deletions(-) create mode 100644 hw/ip/sfi_ctrl/data/sfi_ctrl.hjson diff --git a/hw/ip/sfi_ctrl/data/sfi_ctrl.hjson b/hw/ip/sfi_ctrl/data/sfi_ctrl.hjson new file mode 100644 index 00000000000..a740a60277b --- /dev/null +++ b/hw/ip/sfi_ctrl/data/sfi_ctrl.hjson @@ -0,0 +1,92 @@ +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "sfi_ctrl", + human_name: "Secure Flash Interface Controller", + one_line_desc: "Interfaces and manages a secure flash module (SFM) for safe and secure storage of boot code, keys, credentials and other sensitive information", + one_paragraph_desc: ''' + //TODO: Write this. + ''' + + //TODO: Define this unique comportable IP identifier defined unders KNOWN_CIP_IDS in regtool + cip_id: "", + design_spec: "../doc", + dv_doc: "../doc/dv", + hw_checklist: " + //TODO: Check hw_checklist with someone + ", + sw_checklist: " + //TODO: Check sw_checklist with someone + ", + revisions: [ + { + version: "1.0", + life_stage: "L1", + design_stage: "D0", + verification_stage: "V0" + commit_id: " + //TODO: Will be filled with the first PR + " + } + ], + clocking: [ + { clock: "clk_i", reset: "rst_ni", primary: true }, + { clock: "clock_otp_i", reset: "rst_otp_ni" } + ], + bus_interfaces: [ + { protocol: "tlul", direction: "device", name: "core" }, + { protocol: "tlul", direction: "device", name: "prim", hier_path: "u_eflash.u_flash.u_reg_top"}, + { protocol: "tlul", direction: "device", name: "mem"} + ], + available_input_list: [ + { name: "tck", desc: "jtag_clock" }, + { name: "tms", desc: "jtag_tms" }, + { name: "tdi", desc: "jtag input" } + ], + available_output_list: [ + { name: "tdo", desc: "jtag output" } + ], + interrupt_list: [ + // The first two status interrupts assert by default, since the FIFO is empty. + // This is captured in the Hjson via the `default` key so that automatically generated tests can incorporate this information. + { name: "prog_empty", type: "status", desc: "Program FIFO empty", default: "1" }, + { name: "prog_lvl", type: "status", desc: "Program FIFO drained to level", default: "1" }, + { name: "rd_full", type: "status", desc: "Read FIFO full" }, + { name: "rd_lvl", type: "status", desc: "Read FIFO filled to level" }, + { name: "op_done", type: "event", desc: "Operation complete" }, + { name: "corr_err", type: "event", desc: "Correctable error encountered" } + ], + + alert_list: [ + + ], + + // Define flash_ctrl <-> flash_phy struct package + inter_signal_list: [ + + ], + + countermeasures: [ + + + ], + scan: "true", // Enable `scanmode_i` port + scan_en: "true", // Enable `scan_en_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + + param_list: [ + // The reg parameters can be modified directly through top_*.hjson. + // The template will automatically propagate the appropriate values. + + // Random netlist constants + ], + + features: [ + + ], + + regwidth: "32", + + registers: {} +} diff --git a/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl b/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl index 570729e6e80..1746c87a4c2 100644 --- a/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl +++ b/hw/ip_templates/rstmgr/data/rstmgr.hjson.tpl @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -167,18 +168,22 @@ { name: "RSTMGR.RESET_INFO.CLEAR", desc: "Clear information about the causes of a reset." } +% if with_alert_dump: { name: "RSTMGR.ALERT_INFO.CAPTURE", desc: "Capture alert crash dump information upon reset." } { name: "RSTMGR.ALERT_INFO.ENABLE", desc: "Enable capture of alert crash dump information." } +% endif +% if with_cpu_dump: { name: "RSTMGR.CPU_INFO.CAPTURE", desc: "Capture cpu crash dump information upon reset." } { name: "RSTMGR.CPU_INFO.ENABLE", desc: "Enable capture of cpu crash dump information." } +% endif { name: "RSTMGR.ALERT_HANDLER.RESET_STATUS", desc: "Inform alert handler about reset enable status for each reset." } @@ -226,6 +231,7 @@ ''' }, +% if with_alert_dump: { struct: "alert_crashdump", type: "uni", name: "alert_dump", @@ -236,6 +242,8 @@ ''' }, +% endif +% if with_cpu_dump: { struct: "cpu_crash_dump", type: "uni", name: "cpu_dump", @@ -246,6 +254,7 @@ ''' }, +% endif { struct: "mubi4", type: "uni", name: "sw_rst_req", @@ -342,6 +351,7 @@ }, % for dump_src in crash_dump_srcs: + % if (dump_src == 'alert' and with_alert_dump) or (dump_src == 'cpu' and with_cpu_dump): { name: "${dump_src.upper()}_REGWEN", desc: "${dump_src.capitalize()} write enable", swaccess: "rw0c", @@ -430,6 +440,7 @@ }, ] }, + % endif % endfor diff --git a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson index afd41afb322..fbf2c3dc032 100644 --- a/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson +++ b/hw/ip_templates/rstmgr/data/rstmgr.tpldesc.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { @@ -124,8 +125,14 @@ default: {} } { - name: "with_alert_handler" - desc: "Generate outputs for a rstmgr that would connect to an alert handler" + name: "with_alert_dump" + desc: "Generate inputs and CSRs to capture an alert dump." + type: "bool" + default: "1" + } + { + name: "with_cpu_dump" + desc: "Generate inputs and CSRs to capture a cpu dump." type: "bool" default: "1" } diff --git a/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl b/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl index 227073a287a..dacf6eab548 100644 --- a/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl +++ b/hw/ip_templates/rstmgr/doc/theory_of_operation.md.tpl @@ -134,13 +134,11 @@ The reset manager then checks as follows: - If all reset conditions are satisfied, wait for the reset release to gracefully complete the cycle. -% if with_alert_handler: <%text>### Reset Indications for Alert Handler The alert handler needs to know the status of the various reset domains in the system to avoid false alert indications due to the ping mechanism. To that end, the reset manager outputs a 4bit MuBi signal for each reset domain that indicates whether its reset is active. For more information on this mechanism, see [alert handler documentation](../../alert_handler/doc/theory_of_operation.md#low-power-management-of-alert-channels). -% endif <%text>## Design Details diff --git a/hw/ip_templates/rstmgr/rstmgr.core.tpl b/hw/ip_templates/rstmgr/rstmgr.core.tpl index 0839c5be515..d1e47c2243e 100644 --- a/hw/ip_templates/rstmgr/rstmgr.core.tpl +++ b/hw/ip_templates/rstmgr/rstmgr.core.tpl @@ -8,10 +8,12 @@ description: "Reset manager RTL" filesets: files_rtl: depend: -% if with_alert_handler: +% if with_alert_dump: - ${instance_vlnv("lowrisc:ip:alert_handler_pkg")} % endif +% if with_cpu_dump: - lowrisc:ip:rv_core_ibex_pkg +% endif - lowrisc:ip:tlul - lowrisc:prim:clock_mux2 - lowrisc:prim:esc diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson index 9fdeed0bbbc..64340c42218 100644 --- a/hw/top_darjeeling/data/top_darjeeling.hjson +++ b/hw/top_darjeeling/data/top_darjeeling.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -1230,8 +1231,6 @@ 'pwrmgr_aon.boot_status' : ['soc_dbg_ctrl.boot_status'], 'keymgr_dpe.rom_digest' : ['rom_ctrl0.keymgr_data', 'rom_ctrl1.keymgr_data'], - 'alert_handler.crashdump' : ['rstmgr_aon.alert_dump'], - // DMA LSIO triggers 'dma.lsio_trigger' : ['soc_proxy.dma_lsio_trigger'], 'i2c0.lsio_trigger' : ['soc_proxy.i2c_lsio_trigger'], diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson index f48fcba4734..a79ec3541f3 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/rstmgr.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson index 76482c25d4d..c26bf5585ff 100644 --- a/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson +++ b/hw/top_darjeeling/ip_autogen/rstmgr/data/top_darjeeling_rstmgr.ipconfig.hjson @@ -482,7 +482,8 @@ ] rst_ni: lc_io_div4 export_rsts: {} - with_alert_handler: true + with_alert_dump: true + with_cpu_dump: true topname: darjeeling uniquified_modules: {} module_instance_name: rstmgr diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson index 566645f471d..ab1ad28cf44 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/rstmgr.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 diff --git a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson index c2b47197aee..39e739b7cf3 100644 --- a/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson +++ b/hw/top_earlgrey/ip_autogen/rstmgr/data/top_earlgrey_rstmgr.ipconfig.hjson @@ -690,7 +690,8 @@ ] rst_ni: lc_io_div4 export_rsts: {} - with_alert_handler: true + with_alert_dump: true + with_cpu_dump: true topname: earlgrey uniquified_modules: {} module_instance_name: rstmgr diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson index f5d22de7446..6e79b9b6baf 100644 --- a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson +++ b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson @@ -1949,17 +1949,6 @@ top_signame: rstmgr_aon_rst_en index: -1 } - { - name: alert_dump - desc: Alert handler crash dump information. - struct: alert_crashdump - package: alert_handler_pkg - type: uni - act: rcv - width: 1 - inst_name: rstmgr_aon - index: -1 - } { name: cpu_dump desc: Main processing element crash dump information. @@ -5873,7 +5862,7 @@ { hart: 0x40410000 } - size_byte: 0x80 + size_byte: 0x40 } ] xbar: false @@ -10236,17 +10225,6 @@ top_signame: rstmgr_aon_rst_en index: -1 } - { - name: alert_dump - desc: Alert handler crash dump information. - struct: alert_crashdump - package: alert_handler_pkg - type: uni - act: rcv - width: 1 - inst_name: rstmgr_aon - index: -1 - } { name: cpu_dump desc: Main processing element crash dump information. diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv index 4067393df73..5aaf52ae0ce 100644 --- a/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv @@ -62,7 +62,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h40400000, 32'h4040007f} }}, '{"rstmgr_aon", '{ - '{32'h40410000, 32'h4041007f} + '{32'h40410000, 32'h4041003f} }}, '{"clkmgr_aon", '{ '{32'h40420000, 32'h4042007f} diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg b/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg index fdcaef860d8..c421a559eca 100644 --- a/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg @@ -80,7 +80,7 @@ -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[21:7] -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[29:23] -node tb.dut*.u_pwrmgr_aon tl_*i.a_address[31:31] --node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:7] +-node tb.dut*.u_rstmgr_aon tl_*i.a_address[15:6] -node tb.dut*.u_rstmgr_aon tl_*i.a_address[21:17] -node tb.dut*.u_rstmgr_aon tl_*i.a_address[29:23] -node tb.dut*.u_rstmgr_aon tl_*i.a_address[31:31] diff --git a/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson b/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson index 46ba5b06b05..e8faec95e86 100644 --- a/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson +++ b/hw/top_englishbreakfast/ip/xbar_peri/data/autogen/xbar_peri.gen.hjson @@ -259,7 +259,7 @@ { hart: 0x40410000 } - size_byte: 0x80 + size_byte: 0x40 } ] xbar: false diff --git a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg index 237fa015132..81948bfb7a9 100644 --- a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg +++ b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_cover.cfg @@ -46,7 +46,7 @@ -node tb.dut tl_pwrmgr_aon_o.a_address[21:7] -node tb.dut tl_pwrmgr_aon_o.a_address[29:23] -node tb.dut tl_pwrmgr_aon_o.a_address[31:31] --node tb.dut tl_rstmgr_aon_o.a_address[15:7] +-node tb.dut tl_rstmgr_aon_o.a_address[15:6] -node tb.dut tl_rstmgr_aon_o.a_address[21:17] -node tb.dut tl_rstmgr_aon_o.a_address[29:23] -node tb.dut tl_rstmgr_aon_o.a_address[31:31] diff --git a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv index 8d20c8b6438..9aab94f61f3 100644 --- a/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_englishbreakfast/ip/xbar_peri/dv/autogen/xbar_env_pkg__params.sv @@ -32,7 +32,7 @@ tl_device_t xbar_devices[$] = '{ '{32'h40400000, 32'h4040007f} }}, '{"rstmgr_aon", '{ - '{32'h40410000, 32'h4041007f} + '{32'h40410000, 32'h4041003f} }}, '{"clkmgr_aon", '{ '{32'h40420000, 32'h4042007f} diff --git a/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv b/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv index b5713396993..43281ca79a9 100644 --- a/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv +++ b/hw/top_englishbreakfast/ip/xbar_peri/rtl/autogen/tl_peri_pkg.sv @@ -27,7 +27,7 @@ package tl_peri_pkg; localparam logic [31:0] ADDR_MASK_RV_TIMER = 32'h 000001ff; localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_PWRMGR_AON = 32'h 0000007f; - localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_RSTMGR_AON = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_CLKMGR_AON = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_PINMUX_AON = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_AST = 32'h 000003ff; diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/rstmgr.hjson b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/rstmgr.hjson index a6134a68091..e6279668eb6 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/rstmgr.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/rstmgr.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -170,12 +171,6 @@ { name: "RSTMGR.RESET_INFO.CLEAR", desc: "Clear information about the causes of a reset." } - { name: "RSTMGR.ALERT_INFO.CAPTURE", - desc: "Capture alert crash dump information upon reset." - } - { name: "RSTMGR.ALERT_INFO.ENABLE", - desc: "Enable capture of alert crash dump information." - } { name: "RSTMGR.CPU_INFO.CAPTURE", desc: "Capture cpu crash dump information upon reset." } @@ -229,16 +224,6 @@ ''' }, - { struct: "alert_crashdump", - type: "uni", - name: "alert_dump", - act: "rcv", - package: "alert_handler_pkg", - desc: ''' - Alert handler crash dump information. - ''' - }, - { struct: "cpu_crash_dump", type: "uni", name: "cpu_dump", @@ -337,94 +322,6 @@ ] }, - { name: "ALERT_REGWEN", - desc: "Alert write enable", - swaccess: "rw0c", - hwaccess: "none", - fields: [ - { bits: "0", - name: "EN", - resval: "1" - desc: ''' - When 1, !!ALERT_INFO_CTRL can be modified. - ''' - }, - ] - } - - { name: "ALERT_INFO_CTRL", - desc: ''' - Alert info dump controls. - ''', - swaccess: "rw", - hwaccess: "hro", - sync: "clk_por_i", - regwen: "ALERT_REGWEN", - fields: [ - { bits: "0", - name: "EN", - hwaccess: "hrw", - desc: ''' - Enable alert dump to capture new information. - This field is automatically set to 0 upon system reset (even if rstmgr is not reset). - ''' - resval: "0" - }, - - { bits: "4+IdxWidth-1:4", - name: "INDEX", - desc: ''' - Controls which 32-bit value to read. - ''' - resval: "0" - }, - ] - }, - - { name: "ALERT_INFO_ATTR", - desc: ''' - Alert info dump attributes. - ''', - swaccess: "ro", - hwaccess: "hwo", - sync: "clk_por_i", - hwext: "true", - fields: [ - { bits: "IdxWidth-1:0", - name: "CNT_AVAIL", - swaccess: "ro", - hwaccess: "hwo", - desc: ''' - The number of 32-bit values contained in the alert info dump. - ''' - resval: "0", - tags: [// This field is tied to a design constant, thus the - // default value is never 0. Since there is not a way - // to express this behavior at the moment, exclude from automated checks. - "excl:CsrAllTests:CsrExclCheck"] - }, - ] - }, - - { name: "ALERT_INFO", - desc: ''' - Alert dump information prior to last reset. - Which value read is controlled by the !!ALERT_INFO_CTRL register. - ''', - swaccess: "ro", - hwaccess: "hwo", - sync: "clk_por_i", - hwext: "true", - fields: [ - { bits: "31:0", - name: "VALUE", - desc: ''' - The current 32-bit value of crash dump. - ''' - resval: "0", - }, - ] - }, { name: "CPU_REGWEN", desc: "Cpu write enable", swaccess: "rw0c", diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson index 2d8fba0d5c1..2fd67ddcdb1 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/data/top_englishbreakfast_rstmgr.ipconfig.hjson @@ -450,7 +450,8 @@ ] rst_ni: lc_io_div4 export_rsts: {} - with_alert_handler: false + with_alert_dump: false + with_cpu_dump: true topname: englishbreakfast uniquified_modules: {} module_instance_name: rstmgr diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/interfaces.md b/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/interfaces.md index 7dd92be3693..7e69224f26c 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/interfaces.md +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/interfaces.md @@ -21,16 +21,15 @@ Referring to the [Comportable guideline for peripheral device functionality](htt ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:------------|:-----------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------| -| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. | -| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. | -| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. | -| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. | -| alert_dump | alert_handler_pkg::alert_crashdump | uni | rcv | 1 | Alert handler crash dump information. | -| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. | -| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. | -| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:------------|:---------------------------------|:--------|:------|--------:|:-----------------------------------------------------------------------------------------------------------------------------| +| por_n | logic | uni | rcv | 2 | Root power on reset signals from ast. There is one root reset signal for each core power domain. | +| pwr | pwr_rst | req_rsp | rsp | 1 | Reset request signals from power manager. Power manager can request for specific domains of the lc/sys reset tree to assert. | +| resets | rstmgr_pkg::rstmgr_out | uni | req | 1 | Leaf resets fed to the system. | +| rst_en | rstmgr_pkg::rstmgr_rst_en | uni | req | 1 | Low-power-group outputs used by alert handler. | +| cpu_dump | rv_core_ibex_pkg::cpu_crash_dump | uni | rcv | 1 | Main processing element crash dump information. | +| sw_rst_req | prim_mubi_pkg::mubi4 | uni | req | 1 | Software requested system reset to pwrmgr. | +| tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Security Alerts diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/registers.md b/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/registers.md index a764b8e34f1..714675f9fa3 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/registers.md +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/doc/registers.md @@ -3,26 +3,22 @@ ## Summary -| Name | Offset | Length | Description | -|:---------------------------------------------|:---------|---------:|:-------------------------------------------------------------------| -| rstmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | -| rstmgr.[`RESET_REQ`](#reset_req) | 0x4 | 4 | Software requested system reset. | -| rstmgr.[`RESET_INFO`](#reset_info) | 0x8 | 4 | Device reset reason. | -| rstmgr.[`ALERT_REGWEN`](#alert_regwen) | 0xc | 4 | Alert write enable | -| rstmgr.[`ALERT_INFO_CTRL`](#alert_info_ctrl) | 0x10 | 4 | Alert info dump controls. | -| rstmgr.[`ALERT_INFO_ATTR`](#alert_info_attr) | 0x14 | 4 | Alert info dump attributes. | -| rstmgr.[`ALERT_INFO`](#alert_info) | 0x18 | 4 | Alert dump information prior to last reset. | -| rstmgr.[`CPU_REGWEN`](#cpu_regwen) | 0x1c | 4 | Cpu write enable | -| rstmgr.[`CPU_INFO_CTRL`](#cpu_info_ctrl) | 0x20 | 4 | Cpu info dump controls. | -| rstmgr.[`CPU_INFO_ATTR`](#cpu_info_attr) | 0x24 | 4 | Cpu info dump attributes. | -| rstmgr.[`CPU_INFO`](#cpu_info) | 0x28 | 4 | Cpu dump information prior to last reset. | -| rstmgr.[`SW_RST_REGWEN_0`](#sw_rst_regwen) | 0x2c | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_1`](#sw_rst_regwen) | 0x30 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_REGWEN_2`](#sw_rst_regwen) | 0x34 | 4 | Register write enable for software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x38 | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x3c | 4 | Software controllable resets. | -| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x40 | 4 | Software controllable resets. | -| rstmgr.[`ERR_CODE`](#err_code) | 0x44 | 4 | A bit vector of all the errors that have occurred in reset manager | +| Name | Offset | Length | Description | +|:-------------------------------------------|:---------|---------:|:-------------------------------------------------------------------| +| rstmgr.[`ALERT_TEST`](#alert_test) | 0x0 | 4 | Alert Test Register | +| rstmgr.[`RESET_REQ`](#reset_req) | 0x4 | 4 | Software requested system reset. | +| rstmgr.[`RESET_INFO`](#reset_info) | 0x8 | 4 | Device reset reason. | +| rstmgr.[`CPU_REGWEN`](#cpu_regwen) | 0xc | 4 | Cpu write enable | +| rstmgr.[`CPU_INFO_CTRL`](#cpu_info_ctrl) | 0x10 | 4 | Cpu info dump controls. | +| rstmgr.[`CPU_INFO_ATTR`](#cpu_info_attr) | 0x14 | 4 | Cpu info dump attributes. | +| rstmgr.[`CPU_INFO`](#cpu_info) | 0x18 | 4 | Cpu dump information prior to last reset. | +| rstmgr.[`SW_RST_REGWEN_0`](#sw_rst_regwen) | 0x1c | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_1`](#sw_rst_regwen) | 0x20 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_REGWEN_2`](#sw_rst_regwen) | 0x24 | 4 | Register write enable for software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_0`](#sw_rst_ctrl_n) | 0x28 | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_1`](#sw_rst_ctrl_n) | 0x2c | 4 | Software controllable resets. | +| rstmgr.[`SW_RST_CTRL_N_2`](#sw_rst_ctrl_n) | 0x30 | 4 | Software controllable resets. | +| rstmgr.[`ERR_CODE`](#err_code) | 0x34 | 4 | A bit vector of all the errors that have occurred in reset manager | ## ALERT_TEST Alert Test Register @@ -96,80 +92,9 @@ Indicates when a device has reset due low power exit. ### RESET_INFO . POR Indicates when a device has reset due to power up. -## ALERT_REGWEN -Alert write enable -- Offset: `0xc` -- Reset default: `0x1` -- Reset mask: `0x1` - -### Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:---------------------------------------------------------------| -| 31:1 | | | | Reserved | -| 0 | rw0c | 0x1 | EN | When 1, [`ALERT_INFO_CTRL`](#alert_info_ctrl) can be modified. | - -## ALERT_INFO_CTRL -Alert info dump controls. -- Offset: `0x10` -- Reset default: `0x0` -- Reset mask: `0xf1` -- Register enable: [`ALERT_REGWEN`](#alert_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "EN", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 3}, {"name": "INDEX", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:------------------------------------------------------------------------------------------------------------------------------------| -| 31:8 | | | | Reserved | -| 7:4 | rw | 0x0 | INDEX | Controls which 32-bit value to read. | -| 3:1 | | | | Reserved | -| 0 | rw | 0x0 | EN | Enable alert dump to capture new information. This field is automatically set to 0 upon system reset (even if rstmgr is not reset). | - -## ALERT_INFO_ATTR -Alert info dump attributes. -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0xf` - -### Fields - -```wavejson -{"reg": [{"name": "CNT_AVAIL", "bits": 4, "attr": ["ro"], "rotate": -90}, {"bits": 28}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:----------|:--------------------------------------------------------------| -| 31:4 | | | | Reserved | -| 3:0 | ro | 0x0 | CNT_AVAIL | The number of 32-bit values contained in the alert info dump. | - -## ALERT_INFO - Alert dump information prior to last reset. - Which value read is controlled by the [`ALERT_INFO_CTRL`](#alert_info_ctrl) register. -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0xffffffff` - -### Fields - -```wavejson -{"reg": [{"name": "VALUE", "bits": 32, "attr": ["ro"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | Description | -|:------:|:------:|:-------:|:-------|:----------------------------------------| -| 31:0 | ro | 0x0 | VALUE | The current 32-bit value of crash dump. | - ## CPU_REGWEN Cpu write enable -- Offset: `0x1c` +- Offset: `0xc` - Reset default: `0x1` - Reset mask: `0x1` @@ -186,7 +111,7 @@ Cpu write enable ## CPU_INFO_CTRL Cpu info dump controls. -- Offset: `0x20` +- Offset: `0x10` - Reset default: `0x0` - Reset mask: `0xf1` - Register enable: [`CPU_REGWEN`](#cpu_regwen) @@ -206,7 +131,7 @@ Cpu info dump controls. ## CPU_INFO_ATTR Cpu info dump attributes. -- Offset: `0x24` +- Offset: `0x14` - Reset default: `0x0` - Reset mask: `0xf` @@ -224,7 +149,7 @@ Cpu info dump attributes. ## CPU_INFO Cpu dump information prior to last reset. Which value read is controlled by the [`CPU_INFO_CTRL`](#cpu_info_ctrl) register. -- Offset: `0x28` +- Offset: `0x18` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -249,9 +174,9 @@ When a particular bit value is 1, the corresponding value in [`SW_RST_CTRL_N`](# | Name | Offset | |:----------------|:---------| -| SW_RST_REGWEN_0 | 0x2c | -| SW_RST_REGWEN_1 | 0x30 | -| SW_RST_REGWEN_2 | 0x34 | +| SW_RST_REGWEN_0 | 0x1c | +| SW_RST_REGWEN_1 | 0x20 | +| SW_RST_REGWEN_2 | 0x24 | ### Fields @@ -277,9 +202,9 @@ When a particular bit value is 1, the corresponding module is not held in reset. | Name | Offset | |:----------------|:---------| -| SW_RST_CTRL_N_0 | 0x38 | -| SW_RST_CTRL_N_1 | 0x3c | -| SW_RST_CTRL_N_2 | 0x40 | +| SW_RST_CTRL_N_0 | 0x28 | +| SW_RST_CTRL_N_1 | 0x2c | +| SW_RST_CTRL_N_2 | 0x30 | ### Fields @@ -295,7 +220,7 @@ When a particular bit value is 1, the corresponding module is not held in reset. ## ERR_CODE A bit vector of all the errors that have occurred in reset manager -- Offset: `0x44` +- Offset: `0x34` - Reset default: `0x0` - Reset mask: `0x7` diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv b/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv index d92a33628dc..7f2e5077a03 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_pkg.sv @@ -15,10 +15,10 @@ package rstmgr_reg_pkg; parameter int NumAlerts = 2; // Address widths within the block - parameter int BlockAw = 7; + parameter int BlockAw = 6; // Number of registers for every interface - parameter int NumRegs = 18; + parameter int NumRegs = 14; // Alert indices typedef enum int { @@ -54,15 +54,6 @@ package rstmgr_reg_pkg; } sw_reset; } rstmgr_reg2hw_reset_info_reg_t; - typedef struct packed { - struct packed { - logic [3:0] q; - } index; - struct packed { - logic q; - } en; - } rstmgr_reg2hw_alert_info_ctrl_reg_t; - typedef struct packed { struct packed { logic [3:0] q; @@ -108,21 +99,6 @@ package rstmgr_reg_pkg; } low_power_exit; } rstmgr_hw2reg_reset_info_reg_t; - typedef struct packed { - struct packed { - logic d; - logic de; - } en; - } rstmgr_hw2reg_alert_info_ctrl_reg_t; - - typedef struct packed { - logic [3:0] d; - } rstmgr_hw2reg_alert_info_attr_reg_t; - - typedef struct packed { - logic [31:0] d; - } rstmgr_hw2reg_alert_info_reg_t; - typedef struct packed { struct packed { logic d; @@ -155,10 +131,9 @@ package rstmgr_reg_pkg; // Register -> HW type typedef struct packed { - rstmgr_reg2hw_alert_test_reg_t alert_test; // [28:25] - rstmgr_reg2hw_reset_req_reg_t reset_req; // [24:21] - rstmgr_reg2hw_reset_info_reg_t reset_info; // [20:16] - rstmgr_reg2hw_alert_info_ctrl_reg_t alert_info_ctrl; // [15:11] + rstmgr_reg2hw_alert_test_reg_t alert_test; // [23:20] + rstmgr_reg2hw_reset_req_reg_t reset_req; // [19:16] + rstmgr_reg2hw_reset_info_reg_t reset_info; // [15:11] rstmgr_reg2hw_cpu_info_ctrl_reg_t cpu_info_ctrl; // [10:6] rstmgr_reg2hw_sw_rst_ctrl_n_mreg_t [2:0] sw_rst_ctrl_n; // [5:3] rstmgr_reg2hw_err_code_reg_t err_code; // [2:0] @@ -166,11 +141,8 @@ package rstmgr_reg_pkg; // HW -> register type typedef struct packed { - rstmgr_hw2reg_reset_req_reg_t reset_req; // [95:91] - rstmgr_hw2reg_reset_info_reg_t reset_info; // [90:82] - rstmgr_hw2reg_alert_info_ctrl_reg_t alert_info_ctrl; // [81:80] - rstmgr_hw2reg_alert_info_attr_reg_t alert_info_attr; // [79:76] - rstmgr_hw2reg_alert_info_reg_t alert_info; // [75:44] + rstmgr_hw2reg_reset_req_reg_t reset_req; // [57:53] + rstmgr_hw2reg_reset_info_reg_t reset_info; // [52:44] rstmgr_hw2reg_cpu_info_ctrl_reg_t cpu_info_ctrl; // [43:42] rstmgr_hw2reg_cpu_info_attr_reg_t cpu_info_attr; // [41:38] rstmgr_hw2reg_cpu_info_reg_t cpu_info; // [37:6] @@ -178,33 +150,25 @@ package rstmgr_reg_pkg; } rstmgr_hw2reg_t; // Register offsets - parameter logic [BlockAw-1:0] RSTMGR_ALERT_TEST_OFFSET = 7'h 0; - parameter logic [BlockAw-1:0] RSTMGR_RESET_REQ_OFFSET = 7'h 4; - parameter logic [BlockAw-1:0] RSTMGR_RESET_INFO_OFFSET = 7'h 8; - parameter logic [BlockAw-1:0] RSTMGR_ALERT_REGWEN_OFFSET = 7'h c; - parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_CTRL_OFFSET = 7'h 10; - parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_ATTR_OFFSET = 7'h 14; - parameter logic [BlockAw-1:0] RSTMGR_ALERT_INFO_OFFSET = 7'h 18; - parameter logic [BlockAw-1:0] RSTMGR_CPU_REGWEN_OFFSET = 7'h 1c; - parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 7'h 20; - parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 7'h 24; - parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_OFFSET = 7'h 28; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_0_OFFSET = 7'h 2c; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_1_OFFSET = 7'h 30; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_2_OFFSET = 7'h 34; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 7'h 38; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 7'h 3c; - parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 7'h 40; - parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] RSTMGR_ALERT_TEST_OFFSET = 6'h 0; + parameter logic [BlockAw-1:0] RSTMGR_RESET_REQ_OFFSET = 6'h 4; + parameter logic [BlockAw-1:0] RSTMGR_RESET_INFO_OFFSET = 6'h 8; + parameter logic [BlockAw-1:0] RSTMGR_CPU_REGWEN_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_CTRL_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_ATTR_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] RSTMGR_CPU_INFO_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_0_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_1_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_REGWEN_2_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_0_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_1_OFFSET = 6'h 2c; + parameter logic [BlockAw-1:0] RSTMGR_SW_RST_CTRL_N_2_OFFSET = 6'h 30; + parameter logic [BlockAw-1:0] RSTMGR_ERR_CODE_OFFSET = 6'h 34; // Reset values for hwext registers and their fields parameter logic [1:0] RSTMGR_ALERT_TEST_RESVAL = 2'h 0; parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_FAULT_RESVAL = 1'h 0; parameter logic [0:0] RSTMGR_ALERT_TEST_FATAL_CNSTY_FAULT_RESVAL = 1'h 0; - parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_RESVAL = 4'h 0; - parameter logic [3:0] RSTMGR_ALERT_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; - parameter logic [31:0] RSTMGR_ALERT_INFO_RESVAL = 32'h 0; - parameter logic [31:0] RSTMGR_ALERT_INFO_VALUE_RESVAL = 32'h 0; parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_RESVAL = 4'h 0; parameter logic [3:0] RSTMGR_CPU_INFO_ATTR_CNT_AVAIL_RESVAL = 4'h 0; parameter logic [31:0] RSTMGR_CPU_INFO_RESVAL = 32'h 0; @@ -215,10 +179,6 @@ package rstmgr_reg_pkg; RSTMGR_ALERT_TEST, RSTMGR_RESET_REQ, RSTMGR_RESET_INFO, - RSTMGR_ALERT_REGWEN, - RSTMGR_ALERT_INFO_CTRL, - RSTMGR_ALERT_INFO_ATTR, - RSTMGR_ALERT_INFO, RSTMGR_CPU_REGWEN, RSTMGR_CPU_INFO_CTRL, RSTMGR_CPU_INFO_ATTR, @@ -233,25 +193,21 @@ package rstmgr_reg_pkg; } rstmgr_id_e; // Register width information to check illegal writes - parameter logic [3:0] RSTMGR_PERMIT [18] = '{ + parameter logic [3:0] RSTMGR_PERMIT [14] = '{ 4'b 0001, // index[ 0] RSTMGR_ALERT_TEST 4'b 0001, // index[ 1] RSTMGR_RESET_REQ 4'b 0001, // index[ 2] RSTMGR_RESET_INFO - 4'b 0001, // index[ 3] RSTMGR_ALERT_REGWEN - 4'b 0001, // index[ 4] RSTMGR_ALERT_INFO_CTRL - 4'b 0001, // index[ 5] RSTMGR_ALERT_INFO_ATTR - 4'b 1111, // index[ 6] RSTMGR_ALERT_INFO - 4'b 0001, // index[ 7] RSTMGR_CPU_REGWEN - 4'b 0001, // index[ 8] RSTMGR_CPU_INFO_CTRL - 4'b 0001, // index[ 9] RSTMGR_CPU_INFO_ATTR - 4'b 1111, // index[10] RSTMGR_CPU_INFO - 4'b 0001, // index[11] RSTMGR_SW_RST_REGWEN_0 - 4'b 0001, // index[12] RSTMGR_SW_RST_REGWEN_1 - 4'b 0001, // index[13] RSTMGR_SW_RST_REGWEN_2 - 4'b 0001, // index[14] RSTMGR_SW_RST_CTRL_N_0 - 4'b 0001, // index[15] RSTMGR_SW_RST_CTRL_N_1 - 4'b 0001, // index[16] RSTMGR_SW_RST_CTRL_N_2 - 4'b 0001 // index[17] RSTMGR_ERR_CODE + 4'b 0001, // index[ 3] RSTMGR_CPU_REGWEN + 4'b 0001, // index[ 4] RSTMGR_CPU_INFO_CTRL + 4'b 0001, // index[ 5] RSTMGR_CPU_INFO_ATTR + 4'b 1111, // index[ 6] RSTMGR_CPU_INFO + 4'b 0001, // index[ 7] RSTMGR_SW_RST_REGWEN_0 + 4'b 0001, // index[ 8] RSTMGR_SW_RST_REGWEN_1 + 4'b 0001, // index[ 9] RSTMGR_SW_RST_REGWEN_2 + 4'b 0001, // index[10] RSTMGR_SW_RST_CTRL_N_0 + 4'b 0001, // index[11] RSTMGR_SW_RST_CTRL_N_1 + 4'b 0001, // index[12] RSTMGR_SW_RST_CTRL_N_2 + 4'b 0001 // index[13] RSTMGR_ERR_CODE }; endpackage diff --git a/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv b/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv index e59e44575d0..1c2fbc2849f 100644 --- a/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv +++ b/hw/top_englishbreakfast/ip_autogen/rstmgr/rtl/rstmgr_reg_top.sv @@ -23,7 +23,7 @@ module rstmgr_reg_top ( import rstmgr_reg_pkg::* ; - localparam int AW = 7; + localparam int AW = 6; localparam int DW = 32; localparam int DBW = DW/8; // Byte Width @@ -54,9 +54,9 @@ module rstmgr_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [17:0] reg_we_check; + logic [13:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(18) + .OneHotWidth(14) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -138,18 +138,6 @@ module rstmgr_reg_top ( logic reset_info_sw_reset_wd; logic [3:0] reset_info_hw_req_qs; logic [3:0] reset_info_hw_req_wd; - logic alert_regwen_we; - logic alert_regwen_qs; - logic alert_regwen_wd; - logic alert_info_ctrl_we; - logic alert_info_ctrl_en_qs; - logic alert_info_ctrl_en_wd; - logic [3:0] alert_info_ctrl_index_qs; - logic [3:0] alert_info_ctrl_index_wd; - logic alert_info_attr_re; - logic [3:0] alert_info_attr_qs; - logic alert_info_re; - logic [31:0] alert_info_qs; logic cpu_regwen_we; logic cpu_regwen_qs; logic cpu_regwen_wd; @@ -366,127 +354,6 @@ module rstmgr_reg_top ( ); - // R[alert_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_alert_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (alert_regwen_we), - .wd (alert_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (alert_regwen_qs) - ); - - - // R[alert_info_ctrl]: V(False) - // Create REGWEN-gated WE signal - logic alert_info_ctrl_gated_we; - assign alert_info_ctrl_gated_we = alert_info_ctrl_we & alert_regwen_qs; - // F[en]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_alert_info_ctrl_en ( - // sync clock and reset required for this register - .clk_i (clk_por_i), - .rst_ni (rst_por_ni), - - // from register interface - .we (alert_info_ctrl_gated_we), - .wd (alert_info_ctrl_en_wd), - - // from internal hardware - .de (hw2reg.alert_info_ctrl.en.de), - .d (hw2reg.alert_info_ctrl.en.d), - - // to internal hardware - .qe (), - .q (reg2hw.alert_info_ctrl.en.q), - .ds (), - - // to register interface (read) - .qs (alert_info_ctrl_en_qs) - ); - - // F[index]: 7:4 - prim_subreg #( - .DW (4), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (4'h0), - .Mubi (1'b0) - ) u_alert_info_ctrl_index ( - // sync clock and reset required for this register - .clk_i (clk_por_i), - .rst_ni (rst_por_ni), - - // from register interface - .we (alert_info_ctrl_gated_we), - .wd (alert_info_ctrl_index_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.alert_info_ctrl.index.q), - .ds (), - - // to register interface (read) - .qs (alert_info_ctrl_index_qs) - ); - - - // R[alert_info_attr]: V(True) - prim_subreg_ext #( - .DW (4) - ) u_alert_info_attr ( - .re (alert_info_attr_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.alert_info_attr.d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (alert_info_attr_qs) - ); - - - // R[alert_info]: V(True) - prim_subreg_ext #( - .DW (32) - ) u_alert_info ( - .re (alert_info_re), - .we (1'b0), - .wd ('0), - .d (hw2reg.alert_info.d), - .qre (), - .qe (), - .q (), - .ds (), - .qs (alert_info_qs) - ); - - // R[cpu_regwen]: V(False) prim_subreg #( .DW (1), @@ -875,26 +742,22 @@ module rstmgr_reg_top ( - logic [17:0] addr_hit; + logic [13:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == RSTMGR_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == RSTMGR_RESET_REQ_OFFSET); addr_hit[ 2] = (reg_addr == RSTMGR_RESET_INFO_OFFSET); - addr_hit[ 3] = (reg_addr == RSTMGR_ALERT_REGWEN_OFFSET); - addr_hit[ 4] = (reg_addr == RSTMGR_ALERT_INFO_CTRL_OFFSET); - addr_hit[ 5] = (reg_addr == RSTMGR_ALERT_INFO_ATTR_OFFSET); - addr_hit[ 6] = (reg_addr == RSTMGR_ALERT_INFO_OFFSET); - addr_hit[ 7] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET); - addr_hit[ 8] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET); - addr_hit[ 9] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET); - addr_hit[10] = (reg_addr == RSTMGR_CPU_INFO_OFFSET); - addr_hit[11] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET); - addr_hit[12] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET); - addr_hit[13] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET); - addr_hit[14] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); - addr_hit[15] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); - addr_hit[16] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); - addr_hit[17] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); + addr_hit[ 3] = (reg_addr == RSTMGR_CPU_REGWEN_OFFSET); + addr_hit[ 4] = (reg_addr == RSTMGR_CPU_INFO_CTRL_OFFSET); + addr_hit[ 5] = (reg_addr == RSTMGR_CPU_INFO_ATTR_OFFSET); + addr_hit[ 6] = (reg_addr == RSTMGR_CPU_INFO_OFFSET); + addr_hit[ 7] = (reg_addr == RSTMGR_SW_RST_REGWEN_0_OFFSET); + addr_hit[ 8] = (reg_addr == RSTMGR_SW_RST_REGWEN_1_OFFSET); + addr_hit[ 9] = (reg_addr == RSTMGR_SW_RST_REGWEN_2_OFFSET); + addr_hit[10] = (reg_addr == RSTMGR_SW_RST_CTRL_N_0_OFFSET); + addr_hit[11] = (reg_addr == RSTMGR_SW_RST_CTRL_N_1_OFFSET); + addr_hit[12] = (reg_addr == RSTMGR_SW_RST_CTRL_N_2_OFFSET); + addr_hit[13] = (reg_addr == RSTMGR_ERR_CODE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -915,11 +778,7 @@ module rstmgr_reg_top ( (addr_hit[10] & (|(RSTMGR_PERMIT[10] & ~reg_be))) | (addr_hit[11] & (|(RSTMGR_PERMIT[11] & ~reg_be))) | (addr_hit[12] & (|(RSTMGR_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(RSTMGR_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(RSTMGR_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(RSTMGR_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(RSTMGR_PERMIT[17] & ~reg_be))))); + (addr_hit[13] & (|(RSTMGR_PERMIT[13] & ~reg_be))))); end // Generate write-enables @@ -940,42 +799,32 @@ module rstmgr_reg_top ( assign reset_info_sw_reset_wd = reg_wdata[2]; assign reset_info_hw_req_wd = reg_wdata[6:3]; - assign alert_regwen_we = addr_hit[3] & reg_we & !reg_error; - - assign alert_regwen_wd = reg_wdata[0]; - assign alert_info_ctrl_we = addr_hit[4] & reg_we & !reg_error; - - assign alert_info_ctrl_en_wd = reg_wdata[0]; - - assign alert_info_ctrl_index_wd = reg_wdata[7:4]; - assign alert_info_attr_re = addr_hit[5] & reg_re & !reg_error; - assign alert_info_re = addr_hit[6] & reg_re & !reg_error; - assign cpu_regwen_we = addr_hit[7] & reg_we & !reg_error; + assign cpu_regwen_we = addr_hit[3] & reg_we & !reg_error; assign cpu_regwen_wd = reg_wdata[0]; - assign cpu_info_ctrl_we = addr_hit[8] & reg_we & !reg_error; + assign cpu_info_ctrl_we = addr_hit[4] & reg_we & !reg_error; assign cpu_info_ctrl_en_wd = reg_wdata[0]; assign cpu_info_ctrl_index_wd = reg_wdata[7:4]; - assign cpu_info_attr_re = addr_hit[9] & reg_re & !reg_error; - assign cpu_info_re = addr_hit[10] & reg_re & !reg_error; - assign sw_rst_regwen_0_we = addr_hit[11] & reg_we & !reg_error; + assign cpu_info_attr_re = addr_hit[5] & reg_re & !reg_error; + assign cpu_info_re = addr_hit[6] & reg_re & !reg_error; + assign sw_rst_regwen_0_we = addr_hit[7] & reg_we & !reg_error; assign sw_rst_regwen_0_wd = reg_wdata[0]; - assign sw_rst_regwen_1_we = addr_hit[12] & reg_we & !reg_error; + assign sw_rst_regwen_1_we = addr_hit[8] & reg_we & !reg_error; assign sw_rst_regwen_1_wd = reg_wdata[0]; - assign sw_rst_regwen_2_we = addr_hit[13] & reg_we & !reg_error; + assign sw_rst_regwen_2_we = addr_hit[9] & reg_we & !reg_error; assign sw_rst_regwen_2_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_0_we = addr_hit[14] & reg_we & !reg_error; + assign sw_rst_ctrl_n_0_we = addr_hit[10] & reg_we & !reg_error; assign sw_rst_ctrl_n_0_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_1_we = addr_hit[15] & reg_we & !reg_error; + assign sw_rst_ctrl_n_1_we = addr_hit[11] & reg_we & !reg_error; assign sw_rst_ctrl_n_1_wd = reg_wdata[0]; - assign sw_rst_ctrl_n_2_we = addr_hit[16] & reg_we & !reg_error; + assign sw_rst_ctrl_n_2_we = addr_hit[12] & reg_we & !reg_error; assign sw_rst_ctrl_n_2_wd = reg_wdata[0]; @@ -984,21 +833,17 @@ module rstmgr_reg_top ( reg_we_check[0] = alert_test_we; reg_we_check[1] = reset_req_we; reg_we_check[2] = reset_info_we; - reg_we_check[3] = alert_regwen_we; - reg_we_check[4] = alert_info_ctrl_gated_we; + reg_we_check[3] = cpu_regwen_we; + reg_we_check[4] = cpu_info_ctrl_gated_we; reg_we_check[5] = 1'b0; reg_we_check[6] = 1'b0; - reg_we_check[7] = cpu_regwen_we; - reg_we_check[8] = cpu_info_ctrl_gated_we; - reg_we_check[9] = 1'b0; - reg_we_check[10] = 1'b0; - reg_we_check[11] = sw_rst_regwen_0_we; - reg_we_check[12] = sw_rst_regwen_1_we; - reg_we_check[13] = sw_rst_regwen_2_we; - reg_we_check[14] = sw_rst_ctrl_n_0_gated_we; - reg_we_check[15] = sw_rst_ctrl_n_1_gated_we; - reg_we_check[16] = sw_rst_ctrl_n_2_gated_we; - reg_we_check[17] = 1'b0; + reg_we_check[7] = sw_rst_regwen_0_we; + reg_we_check[8] = sw_rst_regwen_1_we; + reg_we_check[9] = sw_rst_regwen_2_we; + reg_we_check[10] = sw_rst_ctrl_n_0_gated_we; + reg_we_check[11] = sw_rst_ctrl_n_1_gated_we; + reg_we_check[12] = sw_rst_ctrl_n_2_gated_we; + reg_we_check[13] = 1'b0; end // Read data return @@ -1022,64 +867,47 @@ module rstmgr_reg_top ( end addr_hit[3]: begin - reg_rdata_next[0] = alert_regwen_qs; - end - - addr_hit[4]: begin - reg_rdata_next[0] = alert_info_ctrl_en_qs; - reg_rdata_next[7:4] = alert_info_ctrl_index_qs; - end - - addr_hit[5]: begin - reg_rdata_next[3:0] = alert_info_attr_qs; - end - - addr_hit[6]: begin - reg_rdata_next[31:0] = alert_info_qs; - end - - addr_hit[7]: begin reg_rdata_next[0] = cpu_regwen_qs; end - addr_hit[8]: begin + addr_hit[4]: begin reg_rdata_next[0] = cpu_info_ctrl_en_qs; reg_rdata_next[7:4] = cpu_info_ctrl_index_qs; end - addr_hit[9]: begin + addr_hit[5]: begin reg_rdata_next[3:0] = cpu_info_attr_qs; end - addr_hit[10]: begin + addr_hit[6]: begin reg_rdata_next[31:0] = cpu_info_qs; end - addr_hit[11]: begin + addr_hit[7]: begin reg_rdata_next[0] = sw_rst_regwen_0_qs; end - addr_hit[12]: begin + addr_hit[8]: begin reg_rdata_next[0] = sw_rst_regwen_1_qs; end - addr_hit[13]: begin + addr_hit[9]: begin reg_rdata_next[0] = sw_rst_regwen_2_qs; end - addr_hit[14]: begin + addr_hit[10]: begin reg_rdata_next[0] = sw_rst_ctrl_n_0_qs; end - addr_hit[15]: begin + addr_hit[11]: begin reg_rdata_next[0] = sw_rst_ctrl_n_1_qs; end - addr_hit[16]: begin + addr_hit[12]: begin reg_rdata_next[0] = sw_rst_ctrl_n_2_qs; end - addr_hit[17]: begin + addr_hit[13]: begin reg_rdata_next[0] = err_code_reg_intg_err_qs; reg_rdata_next[1] = err_code_reset_consistency_err_qs; reg_rdata_next[2] = err_code_fsm_err_qs; diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv index fbbd927825b..62ce5dbd5bf 100644 --- a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv +++ b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv @@ -903,7 +903,6 @@ module top_englishbreakfast #( .pwr_o(pwrmgr_aon_pwr_rst_rsp), .resets_o(rstmgr_aon_resets), .rst_en_o(rstmgr_aon_rst_en), - .alert_dump_i(alert_handler_pkg::ALERT_CRASHDUMP_DEFAULT), .cpu_dump_i(rv_core_ibex_crash_dump), .sw_rst_req_o(rstmgr_aon_sw_rst_req), .tl_i(rstmgr_aon_tl_req), diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv index fe489a3ac49..6ba4d9e0456 100644 --- a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv +++ b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv @@ -97,7 +97,7 @@ package top_englishbreakfast_pkg; /** * Peripheral size in bytes for rstmgr_aon in top englishbreakfast. */ - parameter int unsigned TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES = 32'h80; + parameter int unsigned TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES = 32'h40; /** * Peripheral base address for clkmgr_aon in top englishbreakfast. diff --git a/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs b/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs index 5184f830de8..0417d83cd57 100644 --- a/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs +++ b/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs @@ -145,7 +145,7 @@ pub const RSTMGR_AON_BASE_ADDR: usize = 0x40410000; /// memory-mapped registers associated with this peripheral should have an /// address between #RSTMGR_AON_BASE_ADDR and /// `RSTMGR_AON_BASE_ADDR + RSTMGR_AON_SIZE_BYTES`. -pub const RSTMGR_AON_SIZE_BYTES: usize = 0x80; +pub const RSTMGR_AON_SIZE_BYTES: usize = 0x40; /// Peripheral base address for clkmgr_aon in top englishbreakfast. /// diff --git a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h index 933a64fb09c..c249744e034 100644 --- a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h +++ b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h @@ -189,7 +189,7 @@ extern "C" { * address between #TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR and * `TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES`. */ -#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80u +#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x40u /** * Peripheral base address for clkmgr_aon in top englishbreakfast. diff --git a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h index fb50a6f0b7a..1db200b958c 100644 --- a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h +++ b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h @@ -208,7 +208,7 @@ * address between #TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR and * `TOP_ENGLISHBREAKFAST_RSTMGR_AON_BASE_ADDR + TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES`. */ -#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x80 +#define TOP_ENGLISHBREAKFAST_RSTMGR_AON_SIZE_BYTES 0x40 /** * Peripheral base address for clkmgr_aon in top englishbreakfast. * diff --git a/util/topgen.py b/util/topgen.py index ce2b8ffc026..4e7ec0396bb 100755 --- a/util/topgen.py +++ b/util/topgen.py @@ -1,5 +1,6 @@ #!/usr/bin/env python3 # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 r"""Top Module Generator @@ -617,9 +618,12 @@ def _get_rstmgr_params(top: ConfigT) -> ParamsT: n_rstreqs = len(top["reset_requests"]["peripheral"]) # Will connect to alert_handler - with_alert_handler = lib.find_module(top['module'], + with_alert_dump = lib.find_module(top['module'], 'alert_handler') is not None + # Will have an instance of Ibex + with_cpu_dump = lib.find_module(top['module'], 'rv_core_ibex') is not None + ipgen_params = get_ipgen_params(rstmgr) ipgen_params.update({ "clk_freqs": clk_freqs, @@ -631,7 +635,8 @@ def _get_rstmgr_params(top: ConfigT) -> ParamsT: "leaf_rsts": leaf_rsts, "rst_ni": rst_ni['rst_ni']['name'], "export_rsts": top["exported_rsts"], - "with_alert_handler": with_alert_handler, + "with_alert_dump": with_alert_dump, + "with_cpu_dump": with_cpu_dump }) return ipgen_params