diff --git a/BLOCKFILE b/BLOCKFILE index ba11f0f5059..bdf3a2c2c3c 100644 --- a/BLOCKFILE +++ b/BLOCKFILE @@ -1,3 +1,8 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + # If a PR changes a file that matches a pattern in this file it will be blocked # from merged by CI. The patterns as glob-like patterns matched using python # fnmatch. In particular note there is no special handling for '/' so '*' can @@ -41,6 +46,7 @@ hw/ip/aon_timer/rtl/* hw/ip/csrng/rtl/* hw/ip/edn/rtl/* hw/ip/entropy_src/rtl/* +hw/ip/flash_macro_wrapper/rtl/* hw/ip/hmac/rtl/* hw/ip/i2c/rtl/* hw/ip/keymgr/rtl/* @@ -89,6 +95,7 @@ hw/ip/sysrst_ctrl/data/sysrst_ctrl.hjson hw/ip/otbn/data/otbn.hjson hw/ip/otp_macro/data/otp_macro.hjson hw/ip/entropy_src/data/entropy_src.hjson +hw/ip/flash_macro_wrapper/data/flash_macro_wrapper.hjson hw/ip/aes/data/aes.hjson hw/ip/i2c/data/i2c.hjson hw/top_earlgrey/data/otp/otp_ctrl.hjson diff --git a/hw/Makefile b/hw/Makefile index 34dc545fc5f..0937a080b5f 100644 --- a/hw/Makefile +++ b/hw/Makefile @@ -19,34 +19,35 @@ endif # The IPs listed here have their collateral generated by an invocation of # regtool triggered here; those not in this list have their reg collateral # generated by ipgen or topgen. -IPS ?= aes \ - adc_ctrl \ - aon_timer \ - csrng \ - dma \ - edn \ - entropy_src \ - hmac \ - i2c \ - keymgr \ - keymgr_dpe \ - kmac \ - lc_ctrl \ - mbx \ - otbn \ - otp_macro \ - pattgen \ - pwm \ - rom_ctrl \ - rv_dm \ - rv_timer \ - sensor_ctrl \ - soc_dbg_ctrl \ - spi_device \ - spi_host \ - sram_ctrl \ - sysrst_ctrl \ - uart \ +IPS ?= aes \ + adc_ctrl \ + aon_timer \ + csrng \ + dma \ + edn \ + entropy_src \ + flash_macro_wrapper \ + hmac \ + i2c \ + keymgr \ + keymgr_dpe \ + kmac \ + lc_ctrl \ + mbx \ + otbn \ + otp_macro \ + pattgen \ + pwm \ + rom_ctrl \ + rv_dm \ + rv_timer \ + sensor_ctrl \ + soc_dbg_ctrl \ + spi_device \ + spi_host \ + sram_ctrl \ + sysrst_ctrl \ + uart \ usbdev TOPS ?= top_darjeeling top_earlgrey top_englishbreakfast diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent.core b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent.core index 1ed195379a3..147d335bb3d 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent.core +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:dv:flash_phy_prim_agent:0.1" @@ -9,7 +10,7 @@ filesets: depend: - lowrisc:dv:dv_utils - lowrisc:dv:dv_lib - - lowrisc:virtual_ip:flash_ctrl_top_specific_pkg + - lowrisc:virtual_ip:flash_phy_macro_pkg files: - flash_phy_prim_if.sv - flash_phy_prim_agent_pkg.sv diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent_pkg.sv b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent_pkg.sv index d908190af7a..03892d54813 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent_pkg.sv +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_agent_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -7,16 +8,14 @@ package flash_phy_prim_agent_pkg; import uvm_pkg::*; import dv_utils_pkg::*; import dv_lib_pkg::*; - import flash_ctrl_top_specific_pkg::*; - + import flash_phy_macro_pkg::DataWidth; + import flash_phy_macro_pkg::NumBanks; + import flash_phy_macro_pkg::flash_phy_macro_bank_req_t; + import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t; // macro includes `include "uvm_macros.svh" `include "dv_macros.svh" - // parameters - localparam int unsigned PhyAddrW = flash_phy_pkg::BankAddrW; - localparam int unsigned PhyDataW = flash_phy_pkg::FullDataWidth; - // local types // forward declare classes to allow typedefs below typedef class flash_phy_prim_item; @@ -26,7 +25,7 @@ package flash_phy_prim_agent_pkg; typedef dv_base_sequencer #(.ITEM_T(flash_phy_prim_item), .CFG_T (flash_phy_prim_agent_cfg)) flash_phy_prim_sequencer; - typedef logic [flash_phy_pkg::FullDataWidth-1:0] fdata_q_t[$]; + typedef logic [DataWidth-1:0] fdata_q_t[$]; // functions diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_driver.sv b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_driver.sv index 909aa811d4d..e1665dcbd49 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_driver.sv +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_driver.sv @@ -3,7 +3,7 @@ // SPDX-License-Identifier: Apache-2.0 class flash_phy_prim_driver extends dv_base_driver #(.ITEM_T(flash_phy_prim_item), - .CFG_T (flash_phy_prim_agent_cfg)); + .CFG_T (flash_phy_prim_agent_cfg)); `uvm_component_utils(flash_phy_prim_driver) // the base class provides the following handles for use: diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_if.sv b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_if.sv index 082f2ec0239..7a78bdc7204 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_if.sv +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_if.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -6,17 +7,19 @@ interface flash_phy_prim_if ( input logic clk, input logic rst_n ); - import flash_phy_pkg::*; + import flash_phy_macro_pkg::NumBanks; + import flash_phy_macro_pkg::flash_phy_macro_bank_req_t; + import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t; - flash_phy_prim_flash_req_t [NumBanks-1:0] req; - flash_phy_prim_flash_rsp_t [NumBanks-1:0] rsp; + flash_phy_macro_bank_req_t [NumBanks-1:0] req; + flash_phy_macro_bank_rsp_t [NumBanks-1:0] rsp; // Inner read request / rdy logic [NumBanks-1:0] rreq; logic [NumBanks-1:0] rdy; // Debug tab - flash_phy_prim_flash_req_t dreq0, dreq1; - flash_phy_prim_flash_rsp_t drsp0, drsp1; + flash_phy_macro_bank_req_t dreq0, dreq1; + flash_phy_macro_bank_rsp_t drsp0, drsp1; assign dreq0 = req[0]; assign drsp0 = rsp[0]; diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_item.sv b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_item.sv index b5018d579a5..b1f8678e026 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_item.sv +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_item.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -7,8 +8,8 @@ class flash_phy_prim_item extends uvm_sequence_item; `uvm_object_utils_begin(flash_phy_prim_item) `uvm_object_utils_end - flash_phy_pkg::flash_phy_prim_flash_req_t req; - flash_phy_pkg::flash_phy_prim_flash_rsp_t rsp; + flash_phy_macro_bank_req_t req; + flash_phy_macro_bank_rsp_t rsp; fdata_q_t fq; `uvm_object_new diff --git a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_monitor.sv b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_monitor.sv index 932119f7edc..9e0f3720252 100644 --- a/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_monitor.sv +++ b/hw/dv/sv/flash_phy_prim_agent/flash_phy_prim_monitor.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -19,7 +20,7 @@ class flash_phy_prim_monitor extends dv_base_monitor #( flash_phy_prim_item w_item[NumBanks]; flash_phy_prim_item r_item[NumBanks]; flash_phy_prim_item lm_item[NumBanks]; - logic [PhyDataW-1:0] write_buffer[NumBanks][$]; + logic [DataWidth-1:0] write_buffer[NumBanks][$]; `uvm_component_new diff --git a/hw/ip/BUILD b/hw/ip/BUILD index b527f0870b1..a6ae3441cd2 100644 --- a/hw/ip/BUILD +++ b/hw/ip/BUILD @@ -1,4 +1,5 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -21,6 +22,7 @@ filegroup( "//hw/ip/dma:rtl_files", "//hw/ip/edn:rtl_files", "//hw/ip/entropy_src:rtl_files", + "//hw/ip/flash_macro_wrapper:rtl_files", "//hw/ip/hmac:rtl_files", "//hw/ip/i2c:rtl_files", "//hw/ip/keymgr:rtl_files", diff --git a/hw/ip/README.md b/hw/ip/README.md index 9b5acdaa23d..154441a10ec 100644 --- a/hw/ip/README.md +++ b/hw/ip/README.md @@ -2,36 +2,37 @@ -| HW Block | Brief Summary | -|------------------|-----------------------------------------------------------------------------------------------------------------------------------| -| [`adc_ctrl`] | Low-power controller for a dual-channel ADC with filtering and debouncing capability | -| [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures | -| [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock | -| [`ascon`] | Ascon authenticated encryption and decryption engine | -| [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software | -| [`dma`] | DMA Controller for the integrated OpenTitan. | -| [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks | -| [`entropy_src`] | Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG | -| [`hmac`] | Accelerator for SHA-2 256/384/512-based keyed HMAC and the hash function | -| [`i2c`] | I2C interface for host and device mode, supporting up to 1 Mbaud data rates | -| [`keymgr`] | Managing identities and root keys; shielding confidential assets from software; providing a key derivation interface for software | -| [`keymgr_dpe`] | Manage multiple DICE sessions in a DPE-compatible way | -| [`kmac`] | Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures | -| [`lc_ctrl`] | Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access | -| [`mbx`] | DOE mailbox for use as an integrated OpenTitan communication channel. | -| [`otbn`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures | -| [`otp_macro`] | OTP macro simulation model and CSR block | -| [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels | -| [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset | -| [`rv_dm`] | Enables debug support for Ibex, access protected by life cycle | -| [`rv_timer`] | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers | -| [`soc_dbg_ctrl`] | Control module to enable or disable debug access | -| [`spi_device`] | Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip | -| [`spi_host`] | Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices | -| [`sram_ctrl`] | Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe | -| [`sysrst_ctrl`] | Manages board-level reset sequencing, interfaces reset and power manager | -| [`uart`] | Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s | -| [`usbdev`] | USB 2.0 Full Speed device interface (12 Mbit/s) | +| HW Block | Brief Summary | +|-------------------------|-----------------------------------------------------------------------------------------------------------------------------------| +| [`adc_ctrl`] | Low-power controller for a dual-channel ADC with filtering and debouncing capability | +| [`aes`] | AES encryption and decryption engine with SCA and FI countermeasures | +| [`aon_timer`] | Wakeup and watchdog timers running on a low-power, always-on clock | +| [`ascon`] | Ascon authenticated encryption and decryption engine | +| [`csrng`] | Takes entropy bits to produce cryptographically secure random numbers for consumption by hardware blocks and by software | +| [`dma`] | DMA Controller for the integrated OpenTitan. | +| [`edn`] | Distributes random numbers produced by CSRNG to hardware blocks | +| [`entropy_src`] | Filters and checks raw entropy bits from a random noise source and forwards them to CSRNG | +| [`flash_macro_wrapper`] | FLASH macro simulation model and CSR block | +| [`hmac`] | Accelerator for SHA-2 256/384/512-based keyed HMAC and the hash function | +| [`i2c`] | I2C interface for host and device mode, supporting up to 1 Mbaud data rates | +| [`keymgr`] | Managing identities and root keys; shielding confidential assets from software; providing a key derivation interface for software | +| [`keymgr_dpe`] | Manage multiple DICE sessions in a DPE-compatible way | +| [`kmac`] | Accelerator for Keccak-based keyed hash message authentication code and SHA-3 hash functions; with SCA and FI countermeasures | +| [`lc_ctrl`] | Manages device life cycle states and transitions, and controls key manager, flash, OTP, and debug access | +| [`mbx`] | DOE mailbox for use as an integrated OpenTitan communication channel. | +| [`otbn`] | Programmable coprocessor for asymmetric cryptography with SCA and FI countermeasures | +| [`otp_macro`] | OTP macro simulation model and CSR block | +| [`pattgen`] | Transmission of short time-dependent data patterns on two clock-parallel output channels | +| [`rom_ctrl`] | Interfaces scrambled boot ROM with system bus and KMAC for initial health check after reset | +| [`rv_dm`] | Enables debug support for Ibex, access protected by life cycle | +| [`rv_timer`] | Memory-mapped timer unit implementing RISC-V mtime and mtimecmp registers | +| [`soc_dbg_ctrl`] | Control module to enable or disable debug access | +| [`spi_device`] | Serial peripheral interface supporting different device modes, suitable for bulk-load of data into and out of the chip | +| [`spi_host`] | Serial peripheral interface for host mode, suitable for interfacing external serial NOR flash devices | +| [`sram_ctrl`] | Interfacing on-chip SRAM blocks with system bus, supports lightweight scrambling, integrity and secure wipe | +| [`sysrst_ctrl`] | Manages board-level reset sequencing, interfaces reset and power manager | +| [`uart`] | Full duplex serial communication interface, supports bit rates of up to 1 Mbit/s | +| [`usbdev`] | USB 2.0 Full Speed device interface (12 Mbit/s) | @@ -44,6 +45,7 @@ [`dma`]: ./dma/README.md [`edn`]: ./edn/README.md [`entropy_src`]: ./entropy_src/README.md +[`flash_macro_wrapper`]: ./flash_macro_wrapper/README.md [`hmac`]: ./hmac/README.md [`i2c`]: ./i2c/README.md [`keymgr`]: ./keymgr/README.md diff --git a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv index 0b70dc1cd26..624aa3a7dd4 100644 --- a/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv +++ b/hw/ip/flash_ctrl/rtl/flash_ctrl_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -26,4 +27,17 @@ package flash_ctrl_pkg; } }; + // Flash Program Operations Supported + typedef enum logic { + FlashProgNormal = 0, + FlashProgRepair = 1 + } flash_prog_e; + parameter int ProgTypes = 2; + + // Flash partition type + typedef enum logic { + FlashPartData = 1'b0, + FlashPartInfo = 1'b1 + } flash_part_e; + endpackage : flash_ctrl_pkg diff --git a/hw/ip/flash_macro_wrapper/BUILD b/hw/ip/flash_macro_wrapper/BUILD new file mode 100644 index 00000000000..dc8f0bbf6dd --- /dev/null +++ b/hw/ip/flash_macro_wrapper/BUILD @@ -0,0 +1,24 @@ +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "rtl_files", + srcs = glob( + ["**"], + exclude = [ + "dv/**", + "doc/**", + "README.md", + ], + ) + [ + "//hw/ip/flash_macro_wrapper/data:all_files", + ], +) + +filegroup( + name = "doc_files", + srcs = glob(["**/*.md"]), +) diff --git a/hw/ip/flash_macro_wrapper/README.md b/hw/ip/flash_macro_wrapper/README.md new file mode 100644 index 00000000000..4b6158a0038 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/README.md @@ -0,0 +1,16 @@ +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# FLASH MACRO WRAPPER HWIP Technical Specification + +# Overview + +This document specifies the FLASH MACRO WRAPPER hardware IP functionality. +The FLASH MACRO WRAPPER is a comportable IP that wraps one or more flash bank macros. +This block is expected to be used in conjunction with a Flash Controller, and most of the features of the macro wrapper correspond to features of the controller. + +## Features + +The FLASH MACRO WRAPPER wraps flash macros, which can be either a simulation model, or vendor specific macro cells. +The wrapper features a CSR block for vendor specific operations. diff --git a/hw/ip/flash_macro_wrapper/data/BUILD b/hw/ip/flash_macro_wrapper/data/BUILD new file mode 100644 index 00000000000..3a11773a723 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/data/BUILD @@ -0,0 +1,11 @@ +# Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +package(default_visibility = ["//visibility:public"]) + +filegroup( + name = "all_files", + srcs = glob(["**"]), +) diff --git a/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper.hjson b/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper.hjson new file mode 100644 index 00000000000..d001457ba4d --- /dev/null +++ b/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper.hjson @@ -0,0 +1,1053 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +{ + name: "flash_macro_wrapper", + human_name: "FLASH Macro Wrapper", + one_line_desc: "FLASH macro simulation model and CSR block", + one_paragraph_desc: ''' + FLASH macro has flash memory arrays for non-volatile data storage. + It is tightly coupled to the FLASH controller, but placed at the top for + ease of integration. It contains a CSR block for testing and macro specific + functionality. + ''' + // Unique comportable IP identifier defined under KNOWN_CIP_IDS in the regtool. + cip_id: "45", + design_spec: "../doc", +# dv_doc: "../doc/dv", +# hw_checklist: "../doc/checklist", +# sw_checklist: "/sw/device/lib/dif/dif_pwm", + revisions: [ + { + version: "2.0.0", + life_stage: "L1", + design_stage: "D2S", + verification_stage: "V2S", + dif_stage: "S2", + notes: "Use FLASH_CTRL to perform block level verification.", + } + ] + clocking: [ + {clock: "clk_i", reset: "rst_ni", primary: true}, + ] + bus_interfaces: [ + { protocol: "tlul", direction: "device" } + ], + scan: "true", // Enable `scanmode_i` port + scan_reset: "true", // Enable `scan_rst_ni` port + scan_en: "true", // Enable `scan_en_i` port + available_input_list: [ + { name: "tck", desc: "jtag clock" }, + { name: "tms", desc: "jtag tms" }, + { name: "tdi", desc: "jtag input" }, + ], + available_output_list: [ + { name: "tdo", desc: "jtag output" }, + ], +/* + available_output_list: [ + { name: "test", + width: 8, + desc: "Test-related GPIOs. Only active in DFT-enabled life cycle states." + } + ], +*/ + regwidth: "32", + param_list: [ + { name: "NumBanks", + desc: "Number of flash banks", + type: "int", + default: "2", + local: "false", + }, + { name: "InfosPerBank", + desc: "Info pages per bank", + type: "int", + default: "10", + local: "false", + }, + { name: "InfoTypes", + desc: "Number of different info page types per bank", + type: "int", + default: "3", + local: "false", + }, + { name: "InfoTypesWidth", + desc: "Number of bits to encode the info page types", + type: "int", + default: "2", + local: "false", + }, + { name: "PagesPerBank", + desc: "Number of data pages per bank", + type: "int", + default: "256", + local: "false", + }, + { name: "WordsPerPage", + desc: "Number of words per data page", + type: "int", + default: "256", + local: "false", + }, + { name: "DataWidth", + desc: "Number of bits per data word", + type: "int", + default: "72", + local: "false", + }, + { name: "TestModeWidth", + desc: "Number of bits to encode test mode", + type: "int", + default: "2", + local: "false", + }, + ], + alert_list: [], + features: [] + countermeasures: [ + { name: "REG.BUS.INTEGRITY", + desc: ''' + End-to-end bus integrity scheme. + ''' + }, + { name: "LC_CTRL.INTERSIG.MUBI", + desc: ''' + Life cycle control signals are used enable jtag access to the flash macro. + ''' + } + ], + inter_signal_list: [ + { struct: "flash_phy_macro", + type: "req_rsp", + name: "flash", + act: "rsp", + package: "flash_phy_macro_pkg", + desc: "Data interface to the flash controller" + }, + + { struct: "flash_macro_status", + type: "uni", + name: "status", + act: "req", + package: "flash_phy_macro_pkg", + }, + + { struct: "lc_tx", + package: "lc_ctrl_pkg", + type: "uni" + act: "rcv" + name: "lc_nvm_debug_en" + }, + + { struct: "mubi4" + package: "prim_mubi_pkg" + type: "uni" + act: "rcv" + name: "bist_enable" + }, + + { struct: "logic" + package: "" + type: "uni" + act: "rcv" + name: "power_down_h" + }, + { struct: "logic" + package: "" + type: "uni" + act: "rcv" + name: "power_ready_h" + }, + { struct: "", + package: "", + width: "2", + type: "io" + act: "none" + name: "test_mode_a" + }, + { struct: "", + package: "", + type: "io" + act: "none" + name: "test_voltage_h" + }, + { struct: "ast_obs_ctrl", + type: "uni", + name: "obs_ctrl", + act: "rcv", + package: "ast_pkg" + } + + { struct: "logic", + type: "uni", + name: "fla_obs", + act: "req", + width: "8", + package: "" + } + ], + + registers: [ + { + name: "CSR0_REGWEN", + desc: "", + fields: [ + { + bits: "0", + name: "field0", + swaccess: "rw0c", + hwaccess: "none", + resval: "1", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False" + }, + { + name: "CSR1", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "12:8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR2", + desc: "", + fields: [ + { + bits: "0", + name: "field0", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "1", + name: "field1", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "2", + name: "field2", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "3", + name: "field3", + swaccess: "rw", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "4", + name: "field4", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "5", + name: "field5", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "6", + name: "field6", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "7", + name: "field7", + swaccess: "rw", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False" + }, + { + name: "CSR3", + desc: "", + fields: [ + { + bits: "3:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "7:4", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "10:8", + name: "field2", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "13:11", + name: "field3", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "16:14", + name: "field4", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "19:17", + name: "field5", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "20", + name: "field6", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "23:21", + name: "field7", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "25:24", + name: "field8", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "27:26", + name: "field9", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR4", + desc: "", + fields: [ + { + bits: "2:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "5:3", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "8:6", + name: "field2", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "11:9", + name: "field3", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR5", + desc: "", + fields: [ + { + bits: "2:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "4:3", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "13:5", + name: "field2", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "18:14", + name: "field3", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "22:19", + name: "field4", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR6", + desc: "", + fields: [ + { + bits: "2:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "5:3", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "13:6", + name: "field2", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "16:14", + name: "field3", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "18:17", + name: "field4", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "20:19", + name: "field5", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "22:21", + name: "field6", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "23", + name: "field7", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "24", + name: "field8", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR7", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "16:8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR8", + desc: "", + fields: [ + { + bits: "31:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR9", + desc: "", + fields: [ + { + bits: "31:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR10", + desc: "", + fields: [ + { + bits: "31:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR11", + desc: "", + fields: [ + { + bits: "31:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR12", + desc: "", + fields: [ + { + bits: "9:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR13", + desc: "", + fields: [ + { + bits: "19:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "20", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR14", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR15", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR16", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR17", + desc: "", + fields: [ + { + bits: "7:0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "8", + name: "field1", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR18", + desc: "", + fields: [ + { + bits: "0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR19", + desc: "", + fields: [ + { + bits: "0", + name: "field0", + swaccess: "rw", + hwaccess: "hro", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False", + regwen: "CSR0_REGWEN" + }, + { + name: "CSR20", + desc: "", + fields: [ + { + bits: "0", + name: "field0", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "1", + name: "field1", + swaccess: "rw1c", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + }, + { + bits: "2", + name: "field2", + swaccess: "ro", + hwaccess: "hrw", + resval: "0", + tags: [], + desc: "", + enum: [] + } + ], + hwext: "False", + hwqe: "False", + hwre: "False", + tags: [], + shadowed: "False" + } + ] +} diff --git a/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper_sec_cm_testplan.hjson b/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper_sec_cm_testplan.hjson new file mode 100644 index 00000000000..37593d79f8f --- /dev/null +++ b/hw/ip/flash_macro_wrapper/data/flash_macro_wrapper_sec_cm_testplan.hjson @@ -0,0 +1,40 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 + +// Security countermeasures testplan extracted from the IP Hjson using reggen. +// +// This testplan is auto-generated only the first time it is created. This is +// because this testplan needs to be hand-editable. It is possible that these +// testpoints can go out of date if the spec is updated with new +// countermeasures. When `reggen` is invoked when this testplan already exists, +// It checks if the list of testpoints is up-to-date and enforces the user to +// make further manual updates. +// +// These countermeasures and their descriptions can be found here: +// .../flash_macro_wrapper/data/flash_macro_wrapper.hjson +// +// It is possible that the testing of some of these countermeasures may already +// be covered as a testpoint in a different testplan. This duplication is ok - +// the test would have likely already been developed. We simply map those tests +// to the testpoints below using the `tests` key. +// +// Please ensure that this testplan is imported in: +// .../flash_macro_wrapper/data/flash_macro_wrapper_testplan.hjson +{ + testpoints: [ + { + name: sec_cm_reg_bus_integrity + desc: "Verify the countermeasure(s) REG.BUS.INTEGRITY." + stage: V2S + tests: [] + } + { + name: sec_cm_lc_ctrl_intersig_mubi + desc: "Verify the countermeasure(s) LC_CTRL.INTERSIG.MUBI." + stage: V2S + tests: [] + } + ] +} diff --git a/hw/ip/flash_macro_wrapper/defs.bzl b/hw/ip/flash_macro_wrapper/defs.bzl new file mode 100644 index 00000000000..2c3684fa188 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/defs.bzl @@ -0,0 +1,9 @@ +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +load("//rules/opentitan:hw.bzl", "opentitan_ip") + +FLASH_MACRO_WRAPPER = opentitan_ip( + name = "flash_macro_wrapper", + hjson = "//hw/ip/flash_macro_wrapper/data:flash_macro_wrapper.hjson", +) diff --git a/hw/ip/flash_macro_wrapper/dv/env/flash_macro_wrapper_env.core b/hw/ip/flash_macro_wrapper/dv/env/flash_macro_wrapper_env.core new file mode 100644 index 00000000000..212832f4c75 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/dv/env/flash_macro_wrapper_env.core @@ -0,0 +1,27 @@ +CAPI=2: +# Copyright lowRISC contributors (OpenTitan project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: "lowrisc:dv:flash_macro_wrapper_env:0.1" +description: "FLASH_MACRO_WRAPPER DV UVM environment" + +filesets: + files_dv: + depend: + - lowrisc:dv:ralgen + - lowrisc:dv:cip_lib + +generate: + ral: + generator: ralgen + parameters: + name: flash_macro_wrapper + ip_hjson: ../../data/flash_macro_wrapper.hjson + position: prepend + +targets: + default: + filesets: + - files_dv + generate: + - ral diff --git a/hw/ip/prim_generic/prim_generic_flash.core b/hw/ip/flash_macro_wrapper/flash_macro_wrapper.core similarity index 57% rename from hw/ip/prim_generic/prim_generic_flash.core rename to hw/ip/flash_macro_wrapper/flash_macro_wrapper.core index 5a8cd51d1b8..467e6184829 100644 --- a/hw/ip/prim_generic/prim_generic_flash.core +++ b/hw/ip/flash_macro_wrapper/flash_macro_wrapper.core @@ -1,25 +1,26 @@ CAPI=2: -# Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: "lowrisc:prim_generic:flash" -description: "prim" -virtual: - - lowrisc:prim:flash +name: "lowrisc:ip:flash_macro_wrapper:0.1" +description: "Flash macro wrapper" filesets: files_rtl: depend: - lowrisc:tlul:headers + - lowrisc:prim:mubi_pkg - lowrisc:prim:ram_1p - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" - - lowrisc:virtual_ip:flash_ctrl_top_specific_pkg - - lowrisc:virtual_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_ctrl_pkg + - lowrisc:ip:flash_macro_wrapper_pkg + - lowrisc:ip:flash_macro_wrapper_reg_top + - lowrisc:virtual_ip:flash_phy_macro_pkg files: - - rtl/prim_generic_flash_bank.sv - - rtl/prim_flash.sv + - rtl/flash_macro_bank.sv + - rtl/flash_macro_wrapper.sv file_type: systemVerilogSource files_verilator_waiver: @@ -27,7 +28,7 @@ filesets: # common waivers - lowrisc:lint:common files: - - lint/prim_generic_flash.vlt + - lint/flash_macro_wrapper.vlt file_type: vlt files_ascentlint_waiver: @@ -35,7 +36,7 @@ filesets: # common waivers - lowrisc:lint:common files: - - lint/prim_generic_flash.waiver + - lint/flash_macro_wrapper.waiver file_type: waiver files_veriblelint_waiver: @@ -44,9 +45,20 @@ filesets: - lowrisc:lint:common targets: - default: + default: &default_target filesets: - tool_verilator ? (files_verilator_waiver) - tool_ascentlint ? (files_ascentlint_waiver) - tool_veriblelint ? (files_veriblelint_waiver) - files_rtl + + lint: + <<: *default_target + default_tool: verilator + parameters: + - SYNTHESIS=true + tools: + verilator: + mode: lint-only + verilator_options: + - "-Wall" diff --git a/hw/ip/flash_macro_wrapper/flash_macro_wrapper_pkg.core b/hw/ip/flash_macro_wrapper/flash_macro_wrapper_pkg.core new file mode 100644 index 00000000000..5b3b16e3427 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/flash_macro_wrapper_pkg.core @@ -0,0 +1,18 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:ip:flash_macro_wrapper_pkg" +description: "Flash macro wrapper package" + +filesets: + files_rtl: + files: + - rtl/flash_macro_wrapper_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/flash_macro_wrapper/flash_macro_wrapper_reg_top.core b/hw/ip/flash_macro_wrapper/flash_macro_wrapper_reg_top.core new file mode 100644 index 00000000000..b8e81540736 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/flash_macro_wrapper_reg_top.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:ip:flash_macro_wrapper_reg_top" +description: "Flash macro wrapper register block" + +filesets: + files_rtl: + depend: + - lowrisc:ip:tlul + - lowrisc:prim:subreg + files: + - rtl/flash_macro_wrapper_reg_pkg.sv + - rtl/flash_macro_wrapper_reg_top.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip/prim_generic/lint/prim_generic_flash.vlt b/hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.vlt similarity index 68% rename from hw/ip/prim_generic/lint/prim_generic_flash.vlt rename to hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.vlt index b8340b20851..073d9c58e29 100644 --- a/hw/ip/prim_generic/lint/prim_generic_flash.vlt +++ b/hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.vlt @@ -1,4 +1,4 @@ -// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // diff --git a/hw/ip/prim_generic/lint/prim_generic_flash.waiver b/hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.waiver similarity index 51% rename from hw/ip/prim_generic/lint/prim_generic_flash.waiver rename to hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.waiver index d69580656bb..b1efe2516fc 100644 --- a/hw/ip/prim_generic/lint/prim_generic_flash.waiver +++ b/hw/ip/flash_macro_wrapper/lint/flash_macro_wrapper.waiver @@ -1,12 +1,13 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # -# waiver file for prim_flash +# waiver file for flash_macro_wrapper # The prim generic module does not make use of the IO ports -waive -rules INOUT_AS_IN -location {prim_flash.sv} \ - -regexp {Inout port 'flash_.*_io' has no driver} +waive -rules INOUT_AS_IN -location {flash_macro_wrapper.sv} \ + -regexp {Inout port 'test_.*_io' has no driver} -waive -rules {RESET_USE} -location {prim_generic_flash_bank.sv} -regexp {rst_ni' is connected to 'prim_ram_1p' port 'rst_ni', and used as an asynchronous reset or set at prim_generic_flash_bank.sv} \ +waive -rules {RESET_USE} -location {flash_macro_bank.sv} -regexp {rst_ni' is connected to 'prim_ram_1p' port 'rst_ni', and used as an asynchronous reset or set at flash_macro_bank.sv} \ -comment "rst_ni is the asynchronous reset of prim_ram_1p_adv. It's unused in the generic implementation, but other implementations may use it." diff --git a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv b/hw/ip/flash_macro_wrapper/rtl/flash_macro_bank.sv similarity index 86% rename from hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv rename to hw/ip/flash_macro_wrapper/rtl/flash_macro_bank.sv index 5ecb7ec2c6c..af721f1d8d0 100644 --- a/hw/ip/prim_generic/rtl/prim_generic_flash_bank.sv +++ b/hw/ip/flash_macro_wrapper/rtl/flash_macro_bank.sv @@ -1,11 +1,12 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // // Emulate a single generic flash bank // -module prim_generic_flash_bank #( +module flash_macro_bank #( parameter int InfosPerBank = 1, // info pages per bank parameter int InfoTypes = 1, // different info types parameter int InfoTypesWidth = 1, // different info types @@ -18,28 +19,28 @@ module prim_generic_flash_bank #( localparam int WordW = $clog2(WordsPerPage), localparam int AddrW = PageW + WordW ) ( - input clk_i, - input rst_ni, - input rd_i, - input prog_i, - input prog_last_i, + input clk_i, + input rst_ni, + input rd_i, + input prog_i, + input prog_last_i, // the generic model does not make use of program types - input flash_ctrl_top_specific_pkg::flash_prog_e prog_type_i, - input pg_erase_i, - input bk_erase_i, - input erase_suspend_req_i, - input he_i, - input [AddrW-1:0] addr_i, - input flash_ctrl_top_specific_pkg::flash_part_e part_i, - input [InfoTypesWidth-1:0] info_sel_i, - input [DataWidth-1:0] prog_data_i, - output logic ack_o, - output logic done_o, - output logic [DataWidth-1:0] rd_data_o, - input init_i, - output logic init_busy_o, - input flash_power_ready_h_i, - input flash_power_down_h_i + input flash_ctrl_pkg::flash_prog_e prog_type_i, + input pg_erase_i, + input bk_erase_i, + input erase_suspend_req_i, + input he_i, + input [AddrW-1:0] addr_i, + input flash_ctrl_pkg::flash_part_e part_i, + input [InfoTypesWidth-1:0] info_sel_i, + input [DataWidth-1:0] prog_data_i, + output logic ack_o, + output logic done_o, + output logic [DataWidth-1:0] rd_data_o, + input init_i, + output logic init_busy_o, + input flash_power_ready_h_i, + input flash_power_down_h_i ); `ifdef SYNTHESIS @@ -101,7 +102,7 @@ module prim_generic_flash_bank #( logic mem_wr; logic [DataWidth-1:0] mem_wdata; logic [AddrW-1:0] mem_addr; - flash_ctrl_top_specific_pkg::flash_part_e mem_part; + flash_ctrl_pkg::flash_part_e mem_part; logic mem_bk_erase; logic [InfoTypesWidth-1:0] mem_info_sel; @@ -110,11 +111,11 @@ module prim_generic_flash_bank #( logic rd; logic prog; logic prog_last; - flash_ctrl_top_specific_pkg::flash_prog_e prog_type; + flash_ctrl_pkg::flash_prog_e prog_type; logic pg_erase; logic bk_erase; logic [AddrW-1:0] addr; - flash_ctrl_top_specific_pkg::flash_part_e part; + flash_ctrl_pkg::flash_part_e part; logic [InfoTypesWidth-1:0] info_sel; logic [DataWidth-1:0] prog_data; } cmd_payload_t; @@ -216,11 +217,11 @@ module prim_generic_flash_bank #( end // latch partition being read since the command fifo is popped early - flash_ctrl_top_specific_pkg::flash_part_e rd_part_q; + flash_ctrl_pkg::flash_part_e rd_part_q; logic [InfoTypesWidth-1:0] info_sel_q; always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin - rd_part_q <= flash_ctrl_top_specific_pkg::FlashPartData; + rd_part_q <= flash_ctrl_pkg::FlashPartData; info_sel_q <= '0; end else if (mem_rd_d) begin rd_part_q <= cmd_q.part; @@ -401,7 +402,7 @@ module prim_generic_flash_bank #( // OR if it's a bank erase logic data_mem_req; assign data_mem_req = mem_req & - (mem_part == flash_ctrl_top_specific_pkg::FlashPartData | + (mem_part == flash_ctrl_pkg::FlashPartData | mem_bk_erase); prim_ram_1p #( @@ -427,7 +428,7 @@ module prim_generic_flash_bank #( // if NOT bank erase, then only the selected info partition is erased logic info_mem_req; assign info_mem_req = mem_req & - (mem_part == flash_ctrl_top_specific_pkg::FlashPartInfo) & + (mem_part == flash_ctrl_pkg::FlashPartInfo) & ((mem_info_sel == info_type) | mem_bk_erase); prim_ram_1p #( @@ -449,14 +450,14 @@ module prim_generic_flash_bank #( end assign rd_data_info = rd_nom_data_info[info_sel_q]; - assign rd_data_d = rd_part_q == flash_ctrl_top_specific_pkg::FlashPartData + assign rd_data_d = rd_part_q == flash_ctrl_pkg::FlashPartData ? rd_data_main : rd_data_info; - flash_ctrl_top_specific_pkg::flash_prog_e unused_prog_type; + flash_ctrl_pkg::flash_prog_e unused_prog_type; assign unused_prog_type = cmd_q.prog_type; logic unused_he; assign unused_he = he_i; -endmodule // prim_generic_flash_bank +endmodule : flash_macro_bank diff --git a/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper.sv b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper.sv new file mode 100644 index 00000000000..1fe53ad2943 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper.sv @@ -0,0 +1,195 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Flash macro wrapper +// + +module flash_macro_wrapper + import flash_ctrl_pkg::*; + import flash_macro_wrapper_pkg::*; + import flash_phy_macro_pkg::*; +#( + parameter int NumBanks = 2, // number of banks + parameter int InfosPerBank = 1, // info pages per bank + parameter int InfoTypes = 1, // different info types + parameter int InfoTypesWidth = 1, // different info types + parameter int PagesPerBank = 256,// data pages per bank + parameter int WordsPerPage = 256,// words per page + parameter int DataWidth = 32, // bits per word + parameter int TestModeWidth = 2 +) ( + input logic clk_i, + input logic rst_ni, + input flash_phy_macro_req_t flash_i, + output flash_phy_macro_rsp_t flash_o, + output flash_macro_status_t status_o, + // life cycle interface + // SEC_CM: LC_CTRL.INTERSIG.MUBI + input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, + input logic cio_tck_i, + input logic cio_tdi_i, + input logic cio_tms_i, + output logic cio_tdo_o, + output logic cio_tdo_en_o, + input prim_mubi_pkg::mubi4_t bist_enable_i, + input prim_mubi_pkg::mubi4_t scanmode_i, + input logic scan_en_i, + input logic scan_rst_ni, + input logic power_ready_h_i, + input logic power_down_h_i, + inout [TestModeWidth-1:0] test_mode_a_io, + inout test_voltage_h_io, + input tlul_pkg::tl_h2d_t tl_i, + output tlul_pkg::tl_d2h_t tl_o, + // Observability + input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, + output fla_obs_t fla_obs_o +); + import lc_ctrl_pkg::lc_tx_test_true_strict; + + lc_ctrl_pkg::lc_tx_t [FlashLcDftLast-1:0] lc_nvm_debug_en; + prim_lc_sync #( + .NumCopies(int'(FlashLcDftLast)) + ) u_lc_nvm_debug_en_sync ( + .clk_i, + .rst_ni, + .lc_en_i(lc_nvm_debug_en_i), + .lc_en_o(lc_nvm_debug_en) + ); + + logic tck; + assign tck = cio_tck_i & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTckSel]); + + logic tdi; + assign tdi = cio_tdi_i & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdiSel]); + + logic tms; + assign tms = cio_tms_i & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTmsSel]); + + logic tdo; + // Xor tdo to prevent this logic from getting removed in the open-source model. + assign cio_tdo_o = tdo ^ lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdoSel]); + + // if nvm debug is enabled, bist_enable_qual controls entry to flash test mode. + // if nvm debug is disabled, bist_enable_qual is always turned off. + prim_mubi_pkg::mubi4_t bist_enable_qual; + assign bist_enable_qual = (lc_tx_test_true_strict(lc_nvm_debug_en[FlashBistSel])) ? + bist_enable_i : + prim_mubi_pkg::MuBi4False; + + // convert this into a tlul write later + logic init; + assign init = 1'b1; + + logic [NumBanks-1:0] init_busy; + assign status_o.init_busy = |init_busy; + + // this represents the type of program operations that are supported + assign status_o.prog_type_avail[FlashProgNormal] = 1'b1; + assign status_o.prog_type_avail[FlashProgRepair] = 1'b1; + + for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_flash_banks + + flash_macro_bank #( + .InfosPerBank(InfosPerBank), + .InfoTypes(InfoTypes), + .InfoTypesWidth(InfoTypesWidth), + .PagesPerBank(PagesPerBank), + .WordsPerPage(WordsPerPage), + .DataWidth(DataWidth) + ) u_flash_macro_bank ( + .clk_i, + .rst_ni, + .rd_i(flash_i.bank_reqs[bank].rd_req), + .prog_i(flash_i.bank_reqs[bank].prog_req), + .prog_last_i(flash_i.bank_reqs[bank].prog_last), + .prog_type_i(flash_i.bank_reqs[bank].prog_type), + .pg_erase_i(flash_i.bank_reqs[bank].pg_erase_req), + .bk_erase_i(flash_i.bank_reqs[bank].bk_erase_req), + .erase_suspend_req_i(flash_i.bank_reqs[bank].erase_suspend_req), + .he_i(flash_i.bank_reqs[bank].he), + .addr_i(flash_i.bank_reqs[bank].addr), + .part_i(flash_i.bank_reqs[bank].part), + .info_sel_i(flash_i.bank_reqs[bank].info_sel), + .prog_data_i(flash_i.bank_reqs[bank].prog_full_data), + .ack_o(flash_o.bank_rsps[bank].ack), + .done_o(flash_o.bank_rsps[bank].done), + .rd_data_o(flash_o.bank_rsps[bank].rdata), + .init_i(init), + .init_busy_o(init_busy[bank]), + .flash_power_ready_h_i (power_ready_h_i), + .flash_power_down_h_i (power_down_h_i) + ); + end + + logic unused_scanmode; + logic unused_scan_en; + logic unused_scan_rst_n; + logic [TestModeWidth-1:0] unused_flash_test_mode; + logic unused_flash_test_voltage; + logic unused_tck; + logic unused_tdi; + logic unused_tms; + logic unused_bist_enable_qual; + + assign unused_scanmode = ^scanmode_i; + assign unused_scan_en = scan_en_i; + assign unused_scan_rst_n = scan_rst_ni; + assign unused_flash_test_mode = test_mode_a_io; + assign unused_flash_test_voltage = test_voltage_h_io; + assign unused_tck = tck; + assign unused_tdi = tdi; + assign unused_tms = tms; + assign unused_bist_enable_qual = ^bist_enable_qual; + assign tdo = '0; + assign cio_tdo_en_o = '1; + + //////////////////////////////////// + // TL-UL Test Interface Emulation // + //////////////////////////////////// + + logic intg_err; + flash_macro_wrapper_reg_pkg::flash_macro_wrapper_reg2hw_t reg2hw; + flash_macro_wrapper_reg_pkg::flash_macro_wrapper_hw2reg_t hw2reg; + + // SEC_CM: REG.BUS.INTEGRITY + flash_macro_wrapper_reg_top u_reg_top ( + .clk_i, + .rst_ni, + .tl_i (tl_i), + .tl_o (tl_o), + .reg2hw (reg2hw), + .hw2reg (hw2reg), + .intg_err_o(intg_err) + ); + + logic unused_reg_sig; + assign unused_reg_sig = ^reg2hw; + assign hw2reg = '0; + + // open source model has no error response at the moment + assign status_o.flash_err = 1'b0; + + assign status_o.fatal_alert = intg_err; + assign status_o.recov_alert = 1'b0; + + logic unused_obs; + assign unused_obs = |obs_ctrl_i; + assign fla_obs_o = '0; + + // Assertions + `ASSERT_KNOWN(PrimTlDValidKnownO_A, tl_o.d_valid ) + `ASSERT_KNOWN(PrimTlAReadyKnownO_A, tl_o.a_ready ) + `ASSERT_KNOWN_IF(PrimRspPayLoad_A, tl_o, tl_o.d_valid) + `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o ) + `ASSERT(TdoOeIsOne_A, cio_tdo_en_o === 1'b1) + + `ASSERT_ERROR_TRIGGER_ERR(PrimRegWeOnehotCheck_A, + u_reg_top.u_prim_reg_we_check.u_prim_onehot_check, status_o.fatal_alert, 0, + `_SEC_CM_ALERT_MAX_CYC, err_o, `ASSERT_DEFAULT_CLK, `ASSERT_DEFAULT_RST) + `ASSUME_FPV(PrimRegWeOneHotCheck_ATriggerAfterAlertInit_S, + $stable(rst_ni) == 0 |-> u_state_regs.err_o == 0 [*10]) + +endmodule : flash_macro_wrapper diff --git a/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_pkg.sv b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_pkg.sv new file mode 100644 index 00000000000..60bb1b489ca --- /dev/null +++ b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_pkg.sv @@ -0,0 +1,23 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Flash Wrapper package. +// + +package flash_macro_wrapper_pkg; + + typedef logic [7:0] fla_obs_t; + + // dft_en jtag selection + typedef enum logic [2:0] { + FlashLcTckSel, + FlashLcTdiSel, + FlashLcTmsSel, + FlashLcTdoSel, + FlashBistSel, + FlashLcDftLast + } flash_lc_jtag_e; + +endpackage : flash_macro_wrapper_pkg diff --git a/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_pkg.sv b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_pkg.sv new file mode 100644 index 00000000000..335b328dc94 --- /dev/null +++ b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_pkg.sv @@ -0,0 +1,399 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package flash_macro_wrapper_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 7; + + // Number of registers for every interface + parameter int NumRegs = 21; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + struct packed { + logic [4:0] q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr1_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field7; + struct packed { + logic q; + } field6; + struct packed { + logic q; + } field5; + struct packed { + logic q; + } field4; + struct packed { + logic q; + } field3; + struct packed { + logic q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic q; + } field0; + } flash_macro_wrapper_reg2hw_csr2_reg_t; + + typedef struct packed { + struct packed { + logic [1:0] q; + } field9; + struct packed { + logic [1:0] q; + } field8; + struct packed { + logic [2:0] q; + } field7; + struct packed { + logic q; + } field6; + struct packed { + logic [2:0] q; + } field5; + struct packed { + logic [2:0] q; + } field4; + struct packed { + logic [2:0] q; + } field3; + struct packed { + logic [2:0] q; + } field2; + struct packed { + logic [3:0] q; + } field1; + struct packed { + logic [3:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr3_reg_t; + + typedef struct packed { + struct packed { + logic [2:0] q; + } field3; + struct packed { + logic [2:0] q; + } field2; + struct packed { + logic [2:0] q; + } field1; + struct packed { + logic [2:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr4_reg_t; + + typedef struct packed { + struct packed { + logic [3:0] q; + } field4; + struct packed { + logic [4:0] q; + } field3; + struct packed { + logic [8:0] q; + } field2; + struct packed { + logic [1:0] q; + } field1; + struct packed { + logic [2:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr5_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field8; + struct packed { + logic q; + } field7; + struct packed { + logic [1:0] q; + } field6; + struct packed { + logic [1:0] q; + } field5; + struct packed { + logic [1:0] q; + } field4; + struct packed { + logic [2:0] q; + } field3; + struct packed { + logic [7:0] q; + } field2; + struct packed { + logic [2:0] q; + } field1; + struct packed { + logic [2:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr6_reg_t; + + typedef struct packed { + struct packed { + logic [8:0] q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr7_reg_t; + + typedef struct packed { + logic [31:0] q; + } flash_macro_wrapper_reg2hw_csr8_reg_t; + + typedef struct packed { + logic [31:0] q; + } flash_macro_wrapper_reg2hw_csr9_reg_t; + + typedef struct packed { + logic [31:0] q; + } flash_macro_wrapper_reg2hw_csr10_reg_t; + + typedef struct packed { + logic [31:0] q; + } flash_macro_wrapper_reg2hw_csr11_reg_t; + + typedef struct packed { + logic [9:0] q; + } flash_macro_wrapper_reg2hw_csr12_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field1; + struct packed { + logic [19:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr13_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr14_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr15_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr16_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field1; + struct packed { + logic [7:0] q; + } field0; + } flash_macro_wrapper_reg2hw_csr17_reg_t; + + typedef struct packed { + logic q; + } flash_macro_wrapper_reg2hw_csr18_reg_t; + + typedef struct packed { + logic q; + } flash_macro_wrapper_reg2hw_csr19_reg_t; + + typedef struct packed { + struct packed { + logic q; + } field2; + struct packed { + logic q; + } field1; + struct packed { + logic q; + } field0; + } flash_macro_wrapper_reg2hw_csr20_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } field7; + struct packed { + logic d; + logic de; + } field6; + struct packed { + logic d; + logic de; + } field5; + struct packed { + logic d; + logic de; + } field4; + struct packed { + logic d; + logic de; + } field3; + struct packed { + logic d; + logic de; + } field2; + struct packed { + logic d; + logic de; + } field1; + struct packed { + logic d; + logic de; + } field0; + } flash_macro_wrapper_hw2reg_csr2_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } field2; + struct packed { + logic d; + logic de; + } field1; + struct packed { + logic d; + logic de; + } field0; + } flash_macro_wrapper_hw2reg_csr20_reg_t; + + // Register -> HW type + typedef struct packed { + flash_macro_wrapper_reg2hw_csr1_reg_t csr1; // [325:313] + flash_macro_wrapper_reg2hw_csr2_reg_t csr2; // [312:305] + flash_macro_wrapper_reg2hw_csr3_reg_t csr3; // [304:277] + flash_macro_wrapper_reg2hw_csr4_reg_t csr4; // [276:265] + flash_macro_wrapper_reg2hw_csr5_reg_t csr5; // [264:242] + flash_macro_wrapper_reg2hw_csr6_reg_t csr6; // [241:217] + flash_macro_wrapper_reg2hw_csr7_reg_t csr7; // [216:200] + flash_macro_wrapper_reg2hw_csr8_reg_t csr8; // [199:168] + flash_macro_wrapper_reg2hw_csr9_reg_t csr9; // [167:136] + flash_macro_wrapper_reg2hw_csr10_reg_t csr10; // [135:104] + flash_macro_wrapper_reg2hw_csr11_reg_t csr11; // [103:72] + flash_macro_wrapper_reg2hw_csr12_reg_t csr12; // [71:62] + flash_macro_wrapper_reg2hw_csr13_reg_t csr13; // [61:41] + flash_macro_wrapper_reg2hw_csr14_reg_t csr14; // [40:32] + flash_macro_wrapper_reg2hw_csr15_reg_t csr15; // [31:23] + flash_macro_wrapper_reg2hw_csr16_reg_t csr16; // [22:14] + flash_macro_wrapper_reg2hw_csr17_reg_t csr17; // [13:5] + flash_macro_wrapper_reg2hw_csr18_reg_t csr18; // [4:4] + flash_macro_wrapper_reg2hw_csr19_reg_t csr19; // [3:3] + flash_macro_wrapper_reg2hw_csr20_reg_t csr20; // [2:0] + } flash_macro_wrapper_reg2hw_t; + + // HW -> register type + typedef struct packed { + flash_macro_wrapper_hw2reg_csr2_reg_t csr2; // [21:6] + flash_macro_wrapper_hw2reg_csr20_reg_t csr20; // [5:0] + } flash_macro_wrapper_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR0_REGWEN_OFFSET = 7'h 0; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR1_OFFSET = 7'h 4; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR2_OFFSET = 7'h 8; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR3_OFFSET = 7'h c; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR4_OFFSET = 7'h 10; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR5_OFFSET = 7'h 14; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR6_OFFSET = 7'h 18; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR7_OFFSET = 7'h 1c; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR8_OFFSET = 7'h 20; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR9_OFFSET = 7'h 24; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR10_OFFSET = 7'h 28; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR11_OFFSET = 7'h 2c; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR12_OFFSET = 7'h 30; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR13_OFFSET = 7'h 34; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR14_OFFSET = 7'h 38; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR15_OFFSET = 7'h 3c; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR16_OFFSET = 7'h 40; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR17_OFFSET = 7'h 44; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR18_OFFSET = 7'h 48; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR19_OFFSET = 7'h 4c; + parameter logic [BlockAw-1:0] FLASH_MACRO_WRAPPER_CSR20_OFFSET = 7'h 50; + + // Register index + typedef enum int { + FLASH_MACRO_WRAPPER_CSR0_REGWEN, + FLASH_MACRO_WRAPPER_CSR1, + FLASH_MACRO_WRAPPER_CSR2, + FLASH_MACRO_WRAPPER_CSR3, + FLASH_MACRO_WRAPPER_CSR4, + FLASH_MACRO_WRAPPER_CSR5, + FLASH_MACRO_WRAPPER_CSR6, + FLASH_MACRO_WRAPPER_CSR7, + FLASH_MACRO_WRAPPER_CSR8, + FLASH_MACRO_WRAPPER_CSR9, + FLASH_MACRO_WRAPPER_CSR10, + FLASH_MACRO_WRAPPER_CSR11, + FLASH_MACRO_WRAPPER_CSR12, + FLASH_MACRO_WRAPPER_CSR13, + FLASH_MACRO_WRAPPER_CSR14, + FLASH_MACRO_WRAPPER_CSR15, + FLASH_MACRO_WRAPPER_CSR16, + FLASH_MACRO_WRAPPER_CSR17, + FLASH_MACRO_WRAPPER_CSR18, + FLASH_MACRO_WRAPPER_CSR19, + FLASH_MACRO_WRAPPER_CSR20 + } flash_macro_wrapper_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] FLASH_MACRO_WRAPPER_PERMIT [21] = '{ + 4'b 0001, // index[ 0] FLASH_MACRO_WRAPPER_CSR0_REGWEN + 4'b 0011, // index[ 1] FLASH_MACRO_WRAPPER_CSR1 + 4'b 0001, // index[ 2] FLASH_MACRO_WRAPPER_CSR2 + 4'b 1111, // index[ 3] FLASH_MACRO_WRAPPER_CSR3 + 4'b 0011, // index[ 4] FLASH_MACRO_WRAPPER_CSR4 + 4'b 0111, // index[ 5] FLASH_MACRO_WRAPPER_CSR5 + 4'b 1111, // index[ 6] FLASH_MACRO_WRAPPER_CSR6 + 4'b 0111, // index[ 7] FLASH_MACRO_WRAPPER_CSR7 + 4'b 1111, // index[ 8] FLASH_MACRO_WRAPPER_CSR8 + 4'b 1111, // index[ 9] FLASH_MACRO_WRAPPER_CSR9 + 4'b 1111, // index[10] FLASH_MACRO_WRAPPER_CSR10 + 4'b 1111, // index[11] FLASH_MACRO_WRAPPER_CSR11 + 4'b 0011, // index[12] FLASH_MACRO_WRAPPER_CSR12 + 4'b 0111, // index[13] FLASH_MACRO_WRAPPER_CSR13 + 4'b 0011, // index[14] FLASH_MACRO_WRAPPER_CSR14 + 4'b 0011, // index[15] FLASH_MACRO_WRAPPER_CSR15 + 4'b 0011, // index[16] FLASH_MACRO_WRAPPER_CSR16 + 4'b 0011, // index[17] FLASH_MACRO_WRAPPER_CSR17 + 4'b 0001, // index[18] FLASH_MACRO_WRAPPER_CSR18 + 4'b 0001, // index[19] FLASH_MACRO_WRAPPER_CSR19 + 4'b 0001 // index[20] FLASH_MACRO_WRAPPER_CSR20 + }; + +endpackage diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_top.sv similarity index 93% rename from hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv rename to hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_top.sv index 873559c1c81..e4d877b7fce 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv +++ b/hw/ip/flash_macro_wrapper/rtl/flash_macro_wrapper_reg_top.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -6,20 +7,20 @@ `include "prim_assert.sv" -module flash_ctrl_prim_reg_top ( +module flash_macro_wrapper_reg_top ( input clk_i, input rst_ni, input tlul_pkg::tl_h2d_t tl_i, output tlul_pkg::tl_d2h_t tl_o, // To HW - output flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw, // Write - input flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg, // Read + output flash_macro_wrapper_reg_pkg::flash_macro_wrapper_reg2hw_t reg2hw, // Write + input flash_macro_wrapper_reg_pkg::flash_macro_wrapper_hw2reg_t hw2reg, // Read // Integrity check errors output logic intg_err_o ); - import flash_ctrl_reg_pkg::* ; + import flash_macro_wrapper_reg_pkg::* ; localparam int AW = 7; localparam int DW = 32; @@ -2003,27 +2004,27 @@ module flash_ctrl_prim_reg_top ( logic [20:0] addr_hit; always_comb begin - addr_hit[ 0] = (reg_addr == FLASH_CTRL_CSR0_REGWEN_OFFSET); - addr_hit[ 1] = (reg_addr == FLASH_CTRL_CSR1_OFFSET); - addr_hit[ 2] = (reg_addr == FLASH_CTRL_CSR2_OFFSET); - addr_hit[ 3] = (reg_addr == FLASH_CTRL_CSR3_OFFSET); - addr_hit[ 4] = (reg_addr == FLASH_CTRL_CSR4_OFFSET); - addr_hit[ 5] = (reg_addr == FLASH_CTRL_CSR5_OFFSET); - addr_hit[ 6] = (reg_addr == FLASH_CTRL_CSR6_OFFSET); - addr_hit[ 7] = (reg_addr == FLASH_CTRL_CSR7_OFFSET); - addr_hit[ 8] = (reg_addr == FLASH_CTRL_CSR8_OFFSET); - addr_hit[ 9] = (reg_addr == FLASH_CTRL_CSR9_OFFSET); - addr_hit[10] = (reg_addr == FLASH_CTRL_CSR10_OFFSET); - addr_hit[11] = (reg_addr == FLASH_CTRL_CSR11_OFFSET); - addr_hit[12] = (reg_addr == FLASH_CTRL_CSR12_OFFSET); - addr_hit[13] = (reg_addr == FLASH_CTRL_CSR13_OFFSET); - addr_hit[14] = (reg_addr == FLASH_CTRL_CSR14_OFFSET); - addr_hit[15] = (reg_addr == FLASH_CTRL_CSR15_OFFSET); - addr_hit[16] = (reg_addr == FLASH_CTRL_CSR16_OFFSET); - addr_hit[17] = (reg_addr == FLASH_CTRL_CSR17_OFFSET); - addr_hit[18] = (reg_addr == FLASH_CTRL_CSR18_OFFSET); - addr_hit[19] = (reg_addr == FLASH_CTRL_CSR19_OFFSET); - addr_hit[20] = (reg_addr == FLASH_CTRL_CSR20_OFFSET); + addr_hit[ 0] = (reg_addr == FLASH_MACRO_WRAPPER_CSR0_REGWEN_OFFSET); + addr_hit[ 1] = (reg_addr == FLASH_MACRO_WRAPPER_CSR1_OFFSET); + addr_hit[ 2] = (reg_addr == FLASH_MACRO_WRAPPER_CSR2_OFFSET); + addr_hit[ 3] = (reg_addr == FLASH_MACRO_WRAPPER_CSR3_OFFSET); + addr_hit[ 4] = (reg_addr == FLASH_MACRO_WRAPPER_CSR4_OFFSET); + addr_hit[ 5] = (reg_addr == FLASH_MACRO_WRAPPER_CSR5_OFFSET); + addr_hit[ 6] = (reg_addr == FLASH_MACRO_WRAPPER_CSR6_OFFSET); + addr_hit[ 7] = (reg_addr == FLASH_MACRO_WRAPPER_CSR7_OFFSET); + addr_hit[ 8] = (reg_addr == FLASH_MACRO_WRAPPER_CSR8_OFFSET); + addr_hit[ 9] = (reg_addr == FLASH_MACRO_WRAPPER_CSR9_OFFSET); + addr_hit[10] = (reg_addr == FLASH_MACRO_WRAPPER_CSR10_OFFSET); + addr_hit[11] = (reg_addr == FLASH_MACRO_WRAPPER_CSR11_OFFSET); + addr_hit[12] = (reg_addr == FLASH_MACRO_WRAPPER_CSR12_OFFSET); + addr_hit[13] = (reg_addr == FLASH_MACRO_WRAPPER_CSR13_OFFSET); + addr_hit[14] = (reg_addr == FLASH_MACRO_WRAPPER_CSR14_OFFSET); + addr_hit[15] = (reg_addr == FLASH_MACRO_WRAPPER_CSR15_OFFSET); + addr_hit[16] = (reg_addr == FLASH_MACRO_WRAPPER_CSR16_OFFSET); + addr_hit[17] = (reg_addr == FLASH_MACRO_WRAPPER_CSR17_OFFSET); + addr_hit[18] = (reg_addr == FLASH_MACRO_WRAPPER_CSR18_OFFSET); + addr_hit[19] = (reg_addr == FLASH_MACRO_WRAPPER_CSR19_OFFSET); + addr_hit[20] = (reg_addr == FLASH_MACRO_WRAPPER_CSR20_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -2031,27 +2032,27 @@ module flash_ctrl_prim_reg_top ( // Check sub-word write is permitted always_comb begin wr_err = (reg_we & - ((addr_hit[ 0] & (|(FLASH_CTRL_PRIM_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(FLASH_CTRL_PRIM_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(FLASH_CTRL_PRIM_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(FLASH_CTRL_PRIM_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(FLASH_CTRL_PRIM_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(FLASH_CTRL_PRIM_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(FLASH_CTRL_PRIM_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(FLASH_CTRL_PRIM_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(FLASH_CTRL_PRIM_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(FLASH_CTRL_PRIM_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(FLASH_CTRL_PRIM_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(FLASH_CTRL_PRIM_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(FLASH_CTRL_PRIM_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(FLASH_CTRL_PRIM_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(FLASH_CTRL_PRIM_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(FLASH_CTRL_PRIM_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(FLASH_CTRL_PRIM_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(FLASH_CTRL_PRIM_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(FLASH_CTRL_PRIM_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(FLASH_CTRL_PRIM_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(FLASH_CTRL_PRIM_PERMIT[20] & ~reg_be))))); + ((addr_hit[ 0] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(FLASH_MACRO_WRAPPER_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(FLASH_MACRO_WRAPPER_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(FLASH_MACRO_WRAPPER_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(FLASH_MACRO_WRAPPER_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(FLASH_MACRO_WRAPPER_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(FLASH_MACRO_WRAPPER_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(FLASH_MACRO_WRAPPER_PERMIT[15] & ~reg_be))) | + (addr_hit[16] & (|(FLASH_MACRO_WRAPPER_PERMIT[16] & ~reg_be))) | + (addr_hit[17] & (|(FLASH_MACRO_WRAPPER_PERMIT[17] & ~reg_be))) | + (addr_hit[18] & (|(FLASH_MACRO_WRAPPER_PERMIT[18] & ~reg_be))) | + (addr_hit[19] & (|(FLASH_MACRO_WRAPPER_PERMIT[19] & ~reg_be))) | + (addr_hit[20] & (|(FLASH_MACRO_WRAPPER_PERMIT[20] & ~reg_be))))); end // Generate write-enables diff --git a/hw/ip/prim_generic/rtl/prim_flash.sv b/hw/ip/prim_generic/rtl/prim_flash.sv deleted file mode 100644 index ad6dd0e8539..00000000000 --- a/hw/ip/prim_generic/rtl/prim_flash.sv +++ /dev/null @@ -1,148 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Overall flash wrapper -// - -module prim_flash #( - parameter int NumBanks = 2, // number of banks - parameter int InfosPerBank = 1, // info pages per bank - parameter int InfoTypes = 1, // different info types - parameter int InfoTypesWidth = 1, // different info types - parameter int PagesPerBank = 256,// data pages per bank - parameter int WordsPerPage = 256,// words per page - parameter int DataWidth = 32, // bits per word - parameter int TestModeWidth = 2 -) ( - input clk_i, - input rst_ni, - input flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] flash_req_i, - output flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] flash_rsp_o, - output logic [flash_phy_pkg::ProgTypes-1:0] prog_type_avail_o, - output init_busy_o, - input tck_i, - input tdi_i, - input tms_i, - output logic tdo_o, - input prim_mubi_pkg::mubi4_t bist_enable_i, - input prim_mubi_pkg::mubi4_t scanmode_i, - input scan_en_i, - input scan_rst_ni, - input flash_power_ready_h_i, - input flash_power_down_h_i, - inout [TestModeWidth-1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - output logic flash_err_o, - // Alert indication (to be connected to alert sender in the instantiating IP) - output logic fatal_alert_o, - output logic recov_alert_o, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // Observability - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o -); - - // convert this into a tlul write later - logic init; - assign init = 1'b1; - - logic [NumBanks-1:0] init_busy; - assign init_busy_o = |init_busy; - - // this represents the type of program operations that are supported - assign prog_type_avail_o[flash_ctrl_top_specific_pkg::FlashProgNormal] = 1'b1; - assign prog_type_avail_o[flash_ctrl_top_specific_pkg::FlashProgRepair] = 1'b1; - - for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_prim_flash_banks - - prim_generic_flash_bank #( - .InfosPerBank(InfosPerBank), - .InfoTypes(InfoTypes), - .InfoTypesWidth(InfoTypesWidth), - .PagesPerBank(PagesPerBank), - .WordsPerPage(WordsPerPage), - .DataWidth(DataWidth) - ) u_prim_flash_bank ( - .clk_i, - .rst_ni, - .rd_i(flash_req_i[bank].rd_req), - .prog_i(flash_req_i[bank].prog_req), - .prog_last_i(flash_req_i[bank].prog_last), - .prog_type_i(flash_req_i[bank].prog_type), - .pg_erase_i(flash_req_i[bank].pg_erase_req), - .bk_erase_i(flash_req_i[bank].bk_erase_req), - .erase_suspend_req_i(flash_req_i[bank].erase_suspend_req), - .he_i(flash_req_i[bank].he), - .addr_i(flash_req_i[bank].addr), - .part_i(flash_req_i[bank].part), - .info_sel_i(flash_req_i[bank].info_sel), - .prog_data_i(flash_req_i[bank].prog_full_data), - .ack_o(flash_rsp_o[bank].ack), - .done_o(flash_rsp_o[bank].done), - .rd_data_o(flash_rsp_o[bank].rdata), - .init_i(init), - .init_busy_o(init_busy[bank]), - .flash_power_ready_h_i, - .flash_power_down_h_i - ); - end - - logic unused_scanmode; - logic unused_scan_en; - logic unused_scan_rst_n; - logic [TestModeWidth-1:0] unused_flash_test_mode; - logic unused_flash_test_voltage; - logic unused_tck; - logic unused_tdi; - logic unused_tms; - - assign unused_scanmode = ^scanmode_i; - assign unused_scan_en = scan_en_i; - assign unused_scan_rst_n = scan_rst_ni; - assign unused_flash_test_mode = flash_test_mode_a_io; - assign unused_flash_test_voltage = flash_test_voltage_h_io; - assign unused_tck = tck_i; - assign unused_tdi = tdi_i; - assign unused_tms = tms_i; - assign tdo_o = '0; - - //////////////////////////////////// - // TL-UL Test Interface Emulation // - //////////////////////////////////// - - logic intg_err; - flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw; - flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg; - flash_ctrl_prim_reg_top u_reg_top ( - .clk_i, - .rst_ni, - .tl_i (tl_i), - .tl_o (tl_o), - .reg2hw (reg2hw), - .hw2reg (hw2reg), - .intg_err_o(intg_err) - ); - - logic unused_reg_sig; - assign unused_reg_sig = ^reg2hw; - assign hw2reg = '0; - - logic unused_bist_enable; - assign unused_bist_enable = ^bist_enable_i; - - // open source model has no error response at the moment - assign flash_err_o = 1'b0; - - assign fatal_alert_o = intg_err; - assign recov_alert_o = 1'b0; - - logic unused_obs; - assign unused_obs = |obs_ctrl_i; - assign fla_obs_o = '0; - - `ASSERT_PRIM_REG_WE_ONEHOT_ERROR_TRIGGER_ALERT(PrimRegWeOnehotCheck_A, - u_reg_top, flash_ctrl.alert_tx_o[3]) - -endmodule // prim_flash diff --git a/hw/ip_templates/flash_ctrl/README.md.tpl b/hw/ip_templates/flash_ctrl/README.md.tpl index 0fc516d338d..2c8cf798e0c 100644 --- a/hw/ip_templates/flash_ctrl/README.md.tpl +++ b/hw/ip_templates/flash_ctrl/README.md.tpl @@ -1,3 +1,8 @@ +## Copyright lowRISC contributors (OpenTitan project). +## Copyright zeroRISC Inc. +## Licensed under the Apache License, Version 2.0, see LICENSE for details. +## SPDX-License-Identifier: Apache-2.0 +## # Flash Controller HWIP Technical Specification [`flash_ctrl`](https://reports.opentitan.org/hw/top_${topname}/ip_autogen/flash_ctrl/dv/latest/report.html): @@ -193,3 +198,14 @@ During production and RMA states, the isolated page is also readable. * Both `lc_iso_part_sw_wr_en` and `lc_iso_part_sw_rd_en` are set. See [life cycle](../../../ip/lc_ctrl/README.md#iso_part_sw_rd_en-and-iso_part_sw_wr_en) for more details + +${"##"} IP Blocks Organization + +The flash macro wrapper is provided by a separate IP block that is directly instantiated under the top level. +As such it has its own IP documentation (https://opentitan.org/book/hw/ip/flash_macro_wrapper/index.html). +This split allows the controller to be independent of low level testing and vendor specific interfaces to the Flash Macro. +It makes it simpler to make changes for different vendor flash macros. + +In terms of the top generation (https://opentitan.org/book/util/topgen/index.html#overview), the controller is an ipgen peripheral, while the macro is generic. +The controller can be generated with different parameters that directly affect the macro. +The macro wrapper is parameterized at the top-level so that it matches the controller's configuration. diff --git a/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl b/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl index 77facbbfdaa..f8bf18ba484 100644 --- a/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl +++ b/hw/ip_templates/flash_ctrl/data/flash_ctrl.hjson.tpl @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -21,7 +22,7 @@ one_line_desc: "Interfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe", one_paragraph_desc: ''' Flash Controller interfaces the integrated, non-volatile flash memory with software and other hardware components in the system, such as Life Cycle Controller, Key Manager, and OTP Controller. - It consists of the open source flash controller that interfaces with a third party flash module. + It consists of the open source flash controller that interfaces with a third party flash macro. The protocol controller handles read, program, and erase requests, as well as life cycle RMA entry. It supports differentiation between informational and data flash partitions, flash memory protection at page boundaries, and the handling of key manager secrets inaccessible to software. The actual physical controller is highly parameterized (number of banks, number of pages for each bank, number of words and word size for each page, and number of read buffers) and supports XEX scrambling configurable by software, as well as two types of ECC support configurable on a page boundary. @@ -54,17 +55,9 @@ ] bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.u_reg_top"} { protocol: "tlul", direction: "device", name: "mem" } ], - available_input_list: [ - { name: "tck", desc: "jtag clock" }, - { name: "tms", desc: "jtag tms" }, - { name: "tdi", desc: "jtag input" }, - ], - available_output_list: [ - { name: "tdo", desc: "jtag output" }, - ], + interrupt_list: [ // The first two status interrupts assert by default, since the FIFO is empty. // This is captured in the Hjson via the `default` key so that automatically generated tests can incorporate this information. @@ -111,46 +104,6 @@ package: "otp_ctrl_pkg" }, - { struct: "lc_tx", - package: "lc_ctrl_pkg", - type: "uni" - act: "rcv" - name: "lc_nvm_debug_en" - }, - - { struct: "mubi4" - package: "prim_mubi_pkg" - type: "uni" - act: "rcv" - name: "flash_bist_enable" - }, - - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_down_h" - }, - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_ready_h" - }, - { struct: "", - package: "", - width: "2", - type: "io" - act: "none" - name: "flash_test_mode_a" - }, - { struct: "", - package: "", - type: "io" - act: "none" - name: "flash_test_voltage_h" - }, - { struct: "lc_tx" type: "uni" name: "lc_creator_seed_sw_rw_en" @@ -226,24 +179,25 @@ name: "keymgr", act: "req", package: "flash_ctrl_pkg" - } - - { struct: "ast_obs_ctrl", - type: "uni", - name: "obs_ctrl", - act: "rcv", - package: "ast_pkg" - } + }, - { struct: "logic", - type: "uni", - name: "fla_obs", - act: "req", - width: "8", - package: "" - } + { struct: "flash_phy_macro", + type: "req_rsp", + name: "flash_macro", + act: "req", + package: "flash_phy_macro_pkg", + desc: "Data interface to the flash macro wrapper" + }, + { struct: "flash_macro_status", + type: "uni", + name: "flash_macro_status", + act: "rcv", + package: "flash_phy_macro_pkg", + desc: "Status interface from the flash macro wrapper" + }, ], + countermeasures: [ { name: "REG.BUS.INTEGRITY", desc: ''' @@ -397,9 +351,6 @@ } ] - scan: "true", // Enable `scanmode_i` port - scan_en: "true", // Enable `scan_en_i` port - scan_reset: "true", // Enable `scan_rst_ni` port param_list: [ // The reg parameters can be modified directly through top_*.hjson. // The template will automatically propagate the appropriate values. @@ -1832,867 +1783,6 @@ }, ], - prim: [ - { - name: "CSR0_REGWEN", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw0c", - hwaccess: "none", - resval: "1", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR1", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "12:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR2", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "3", - name: "field3", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4", - name: "field4", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5", - name: "field5", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "6", - name: "field6", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7", - name: "field7", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR3", - desc: "", - fields: [ - { - bits: "3:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7:4", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "10:8", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:11", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "19:17", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23:21", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "25:24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "27:26", - name: "field9", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR4", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "11:9", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR5", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:5", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:19", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR6", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:17", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20:19", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:21", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR7", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR8", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR9", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR10", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR11", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR12", - desc: "", - fields: [ - { - bits: "9:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR13", - desc: "", - fields: [ - { - bits: "19:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR14", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR15", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR16", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR17", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR18", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR19", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR20", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "ro", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - } - ], } memory: { mem: {} diff --git a/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov.core.tpl b/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov.core.tpl index 9ea3b482c99..5dc9de80c70 100644 --- a/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov.core.tpl +++ b/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov.core.tpl @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: ${instance_vlnv("lowrisc:dv:flash_ctrl_cov")} @@ -9,6 +10,7 @@ filesets: files_dv: depend: - lowrisc:dv:dv_utils + - lowrisc:ip:flash_macro_wrapper - ${instance_vlnv("lowrisc:ip:flash_ctrl")} files: - flash_ctrl_cov_bind.sv diff --git a/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv b/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv index 4c20c8dd914..2de0af16b01 100644 --- a/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv +++ b/hw/ip_templates/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv @@ -1,25 +1,33 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Binds FLASH_CTRL functional coverage interface to the top level FLASH_CTRL module. -`define FLASH_COV_LC_TX_BIND(__name) \ +// Binds LC_TX functional coverage interface to the top level FLASH_CTRL module. +`define FLASH_CTRL_COV_LC_TX_BIND(__name) \ bind flash_ctrl cip_lc_tx_cov_if u_``__name``_cov_if( \ .rst_ni (rst_ni), \ .val (``__name``_i) \ ); +// Binds LC_TX functional coverage interface to the top level FLASH_MACRO_WRAPPER module. +`define FLASH_MACRO_COV_LC_TX_BIND(__name) \ + bind flash_macro_wrapper cip_lc_tx_cov_if u_``__name``_cov_if( \ + .rst_ni (rst_ni), \ + .val (``__name``_i) \ + ); + module flash_ctrl_cov_bind; - `FLASH_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) - `FLASH_COV_LC_TX_BIND(lc_seed_hw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_escalate_en) - `FLASH_COV_LC_TX_BIND(lc_nvm_debug_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_seed_hw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_escalate_en) + `FLASH_MACRO_COV_LC_TX_BIND(lc_nvm_debug_en) - bind prim_generic_flash_bank flash_ctrl_phy_cov_if u_phy_cov_if + bind flash_macro_bank flash_ctrl_phy_cov_if u_phy_cov_if ( .clk_i(clk_i), .rst_ni(rst_ni), diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core.tpl b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core.tpl index 98312786c88..b4391ebac5f 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core.tpl +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env.core.tpl @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: ${instance_vlnv("lowrisc:dv:flash_ctrl_env:0.1")} @@ -16,6 +17,7 @@ filesets: - lowrisc:dv:mem_bkdr_util - ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg")} - ${instance_vlnv("lowrisc:constants:top_pkg")} + - lowrisc:dv:flash_macro_wrapper_env files: - flash_ctrl_eflash_ral_pkg.sv - flash_ctrl_env_pkg.sv diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv index 23f71cb546e..300019d23c6 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 typedef class flash_ctrl_scoreboard; @@ -28,7 +29,6 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( // interface virtual flash_ctrl_if flash_ctrl_vif; virtual clk_rst_if clk_rst_vif_flash_ctrl_eflash_reg_block; - virtual clk_rst_if clk_rst_vif_flash_ctrl_prim_reg_block; virtual flash_ctrl_mem_if flash_ctrl_mem_vif[NumBanks]; // knobs @@ -283,7 +283,7 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( endfunction // get_region_from_info virtual function void initialize(addr_t csr_base_addr = '1); - string prim_ral_name = "flash_ctrl_prim_reg_block"; + string prim_ral_name = "flash_macro_wrapper_reg_block"; string fast_rcvr_name = ""; list_of_alerts = flash_ctrl_env_pkg::LIST_OF_ALERTS; @@ -594,13 +594,13 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( data_4s_t loc_data = (scheme == FlashMemInitCustom) ? data[i] : (scheme == FlashMemInitRandomize) ? $urandom() : wr_data; - _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); `uvm_info(`gfn, $sformatf( "flash_mem_bkdr_write: partition = %s, {%s} = 0x%0h", flash_op.partition.name(), addr_attrs.sprint(), loc_data - ), UVM_HIGH) + ), UVM_MEDIUM) + _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); // update the scoreboard on backdoor-programs as well mem_data[0] = loc_data; diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv index ae9842cc4e0..4cebe708137 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -15,7 +16,7 @@ package flash_ctrl_env_pkg; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_core_ral_pkg::*; import flash_ctrl_eflash_ral_pkg::*; - import flash_ctrl_prim_ral_pkg::*; + import flash_macro_wrapper_ral_pkg::*; import flash_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import prim_mubi_pkg::*; @@ -441,7 +442,9 @@ package flash_ctrl_env_pkg; end endfunction // flash_otf_print_data64 - function automatic flash_dv_part_e get_part_name(flash_phy_pkg::flash_phy_prim_flash_req_t req); + function automatic flash_dv_part_e get_part_name( + input flash_phy_macro_pkg::flash_phy_macro_bank_req_t req + ); flash_dv_part_e part; if (req.part == 0) return FlashPartData; diff --git a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_mem_if.sv b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_mem_if.sv index 33bdf2f7a37..ea8904d3366 100644 --- a/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_mem_if.sv +++ b/hw/ip_templates/flash_ctrl/dv/env/flash_ctrl_mem_if.sv @@ -1,16 +1,17 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -import flash_ctrl_top_specific_pkg::*; + interface flash_ctrl_mem_if ( input logic clk_i, input logic rst_ni, input logic data_mem_req, input logic mem_wr, - input logic [BankAddrW-1:0] mem_addr, - input logic [flash_phy_pkg::FullDataWidth-1:0] mem_wdata, - input flash_part_e mem_part, - input logic [InfoTypesWidth-1:0] mem_info_sel, + input logic [flash_phy_macro_pkg::BankAddrW-1:0] mem_addr, + input logic [flash_phy_macro_pkg::DataWidth-1:0] mem_wdata, + input flash_ctrl_pkg::flash_part_e mem_part, + input logic [flash_phy_macro_pkg::InfoTypesWidth-1:0] mem_info_sel, input logic info0_mem_req, input logic info1_mem_req, input logic info2_mem_req diff --git a/hw/ip_templates/flash_ctrl/dv/tb/tb.sv b/hw/ip_templates/flash_ctrl/dv/tb/tb.sv index c6a53be8537..e415644116e 100644 --- a/hw/ip_templates/flash_ctrl/dv/tb/tb.sv +++ b/hw/ip_templates/flash_ctrl/dv/tb/tb.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,10 +8,14 @@ module tb; import uvm_pkg::*; import top_pkg::*; import dv_utils_pkg::*; + import flash_ctrl_pkg::*; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_env_pkg::*; import flash_ctrl_test_pkg::*; import flash_ctrl_bkdr_util_pkg::flash_ctrl_bkdr_util; + import flash_phy_macro_pkg::flash_phy_macro_req_t; + import flash_phy_macro_pkg::flash_phy_macro_rsp_t; + import flash_phy_macro_pkg::flash_macro_status_t; // macro includes `include "uvm_macros.svh" @@ -39,6 +44,9 @@ module tb; wire intr_op_done; wire intr_err; wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + flash_phy_macro_req_t flash_macro_req; + flash_phy_macro_rsp_t flash_macro_rsp; + flash_macro_status_t flash_macro_status; ast_pkg::ast_obs_ctrl_t obs_ctrl; @@ -73,9 +81,9 @@ module tb; .rst_n(rst_n) ); - `define FLASH_DEVICE_HIER tb.dut.u_eflash.u_flash - assign fpp_if.req = `FLASH_DEVICE_HIER.flash_req_i; - assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_rsp_o; + `define FLASH_DEVICE_HIER tb.flash_macro_wrapper + assign fpp_if.req = `FLASH_DEVICE_HIER.flash_i; + assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_o; for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_bank_loop assign fpp_if.rreq[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.req_i; assign fpp_if.rdy[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.rdy_o; @@ -142,11 +150,9 @@ module tb; .clk_otp_i (clk), .rst_otp_ni (rst_n), - // various tlul interfaces + // tlul interfaces .core_tl_i(tl_if.h2d), .core_tl_o(tl_if.d2h), - .prim_tl_i(prim_tl_if.h2d), - .prim_tl_o(prim_tl_if.d2h), .mem_tl_i (eflash_tl_if.h2d), .mem_tl_o (eflash_tl_if.d2h), @@ -160,7 +166,6 @@ module tb; .lc_iso_part_sw_rd_en_i (flash_ctrl_if.lc_iso_part_sw_rd_en), .lc_iso_part_sw_wr_en_i (flash_ctrl_if.lc_iso_part_sw_wr_en), .lc_seed_hw_rd_en_i (flash_ctrl_if.lc_seed_hw_rd_en), - .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), .lc_escalate_en_i (flash_ctrl_if.lc_escalate_en), // life cycle rma handling @@ -173,23 +178,9 @@ module tb; .keymgr_o(flash_ctrl_if.keymgr), // flash prim signals - .flash_power_ready_h_i (flash_ctrl_if.power_ready_h), - .flash_power_down_h_i (flash_power_down_h), - .flash_bist_enable_i (prim_mubi_pkg::MuBi4False), - .flash_test_mode_a_io (flash_test_mode_a), - .flash_test_voltage_h_io(flash_test_v), - - // test - .scanmode_i (prim_mubi_pkg::MuBi4False), - .scan_rst_ni('0), - .scan_en_i ('0), - - // JTAG - .cio_tck_i (flash_ctrl_if.cio_tck), - .cio_tms_i (flash_ctrl_if.cio_tms), - .cio_tdi_i (flash_ctrl_if.cio_tdi), - .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), - .cio_tdo_o (flash_ctrl_if.cio_tdo), + .flash_macro_o (flash_macro_req), + .flash_macro_i (flash_macro_rsp), + .flash_macro_status_i (flash_macro_status), // alerts and interrupts .intr_prog_empty_o(intr_prog_empty), @@ -199,12 +190,43 @@ module tb; .intr_op_done_o (intr_op_done), .intr_corr_err_o (intr_err), .alert_rx_i (alert_rx), - .alert_tx_o (alert_tx), + .alert_tx_o (alert_tx) - // Observability - .obs_ctrl_i(obs_ctrl), - .fla_obs_o ( ) + ); + flash_macro_wrapper #( + .NumBanks(flash_phy_macro_pkg::NumBanks), + .InfosPerBank(flash_phy_macro_pkg::InfosPerBank), + .InfoTypes(flash_phy_macro_pkg::InfoTypes), + .InfoTypesWidth(flash_phy_macro_pkg::InfoTypesWidth), + .PagesPerBank(flash_phy_macro_pkg::PagesPerBank), + .WordsPerPage(flash_phy_macro_pkg::WordsPerPage), + .DataWidth(flash_phy_pkg::FullDataWidth) + ) flash_macro_wrapper ( + .clk_i (clk), + .rst_ni (rst_n), + .tl_i (prim_tl_if.h2d), + .tl_o (prim_tl_if.d2h), + .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), + .flash_i (flash_macro_req), + .flash_o (flash_macro_rsp), + .status_o (flash_macro_status), + // JTAG + .cio_tck_i (flash_ctrl_if.cio_tck), + .cio_tms_i (flash_ctrl_if.cio_tms), + .cio_tdi_i (flash_ctrl_if.cio_tdi), + .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), + .cio_tdo_o (flash_ctrl_if.cio_tdo), + .bist_enable_i(prim_mubi_pkg::MuBi4False), + .obs_ctrl_i (obs_ctrl), + .fla_obs_o ( ), + .scanmode_i (prim_mubi_pkg::MuBi4False), + .scan_en_i ('0), + .scan_rst_ni ('0), + .power_ready_h_i (flash_ctrl_if.power_ready_h), + .power_down_h_i (flash_power_down_h), + .test_mode_a_io (flash_test_mode_a), + .test_voltage_h_io (flash_test_v) ); // Create edge in flash_power_down_h_i, whenever reset is asserted @@ -243,25 +265,22 @@ module tb; // // For eflash of a specific vendor implementation, set the hierarchy to the memory element // correctly when creating these instances in the extended testbench. - `define FLASH_BANK_HIER(i) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank + `define FLASH_BANK_HIER(i) \ + tb.flash_macro_wrapper.gen_flash_banks[i].u_flash_macro_bank - `define FLASH_DATA_MEM_HIER(i) \ + `define FLASH_DATA_MEM_HIER(i) \ `FLASH_BANK_HIER(i).u_mem.mem - `define FLASH_DATA_MEM_HIER_STR(i) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.mem"}, i) + `define FLASH_DATA_MEM_HIER_STR(i) \ + $sformatf("tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.u_mem.mem", i) - `define FLASH_INFO_MEM_HIER(i, j) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank.gen_info_types[j].u_info_mem.mem + `define FLASH_INFO_MEM_HIER(i, j) \ + tb.flash_macro_wrapper.gen_flash_banks[i]. \ + u_flash_macro_bank.gen_info_types[j].u_info_mem.mem - `define FLASH_INFO_MEM_HIER_STR(i, j) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.gen_info_types[%0d].", \ - "u_info_mem.mem"}, i, j) + `define FLASH_INFO_MEM_HIER_STR(i, j) \ + $sformatf({"tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.", \ + "gen_info_types[%0d].u_info_mem.mem"}, i, j) if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_generic for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_each_bank @@ -276,6 +295,9 @@ module tb; .n_bits($bits(`FLASH_DATA_MEM_HIER(i))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d part=%s fails", i, part.name()), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -291,6 +313,9 @@ module tb; .n_bits($bits(`FLASH_INFO_MEM_HIER(i, j))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d, part=%s, info=%0d fails", i, part.name(), j), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -337,7 +362,8 @@ module tb; uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif_flash_ctrl_eflash_reg_block", clk_rst_if); uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", - "clk_rst_vif_flash_ctrl_prim_reg_block", clk_rst_if); + "clk_rst_vif_flash_macro_wrapper_reg_block", + clk_rst_if); uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shadowed_if); @@ -346,8 +372,8 @@ module tb; tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_eflash_reg_block*", "vif", eflash_tl_if); - uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_prim_reg_block*", "vif", - prim_tl_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_macro_wrapper_reg_block*", + "vif", prim_tl_if); uvm_config_db#(virtual flash_ctrl_if)::set(null, "*.env", "flash_ctrl_vif", flash_ctrl_if); uvm_config_db#(virtual flash_phy_prim_if)::set(null, "*.env.m_fpp_agent*", "vif", fpp_if); $timeformat(-9, 1, " ns", 9); diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl index 618663a4449..460a8253296 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl.core.tpl @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: ${instance_vlnv("lowrisc:ip:flash_ctrl:0.1")} @@ -8,11 +9,14 @@ description: "Flash Controller" filesets: files_rtl: depend: + - ${instance_vlnv("lowrisc:ip:flash_phy_macro_pkg")} + - ${instance_vlnv("lowrisc:ip:flash_phy_pkg")} + - ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg")} - lowrisc:ip:tlul + - lowrisc:ip:flash_macro_wrapper - lowrisc:prim:all - lowrisc:prim:count - lowrisc:prim:edge_detector - - lowrisc:prim:flash - lowrisc:prim:flop_2sync - lowrisc:prim:gf_mult - lowrisc:prim:lc_sync @@ -22,7 +26,6 @@ filesets: # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:ip:otp_ctrl_pkg - - ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg")} - ${instance_vlnv("lowrisc:ip:flash_ctrl_reg")} - ${instance_vlnv("lowrisc:constants:top_pkg")} - lowrisc:ip:jtag_pkg diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl_top_specific_pkg.core.tpl b/hw/ip_templates/flash_ctrl/flash_ctrl_top_specific_pkg.core.tpl index 449888cb64f..00c9885aace 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl_top_specific_pkg.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_ctrl_top_specific_pkg.core.tpl @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg:0.1")} @@ -17,13 +18,11 @@ filesets: - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - lowrisc:tlul:headers - - lowrisc:ip:flash_ctrl_pkg - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" files: - rtl/flash_ctrl_reg_pkg.sv - rtl/flash_ctrl_top_specific_pkg.sv - - rtl/flash_phy_pkg.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core.tpl b/hw/ip_templates/flash_ctrl/flash_phy_macro_pkg.core.tpl similarity index 51% rename from hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core.tpl rename to hw/ip_templates/flash_ctrl/flash_phy_macro_pkg.core.tpl index 1d0c5430d9c..143006b70ce 100644 --- a/hw/ip_templates/flash_ctrl/flash_ctrl_prim_reg_top.core.tpl +++ b/hw/ip_templates/flash_ctrl/flash_phy_macro_pkg.core.tpl @@ -1,30 +1,24 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: ${instance_vlnv("lowrisc:ip:flash_ctrl_prim_reg_top:1.0")} -description: "Generic register top for the FLASH wrapper" +name: ${instance_vlnv("lowrisc:ip:flash_phy_macro_pkg:0.1")} +description: "Flash phy interface to flash macro" virtual: - - lowrisc:virtual_ip:flash_ctrl_prim_reg_top + - lowrisc:virtual_ip:flash_phy_macro_pkg filesets: files_rtl: depend: + - lowrisc:ip:tlul - ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg")} - - lowrisc:prim:subreg +# - ${instance_vlnv("lowrisc:ip:flash_phy_pkg")} files: - - rtl/flash_ctrl_prim_reg_top.sv + - rtl/flash_phy_macro_pkg.sv file_type: systemVerilogSource - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - - targets: - default: &default_target + default: filesets: - files_rtl - toplevel: lc_ctrl diff --git a/hw/ip_templates/flash_ctrl/flash_phy_pkg.core.tpl b/hw/ip_templates/flash_ctrl/flash_phy_pkg.core.tpl new file mode 100644 index 00000000000..73092271e07 --- /dev/null +++ b/hw/ip_templates/flash_ctrl/flash_phy_pkg.core.tpl @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: ${instance_vlnv("lowrisc:ip:flash_phy_pkg:0.1")} +description: "Top specific flash phy package" +virtual: + - lowrisc:virtual_ip:flash_phy_pkg + +filesets: + files_rtl: + depend: + - ${instance_vlnv("lowrisc:ip:flash_ctrl_top_specific_pkg")} + - ${instance_vlnv("lowrisc:ip:flash_phy_macro_pkg")} + files: + - rtl/flash_phy_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl index a23f2a230c7..1da3723f7e1 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl.sv.tpl @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -39,13 +40,10 @@ module flash_ctrl input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i, input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i, input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, // Bus Interface input tlul_pkg::tl_h2d_t core_tl_i, output tlul_pkg::tl_d2h_t core_tl_o, - input tlul_pkg::tl_h2d_t prim_tl_i, - output tlul_pkg::tl_d2h_t prim_tl_o, input tlul_pkg::tl_h2d_t mem_tl_i, output tlul_pkg::tl_d2h_t mem_tl_o, @@ -59,13 +57,6 @@ module flash_ctrl output pwrmgr_pkg::pwr_flash_t pwrmgr_o, output keymgr_flash_t keymgr_o, - // IOs - input cio_tck_i, - input cio_tms_i, - input cio_tdi_i, - output logic cio_tdo_en_o, - output logic cio_tdo_o, - // Interrupts output logic intr_corr_err_o, // Correctable errors encountered output logic intr_prog_empty_o, // Program fifo is empty @@ -74,23 +65,14 @@ module flash_ctrl output logic intr_rd_lvl_o, // Read fifo is full output logic intr_op_done_o, // Requested flash operation (wr/erase) done + // Flash macro interface + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_i, + input flash_phy_macro_pkg::flash_macro_status_t flash_macro_status_i, + // Alerts input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, - - // Observability - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - - // Flash test interface - input scan_en_i, - input prim_mubi_pkg::mubi4_t scanmode_i, - input scan_rst_ni, - input prim_mubi_pkg::mubi4_t flash_bist_enable_i, - input flash_power_down_h_i, - input flash_power_ready_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io + output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o ); ////////////////////////////////////////////////////////// @@ -900,12 +882,6 @@ module flash_ctrl assign flash_phy_req.rand_data_key = rand_data_key; assign flash_phy_req.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q; assign flash_phy_req.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q; - assign flash_phy_req.jtag_req.tck = cio_tck_i; - assign flash_phy_req.jtag_req.tms = cio_tms_i; - assign flash_phy_req.jtag_req.tdi = cio_tdi_i; - assign flash_phy_req.jtag_req.trst_n = '0; - assign cio_tdo_o = flash_phy_rsp.jtag_rsp.tdo; - assign cio_tdo_en_o = flash_phy_rsp.jtag_rsp.tdo_oe; assign flash_rd_err = flash_phy_rsp.rd_err; assign flash_rd_data = flash_phy_rsp.rd_data; assign flash_phy_busy = flash_phy_rsp.init_busy; @@ -934,12 +910,11 @@ module flash_ctrl logic [NumAlerts-1:0] alert_srcs; logic [NumAlerts-1:0] alert_tests; - logic fatal_prim_flash_alert, recov_prim_flash_alert; // An excessive number of recoverable errors may also indicate an attack logic recov_err; assign recov_err = (sw_ctrl_done & |sw_ctrl_err) | - flash_phy_rsp.macro_err | + flash_macro_status_i.flash_err | update_err; logic fatal_err; @@ -952,8 +927,8 @@ module flash_ctrl assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err); assign alert_srcs = { - recov_prim_flash_alert, - fatal_prim_flash_alert, + flash_macro_status_i.recov_alert, + flash_macro_status_i.fatal_alert, fatal_err, fatal_std_err, recov_err @@ -1084,7 +1059,7 @@ module flash_ctrl assign hw2reg.err_code.prog_win_err.de = sw_ctrl_err.prog_win_err; assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err; assign hw2reg.err_code.update_err.de = update_err; - assign hw2reg.err_code.macro_err.de = flash_phy_rsp.macro_err; + assign hw2reg.err_code.macro_err.de = flash_macro_status_i.flash_err; assign hw2reg.err_addr.d = {ctrl_err_addr, {BusByteWidth{1'h0}}}; assign hw2reg.err_addr.de = sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | @@ -1355,21 +1330,10 @@ module flash_ctrl .host_rdata_o (flash_host_rdata), .flash_ctrl_i (flash_phy_req), .flash_ctrl_o (flash_phy_rsp), - .tl_i (prim_tl_i), - .tl_o (prim_tl_o), - .obs_ctrl_i, - .fla_obs_o, - .lc_nvm_debug_en_i, - .flash_bist_enable_i, - .flash_power_down_h_i, - .flash_power_ready_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .fatal_prim_flash_alert_o(fatal_prim_flash_alert), - .recov_prim_flash_alert_o(recov_prim_flash_alert), - .scanmode_i, - .scan_en_i, - .scan_rst_ni + .flash_macro_req_o (flash_macro_o), + .flash_macro_rsp_i (flash_macro_i), + .prog_type_avail_i (flash_macro_status_i.prog_type_avail), + .init_busy_i (flash_macro_status_i.init_busy) ); ///////////////////////////////// @@ -1379,9 +1343,6 @@ module flash_ctrl `ASSERT_KNOWN(TlDValidKnownO_A, core_tl_o.d_valid ) `ASSERT_KNOWN(TlAReadyKnownO_A, core_tl_o.a_ready ) `ASSERT_KNOWN_IF(RspPayLoad_A, core_tl_o, core_tl_o.d_valid) - `ASSERT_KNOWN(PrimTlDValidKnownO_A, prim_tl_o.d_valid ) - `ASSERT_KNOWN(PrimTlAReadyKnownO_A, prim_tl_o.a_ready ) - `ASSERT_KNOWN_IF(PrimRspPayLoad_A, prim_tl_o, prim_tl_o.d_valid) `ASSERT_KNOWN(MemTlDValidKnownO_A, mem_tl_o.d_valid ) `ASSERT_KNOWN(MemTlAReadyKnownO_A, mem_tl_o.a_ready ) `ASSERT_KNOWN_IF(MemRspPayLoad_A, mem_tl_o, mem_tl_o.d_valid) @@ -1397,8 +1358,6 @@ module flash_ctrl `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o ) `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o ) `ASSERT_KNOWN(IntrErrO_A, intr_corr_err_o ) - `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o ) - `ASSERT(TdoEnIsOne_A, cio_tdo_en_o === 1'b1) // combined indication that an operation has started // This is used only for assertions diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_prog.sv b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_prog.sv index 235bf9effaf..ee9c5a687f7 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_prog.sv +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_prog.sv @@ -1,11 +1,15 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // // Faux Flash Prog Control // -module flash_ctrl_prog import flash_ctrl_top_specific_pkg::*; ( +module flash_ctrl_prog + import flash_ctrl_pkg::*; + import flash_ctrl_top_specific_pkg::*; +( input clk_i, input rst_ni, diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv.tpl b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv.tpl index 68b0e7b048b..bf88236dc52 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv.tpl +++ b/hw/ip_templates/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv.tpl @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -14,7 +15,13 @@ package flash_ctrl_top_specific_pkg; export flash_ctrl_pkg::OwnerSeedIdx; export flash_ctrl_pkg::SeedWidth; export flash_ctrl_pkg::KeyWidth; + export flash_ctrl_pkg::FlashProgNormal; + export flash_ctrl_pkg::FlashProgRepair; export flash_ctrl_pkg::flash_key_t; + export flash_ctrl_pkg::FlashPartData; + export flash_ctrl_pkg::FlashPartInfo; + export flash_ctrl_pkg::flash_part_e; + export flash_ctrl_pkg::flash_prog_e; export flash_ctrl_pkg::keymgr_flash_t; // design parameters that can be altered through topgen @@ -328,13 +335,6 @@ package flash_ctrl_top_specific_pkg; FlashOpInvalid = 2'h3 } flash_op_e; - // Flash Program Operations Supported - typedef enum logic { - FlashProgNormal = 0, - FlashProgRepair = 1 - } flash_prog_e; - parameter int ProgTypes = 2; - // Flash Erase Operations Supported typedef enum logic { FlashErasePage = 0, @@ -354,12 +354,6 @@ package flash_ctrl_top_specific_pkg; ReadDir = 1'b1 } flash_flfo_dir_e; - // Flash partition type - typedef enum logic { - FlashPartData = 1'b0, - FlashPartInfo = 1'b1 - } flash_part_e; - // Flash controller to memory typedef struct packed { logic req; @@ -385,7 +379,6 @@ package flash_ctrl_top_specific_pkg; logic [KeyWidth-1:0] rand_data_key; logic alert_trig; logic alert_ack; - jtag_pkg::jtag_req_t jtag_req; prim_mubi_pkg::mubi4_t flash_disable; } flash_req_t; @@ -414,7 +407,6 @@ package flash_ctrl_top_specific_pkg; rand_data_key: '0, alert_trig: 1'b0, alert_ack: 1'b0, - jtag_req: '0, flash_disable: prim_mubi_pkg::MuBi4False }; @@ -427,10 +419,8 @@ package flash_ctrl_top_specific_pkg; logic rd_err; logic [BusFullWidth-1:0] rd_data; logic init_busy; - logic macro_err; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; - jtag_pkg::jtag_rsp_t jtag_rsp; logic prog_intg_err; logic storage_relbl_err; logic storage_intg_err; @@ -450,10 +440,8 @@ package flash_ctrl_top_specific_pkg; rd_err: '0, rd_data: '0, init_busy: 1'b0, - macro_err: 1'b0, ecc_single_err: '0, ecc_addr: '0, - jtag_rsp: '0, prog_intg_err: '0, storage_relbl_err: '0, storage_intg_err: '0, @@ -517,16 +505,6 @@ package flash_ctrl_top_specific_pkg; } }; - // dft_en jtag selection - typedef enum logic [2:0] { - FlashLcTckSel, - FlashLcTdiSel, - FlashLcTmsSel, - FlashLcTdoSel, - FlashBistSel, - FlashLcDftLast - } flash_lc_jtag_e; - // Error bit positioning typedef struct packed { logic invalid_op_err; diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_phy.sv b/hw/ip_templates/flash_ctrl/rtl/flash_phy.sv index 8ae5f802e8f..88c6ae3633e 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_phy.sv +++ b/hw/ip_templates/flash_ctrl/rtl/flash_phy.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -11,6 +12,7 @@ // correctly collecting the responses in order. module flash_phy + import flash_ctrl_pkg::ProgTypes; import flash_ctrl_top_specific_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -25,27 +27,14 @@ module flash_phy output logic host_req_done_o, output logic [BusFullWidth-1:0] host_rdata_o, output logic host_rderr_o, - input flash_req_t flash_ctrl_i, + input flash_req_t flash_ctrl_i, output flash_rsp_t flash_ctrl_o, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - input mubi4_t scanmode_i, - input scan_en_i, - input scan_rst_ni, - input flash_power_ready_h_i, - input flash_power_down_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - input mubi4_t flash_bist_enable_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - output logic fatal_prim_flash_alert_o, - output logic recov_prim_flash_alert_o + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_req_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_rsp_i, + input logic [ProgTypes-1:0] prog_type_avail_i, + input logic init_busy_i ); - import prim_mubi_pkg::MuBi4False; - // Flash macro outstanding refers to how many reads we allow a macro to move ahead of an // in order blocking read. Since the data cannot be returned out of order, this simply // does the reads in advance and store them in a FIFO @@ -86,8 +75,6 @@ module flash_phy logic [NumBanks-1:0] rd_done; logic [NumBanks-1:0] prog_done; logic [NumBanks-1:0] erase_done; - logic init_busy; - logic [ProgTypes-1:0] prog_type_avail; // common interface logic [BusFullWidth-1:0] rd_data_host [NumBanks]; @@ -130,13 +117,13 @@ module flash_phy assign host_rdata_o = host_rsp_data[rsp_bank_sel]; // all banks are assumed to be the same in terms of prog_type support - assign flash_ctrl_o.prog_type_avail = prog_type_avail; + assign flash_ctrl_o.prog_type_avail = prog_type_avail_i; assign flash_ctrl_o.rd_done = rd_done[ctrl_bank_sel]; assign flash_ctrl_o.prog_done = prog_done[ctrl_bank_sel]; assign flash_ctrl_o.erase_done = erase_done[ctrl_bank_sel]; assign flash_ctrl_o.rd_data = rd_data_ctrl[ctrl_bank_sel]; assign flash_ctrl_o.rd_err = rd_err[ctrl_bank_sel]; - assign flash_ctrl_o.init_busy = init_busy; + assign flash_ctrl_o.init_busy = init_busy_i; assign flash_ctrl_o.prog_intg_err = |prog_intg_err; assign flash_ctrl_o.storage_relbl_err = |relbl_ecc_err; assign flash_ctrl_o.storage_intg_err = |intg_ecc_err; @@ -202,10 +189,8 @@ module flash_phy assign host_ecc_en = mubi4_test_true_strict(mubi4_and_hi(region_cfg.ecc_en, region_cfg.en)); // Prim flash to flash_phy_core connections - flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; - flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; - flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] prim_flash_req; - flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] prim_flash_rsp; + flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; + flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; @@ -294,8 +279,8 @@ module flash_phy .flash_disable_i(flash_disable[bank]), .scramble_req_o(scramble_req[bank]), .scramble_rsp_i(scramble_rsp[bank]), - .prim_flash_req_o(prim_flash_req[bank]), - .prim_flash_rsp_i(prim_flash_rsp[bank]), + .flash_macro_req_o(flash_macro_req_o.bank_reqs[bank]), + .flash_macro_rsp_i(flash_macro_rsp_i.bank_rsps[bank]), .ecc_single_err_o(ecc_single_err[bank]), .ecc_addr_o(ecc_addr[bank][BusBankAddrW-1:0]), .fsm_err_o(fsm_err[bank]), @@ -328,72 +313,9 @@ module flash_phy .arb_err_o(scramble_arb_err) // fatal error from redundant arbiter logic ); - // life cycle handling - logic tdo; - lc_ctrl_pkg::lc_tx_t [FlashLcDftLast-1:0] lc_nvm_debug_en; - - assign flash_ctrl_o.jtag_rsp.tdo = tdo & - lc_ctrl_pkg::lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdoSel]); - - prim_lc_sync #( - .NumCopies(int'(FlashLcDftLast)) - ) u_lc_nvm_debug_en_sync ( - .clk_i, - .rst_ni, - .lc_en_i(lc_nvm_debug_en_i), - .lc_en_o(lc_nvm_debug_en) - ); - - import lc_ctrl_pkg::lc_tx_test_true_strict; - // if nvm debug is enabled, flash_bist_enable controls entry to flash test mode. - // if nvm debug is disabled, flash_bist_enable is always turned off. - mubi4_t bist_enable_qual; - assign bist_enable_qual = (lc_tx_test_true_strict(lc_nvm_debug_en[FlashBistSel])) ? - flash_bist_enable_i : - MuBi4False; - - prim_flash #( - .NumBanks(NumBanks), - .InfosPerBank(InfosPerBank), - .InfoTypes(InfoTypes), - .InfoTypesWidth(InfoTypesWidth), - .PagesPerBank(PagesPerBank), - .WordsPerPage(WordsPerPage), - .DataWidth(flash_phy_pkg::FullDataWidth) - ) u_flash ( - .clk_i, - .rst_ni, - .tl_i, - .tl_o, - .flash_req_i(prim_flash_req), - .flash_rsp_o(prim_flash_rsp), - .prog_type_avail_o(prog_type_avail), - .init_busy_o(init_busy), - .tck_i(flash_ctrl_i.jtag_req.tck & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTckSel])), - .tdi_i(flash_ctrl_i.jtag_req.tdi & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdiSel])), - .tms_i(flash_ctrl_i.jtag_req.tms & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTmsSel])), - .tdo_o(tdo), - .bist_enable_i(bist_enable_qual), - .obs_ctrl_i, - .fla_obs_o, - .scanmode_i, - .scan_en_i, - .scan_rst_ni, - .flash_power_ready_h_i, - .flash_power_down_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .flash_err_o(flash_ctrl_o.macro_err), - .fatal_alert_o(fatal_prim_flash_alert_o), - .recov_alert_o(recov_prim_flash_alert_o) - ); logic unused_alert; assign unused_alert = flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack; - logic unused_trst_n; - assign unused_trst_n = flash_ctrl_i.jtag_req.trst_n; - assign flash_ctrl_o.jtag_rsp.tdo_oe = 1'b1; - ////////////////////////////////////////////// // Assertions, Assumptions, and Coverpoints // ///////////////////////////////////////////// diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_phy_core.sv b/hw/ip_templates/flash_ctrl/rtl/flash_phy_core.sv index 576c10780fa..bc91b0f78ac 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_phy_core.sv +++ b/hw/ip_templates/flash_ctrl/rtl/flash_phy_core.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -9,6 +10,8 @@ // scramble, ECC, security and arbitration logic. module flash_phy_core + import flash_phy_macro_pkg::flash_phy_macro_bank_req_t; + import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t; import flash_phy_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -39,8 +42,8 @@ module flash_phy_core input prim_mubi_pkg::mubi4_t flash_disable_i, output scramble_req_t scramble_req_o, input scramble_rsp_t scramble_rsp_i, - input flash_phy_prim_flash_rsp_t prim_flash_rsp_i, - output flash_phy_prim_flash_req_t prim_flash_req_o, + input flash_phy_macro_bank_rsp_t flash_macro_rsp_i, + output flash_phy_macro_bank_req_t flash_macro_req_o, output logic host_req_rdy_o, output logic host_req_done_o, output logic rd_done_o, @@ -566,7 +569,7 @@ module flash_phy_core //////////////////////// // Connections to the actual flash macro wrapper - assign prim_flash_req_o = '{ + assign flash_macro_req_o = '{ rd_req: flash_rd_req, prog_req: flash_prog_req, prog_last: prog_last, @@ -583,9 +586,9 @@ module flash_phy_core prog_full_data: prog_full_data }; - assign ack = prim_flash_rsp_i.ack; - assign done = prim_flash_rsp_i.done; - assign flash_rdata = prim_flash_rsp_i.rdata; + assign ack = flash_macro_rsp_i.ack; + assign done = flash_macro_rsp_i.done; + assign flash_rdata = flash_macro_rsp_i.rdata; ///////////////////////////////// // Assertions diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_phy_macro_pkg.sv b/hw/ip_templates/flash_ctrl/rtl/flash_phy_macro_pkg.sv new file mode 100644 index 00000000000..525a6179743 --- /dev/null +++ b/hw/ip_templates/flash_ctrl/rtl/flash_phy_macro_pkg.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Flash phy macro package +// This has the interface to the flash macro wrapper. It is top-specific, +// but all dependencies are via macro wrapper overridden parameters, so +// it is okay for the flash macro wrapper to depend on this package. + +package flash_phy_macro_pkg; + + import flash_ctrl_pkg::ProgTypes; + + parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; + parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; + parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; + parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; + parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; + parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; + parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth + + flash_ctrl_top_specific_pkg::MetaDataWidth; + parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; + parameter int TestModeWidth = 2; + + // Transaction request to flash macro + typedef struct packed { + logic rd_req; + logic prog_req; + logic prog_last; + flash_ctrl_pkg::flash_prog_e prog_type; + logic pg_erase_req; + logic bk_erase_req; + logic erase_suspend_req; + logic he; + logic [BankAddrW-1:0] addr; + flash_ctrl_pkg::flash_part_e part; + logic [InfoTypesWidth-1:0] info_sel; + logic [DataWidth-1:0] prog_full_data; + } flash_phy_macro_bank_req_t; + + typedef struct packed { + flash_phy_macro_bank_req_t [NumBanks-1:0] bank_reqs; + } flash_phy_macro_req_t; + + // Transaction response from flash macro + typedef struct packed { + logic ack; + logic done; + logic [DataWidth-1:0] rdata; + } flash_phy_macro_bank_rsp_t; + + typedef struct packed { + flash_phy_macro_bank_rsp_t [NumBanks-1:0] bank_rsps; + } flash_phy_macro_rsp_t; + + // Status of flash macro + typedef struct packed { + // What program types flash macro supports + logic [ProgTypes-1:0] prog_type_avail; + // Asserted while flash is getting initialized + logic init_busy; + // Macro error + logic flash_err; + // Alert indications for the phy to connect to alert sender + logic fatal_alert; + logic recov_alert; + } flash_macro_status_t; + +endpackage : flash_phy_macro_pkg diff --git a/hw/ip_templates/flash_ctrl/rtl/flash_phy_pkg.sv b/hw/ip_templates/flash_ctrl/rtl/flash_phy_pkg.sv index a96f558fba3..3cb5cc6befd 100644 --- a/hw/ip_templates/flash_ctrl/rtl/flash_phy_pkg.sv +++ b/hw/ip_templates/flash_ctrl/rtl/flash_phy_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,15 +8,26 @@ package flash_phy_pkg; + import flash_phy_macro_pkg::NumBanks; + import flash_phy_macro_pkg::InfosPerBank; + import flash_phy_macro_pkg::InfoTypes; + import flash_phy_macro_pkg::InfoTypesWidth; + import flash_phy_macro_pkg::PagesPerBank; + import flash_phy_macro_pkg::WordsPerPage; + import flash_phy_macro_pkg::BankAddrW; + + export flash_phy_macro_pkg::NumBanks; + export flash_phy_macro_pkg::InfosPerBank; + export flash_phy_macro_pkg::InfoTypes; + export flash_phy_macro_pkg::InfoTypesWidth; + export flash_phy_macro_pkg::PagesPerBank; + export flash_phy_macro_pkg::WordsPerPage; + export flash_phy_macro_pkg::BankAddrW; + // flash phy parameters - parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; - parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; - parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; - parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; parameter int unsigned BankW = flash_ctrl_top_specific_pkg::BankW; parameter int unsigned PageW = flash_ctrl_top_specific_pkg::PageW; parameter int unsigned WordW = flash_ctrl_top_specific_pkg::WordW; - parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth; parameter int unsigned EccWidth = 8; parameter int unsigned MetaDataWidth = flash_ctrl_top_specific_pkg::MetaDataWidth; @@ -25,17 +37,13 @@ package flash_phy_pkg; // will switch to this after bus widening parameter int unsigned PlainIntgWidth = MetaDataWidth - EccWidth; parameter int unsigned PlainDataWidth = DataWidth + PlainIntgWidth; - //parameter int unsigned ScrDataWidth = DataWidth + EccWidth; parameter int unsigned FullDataWidth = DataWidth + MetaDataWidth; - parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; - parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; // flash ctrl / bus parameters parameter int unsigned BusWidth = flash_ctrl_top_specific_pkg::BusWidth; parameter int unsigned BusFullWidth = flash_ctrl_top_specific_pkg::BusFullWidth; parameter int unsigned BusBankAddrW = flash_ctrl_top_specific_pkg::BusBankAddrW; parameter int unsigned BusWordW = flash_ctrl_top_specific_pkg::BusWordW; - parameter int unsigned ProgTypes = flash_ctrl_top_specific_pkg::ProgTypes; // address bits remain must be 0 parameter int unsigned AddrBitsRemain = DataWidth % BusWidth; @@ -114,28 +122,6 @@ package flash_phy_pkg; DeScrambleOp = 1'b1 } cipher_ops_e; - // Connections to prim_flash - typedef struct packed { - logic rd_req; - logic prog_req; - logic prog_last; - flash_ctrl_top_specific_pkg::flash_prog_e prog_type; - logic pg_erase_req; - logic bk_erase_req; - logic erase_suspend_req; - logic he; - logic [BankAddrW-1:0] addr; - flash_ctrl_top_specific_pkg::flash_part_e part; - logic [InfoTypesWidth-1:0] info_sel; - logic [FullDataWidth-1:0] prog_full_data; - } flash_phy_prim_flash_req_t; - - typedef struct packed { - logic ack; - logic done; - logic [FullDataWidth-1:0] rdata; - } flash_phy_prim_flash_rsp_t; - typedef struct packed { logic calc_req; logic op_req; @@ -153,4 +139,4 @@ package flash_phy_pkg; logic [DataWidth-1:0] scrambled_data; } scramble_rsp_t; -endpackage // flash_phy_pkg +endpackage : flash_phy_pkg diff --git a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl index bf5832aa352..056c510bdb3 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.data.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.data.tcl @@ -1,4 +1,5 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # @@ -20,8 +21,8 @@ set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "J set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "JTAG_TCK::SPI_DEV_CLK,SPI_DEV_PASSTHRU_CLK") && (ReceivingFlop =~ "SPI_DEV_D*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {IO_DIV2_CLK and IO_DIV4_CLK can be assigned on the same PAD} -set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[0].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::ast_ext_clk,main_clk") && (receivingflop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (signal == "iob2") && (association == "load-control")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_macro_wrapper.gen_flash_banks[0].u_flash_macro_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::ast_ext_clk,main_clk") && (receivingflop == "top_earlgrey.u_flash_macro_wrapper.gen_flash_banks[1].u_flash_macro_bank.st_q[2:0]") && (signal == "iob2") && (association == "load-control")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dr_q[40]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.dtmcs_q.zero1[31]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {data s_net_no_wave} -expression {(multiclockdomains == "io_div2_clk,io_div4_clk::io_div4_clk,jtag_tck") && (receivingflop == "top_earlgrey.u_lc_ctrl.u_dmi_jtag.i_dmi_jtag_tap.idcode_q[31]") && (signal == "ior2") && (association == "none")} -status {waived} -comment {Multiple clocks can be assigned on the same pad} @@ -57,7 +58,7 @@ set_rule_status -rule {DATA} -expression {(MultiClockDomains == "SPI_DEV_CLK,SPI set_rule_status -rule {DATA} -expression {(MultiClockDomains == "SPI_HOST_CLK,SPI_HOST_PASSTHRU_CLK::IO_DIV4_CLK") && (ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.dio_out_retreg_q*") && (Signal =~ "SPI_HOST_*") && (Association == "None")} -status {Waived} -comment {pinmux dio_out_retreg is quasi-static} set_rule_status -rule {DATA} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.*io_o*_retreg_q*") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {pinmux io_out_retreg is quasi-static} set_rule_status -rule {DATA S_NET_NO_WAVE} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::IO_DIV4_CLK,JTAG_TCK") && (Signal =~ "IO*") && (Association == "None")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} -set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks[1].u_prim_flash_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} +set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV2_CLK,IO_DIV4_CLK::AST_EXT_CLK,MAIN_CLK") && (ReceivingFlop == "top_earlgrey.u_flash_macro_wrapper.gen_flash_banks[1].u_flash_macro_bank.st_q[2:0]") && (Signal == "IOB2") && (Association == "Load-Control")} -status {Waived} -comment {Multiple clocks can be assigned on the same pad} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cmd_info*.q*")} -status {Waived} -comment {spi_device reg is quasi-static} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_spi_device.u_reg.u_cfg*.q*")} -status {Waived} -comment {spi_device reg is quasi-static} set_rule_status -rule {DATA} -expression {(MultiClockDomains == "IO_DIV4_CLK::SPI_DEV_IN_CLK,SPI_DEV_PASSTHRU_IN_CLK") && (Signal =~ "top_earlgrey.u_pinmux_aon.dio_pad_attr_q*.invert")} -status {Waived} -comment {pinmux dio_out_retreg is quasi-static} diff --git a/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl b/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl index 8adcd48dd24..96abcf34e70 100644 --- a/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl +++ b/hw/top_earlgrey/cdc/cdc_waivers.w_masync.tcl @@ -1,4 +1,5 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 # @@ -288,7 +289,7 @@ set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_ set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.u_usbdev_aon_wake.filter_*.gen_async.prim_flop_2sync.u_sync_1.q_o*") && (Driver =~ "USB*")} -status {Waived} -comment {Paired clocks are not recognized by tool} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_pinmux_aon.*io_o*_retreg_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "USB_*") && (Driver =~ "top_earlgrey.u_usbdev.u_reg.u_phy_pins_drive_dp_o.q[0]")} -status {Waived} -comment {Paired clocks are not recognized by tool} -set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_flash_ctrl.u_eflash.u_flash.gen_prim_flash_banks*.u_prim_flash_bank.st_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} +set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_flash_macro_wrapper.gen_flash_banks*.uflash_macro_bank.st_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.i_dmi_jtag_tap.*_q*")} -status {Waived} -comment {Multiple clocks on PAD & included in waived path} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dtmcs_q.zero1[31]") && (MultiClockDomains =~ "AST_EXT_CLK,MAIN_CLK::AST_EXT_CLK,JTAG_TCK,MAIN_CLK") && (Driver =~ "top_earlgrey.u_rv_dm.u_pm_en_sync.gen_flops.u_prim_flop_2sync.u_sync_2.q_o[0]")} -status {Waived} -lastedit_user {root} -lastedit_time {Wednesday, 16 November 2022 16:19:54 PDT} set_rule_status -rule {W_MASYNC} -expression {(ReceivingFlop =~ "top_earlgrey.u_rv_dm.dap.dr_q[40]") && (Driver =~ "top_earlgrey.u_pinmux_aon.mio_pad_attr_q[37].invert")} -status {Waived} -comment {included in waived paths : start signal and receiving signal (flop) have been reviewed and waived in the same error or other errors} diff --git a/hw/top_earlgrey/chip_earlgrey_asic.core b/hw/top_earlgrey/chip_earlgrey_asic.core index 9abdd921bdc..dffbaed8162 100644 --- a/hw/top_earlgrey/chip_earlgrey_asic.core +++ b/hw/top_earlgrey/chip_earlgrey_asic.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_earlgrey_asic:0.1" @@ -10,7 +11,7 @@ filesets: - lowrisc:systems:top_earlgrey:0.1 - lowrisc:systems:top_earlgrey_pkg - lowrisc:systems:top_earlgrey_padring - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top - "fileset_partner ? (partner:systems:top_earlgrey_ast)" - "fileset_partner ? (partner:systems:top_earlgrey_scan_role_pkg)" - "fileset_partner ? (partner:prim_tech:all)" @@ -20,7 +21,6 @@ filesets: # TODO(#27347): prim_legacy_pkg is deprecated - "!fileset_partner ? (lowrisc:prim:prim_legacy_pkg)" - "!fileset_partner ? (lowrisc:prim_generic:all)" - - "!fileset_partner ? (lowrisc:prim_generic:flash)" files: - rtl/autogen/chip_earlgrey_asic.sv file_type: systemVerilogSource diff --git a/hw/top_earlgrey/chip_earlgrey_cw310.core b/hw/top_earlgrey/chip_earlgrey_cw310.core index 1feeee307d5..7f13c9f59b4 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_earlgrey_cw310:0.1" @@ -13,11 +14,10 @@ filesets: - lowrisc:systems:top_earlgrey_ast - lowrisc:systems:top_earlgrey_padring - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_xilinx:all - - lowrisc:prim_generic:flash files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core index d6aab40d608..e933bd33f0e 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core +++ b/hw/top_earlgrey/chip_earlgrey_cw310_hyperdebug.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_earlgrey_cw310_hyperdebug:0.1" @@ -13,11 +14,10 @@ filesets: - lowrisc:systems:top_earlgrey_ast - lowrisc:systems:top_earlgrey_padring - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_xilinx:all - - lowrisc:prim_generic:flash files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_cw340.core b/hw/top_earlgrey/chip_earlgrey_cw340.core index fa50ab67282..64316ea8e5c 100644 --- a/hw/top_earlgrey/chip_earlgrey_cw340.core +++ b/hw/top_earlgrey/chip_earlgrey_cw340.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_earlgrey_cw340:0.1" @@ -13,11 +14,10 @@ filesets: - lowrisc:systems:top_earlgrey_ast - lowrisc:systems:top_earlgrey_padring - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_xilinx_ultrascale:all - - lowrisc:prim_generic:flash files: - rtl/clkgen_xil_ultrascale.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_earlgrey/chip_earlgrey_verilator.core b/hw/top_earlgrey/chip_earlgrey_verilator.core index 789dcad537e..40d08a37a10 100644 --- a/hw/top_earlgrey/chip_earlgrey_verilator.core +++ b/hw/top_earlgrey/chip_earlgrey_verilator.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_earlgrey_verilator:0.1" @@ -13,11 +14,10 @@ filesets: - lowrisc:prim:clock_div - lowrisc:systems:top_earlgrey_ast - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_generic:all - - lowrisc:prim_generic:flash files: - rtl/chip_earlgrey_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_earlgrey/data/autogen/defs.bzl b/hw/top_earlgrey/data/autogen/defs.bzl index 4dbcda0d7c9..35403333af9 100644 --- a/hw/top_earlgrey/data/autogen/defs.bzl +++ b/hw/top_earlgrey/data/autogen/defs.bzl @@ -17,6 +17,7 @@ load("//hw/ip/csrng:defs.bzl", "CSRNG") load("//hw/ip/edn:defs.bzl", "EDN") load("//hw/ip/entropy_src:defs.bzl", "ENTROPY_SRC") load("//hw/top_earlgrey/ip_autogen/flash_ctrl:defs.bzl", "FLASH_CTRL") +load("//hw/ip/flash_macro_wrapper:defs.bzl", "FLASH_MACRO_WRAPPER") load("//hw/top_earlgrey/ip_autogen/gpio:defs.bzl", "GPIO") load("//hw/ip/hmac:defs.bzl", "HMAC") load("//hw/ip/i2c:defs.bzl", "I2C") @@ -55,6 +56,7 @@ EARLGREY_IPS = [ EDN, ENTROPY_SRC, FLASH_CTRL, + FLASH_MACRO_WRAPPER, GPIO, HMAC, I2C, diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson index 06593212032..8f8acb55fd7 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson @@ -604,7 +604,7 @@ sensor_ctrl sram_ctrl_ret_aon flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper rv_plic aes hmac @@ -6076,10 +6076,6 @@ { hart: 0x41000000 } - prim: - { - hart: 0x41008000 - } mem: { hart: 0x20000000 @@ -6162,88 +6158,6 @@ top_signame: flash_ctrl_otp index: -1 } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - top_signame: lc_ctrl_lc_nvm_debug_en - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - top_signame: flash_bist_enable - conn_type: false - index: -1 - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_down_h - conn_type: false - index: -1 - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_ready_h - conn_type: false - index: -1 - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_test_mode_a - conn_type: false - index: -1 - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_test_voltage_h - conn_type: false - index: -1 - } { name: lc_creator_seed_sw_rw_en struct: lc_tx @@ -6381,29 +6295,32 @@ index: -1 } { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv + name: flash_macro + desc: Data interface to the flash macro wrapper + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: req width: 1 inst_name: flash_ctrl default: "" - top_signame: ast_obs_ctrl + end_idx: -1 + top_signame: flash_ctrl_flash_macro index: -1 } { - name: fla_obs - struct: logic + name: flash_macro_status + desc: Status interface from the flash macro wrapper + struct: flash_macro_status + package: flash_phy_macro_pkg type: uni - act: req - width: 8 + act: rcv + width: 1 inst_name: flash_ctrl default: "" - package: "" - external: true - top_signame: flash_obs - conn_type: false + end_idx: -1 + top_type: broadcast + top_signame: flash_ctrl_flash_macro_status index: -1 } { @@ -6420,7 +6337,7 @@ index: -1 } { - name: prim_tl + name: mem_tl struct: tl package: tlul_pkg type: req_rsp @@ -6429,23 +6346,279 @@ inst_name: flash_ctrl default: "" end_idx: -1 - top_signame: flash_ctrl_prim_tl + top_signame: flash_ctrl_mem_tl index: -1 } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: flash_macro_wrapper + type: flash_macro_wrapper + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: { - name: mem_tl + name: lc + domain: "0" + } + } + param_decl: + { + NumBanks: flash_phy_macro_pkg::NumBanks + InfosPerBank: flash_phy_macro_pkg::InfosPerBank + InfoTypes: flash_phy_macro_pkg::InfoTypes + InfoTypesWidth: flash_phy_macro_pkg::InfoTypesWidth + PagesPerBank: flash_phy_macro_pkg::PagesPerBank + WordsPerPage: flash_phy_macro_pkg::WordsPerPage + DataWidth: flash_phy_macro_pkg::DataWidth + TestModeWidth: flash_phy_macro_pkg::TestModeWidth + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + memory: {} + param_list: + [ + { + name: NumBanks + desc: Number of flash banks + type: int + default: flash_phy_macro_pkg::NumBanks + local: "false" + expose: "false" + name_top: FlashMacroWrapperNumBanks + } + { + name: InfosPerBank + desc: Info pages per bank + type: int + default: flash_phy_macro_pkg::InfosPerBank + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfosPerBank + } + { + name: InfoTypes + desc: Number of different info page types per bank + type: int + default: flash_phy_macro_pkg::InfoTypes + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfoTypes + } + { + name: InfoTypesWidth + desc: Number of bits to encode the info page types + type: int + default: flash_phy_macro_pkg::InfoTypesWidth + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfoTypesWidth + } + { + name: PagesPerBank + desc: Number of data pages per bank + type: int + default: flash_phy_macro_pkg::PagesPerBank + local: "false" + expose: "false" + name_top: FlashMacroWrapperPagesPerBank + } + { + name: WordsPerPage + desc: Number of words per data page + type: int + default: flash_phy_macro_pkg::WordsPerPage + local: "false" + expose: "false" + name_top: FlashMacroWrapperWordsPerPage + } + { + name: DataWidth + desc: Number of bits per data word + type: int + default: flash_phy_macro_pkg::DataWidth + local: "false" + expose: "false" + name_top: FlashMacroWrapperDataWidth + } + { + name: TestModeWidth + desc: Number of bits to encode test mode + type: int + default: flash_phy_macro_pkg::TestModeWidth + local: "false" + expose: "false" + name_top: FlashMacroWrapperTestModeWidth + } + ] + inter_signal_list: + [ + { + name: flash + desc: Data interface to the flash controller + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro + index: -1 + } + { + name: status + struct: flash_macro_status + package: flash_phy_macro_pkg + type: uni + act: req + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro_status + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: lc_ctrl_lc_nvm_debug_en + index: -1 + } + { + name: bist_enable + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: flash_bist_enable + conn_type: false + index: -1 + } + { + name: power_down_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_down_h + conn_type: false + index: -1 + } + { + name: power_ready_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_ready_h + conn_type: false + index: -1 + } + { + name: test_mode_a + struct: "" + type: io + act: none + width: 2 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_test_mode_a + conn_type: false + index: -1 + } + { + name: test_voltage_h + struct: "" + type: io + act: none + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_test_voltage_h + conn_type: false + index: -1 + } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_obs + conn_type: false + index: -1 + } + { + name: tl struct: tl package: tlul_pkg type: req_rsp act: rsp width: 1 - inst_name: flash_ctrl + inst_name: flash_macro_wrapper default: "" end_idx: -1 - top_signame: flash_ctrl_mem_tl + top_signame: flash_macro_wrapper_tl index: -1 } ] + base_addrs: + { + null: + { + hart: 0x41008000 + } + } generate_dif: true domain: [ @@ -9914,7 +10087,7 @@ { ast.obs_ctrl: [ - flash_ctrl.obs_ctrl + flash_macro_wrapper.obs_ctrl otp_macro.obs_ctrl ] ast.ram_1p_cfg: @@ -10170,7 +10343,7 @@ ] lc_ctrl.lc_nvm_debug_en: [ - flash_ctrl.lc_nvm_debug_en + flash_macro_wrapper.lc_nvm_debug_en ] lc_ctrl.lc_hw_debug_clr: [ @@ -10249,6 +10422,14 @@ [ otp_macro.otp ] + flash_ctrl.flash_macro: + [ + flash_macro_wrapper.flash + ] + flash_ctrl.flash_macro_status: + [ + flash_macro_wrapper.status + ] rv_plic.msip: [ rv_core_ibex.irq_software @@ -10343,9 +10524,9 @@ [ main.tl_flash_ctrl__core ] - flash_ctrl.prim_tl: + flash_macro_wrapper.tl: [ - main.tl_flash_ctrl__prim + main.tl_flash_macro_wrapper ] flash_ctrl.mem_tl: [ @@ -10546,12 +10727,12 @@ clkmgr_aon.hi_speed_sel: hi_speed_sel clkmgr_aon.div_step_down_req: div_step_down_req clkmgr_aon.calib_rdy: calib_rdy - flash_ctrl.flash_bist_enable: flash_bist_enable - flash_ctrl.flash_power_down_h: flash_power_down_h - flash_ctrl.flash_power_ready_h: flash_power_ready_h - flash_ctrl.flash_test_mode_a: flash_test_mode_a - flash_ctrl.flash_test_voltage_h: flash_test_voltage_h - flash_ctrl.fla_obs: flash_obs + flash_macro_wrapper.bist_enable: flash_bist_enable + flash_macro_wrapper.power_down_h: flash_power_down_h + flash_macro_wrapper.power_ready_h: flash_power_ready_h + flash_macro_wrapper.test_mode_a: flash_test_mode_a + flash_macro_wrapper.test_voltage_h: flash_test_voltage_h + flash_macro_wrapper.fla_obs: flash_obs entropy_src.entropy_src_rng_enable: es_rng_enable entropy_src.entropy_src_rng_valid: es_rng_valid entropy_src.entropy_src_rng_bits: es_rng_bit @@ -10658,7 +10839,7 @@ spi_host1 usbdev flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper flash_ctrl.mem aes entropy_src @@ -10685,7 +10866,7 @@ spi_host1 usbdev flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper flash_ctrl.mem aes entropy_src @@ -10948,13 +11129,13 @@ pipeline: true } { - name: flash_ctrl.prim + name: flash_macro_wrapper type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: flash_ctrl + inst_type: flash_macro_wrapper addr_range: [ { @@ -11434,7 +11615,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -11442,7 +11623,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -13459,6 +13640,14 @@ desc: "" attr: "" } + { + instance: flash_macro_wrapper + port: "" + connection: muxed + pad: "" + desc: "" + attr: "" + } { instance: sensor_ctrl_aon port: "" @@ -14282,7 +14471,7 @@ glob_idx: 46 } { - name: flash_ctrl_tck + name: flash_macro_wrapper_tck width: 1 type: input idx: -1 @@ -14293,7 +14482,7 @@ glob_idx: 47 } { - name: flash_ctrl_tms + name: flash_macro_wrapper_tms width: 1 type: input idx: -1 @@ -14304,7 +14493,7 @@ glob_idx: 48 } { - name: flash_ctrl_tdi + name: flash_macro_wrapper_tdi width: 1 type: input idx: -1 @@ -14524,7 +14713,7 @@ glob_idx: 51 } { - name: flash_ctrl_tdo + name: flash_macro_wrapper_tdo width: 1 type: output idx: -1 @@ -22496,88 +22685,6 @@ top_signame: flash_ctrl_otp index: -1 } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - top_signame: lc_ctrl_lc_nvm_debug_en - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - top_signame: flash_bist_enable - conn_type: false - index: -1 - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_down_h - conn_type: false - index: -1 - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_ready_h - conn_type: false - index: -1 - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_test_mode_a - conn_type: false - index: -1 - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_test_voltage_h - conn_type: false - index: -1 - } { name: lc_creator_seed_sw_rw_en struct: lc_tx @@ -22715,29 +22822,32 @@ index: -1 } { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv + name: flash_macro + desc: Data interface to the flash macro wrapper + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: req width: 1 inst_name: flash_ctrl default: "" - top_signame: ast_obs_ctrl + end_idx: -1 + top_signame: flash_ctrl_flash_macro index: -1 } { - name: fla_obs - struct: logic + name: flash_macro_status + desc: Status interface from the flash macro wrapper + struct: flash_macro_status + package: flash_phy_macro_pkg type: uni - act: req - width: 8 + act: rcv + width: 1 inst_name: flash_ctrl default: "" - package: "" - external: true - top_signame: flash_obs - conn_type: false + end_idx: -1 + top_type: broadcast + top_signame: flash_ctrl_flash_macro_status index: -1 } { @@ -22754,7 +22864,7 @@ index: -1 } { - name: prim_tl + name: mem_tl struct: tl package: tlul_pkg type: req_rsp @@ -22763,20 +22873,153 @@ inst_name: flash_ctrl default: "" end_idx: -1 - top_signame: flash_ctrl_prim_tl + top_signame: flash_ctrl_mem_tl index: -1 } { - name: mem_tl + name: flash + desc: Data interface to the flash controller + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro + index: -1 + } + { + name: status + struct: flash_macro_status + package: flash_phy_macro_pkg + type: uni + act: req + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro_status + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: lc_ctrl_lc_nvm_debug_en + index: -1 + } + { + name: bist_enable + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: flash_bist_enable + conn_type: false + index: -1 + } + { + name: power_down_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_down_h + conn_type: false + index: -1 + } + { + name: power_ready_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_ready_h + conn_type: false + index: -1 + } + { + name: test_mode_a + struct: "" + type: io + act: none + width: 2 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_test_mode_a + conn_type: false + index: -1 + } + { + name: test_voltage_h + struct: "" + type: io + act: none + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_test_voltage_h + conn_type: false + index: -1 + } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: ast_obs_ctrl + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_obs + conn_type: false + index: -1 + } + { + name: tl struct: tl package: tlul_pkg type: req_rsp act: rsp width: 1 - inst_name: flash_ctrl + inst_name: flash_macro_wrapper default: "" end_idx: -1 - top_signame: flash_ctrl_mem_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -24759,7 +25002,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -24767,7 +25010,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -27120,6 +27363,39 @@ suffix: rsp default: "'0" } + { + package: flash_phy_macro_pkg + struct: flash_phy_macro_req + signame: flash_ctrl_flash_macro_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: flash_phy_macro_pkg + struct: flash_phy_macro_rsp + signame: flash_ctrl_flash_macro_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: flash_phy_macro_pkg::FLASH_PHY_MACRO_RSP_DEFAULT + } + { + package: flash_phy_macro_pkg + struct: flash_macro_status + signame: flash_ctrl_flash_macro_status + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: flash_phy_macro_pkg::FLASH_MACRO_STATUS_DEFAULT + } { package: "" struct: logic @@ -27508,7 +27784,7 @@ { package: tlul_pkg struct: tl_h2d - signame: flash_ctrl_prim_tl_req + signame: flash_macro_wrapper_tl_req width: 1 type: req_rsp end_idx: -1 @@ -27519,7 +27795,7 @@ { package: tlul_pkg struct: tl_d2h - signame: flash_ctrl_prim_tl_rsp + signame: flash_macro_wrapper_tl_rsp width: 1 type: req_rsp end_idx: -1 diff --git a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson index 1a9152edd6a..bbe44bcd221 100644 --- a/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson +++ b/hw/top_earlgrey/data/autogen/top_earlgrey.secrets.testing.gen.hjson @@ -3055,10 +3055,6 @@ { hart: 0x41000000 } - prim: - { - hart: 0x41008000 - } mem: { hart: 0x20000000 diff --git a/hw/top_earlgrey/data/top_earlgrey.hjson b/hw/top_earlgrey/data/top_earlgrey.hjson index 47c961c70e2..c1818b288c4 100644 --- a/hw/top_earlgrey/data/top_earlgrey.hjson +++ b/hw/top_earlgrey/data/top_earlgrey.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -249,7 +250,7 @@ "sensor_ctrl", "sram_ctrl_ret_aon", "flash_ctrl.core", - "flash_ctrl.prim", + "flash_macro_wrapper", "rv_plic", "aes", "hmac", @@ -801,7 +802,6 @@ reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, base_addrs: { core: {hart: "0x41000000"}, - prim: {hart: "0x41008000"}, mem: {hart: "0x20000000"} } param_decl: { @@ -824,6 +824,26 @@ }, attr: "ipgen", }, + { name: "flash_macro_wrapper", + type: "flash_macro_wrapper", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x41008000", + }, + param_decl: { + // Change these to be from package + NumBanks: "flash_phy_macro_pkg::NumBanks", + InfosPerBank: "flash_phy_macro_pkg::InfosPerBank", + InfoTypes: "flash_phy_macro_pkg::InfoTypes", + InfoTypesWidth: "flash_phy_macro_pkg::InfoTypesWidth", + PagesPerBank: "flash_phy_macro_pkg::PagesPerBank", + WordsPerPage: "flash_phy_macro_pkg::WordsPerPage", + DataWidth: "flash_phy_macro_pkg::DataWidth", + TestModeWidth: "flash_phy_macro_pkg::TestModeWidth", + }, + }, { name: "rv_dm", type: "rv_dm", clock_srcs: {clk_i: "main", clk_lc_i: "main"}, @@ -1144,7 +1164,7 @@ // e.g flash_ctrl0.flash: [flash_phy0.flash_ctrl] inter_module: { 'connect': { - 'ast.obs_ctrl' : ['flash_ctrl.obs_ctrl', + 'ast.obs_ctrl' : ['flash_macro_wrapper.obs_ctrl', 'otp_macro.obs_ctrl'], 'ast.ram_1p_cfg' : ['otbn.ram_cfg_imem', 'otbn.ram_cfg_dmem', @@ -1258,7 +1278,7 @@ 'pwrmgr_aon.lc_dft_en', 'rv_dm.lc_dft_en' ], - 'lc_ctrl.lc_nvm_debug_en' : ['flash_ctrl.lc_nvm_debug_en'], + 'lc_ctrl.lc_nvm_debug_en' : ['flash_macro_wrapper.lc_nvm_debug_en'], 'lc_ctrl.lc_hw_debug_clr' : ['pinmux_aon.lc_hw_debug_clr', 'rv_dm.lc_hw_debug_clr'], 'lc_ctrl.lc_hw_debug_en' : ['sram_ctrl_main.lc_hw_debug_en', @@ -1297,6 +1317,10 @@ // OTP OTP_MACRO connections 'otp_ctrl.otp_macro' : ['otp_macro.otp'], + // FLASH_CTRL FLASH_MACRO_WRAPPER connections + 'flash_ctrl.flash_macro' : ['flash_macro_wrapper.flash'], + 'flash_ctrl.flash_macro_status' : ['flash_macro_wrapper.status'], + // rv_plic connections 'rv_plic.msip' : ['rv_core_ibex.irq_software'], 'rv_plic.irq' : ['rv_core_ibex.irq_external'], @@ -1380,12 +1404,12 @@ 'clkmgr_aon.hi_speed_sel' : 'hi_speed_sel', 'clkmgr_aon.div_step_down_req' : 'div_step_down_req', 'clkmgr_aon.calib_rdy' : 'calib_rdy', - 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable', - 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', - 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', - 'flash_ctrl.flash_test_mode_a' : 'flash_test_mode_a', - 'flash_ctrl.flash_test_voltage_h' : 'flash_test_voltage_h', - 'flash_ctrl.fla_obs' : 'flash_obs', + 'flash_macro_wrapper.bist_enable' : 'flash_bist_enable', + 'flash_macro_wrapper.power_down_h' : 'flash_power_down_h', + 'flash_macro_wrapper.power_ready_h' : 'flash_power_ready_h', + 'flash_macro_wrapper.test_mode_a' : 'flash_test_mode_a', + 'flash_macro_wrapper.test_voltage_h' : 'flash_test_voltage_h', + 'flash_macro_wrapper.fla_obs' : 'flash_obs', 'entropy_src.entropy_src_rng_enable' : 'es_rng_enable', 'entropy_src.entropy_src_rng_valid' : 'es_rng_valid', 'entropy_src.entropy_src_rng_bits' : 'es_rng_bit', @@ -1591,54 +1615,55 @@ // signals: [ // USB - { instance: 'usbdev', port: 'usb_dp', connection: 'manual', pad: '' , desc: ''}, - { instance: 'usbdev', port: 'usb_dn', connection: 'manual', pad: '' , desc: ''}, - // SPI Host0 - { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''}, - { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''}, - { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''}, - { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''}, - { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''}, - { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''}, + { instance: 'usbdev', port: 'usb_dp', connection: 'manual', pad: '' , desc: ''}, + { instance: 'usbdev', port: 'usb_dn', connection: 'manual', pad: '' , desc: ''}, + // SPI Host0 + { instance: 'spi_host0', port: 'sck', connection: 'direct', pad: 'SPI_HOST_CLK' , desc: ''}, + { instance: 'spi_host0', port: 'csb', connection: 'direct', pad: 'SPI_HOST_CS_L', desc: ''}, + { instance: 'spi_host0', port: 'sd[0]', connection: 'direct', pad: 'SPI_HOST_D0' , desc: ''}, + { instance: 'spi_host0', port: 'sd[1]', connection: 'direct', pad: 'SPI_HOST_D1' , desc: ''}, + { instance: 'spi_host0', port: 'sd[2]', connection: 'direct', pad: 'SPI_HOST_D2' , desc: ''}, + { instance: 'spi_host0', port: 'sd[3]', connection: 'direct', pad: 'SPI_HOST_D3' , desc: ''}, // SPI Device - { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''}, - { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''}, - { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''}, - { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''}, - { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''}, - { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''}, + { instance: 'spi_device', port: 'sck', connection: 'direct', pad: 'SPI_DEV_CLK' , desc: ''}, + { instance: 'spi_device', port: 'csb', connection: 'direct', pad: 'SPI_DEV_CS_L' , desc: ''}, + { instance: 'spi_device', port: 'sd[0]', connection: 'direct', pad: 'SPI_DEV_D0' , desc: ''}, + { instance: 'spi_device', port: 'sd[1]', connection: 'direct', pad: 'SPI_DEV_D1' , desc: ''}, + { instance: 'spi_device', port: 'sd[2]', connection: 'direct', pad: 'SPI_DEV_D2' , desc: ''}, + { instance: 'spi_device', port: 'sd[3]', connection: 'direct', pad: 'SPI_DEV_D3' , desc: ''}, // MIOs - { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "uart1", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "uart2", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "uart3", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "i2c0", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "i2c1", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "pwm_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "otp_macro", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "gpio", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "uart0", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "uart1", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "uart2", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "uart3", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "i2c0", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "i2c1", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "i2c2", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "pattgen", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "spi_device", port: 'tpm_csb', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "spi_host1", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "flash_ctrl", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "flash_macro_wrapper", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sensor_ctrl_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "pwm_aon", port: '', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "otp_macro", port: 'test[0]', connection: 'muxed' , pad: '' , desc: ''}, // Sysrst ctrl has both muxed and dedicated IOs - { instance: "sysrst_ctrl_aon", port: 'ac_present', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key0_in', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key1_in', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key2_in', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'pwrb_in', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'bat_disable', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'ec_rst_l', connection: 'direct', pad: 'IOR8' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'flash_wp_l', connection: 'direct', pad: 'IOR9' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key0_out', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key1_out', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'key2_out', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'pwrb_out', connection: 'muxed', pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'lid_open', connection: 'muxed' , pad: '' , desc: ''}, - { instance: "sysrst_ctrl_aon", port: 'z3_wakeup', connection: 'muxed' , pad: '' , desc: ''}, - { instance: 'usbdev', port: 'sense', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'ac_present', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key0_in', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key1_in', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key2_in', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'pwrb_in', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'bat_disable', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'ec_rst_l', connection: 'direct', pad: 'IOR8' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'flash_wp_l', connection: 'direct', pad: 'IOR9' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key0_out', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key1_out', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'key2_out', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'pwrb_out', connection: 'muxed', pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'lid_open', connection: 'muxed' , pad: '' , desc: ''}, + { instance: "sysrst_ctrl_aon", port: 'z3_wakeup', connection: 'muxed' , pad: '' , desc: ''}, + { instance: 'usbdev', port: 'sense', connection: 'muxed' , pad: '' , desc: ''}, ], num_wkup_detect: 8, diff --git a/hw/top_earlgrey/data/xbar_main.hjson b/hw/top_earlgrey/data/xbar_main.hjson index 717b7b9e3c5..e8811a0ca02 100644 --- a/hw/top_earlgrey/data/xbar_main.hjson +++ b/hw/top_earlgrey/data/xbar_main.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { name: "main", @@ -109,7 +110,7 @@ req_fifo_pass: false, rsp_fifo_pass: false, }, - { name: "flash_ctrl.prim", + { name: "flash_macro_wrapper", type: "device", clock: "clk_main_i", reset: "rst_main_ni", @@ -222,7 +223,7 @@ rv_core_ibex.cored: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", - "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", + "flash_ctrl.core", "flash_macro_wrapper", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg" @@ -230,7 +231,7 @@ rv_dm.sba: [ "rom_ctrl.rom", "rom_ctrl.regs", "rv_dm.mem", "rv_dm.regs", "sram_ctrl_main.ram", "peri", "spi_host0", "spi_host1", "usbdev", - "flash_ctrl.core", "flash_ctrl.prim", "flash_ctrl.mem", + "flash_ctrl.core", "flash_macro_wrapper", "flash_ctrl.mem", "aes", "entropy_src", "csrng", "edn0", "edn1", "hmac", "rv_plic", "otbn", "keymgr", "kmac", "sram_ctrl_main.regs", "rv_core_ibex.cfg", diff --git a/hw/top_earlgrey/doc/design/README.md b/hw/top_earlgrey/doc/design/README.md index 421b431ff62..e33eebd42d1 100644 --- a/hw/top_earlgrey/doc/design/README.md +++ b/hw/top_earlgrey/doc/design/README.md @@ -388,60 +388,60 @@ The choice of memory, or lack thereof at location 0x0 confers two exclusive bene For the purpose of `top_earlgrey`, the first option has been chosen to benefit software development and testing -| Name | Type | Byte Address | -|:------------------|:--------------|:------------------| -| uart0 | uart | 0x40000000 (regs) | -| uart1 | uart | 0x40010000 (regs) | -| uart2 | uart | 0x40020000 (regs) | -| uart3 | uart | 0x40030000 (regs) | -| gpio | gpio | 0x40040000 (regs) | -| spi_device | spi_device | 0x40050000 (regs) | -| i2c0 | i2c | 0x40080000 (regs) | -| i2c1 | i2c | 0x40090000 (regs) | -| i2c2 | i2c | 0x400A0000 (regs) | -| pattgen | pattgen | 0x400E0000 (regs) | -| rv_timer | rv_timer | 0x40100000 (regs) | -| otp_ctrl | otp_ctrl | 0x40130000 (core) | -| otp_macro | otp_macro | 0x40138000 (prim) | -| lc_ctrl | lc_ctrl | 0x40140000 (regs) | -| | | 0x0 (dmi) | -| alert_handler | alert_handler | 0x40150000 (regs) | -| spi_host0 | spi_host | 0x40300000 (regs) | -| spi_host1 | spi_host | 0x40310000 (regs) | -| usbdev | usbdev | 0x40320000 (regs) | -| pwrmgr_aon | pwrmgr | 0x40400000 (regs) | -| rstmgr_aon | rstmgr | 0x40410000 (regs) | -| clkmgr_aon | clkmgr | 0x40420000 (regs) | -| sysrst_ctrl_aon | sysrst_ctrl | 0x40430000 (regs) | -| adc_ctrl_aon | adc_ctrl | 0x40440000 (regs) | -| pwm_aon | pwm | 0x40450000 (regs) | -| pinmux_aon | pinmux | 0x40460000 (regs) | -| aon_timer_aon | aon_timer | 0x40470000 (regs) | -| ast | ast | 0x40480000 (regs) | -| sensor_ctrl_aon | sensor_ctrl | 0x40490000 (regs) | -| sram_ctrl_ret_aon | sram_ctrl | 0x40500000 (regs) | -| | | 0x40600000 (ram) | -| flash_ctrl | flash_ctrl | 0x41000000 (core) | -| | | 0x41008000 (prim) | -| | | 0x20000000 (mem) | -| rv_dm | rv_dm | 0x00010000 (mem) | -| | | 0x41200000 (regs) | -| | | 0x00001000 (dbg) | -| rv_plic | rv_plic | 0x48000000 (regs) | -| aes | aes | 0x41100000 (regs) | -| hmac | hmac | 0x41110000 (regs) | -| kmac | kmac | 0x41120000 (regs) | -| otbn | otbn | 0x41130000 (regs) | -| keymgr | keymgr | 0x41140000 (regs) | -| csrng | csrng | 0x41150000 (regs) | -| entropy_src | entropy_src | 0x41160000 (regs) | -| edn0 | edn | 0x41170000 (regs) | -| edn1 | edn | 0x41180000 (regs) | -| sram_ctrl_main | sram_ctrl | 0x411C0000 (regs) | -| | | 0x10000000 (ram) | -| rom_ctrl | rom_ctrl | 0x00008000 (rom) | -| | | 0x411e0000 (regs) | -| rv_core_ibex | rv_core_ibex | 0x411F0000 (cfg) | +| Name | Type | Byte Address | +|:--------------------|:--------------------|:------------------| +| uart0 | uart | 0x40000000 (regs) | +| uart1 | uart | 0x40010000 (regs) | +| uart2 | uart | 0x40020000 (regs) | +| uart3 | uart | 0x40030000 (regs) | +| gpio | gpio | 0x40040000 (regs) | +| spi_device | spi_device | 0x40050000 (regs) | +| i2c0 | i2c | 0x40080000 (regs) | +| i2c1 | i2c | 0x40090000 (regs) | +| i2c2 | i2c | 0x400A0000 (regs) | +| pattgen | pattgen | 0x400E0000 (regs) | +| rv_timer | rv_timer | 0x40100000 (regs) | +| otp_ctrl | otp_ctrl | 0x40130000 (core) | +| otp_macro | otp_macro | 0x40138000 (prim) | +| lc_ctrl | lc_ctrl | 0x40140000 (regs) | +| | | 0x0 (dmi) | +| alert_handler | alert_handler | 0x40150000 (regs) | +| spi_host0 | spi_host | 0x40300000 (regs) | +| spi_host1 | spi_host | 0x40310000 (regs) | +| usbdev | usbdev | 0x40320000 (regs) | +| pwrmgr_aon | pwrmgr | 0x40400000 (regs) | +| rstmgr_aon | rstmgr | 0x40410000 (regs) | +| clkmgr_aon | clkmgr | 0x40420000 (regs) | +| sysrst_ctrl_aon | sysrst_ctrl | 0x40430000 (regs) | +| adc_ctrl_aon | adc_ctrl | 0x40440000 (regs) | +| pwm_aon | pwm | 0x40450000 (regs) | +| pinmux_aon | pinmux | 0x40460000 (regs) | +| aon_timer_aon | aon_timer | 0x40470000 (regs) | +| ast | ast | 0x40480000 (regs) | +| sensor_ctrl_aon | sensor_ctrl | 0x40490000 (regs) | +| sram_ctrl_ret_aon | sram_ctrl | 0x40500000 (regs) | +| | | 0x40600000 (ram) | +| flash_ctrl | flash_ctrl | 0x41000000 (core) | +| | | 0x20000000 (mem) | +| flash_macro_wrapper | flash_macro_wrapper | 0x41008000 (regs) | +| rv_dm | rv_dm | 0x00010000 (mem) | +| | | 0x41200000 (regs) | +| | | 0x00001000 (dbg) | +| rv_plic | rv_plic | 0x48000000 (regs) | +| aes | aes | 0x41100000 (regs) | +| hmac | hmac | 0x41110000 (regs) | +| kmac | kmac | 0x41120000 (regs) | +| otbn | otbn | 0x41130000 (regs) | +| keymgr | keymgr | 0x41140000 (regs) | +| csrng | csrng | 0x41150000 (regs) | +| entropy_src | entropy_src | 0x41160000 (regs) | +| edn0 | edn | 0x41170000 (regs) | +| edn1 | edn | 0x41180000 (regs) | +| sram_ctrl_main | sram_ctrl | 0x411C0000 (regs) | +| | | 0x10000000 (ram) | +| rom_ctrl | rom_ctrl | 0x00008000 (rom) | +| | | 0x411e0000 (regs) | +| rv_core_ibex | rv_core_ibex | 0x411F0000 (cfg) | diff --git a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv index bbf446c6f6f..b371582dc07 100644 --- a/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/dv/autogen/tb__xbar_connect.sv @@ -49,7 +49,7 @@ tl_if spi_host0_tl_if(clk_io, rst_n); tl_if spi_host1_tl_if(clk_io_div2, rst_n); tl_if usbdev_tl_if(clk_usb, rst_n); tl_if flash_ctrl__core_tl_if(clk_main, rst_n); -tl_if flash_ctrl__prim_tl_if(clk_main, rst_n); +tl_if flash_macro_wrapper_tl_if(clk_main, rst_n); tl_if flash_ctrl__mem_tl_if(clk_main, rst_n); tl_if hmac_tl_if(clk_main, rst_n); tl_if kmac_tl_if(clk_main, rst_n); @@ -131,7 +131,7 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(spi_host1, spi_host1, tl) `DRIVE_CHIP_TL_DEVICE_IF(usbdev, usbdev, tl) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl) - `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl) + `DRIVE_CHIP_TL_DEVICE_IF(flash_macro_wrapper, flash_macro_wrapper, tl) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl) `DRIVE_CHIP_TL_DEVICE_IF(hmac, hmac, tl) `DRIVE_CHIP_TL_DEVICE_IF(kmac, kmac, tl) diff --git a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv index 7a1851e3e42..acbd287c3c1 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/dv/autogen/xbar_env_pkg__params.sv @@ -31,7 +31,7 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__core", '{ '{32'h41000000, 32'h410001ff} }}, - '{"flash_ctrl__prim", '{ + '{"flash_macro_wrapper", '{ '{32'h41008000, 32'h4100807f} }}, '{"flash_ctrl__mem", '{ @@ -203,7 +203,7 @@ tl_host_t xbar_hosts[$] = '{ "spi_host1", "usbdev", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "flash_ctrl__mem", "aes", "entropy_src", @@ -255,7 +255,7 @@ tl_host_t xbar_hosts[$] = '{ "spi_host1", "usbdev", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "flash_ctrl__mem", "aes", "entropy_src", diff --git a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg index 70f41b35366..ed87f1a4f3f 100644 --- a/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_earlgrey/dv/autogen/xbar_tgl_excl.cfg @@ -50,10 +50,10 @@ -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[23:9] -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[29:25] -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[31:31] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[14:7] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[23:16] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[29:25] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[31:31] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[14:7] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[23:16] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[29:25] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[31:31] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[28:20] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[31:30] -node tb.dut*.u_hmac tl_*i.a_address[15:13] diff --git a/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv b/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv index 37fd31e083c..a6eb468c7be 100644 --- a/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv +++ b/hw/top_earlgrey/dv/env/seq_lib/chip_prim_tl_access_vseq.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -117,7 +118,7 @@ class chip_prim_tl_access_vseq extends chip_stub_cpu_base_vseq; task body(); for (int trans_i = 1; trans_i <= num_trans; trans_i++) begin - uvm_reg otp_prim_regs[$], flash_prim_regs[$]; + uvm_reg otp_prim_regs[$], flash_macro_wrapper_regs[$]; if (trans_i > 1 && $urandom_range(0, 4)) dut_init(); `uvm_info(`gfn, $sformatf("Run iterations %0d/%0d with lc_state %0s", trans_i, num_trans, @@ -131,8 +132,8 @@ class chip_prim_tl_access_vseq extends chip_stub_cpu_base_vseq; if ($urandom_range(0, 1)) begin `uvm_info(`gfn, "Check FLASH_CTRL prim_tl access", UVM_HIGH) - ral.flash_ctrl_prim.get_registers(flash_prim_regs); - rand_rw_prim_regs(flash_prim_regs, get_response_mode(1'b0)); + ral.flash_macro_wrapper.get_registers(flash_macro_wrapper_regs); + rand_rw_prim_regs(flash_macro_wrapper_regs, get_response_mode(1'b0)); end end endtask : body diff --git a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh index 01527d7047b..fc915a6c879 100644 --- a/hw/top_earlgrey/dv/tb/chip_hier_macros.svh +++ b/hw/top_earlgrey/dv/tb/chip_hier_macros.svh @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -12,7 +13,7 @@ `define CPU_HIER `CHIP_HIER.u_rv_core_ibex `define CPU_CORE_HIER `CPU_HIER.u_core `define CPU_TL_ADAPT_D_HIER `CPU_HIER.tl_adapter_host_d_ibex -`define EFLASH_HIER `CHIP_HIER.u_flash_ctrl.u_eflash.u_flash +`define EFLASH_HIER `CHIP_HIER.u_flash_macro_wrapper `define GPIO_HIER `CHIP_HIER.u_gpio `define KEYMGR_HIER `CHIP_HIER.u_keymgr `define LC_CTRL_HIER `CHIP_HIER.u_lc_ctrl @@ -42,8 +43,8 @@ // needs to be upgraded to support all info types. `define MEM_ARRAY_SUB mem `define EFLASH_GENERIC_HIER `EFLASH_HIER -`define FLASH_BANK0_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[0].u_prim_flash_bank -`define FLASH_BANK1_HIER `EFLASH_GENERIC_HIER.gen_prim_flash_banks[1].u_prim_flash_bank +`define FLASH_BANK0_HIER `EFLASH_GENERIC_HIER.gen_flash_banks[0].u_flash_macro_bank +`define FLASH_BANK1_HIER `EFLASH_GENERIC_HIER.gen_flash_banks[1].u_flash_macro_bank `define FLASH0_DATA_MEM_HIER `FLASH_BANK0_HIER.u_mem.`MEM_ARRAY_SUB `define FLASH0_INFO_MEM_HIER `FLASH_BANK0_HIER.gen_info_types[0].u_info_mem.`MEM_ARRAY_SUB `define FLASH1_DATA_MEM_HIER `FLASH_BANK1_HIER.u_mem.`MEM_ARRAY_SUB diff --git a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc index d3c5c8e7673..5ce6d59a7a9 100644 --- a/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc +++ b/hw/top_earlgrey/dv/verilator/chip_sim_tb.cc @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -28,12 +29,12 @@ int main(int argc, char **argv) { 4); // Only handle the lower bank of flash for now. MemArea flash0(top_scope + - ".u_flash_ctrl.u_eflash.u_flash." - "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem", + ".u_flash_macro_wrapper.gen_flash_banks[0]." + "u_flash_macro_bank.u_mem", 0x80000 / 8, 8); MemArea flash1(top_scope + - ".u_flash_ctrl.u_eflash.u_flash." - "gen_prim_flash_banks[1].u_prim_flash_bank.u_mem", + ".u_flash_macro_wrapper.gen_flash_banks[1]." + "u_flash_macro_bank.u_mem", 0x80000 / 8, 8); // Start with the flash region erased. Future loads can overwrite. std::vector all_ones(flash0.GetSizeBytes()); diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson index 6462e8d1293..fa3b46d6b31 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -79,7 +79,7 @@ spi_host1 usbdev flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper flash_ctrl.mem aes entropy_src @@ -106,7 +106,7 @@ spi_host1 usbdev flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper flash_ctrl.mem aes entropy_src @@ -369,13 +369,13 @@ pipeline: true } { - name: flash_ctrl.prim + name: flash_macro_wrapper type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: false rsp_fifo_pass: false - inst_type: flash_ctrl + inst_type: flash_macro_wrapper addr_range: [ { @@ -855,7 +855,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -863,7 +863,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { diff --git a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson index 06b93790393..13f572b5c66 100644 --- a/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_earlgrey/ip/xbar_main/data/autogen/xbar_main.hjson @@ -87,7 +87,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_flash_ctrl__prim" + name: "tl_flash_macro_wrapper" act: "req" package: "tlul_pkg" } diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 84f165db01c..0f4856235bc 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -40,7 +40,7 @@ initial force dut.rst_spi_host1_ni = rst_n; `CONNECT_TL_DEVICE_IF(spi_host1, dut, clk_spi_host1_i, rst_n) `CONNECT_TL_DEVICE_IF(usbdev, dut, clk_usb_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(flash_macro_wrapper, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(hmac, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(kmac, dut, clk_main_i, rst_n) diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg index 528f79c929b..132476bf3dc 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -48,10 +48,10 @@ -node tb.dut tl_flash_ctrl__core_o.a_address[23:9] -node tb.dut tl_flash_ctrl__core_o.a_address[29:25] -node tb.dut tl_flash_ctrl__core_o.a_address[31:31] --node tb.dut tl_flash_ctrl__prim_o.a_address[14:7] --node tb.dut tl_flash_ctrl__prim_o.a_address[23:16] --node tb.dut tl_flash_ctrl__prim_o.a_address[29:25] --node tb.dut tl_flash_ctrl__prim_o.a_address[31:31] +-node tb.dut tl_flash_macro_wrapper_o.a_address[14:7] +-node tb.dut tl_flash_macro_wrapper_o.a_address[23:16] +-node tb.dut tl_flash_macro_wrapper_o.a_address[29:25] +-node tb.dut tl_flash_macro_wrapper_o.a_address[31:31] -node tb.dut tl_flash_ctrl__mem_o.a_address[28:20] -node tb.dut tl_flash_ctrl__mem_o.a_address[31:30] -node tb.dut tl_hmac_o.a_address[15:13] diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index a6c1a5357b3..9b76b96d560 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -35,7 +35,7 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__core", '{ '{32'h41000000, 32'h410001ff} }}, - '{"flash_ctrl__prim", '{ + '{"flash_macro_wrapper", '{ '{32'h41008000, 32'h4100807f} }}, '{"flash_ctrl__mem", '{ @@ -100,7 +100,7 @@ tl_host_t xbar_hosts[$] = '{ "spi_host1", "usbdev", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "flash_ctrl__mem", "aes", "entropy_src", @@ -126,7 +126,7 @@ tl_host_t xbar_hosts[$] = '{ "spi_host1", "usbdev", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "flash_ctrl__mem", "aes", "entropy_src", diff --git a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv index fe56a65c6db..f61fc6b692a 100644 --- a/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_earlgrey/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -80,11 +80,11 @@ module xbar_main_bind; .h2d (tl_flash_ctrl__core_o), .d2h (tl_flash_ctrl__core_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__prim ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_macro_wrapper ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_flash_ctrl__prim_o), - .d2h (tl_flash_ctrl__prim_i) + .h2d (tl_flash_macro_wrapper_o), + .d2h (tl_flash_macro_wrapper_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__mem ( .clk_i (clk_main_i), diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 22a1a4bcaf6..c4098405afa 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -18,7 +18,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_SPACE_SPI_HOST1 = 32'h 40310000; localparam logic [31:0] ADDR_SPACE_USBDEV = 32'h 40320000; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000; - localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000; + localparam logic [31:0] ADDR_SPACE_FLASH_MACRO_WRAPPER = 32'h 41008000; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000; localparam logic [31:0] ADDR_SPACE_HMAC = 32'h 41110000; localparam logic [31:0] ADDR_SPACE_KMAC = 32'h 41120000; @@ -46,7 +46,7 @@ package tl_main_pkg; localparam logic [31:0] ADDR_MASK_SPI_HOST1 = 32'h 0000003f; localparam logic [31:0] ADDR_MASK_USBDEV = 32'h 00000fff; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 000001ff; - localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_FLASH_MACRO_WRAPPER = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 000fffff; localparam logic [31:0] ADDR_MASK_HMAC = 32'h 00001fff; localparam logic [31:0] ADDR_MASK_KMAC = 32'h 00000fff; @@ -75,7 +75,7 @@ package tl_main_pkg; TlSpiHost1 = 6, TlUsbdev = 7, TlFlashCtrlCore = 8, - TlFlashCtrlPrim = 9, + TlFlashMacroWrapper = 9, TlFlashCtrlMem = 10, TlHmac = 11, TlKmac = 12, diff --git a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv index a5bee7720f9..088b5f7c6fb 100644 --- a/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -43,7 +43,7 @@ // -> sm1_43 // -> flash_ctrl.core // -> sm1_44 -// -> flash_ctrl.prim +// -> flash_macro_wrapper // -> sm1_31 // -> flash_ctrl.mem // -> sm1_45 @@ -97,7 +97,7 @@ // -> sm1_43 // -> flash_ctrl.core // -> sm1_44 -// -> flash_ctrl.prim +// -> flash_macro_wrapper // -> sm1_31 // -> flash_ctrl.mem // -> sm1_45 @@ -164,8 +164,8 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_usbdev_i, output tlul_pkg::tl_h2d_t tl_flash_ctrl__core_o, input tlul_pkg::tl_d2h_t tl_flash_ctrl__core_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl__prim_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl__prim_i, + output tlul_pkg::tl_h2d_t tl_flash_macro_wrapper_o, + input tlul_pkg::tl_d2h_t tl_flash_macro_wrapper_i, output tlul_pkg::tl_h2d_t tl_flash_ctrl__mem_o, input tlul_pkg::tl_d2h_t tl_flash_ctrl__mem_i, output tlul_pkg::tl_h2d_t tl_hmac_o, @@ -633,8 +633,8 @@ module xbar_main ( assign tl_flash_ctrl__core_o = tl_sm1_43_ds_h2d; assign tl_sm1_43_ds_d2h = tl_flash_ctrl__core_i; - assign tl_flash_ctrl__prim_o = tl_sm1_44_ds_h2d; - assign tl_sm1_44_ds_d2h = tl_flash_ctrl__prim_i; + assign tl_flash_macro_wrapper_o = tl_sm1_44_ds_h2d; + assign tl_sm1_44_ds_d2h = tl_flash_macro_wrapper_i; assign tl_aes_o = tl_sm1_45_ds_h2d; assign tl_sm1_45_ds_d2h = tl_aes_i; @@ -742,7 +742,7 @@ end dev_sel_s1n_32 = 5'd9; end else if ((tl_s1n_32_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin + ~(ADDR_MASK_FLASH_MACRO_WRAPPER)) == ADDR_SPACE_FLASH_MACRO_WRAPPER) begin dev_sel_s1n_32 = 5'd10; end else if ((tl_s1n_32_us_h2d.a_address & @@ -845,7 +845,7 @@ end dev_sel_s1n_57 = 5'd9; end else if ((tl_s1n_57_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin + ~(ADDR_MASK_FLASH_MACRO_WRAPPER)) == ADDR_SPACE_FLASH_MACRO_WRAPPER) begin dev_sel_s1n_57 = 5'd10; end else if ((tl_s1n_57_us_h2d.a_address & diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/README.md b/hw/top_earlgrey/ip_autogen/flash_ctrl/README.md index 5b939739946..aa86606c66e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/README.md +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/README.md @@ -193,3 +193,14 @@ During production and RMA states, the isolated page is also readable. * Both `lc_iso_part_sw_wr_en` and `lc_iso_part_sw_rd_en` are set. See [life cycle](../../../ip/lc_ctrl/README.md#iso_part_sw_rd_en-and-iso_part_sw_wr_en) for more details + +## IP Blocks Organization + +The flash macro wrapper is provided by a separate IP block that is directly instantiated under the top level. +As such it has its own IP documentation (https://opentitan.org/book/hw/ip/flash_macro_wrapper/index.html). +This split allows the controller to be independent of low level testing and vendor specific interfaces to the Flash Macro. +It makes it simpler to make changes for different vendor flash macros. + +In terms of the top generation (https://opentitan.org/book/util/topgen/index.html#overview), the controller is an ipgen peripheral, while the macro is generic. +The controller can be generated with different parameters that directly affect the macro. +The macro wrapper is parameterized at the top-level so that it matches the controller's configuration. diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson index a27b461d49d..539d5319caf 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/data/flash_ctrl.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -10,7 +11,7 @@ one_line_desc: "Interfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe", one_paragraph_desc: ''' Flash Controller interfaces the integrated, non-volatile flash memory with software and other hardware components in the system, such as Life Cycle Controller, Key Manager, and OTP Controller. - It consists of the open source flash controller that interfaces with a third party flash module. + It consists of the open source flash controller that interfaces with a third party flash macro. The protocol controller handles read, program, and erase requests, as well as life cycle RMA entry. It supports differentiation between informational and data flash partitions, flash memory protection at page boundaries, and the handling of key manager secrets inaccessible to software. The actual physical controller is highly parameterized (number of banks, number of pages for each bank, number of words and word size for each page, and number of read buffers) and supports XEX scrambling configurable by software, as well as two types of ECC support configurable on a page boundary. @@ -43,17 +44,9 @@ ] bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.u_reg_top"} { protocol: "tlul", direction: "device", name: "mem" } ], - available_input_list: [ - { name: "tck", desc: "jtag clock" }, - { name: "tms", desc: "jtag tms" }, - { name: "tdi", desc: "jtag input" }, - ], - available_output_list: [ - { name: "tdo", desc: "jtag output" }, - ], + interrupt_list: [ // The first two status interrupts assert by default, since the FIFO is empty. // This is captured in the Hjson via the `default` key so that automatically generated tests can incorporate this information. @@ -100,46 +93,6 @@ package: "otp_ctrl_pkg" }, - { struct: "lc_tx", - package: "lc_ctrl_pkg", - type: "uni" - act: "rcv" - name: "lc_nvm_debug_en" - }, - - { struct: "mubi4" - package: "prim_mubi_pkg" - type: "uni" - act: "rcv" - name: "flash_bist_enable" - }, - - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_down_h" - }, - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_ready_h" - }, - { struct: "", - package: "", - width: "2", - type: "io" - act: "none" - name: "flash_test_mode_a" - }, - { struct: "", - package: "", - type: "io" - act: "none" - name: "flash_test_voltage_h" - }, - { struct: "lc_tx" type: "uni" name: "lc_creator_seed_sw_rw_en" @@ -215,24 +168,25 @@ name: "keymgr", act: "req", package: "flash_ctrl_pkg" - } - - { struct: "ast_obs_ctrl", - type: "uni", - name: "obs_ctrl", - act: "rcv", - package: "ast_pkg" - } + }, - { struct: "logic", - type: "uni", - name: "fla_obs", - act: "req", - width: "8", - package: "" - } + { struct: "flash_phy_macro", + type: "req_rsp", + name: "flash_macro", + act: "req", + package: "flash_phy_macro_pkg", + desc: "Data interface to the flash macro wrapper" + }, + { struct: "flash_macro_status", + type: "uni", + name: "flash_macro_status", + act: "rcv", + package: "flash_phy_macro_pkg", + desc: "Status interface from the flash macro wrapper" + }, ], + countermeasures: [ { name: "REG.BUS.INTEGRITY", desc: ''' @@ -386,9 +340,6 @@ } ] - scan: "true", // Enable `scanmode_i` port - scan_en: "true", // Enable `scan_en_i` port - scan_reset: "true", // Enable `scan_rst_ni` port param_list: [ // The reg parameters can be modified directly through top_*.hjson. // The template will automatically propagate the appropriate values. @@ -2357,867 +2308,6 @@ }, ], - prim: [ - { - name: "CSR0_REGWEN", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw0c", - hwaccess: "none", - resval: "1", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR1", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "12:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR2", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "3", - name: "field3", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4", - name: "field4", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5", - name: "field5", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "6", - name: "field6", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7", - name: "field7", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR3", - desc: "", - fields: [ - { - bits: "3:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7:4", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "10:8", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:11", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "19:17", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23:21", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "25:24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "27:26", - name: "field9", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR4", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "11:9", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR5", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:5", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:19", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR6", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:17", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20:19", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:21", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR7", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR8", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR9", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR10", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR11", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR12", - desc: "", - fields: [ - { - bits: "9:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR13", - desc: "", - fields: [ - { - bits: "19:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR14", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR15", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR16", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR17", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR18", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR19", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR20", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "ro", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - } - ], } memory: { mem: {} diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/interfaces.md b/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/interfaces.md index ebdb38e93eb..c3bfed55d0e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/interfaces.md +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/interfaces.md @@ -4,45 +4,30 @@ Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`flash_ctrl`** has the following hardware interfaces defined - Primary Clock: **`clk_i`** - Other Clocks: **`clk_otp_i`** -- Bus Device Interfaces (TL-UL): **`core_tl`**, **`prim_tl`**, **`mem_tl`** +- Bus Device Interfaces (TL-UL): **`core_tl`**, **`mem_tl`** - Bus Host Interfaces (TL-UL): *none* - -## Peripheral Pins for Chip IO - -| Pin name | Direction | Description | -|:-----------|:------------|:--------------| -| tck | input | jtag clock | -| tms | input | jtag tms | -| tdi | input | jtag input | -| tdo | output | jtag output | +- Peripheral Pins for Chip IO: *none* ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------------------|:-------------------------------|:--------|:------|--------:|:--------------| -| otp | otp_ctrl_pkg::flash_otp_key | req_rsp | req | 1 | | -| lc_nvm_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| flash_bist_enable | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| flash_power_down_h | logic | uni | rcv | 1 | | -| flash_power_ready_h | logic | uni | rcv | 1 | | -| flash_test_mode_a | | io | none | 2 | | -| flash_test_voltage_h | | io | none | 1 | | -| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | rcv | 1 | | -| pwrmgr | pwrmgr_pkg::pwr_flash | uni | req | 1 | | -| keymgr | flash_ctrl_pkg::keymgr_flash | uni | req | 1 | | -| obs_ctrl | ast_pkg::ast_obs_ctrl | uni | rcv | 1 | | -| fla_obs | logic | uni | req | 8 | | -| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| prim_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| mem_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------------------|:----------------------------------------|:--------|:------|--------:|:----------------------------------------------| +| otp | otp_ctrl_pkg::flash_otp_key | req_rsp | req | 1 | | +| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | rcv | 1 | | +| pwrmgr | pwrmgr_pkg::pwr_flash | uni | req | 1 | | +| keymgr | flash_ctrl_pkg::keymgr_flash | uni | req | 1 | | +| flash_macro | flash_phy_macro_pkg::flash_phy_macro | req_rsp | req | 1 | Data interface to the flash macro wrapper | +| flash_macro_status | flash_phy_macro_pkg::flash_macro_status | uni | rcv | 1 | Status interface from the flash macro wrapper | +| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| mem_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/registers.md b/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/registers.md index add5dd9224a..02fde97364e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/registers.md +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/doc/registers.md @@ -4,7 +4,7 @@ The flash protocol controller maintains two separate access windows for the FIFO It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read). -## Summary of the **`core`** interface's registers +## Summary | Name | Offset | Length | Description | |:-------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------| @@ -1437,686 +1437,5 @@ The FIFO is 16 entries of 4B flash words - Access: `ro` - Byte writes are *not* supported. -## Summary of the **`prim`** interface's registers - -| Name | Offset | Length | Description | -|:-----------------------------------------|:---------|---------:|:--------------| -| flash_ctrl.[`CSR0_REGWEN`](#csr0_regwen) | 0x0 | 4 | | -| flash_ctrl.[`CSR1`](#csr1) | 0x4 | 4 | | -| flash_ctrl.[`CSR2`](#csr2) | 0x8 | 4 | | -| flash_ctrl.[`CSR3`](#csr3) | 0xc | 4 | | -| flash_ctrl.[`CSR4`](#csr4) | 0x10 | 4 | | -| flash_ctrl.[`CSR5`](#csr5) | 0x14 | 4 | | -| flash_ctrl.[`CSR6`](#csr6) | 0x18 | 4 | | -| flash_ctrl.[`CSR7`](#csr7) | 0x1c | 4 | | -| flash_ctrl.[`CSR8`](#csr8) | 0x20 | 4 | | -| flash_ctrl.[`CSR9`](#csr9) | 0x24 | 4 | | -| flash_ctrl.[`CSR10`](#csr10) | 0x28 | 4 | | -| flash_ctrl.[`CSR11`](#csr11) | 0x2c | 4 | | -| flash_ctrl.[`CSR12`](#csr12) | 0x30 | 4 | | -| flash_ctrl.[`CSR13`](#csr13) | 0x34 | 4 | | -| flash_ctrl.[`CSR14`](#csr14) | 0x38 | 4 | | -| flash_ctrl.[`CSR15`](#csr15) | 0x3c | 4 | | -| flash_ctrl.[`CSR16`](#csr16) | 0x40 | 4 | | -| flash_ctrl.[`CSR17`](#csr17) | 0x44 | 4 | | -| flash_ctrl.[`CSR18`](#csr18) | 0x48 | 4 | | -| flash_ctrl.[`CSR19`](#csr19) | 0x4c | 4 | | -| flash_ctrl.[`CSR20`](#csr20) | 0x50 | 4 | | - -## CSR0_REGWEN - -- Offset: `0x0` -- Reset default: `0x1` -- Reset mask: `0x1` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [field0](#csr0_regwen--field0) | - -### CSR0_REGWEN . field0 - -All values are reserved. - -## CSR1 - -- Offset: `0x4` -- Reset default: `0x0` -- Reset mask: `0x1fff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:13 | | | Reserved | -| 12:8 | rw | 0x0 | [field1](#csr1--field1) | -| 7:0 | rw | 0x0 | [field0](#csr1--field0) | - -### CSR1 . field1 - -All values are reserved. - -### CSR1 . field0 - -All values are reserved. - -## CSR2 - -- Offset: `0x8` -- Reset default: `0x0` -- Reset mask: `0xff` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:8 | | | Reserved | -| 7 | rw | 0x0 | [field7](#csr2--field7) | -| 6 | rw1c | 0x0 | [field6](#csr2--field6) | -| 5 | rw1c | 0x0 | [field5](#csr2--field5) | -| 4 | rw1c | 0x0 | [field4](#csr2--field4) | -| 3 | rw | 0x0 | [field3](#csr2--field3) | -| 2 | rw1c | 0x0 | [field2](#csr2--field2) | -| 1 | rw1c | 0x0 | [field1](#csr2--field1) | -| 0 | rw1c | 0x0 | [field0](#csr2--field0) | - -### CSR2 . field7 - -All values are reserved. - -### CSR2 . field6 - -All values are reserved. - -### CSR2 . field5 - -All values are reserved. - -### CSR2 . field4 - -All values are reserved. - -### CSR2 . field3 - -All values are reserved. - -### CSR2 . field2 - -All values are reserved. - -### CSR2 . field1 - -All values are reserved. - -### CSR2 . field0 - -All values are reserved. - -## CSR3 - -- Offset: `0xc` -- Reset default: `0x0` -- Reset mask: `0xfffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field9", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:28 | | | Reserved | -| 27:26 | rw | 0x0 | [field9](#csr3--field9) | -| 25:24 | rw | 0x0 | [field8](#csr3--field8) | -| 23:21 | rw | 0x0 | [field7](#csr3--field7) | -| 20 | rw | 0x0 | [field6](#csr3--field6) | -| 19:17 | rw | 0x0 | [field5](#csr3--field5) | -| 16:14 | rw | 0x0 | [field4](#csr3--field4) | -| 13:11 | rw | 0x0 | [field3](#csr3--field3) | -| 10:8 | rw | 0x0 | [field2](#csr3--field2) | -| 7:4 | rw | 0x0 | [field1](#csr3--field1) | -| 3:0 | rw | 0x0 | [field0](#csr3--field0) | - -### CSR3 . field9 - -All values are reserved. - -### CSR3 . field8 - -All values are reserved. - -### CSR3 . field7 - -All values are reserved. - -### CSR3 . field6 - -All values are reserved. - -### CSR3 . field5 - -All values are reserved. - -### CSR3 . field4 - -All values are reserved. - -### CSR3 . field3 - -All values are reserved. - -### CSR3 . field2 - -All values are reserved. - -### CSR3 . field1 - -All values are reserved. - -### CSR3 . field0 - -All values are reserved. - -## CSR4 - -- Offset: `0x10` -- Reset default: `0x0` -- Reset mask: `0xfff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:12 | | | Reserved | -| 11:9 | rw | 0x0 | [field3](#csr4--field3) | -| 8:6 | rw | 0x0 | [field2](#csr4--field2) | -| 5:3 | rw | 0x0 | [field1](#csr4--field1) | -| 2:0 | rw | 0x0 | [field0](#csr4--field0) | - -### CSR4 . field3 - -All values are reserved. - -### CSR4 . field2 - -All values are reserved. - -### CSR4 . field1 - -All values are reserved. - -### CSR4 . field0 - -All values are reserved. - -## CSR5 - -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0x7fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 5, "attr": ["rw"], "rotate": 0}, {"name": "field4", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:23 | | | Reserved | -| 22:19 | rw | 0x0 | [field4](#csr5--field4) | -| 18:14 | rw | 0x0 | [field3](#csr5--field3) | -| 13:5 | rw | 0x0 | [field2](#csr5--field2) | -| 4:3 | rw | 0x0 | [field1](#csr5--field1) | -| 2:0 | rw | 0x0 | [field0](#csr5--field0) | - -### CSR5 . field4 - -All values are reserved. - -### CSR5 . field3 - -All values are reserved. - -### CSR5 . field2 - -All values are reserved. - -### CSR5 . field1 - -All values are reserved. - -### CSR5 . field0 - -All values are reserved. - -## CSR6 - -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0x1ffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:25 | | | Reserved | -| 24 | rw | 0x0 | [field8](#csr6--field8) | -| 23 | rw | 0x0 | [field7](#csr6--field7) | -| 22:21 | rw | 0x0 | [field6](#csr6--field6) | -| 20:19 | rw | 0x0 | [field5](#csr6--field5) | -| 18:17 | rw | 0x0 | [field4](#csr6--field4) | -| 16:14 | rw | 0x0 | [field3](#csr6--field3) | -| 13:6 | rw | 0x0 | [field2](#csr6--field2) | -| 5:3 | rw | 0x0 | [field1](#csr6--field1) | -| 2:0 | rw | 0x0 | [field0](#csr6--field0) | - -### CSR6 . field8 - -All values are reserved. - -### CSR6 . field7 - -All values are reserved. - -### CSR6 . field6 - -All values are reserved. - -### CSR6 . field5 - -All values are reserved. - -### CSR6 . field4 - -All values are reserved. - -### CSR6 . field3 - -All values are reserved. - -### CSR6 . field2 - -All values are reserved. - -### CSR6 . field1 - -All values are reserved. - -### CSR6 . field0 - -All values are reserved. - -## CSR7 - -- Offset: `0x1c` -- Reset default: `0x0` -- Reset mask: `0x1ffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:17 | | | Reserved | -| 16:8 | rw | 0x0 | [field1](#csr7--field1) | -| 7:0 | rw | 0x0 | [field0](#csr7--field0) | - -### CSR7 . field1 - -All values are reserved. - -### CSR7 . field0 - -All values are reserved. - -## CSR8 - -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr8--field0) | - -### CSR8 . field0 - -All values are reserved. - -## CSR9 - -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr9--field0) | - -### CSR9 . field0 - -All values are reserved. - -## CSR10 - -- Offset: `0x28` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr10--field0) | - -### CSR10 . field0 - -All values are reserved. - -## CSR11 - -- Offset: `0x2c` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr11--field0) | - -### CSR11 . field0 - -All values are reserved. - -## CSR12 - -- Offset: `0x30` -- Reset default: `0x0` -- Reset mask: `0x3ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:10 | | | Reserved | -| 9:0 | rw | 0x0 | [field0](#csr12--field0) | - -### CSR12 . field0 - -All values are reserved. - -## CSR13 - -- Offset: `0x34` -- Reset default: `0x0` -- Reset mask: `0x1fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 20, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:21 | | | Reserved | -| 20 | rw | 0x0 | [field1](#csr13--field1) | -| 19:0 | rw | 0x0 | [field0](#csr13--field0) | - -### CSR13 . field1 - -All values are reserved. - -### CSR13 . field0 - -All values are reserved. - -## CSR14 - -- Offset: `0x38` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr14--field1) | -| 7:0 | rw | 0x0 | [field0](#csr14--field0) | - -### CSR14 . field1 - -All values are reserved. - -### CSR14 . field0 - -All values are reserved. - -## CSR15 - -- Offset: `0x3c` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr15--field1) | -| 7:0 | rw | 0x0 | [field0](#csr15--field0) | - -### CSR15 . field1 - -All values are reserved. - -### CSR15 . field0 - -All values are reserved. - -## CSR16 - -- Offset: `0x40` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr16--field1) | -| 7:0 | rw | 0x0 | [field0](#csr16--field0) | - -### CSR16 . field1 - -All values are reserved. - -### CSR16 . field0 - -All values are reserved. - -## CSR17 - -- Offset: `0x44` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr17--field1) | -| 7:0 | rw | 0x0 | [field0](#csr17--field0) | - -### CSR17 . field1 - -All values are reserved. - -### CSR17 . field0 - -All values are reserved. - -## CSR18 - -- Offset: `0x48` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr18--field0) | - -### CSR18 . field0 - -All values are reserved. - -## CSR19 - -- Offset: `0x4c` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr19--field0) | - -### CSR19 . field0 - -All values are reserved. - -## CSR20 - -- Offset: `0x50` -- Reset default: `0x0` -- Reset mask: `0x7` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:3 | | | Reserved | -| 2 | ro | 0x0 | [field2](#csr20--field2) | -| 1 | rw1c | 0x0 | [field1](#csr20--field1) | -| 0 | rw1c | 0x0 | [field0](#csr20--field0) | - -### CSR20 . field2 - -All values are reserved. - -### CSR20 . field1 - -All values are reserved. - -### CSR20 . field0 - -All values are reserved. - diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core index 0f73c4266b8..dd7b60e4cab 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:earlgrey_dv:flash_ctrl_cov @@ -9,6 +10,7 @@ filesets: files_dv: depend: - lowrisc:dv:dv_utils + - lowrisc:ip:flash_macro_wrapper - lowrisc:earlgrey_ip:flash_ctrl files: - flash_ctrl_cov_bind.sv diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv index 4c20c8dd914..2de0af16b01 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv @@ -1,25 +1,33 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Binds FLASH_CTRL functional coverage interface to the top level FLASH_CTRL module. -`define FLASH_COV_LC_TX_BIND(__name) \ +// Binds LC_TX functional coverage interface to the top level FLASH_CTRL module. +`define FLASH_CTRL_COV_LC_TX_BIND(__name) \ bind flash_ctrl cip_lc_tx_cov_if u_``__name``_cov_if( \ .rst_ni (rst_ni), \ .val (``__name``_i) \ ); +// Binds LC_TX functional coverage interface to the top level FLASH_MACRO_WRAPPER module. +`define FLASH_MACRO_COV_LC_TX_BIND(__name) \ + bind flash_macro_wrapper cip_lc_tx_cov_if u_``__name``_cov_if( \ + .rst_ni (rst_ni), \ + .val (``__name``_i) \ + ); + module flash_ctrl_cov_bind; - `FLASH_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) - `FLASH_COV_LC_TX_BIND(lc_seed_hw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_escalate_en) - `FLASH_COV_LC_TX_BIND(lc_nvm_debug_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_seed_hw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_escalate_en) + `FLASH_MACRO_COV_LC_TX_BIND(lc_nvm_debug_en) - bind prim_generic_flash_bank flash_ctrl_phy_cov_if u_phy_cov_if + bind flash_macro_bank flash_ctrl_phy_cov_if u_phy_cov_if ( .clk_i(clk_i), .rst_ni(rst_ni), diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core index b2a56c7414b..d1eebda05c8 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:earlgrey_dv:flash_ctrl_env:0.1 @@ -16,6 +17,7 @@ filesets: - lowrisc:dv:mem_bkdr_util - lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg - lowrisc:earlgrey_constants:top_pkg + - lowrisc:dv:flash_macro_wrapper_env files: - flash_ctrl_eflash_ral_pkg.sv - flash_ctrl_env_pkg.sv diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv index 23f71cb546e..300019d23c6 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 typedef class flash_ctrl_scoreboard; @@ -28,7 +29,6 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( // interface virtual flash_ctrl_if flash_ctrl_vif; virtual clk_rst_if clk_rst_vif_flash_ctrl_eflash_reg_block; - virtual clk_rst_if clk_rst_vif_flash_ctrl_prim_reg_block; virtual flash_ctrl_mem_if flash_ctrl_mem_vif[NumBanks]; // knobs @@ -283,7 +283,7 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( endfunction // get_region_from_info virtual function void initialize(addr_t csr_base_addr = '1); - string prim_ral_name = "flash_ctrl_prim_reg_block"; + string prim_ral_name = "flash_macro_wrapper_reg_block"; string fast_rcvr_name = ""; list_of_alerts = flash_ctrl_env_pkg::LIST_OF_ALERTS; @@ -594,13 +594,13 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( data_4s_t loc_data = (scheme == FlashMemInitCustom) ? data[i] : (scheme == FlashMemInitRandomize) ? $urandom() : wr_data; - _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); `uvm_info(`gfn, $sformatf( "flash_mem_bkdr_write: partition = %s, {%s} = 0x%0h", flash_op.partition.name(), addr_attrs.sprint(), loc_data - ), UVM_HIGH) + ), UVM_MEDIUM) + _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); // update the scoreboard on backdoor-programs as well mem_data[0] = loc_data; diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv index ae9842cc4e0..4cebe708137 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -15,7 +16,7 @@ package flash_ctrl_env_pkg; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_core_ral_pkg::*; import flash_ctrl_eflash_ral_pkg::*; - import flash_ctrl_prim_ral_pkg::*; + import flash_macro_wrapper_ral_pkg::*; import flash_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import prim_mubi_pkg::*; @@ -441,7 +442,9 @@ package flash_ctrl_env_pkg; end endfunction // flash_otf_print_data64 - function automatic flash_dv_part_e get_part_name(flash_phy_pkg::flash_phy_prim_flash_req_t req); + function automatic flash_dv_part_e get_part_name( + input flash_phy_macro_pkg::flash_phy_macro_bank_req_t req + ); flash_dv_part_e part; if (req.part == 0) return FlashPartData; diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv index 33bdf2f7a37..ea8904d3366 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv @@ -1,16 +1,17 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -import flash_ctrl_top_specific_pkg::*; + interface flash_ctrl_mem_if ( input logic clk_i, input logic rst_ni, input logic data_mem_req, input logic mem_wr, - input logic [BankAddrW-1:0] mem_addr, - input logic [flash_phy_pkg::FullDataWidth-1:0] mem_wdata, - input flash_part_e mem_part, - input logic [InfoTypesWidth-1:0] mem_info_sel, + input logic [flash_phy_macro_pkg::BankAddrW-1:0] mem_addr, + input logic [flash_phy_macro_pkg::DataWidth-1:0] mem_wdata, + input flash_ctrl_pkg::flash_part_e mem_part, + input logic [flash_phy_macro_pkg::InfoTypesWidth-1:0] mem_info_sel, input logic info0_mem_req, input logic info1_mem_req, input logic info2_mem_req diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv index c6a53be8537..e415644116e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/dv/tb/tb.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,10 +8,14 @@ module tb; import uvm_pkg::*; import top_pkg::*; import dv_utils_pkg::*; + import flash_ctrl_pkg::*; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_env_pkg::*; import flash_ctrl_test_pkg::*; import flash_ctrl_bkdr_util_pkg::flash_ctrl_bkdr_util; + import flash_phy_macro_pkg::flash_phy_macro_req_t; + import flash_phy_macro_pkg::flash_phy_macro_rsp_t; + import flash_phy_macro_pkg::flash_macro_status_t; // macro includes `include "uvm_macros.svh" @@ -39,6 +44,9 @@ module tb; wire intr_op_done; wire intr_err; wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + flash_phy_macro_req_t flash_macro_req; + flash_phy_macro_rsp_t flash_macro_rsp; + flash_macro_status_t flash_macro_status; ast_pkg::ast_obs_ctrl_t obs_ctrl; @@ -73,9 +81,9 @@ module tb; .rst_n(rst_n) ); - `define FLASH_DEVICE_HIER tb.dut.u_eflash.u_flash - assign fpp_if.req = `FLASH_DEVICE_HIER.flash_req_i; - assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_rsp_o; + `define FLASH_DEVICE_HIER tb.flash_macro_wrapper + assign fpp_if.req = `FLASH_DEVICE_HIER.flash_i; + assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_o; for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_bank_loop assign fpp_if.rreq[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.req_i; assign fpp_if.rdy[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.rdy_o; @@ -142,11 +150,9 @@ module tb; .clk_otp_i (clk), .rst_otp_ni (rst_n), - // various tlul interfaces + // tlul interfaces .core_tl_i(tl_if.h2d), .core_tl_o(tl_if.d2h), - .prim_tl_i(prim_tl_if.h2d), - .prim_tl_o(prim_tl_if.d2h), .mem_tl_i (eflash_tl_if.h2d), .mem_tl_o (eflash_tl_if.d2h), @@ -160,7 +166,6 @@ module tb; .lc_iso_part_sw_rd_en_i (flash_ctrl_if.lc_iso_part_sw_rd_en), .lc_iso_part_sw_wr_en_i (flash_ctrl_if.lc_iso_part_sw_wr_en), .lc_seed_hw_rd_en_i (flash_ctrl_if.lc_seed_hw_rd_en), - .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), .lc_escalate_en_i (flash_ctrl_if.lc_escalate_en), // life cycle rma handling @@ -173,23 +178,9 @@ module tb; .keymgr_o(flash_ctrl_if.keymgr), // flash prim signals - .flash_power_ready_h_i (flash_ctrl_if.power_ready_h), - .flash_power_down_h_i (flash_power_down_h), - .flash_bist_enable_i (prim_mubi_pkg::MuBi4False), - .flash_test_mode_a_io (flash_test_mode_a), - .flash_test_voltage_h_io(flash_test_v), - - // test - .scanmode_i (prim_mubi_pkg::MuBi4False), - .scan_rst_ni('0), - .scan_en_i ('0), - - // JTAG - .cio_tck_i (flash_ctrl_if.cio_tck), - .cio_tms_i (flash_ctrl_if.cio_tms), - .cio_tdi_i (flash_ctrl_if.cio_tdi), - .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), - .cio_tdo_o (flash_ctrl_if.cio_tdo), + .flash_macro_o (flash_macro_req), + .flash_macro_i (flash_macro_rsp), + .flash_macro_status_i (flash_macro_status), // alerts and interrupts .intr_prog_empty_o(intr_prog_empty), @@ -199,12 +190,43 @@ module tb; .intr_op_done_o (intr_op_done), .intr_corr_err_o (intr_err), .alert_rx_i (alert_rx), - .alert_tx_o (alert_tx), + .alert_tx_o (alert_tx) - // Observability - .obs_ctrl_i(obs_ctrl), - .fla_obs_o ( ) + ); + flash_macro_wrapper #( + .NumBanks(flash_phy_macro_pkg::NumBanks), + .InfosPerBank(flash_phy_macro_pkg::InfosPerBank), + .InfoTypes(flash_phy_macro_pkg::InfoTypes), + .InfoTypesWidth(flash_phy_macro_pkg::InfoTypesWidth), + .PagesPerBank(flash_phy_macro_pkg::PagesPerBank), + .WordsPerPage(flash_phy_macro_pkg::WordsPerPage), + .DataWidth(flash_phy_pkg::FullDataWidth) + ) flash_macro_wrapper ( + .clk_i (clk), + .rst_ni (rst_n), + .tl_i (prim_tl_if.h2d), + .tl_o (prim_tl_if.d2h), + .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), + .flash_i (flash_macro_req), + .flash_o (flash_macro_rsp), + .status_o (flash_macro_status), + // JTAG + .cio_tck_i (flash_ctrl_if.cio_tck), + .cio_tms_i (flash_ctrl_if.cio_tms), + .cio_tdi_i (flash_ctrl_if.cio_tdi), + .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), + .cio_tdo_o (flash_ctrl_if.cio_tdo), + .bist_enable_i(prim_mubi_pkg::MuBi4False), + .obs_ctrl_i (obs_ctrl), + .fla_obs_o ( ), + .scanmode_i (prim_mubi_pkg::MuBi4False), + .scan_en_i ('0), + .scan_rst_ni ('0), + .power_ready_h_i (flash_ctrl_if.power_ready_h), + .power_down_h_i (flash_power_down_h), + .test_mode_a_io (flash_test_mode_a), + .test_voltage_h_io (flash_test_v) ); // Create edge in flash_power_down_h_i, whenever reset is asserted @@ -243,25 +265,22 @@ module tb; // // For eflash of a specific vendor implementation, set the hierarchy to the memory element // correctly when creating these instances in the extended testbench. - `define FLASH_BANK_HIER(i) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank + `define FLASH_BANK_HIER(i) \ + tb.flash_macro_wrapper.gen_flash_banks[i].u_flash_macro_bank - `define FLASH_DATA_MEM_HIER(i) \ + `define FLASH_DATA_MEM_HIER(i) \ `FLASH_BANK_HIER(i).u_mem.mem - `define FLASH_DATA_MEM_HIER_STR(i) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.mem"}, i) + `define FLASH_DATA_MEM_HIER_STR(i) \ + $sformatf("tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.u_mem.mem", i) - `define FLASH_INFO_MEM_HIER(i, j) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank.gen_info_types[j].u_info_mem.mem + `define FLASH_INFO_MEM_HIER(i, j) \ + tb.flash_macro_wrapper.gen_flash_banks[i]. \ + u_flash_macro_bank.gen_info_types[j].u_info_mem.mem - `define FLASH_INFO_MEM_HIER_STR(i, j) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.gen_info_types[%0d].", \ - "u_info_mem.mem"}, i, j) + `define FLASH_INFO_MEM_HIER_STR(i, j) \ + $sformatf({"tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.", \ + "gen_info_types[%0d].u_info_mem.mem"}, i, j) if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_generic for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_each_bank @@ -276,6 +295,9 @@ module tb; .n_bits($bits(`FLASH_DATA_MEM_HIER(i))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d part=%s fails", i, part.name()), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -291,6 +313,9 @@ module tb; .n_bits($bits(`FLASH_INFO_MEM_HIER(i, j))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d, part=%s, info=%0d fails", i, part.name(), j), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -337,7 +362,8 @@ module tb; uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif_flash_ctrl_eflash_reg_block", clk_rst_if); uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", - "clk_rst_vif_flash_ctrl_prim_reg_block", clk_rst_if); + "clk_rst_vif_flash_macro_wrapper_reg_block", + clk_rst_if); uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shadowed_if); @@ -346,8 +372,8 @@ module tb; tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_eflash_reg_block*", "vif", eflash_tl_if); - uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_prim_reg_block*", "vif", - prim_tl_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_macro_wrapper_reg_block*", + "vif", prim_tl_if); uvm_config_db#(virtual flash_ctrl_if)::set(null, "*.env", "flash_ctrl_vif", flash_ctrl_if); uvm_config_db#(virtual flash_phy_prim_if)::set(null, "*.env.m_fpp_agent*", "vif", fpp_if); $timeformat(-9, 1, " ns", 9); diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core index bba09c2a3be..c5844c1ade0 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:earlgrey_ip:flash_ctrl:0.1 @@ -8,11 +9,14 @@ description: "Flash Controller" filesets: files_rtl: depend: + - lowrisc:earlgrey_ip:flash_phy_macro_pkg + - lowrisc:earlgrey_ip:flash_phy_pkg + - lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg - lowrisc:ip:tlul + - lowrisc:ip:flash_macro_wrapper - lowrisc:prim:all - lowrisc:prim:count - lowrisc:prim:edge_detector - - lowrisc:prim:flash - lowrisc:prim:flop_2sync - lowrisc:prim:gf_mult - lowrisc:prim:lc_sync @@ -22,7 +26,6 @@ filesets: # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg - lowrisc:earlgrey_ip:flash_ctrl_reg - lowrisc:earlgrey_constants:top_pkg - lowrisc:ip:jtag_pkg diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core index 790c23bb1fa..e70fb3a538c 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg:0.1 @@ -17,13 +18,11 @@ filesets: - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - lowrisc:tlul:headers - - lowrisc:ip:flash_ctrl_pkg - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" files: - rtl/flash_ctrl_reg_pkg.sv - rtl/flash_ctrl_top_specific_pkg.sv - - rtl/flash_phy_pkg.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core similarity index 51% rename from hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core rename to hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core index ab19b610c92..c07d769296a 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core @@ -1,30 +1,24 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top:1.0 -description: "Generic register top for the FLASH wrapper" +name: lowrisc:earlgrey_ip:flash_phy_macro_pkg:0.1 +description: "Flash phy interface to flash macro" virtual: - - lowrisc:virtual_ip:flash_ctrl_prim_reg_top + - lowrisc:virtual_ip:flash_phy_macro_pkg filesets: files_rtl: depend: + - lowrisc:ip:tlul - lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg - - lowrisc:prim:subreg +# - lowrisc:earlgrey_ip:flash_phy_pkg files: - - rtl/flash_ctrl_prim_reg_top.sv + - rtl/flash_phy_macro_pkg.sv file_type: systemVerilogSource - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - - targets: - default: &default_target + default: filesets: - files_rtl - toplevel: lc_ctrl diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_pkg.core b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_pkg.core new file mode 100644 index 00000000000..3f43ed002be --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/flash_phy_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:earlgrey_ip:flash_phy_pkg:0.1 +description: "Top specific flash phy package" +virtual: + - lowrisc:virtual_ip:flash_phy_pkg + +filesets: + files_rtl: + depend: + - lowrisc:earlgrey_ip:flash_ctrl_top_specific_pkg + - lowrisc:earlgrey_ip:flash_phy_macro_pkg + files: + - rtl/flash_phy_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv index 32263ee71ac..d9393c8cafa 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -39,13 +40,10 @@ module flash_ctrl input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i, input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i, input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, // Bus Interface input tlul_pkg::tl_h2d_t core_tl_i, output tlul_pkg::tl_d2h_t core_tl_o, - input tlul_pkg::tl_h2d_t prim_tl_i, - output tlul_pkg::tl_d2h_t prim_tl_o, input tlul_pkg::tl_h2d_t mem_tl_i, output tlul_pkg::tl_d2h_t mem_tl_o, @@ -59,13 +57,6 @@ module flash_ctrl output pwrmgr_pkg::pwr_flash_t pwrmgr_o, output keymgr_flash_t keymgr_o, - // IOs - input cio_tck_i, - input cio_tms_i, - input cio_tdi_i, - output logic cio_tdo_en_o, - output logic cio_tdo_o, - // Interrupts output logic intr_corr_err_o, // Correctable errors encountered output logic intr_prog_empty_o, // Program fifo is empty @@ -74,23 +65,14 @@ module flash_ctrl output logic intr_rd_lvl_o, // Read fifo is full output logic intr_op_done_o, // Requested flash operation (wr/erase) done + // Flash macro interface + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_i, + input flash_phy_macro_pkg::flash_macro_status_t flash_macro_status_i, + // Alerts input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, - - // Observability - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - - // Flash test interface - input scan_en_i, - input prim_mubi_pkg::mubi4_t scanmode_i, - input scan_rst_ni, - input prim_mubi_pkg::mubi4_t flash_bist_enable_i, - input flash_power_down_h_i, - input flash_power_ready_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io + output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o ); ////////////////////////////////////////////////////////// @@ -901,12 +883,6 @@ module flash_ctrl assign flash_phy_req.rand_data_key = rand_data_key; assign flash_phy_req.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q; assign flash_phy_req.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q; - assign flash_phy_req.jtag_req.tck = cio_tck_i; - assign flash_phy_req.jtag_req.tms = cio_tms_i; - assign flash_phy_req.jtag_req.tdi = cio_tdi_i; - assign flash_phy_req.jtag_req.trst_n = '0; - assign cio_tdo_o = flash_phy_rsp.jtag_rsp.tdo; - assign cio_tdo_en_o = flash_phy_rsp.jtag_rsp.tdo_oe; assign flash_rd_err = flash_phy_rsp.rd_err; assign flash_rd_data = flash_phy_rsp.rd_data; assign flash_phy_busy = flash_phy_rsp.init_busy; @@ -935,12 +911,11 @@ module flash_ctrl logic [NumAlerts-1:0] alert_srcs; logic [NumAlerts-1:0] alert_tests; - logic fatal_prim_flash_alert, recov_prim_flash_alert; // An excessive number of recoverable errors may also indicate an attack logic recov_err; assign recov_err = (sw_ctrl_done & |sw_ctrl_err) | - flash_phy_rsp.macro_err | + flash_macro_status_i.flash_err | update_err; logic fatal_err; @@ -953,8 +928,8 @@ module flash_ctrl assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err); assign alert_srcs = { - recov_prim_flash_alert, - fatal_prim_flash_alert, + flash_macro_status_i.recov_alert, + flash_macro_status_i.fatal_alert, fatal_err, fatal_std_err, recov_err @@ -1085,7 +1060,7 @@ module flash_ctrl assign hw2reg.err_code.prog_win_err.de = sw_ctrl_err.prog_win_err; assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err; assign hw2reg.err_code.update_err.de = update_err; - assign hw2reg.err_code.macro_err.de = flash_phy_rsp.macro_err; + assign hw2reg.err_code.macro_err.de = flash_macro_status_i.flash_err; assign hw2reg.err_addr.d = {ctrl_err_addr, {BusByteWidth{1'h0}}}; assign hw2reg.err_addr.de = sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | @@ -1356,21 +1331,10 @@ module flash_ctrl .host_rdata_o (flash_host_rdata), .flash_ctrl_i (flash_phy_req), .flash_ctrl_o (flash_phy_rsp), - .tl_i (prim_tl_i), - .tl_o (prim_tl_o), - .obs_ctrl_i, - .fla_obs_o, - .lc_nvm_debug_en_i, - .flash_bist_enable_i, - .flash_power_down_h_i, - .flash_power_ready_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .fatal_prim_flash_alert_o(fatal_prim_flash_alert), - .recov_prim_flash_alert_o(recov_prim_flash_alert), - .scanmode_i, - .scan_en_i, - .scan_rst_ni + .flash_macro_req_o (flash_macro_o), + .flash_macro_rsp_i (flash_macro_i), + .prog_type_avail_i (flash_macro_status_i.prog_type_avail), + .init_busy_i (flash_macro_status_i.init_busy) ); ///////////////////////////////// @@ -1380,9 +1344,6 @@ module flash_ctrl `ASSERT_KNOWN(TlDValidKnownO_A, core_tl_o.d_valid ) `ASSERT_KNOWN(TlAReadyKnownO_A, core_tl_o.a_ready ) `ASSERT_KNOWN_IF(RspPayLoad_A, core_tl_o, core_tl_o.d_valid) - `ASSERT_KNOWN(PrimTlDValidKnownO_A, prim_tl_o.d_valid ) - `ASSERT_KNOWN(PrimTlAReadyKnownO_A, prim_tl_o.a_ready ) - `ASSERT_KNOWN_IF(PrimRspPayLoad_A, prim_tl_o, prim_tl_o.d_valid) `ASSERT_KNOWN(MemTlDValidKnownO_A, mem_tl_o.d_valid ) `ASSERT_KNOWN(MemTlAReadyKnownO_A, mem_tl_o.a_ready ) `ASSERT_KNOWN_IF(MemRspPayLoad_A, mem_tl_o, mem_tl_o.d_valid) @@ -1398,8 +1359,6 @@ module flash_ctrl `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o ) `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o ) `ASSERT_KNOWN(IntrErrO_A, intr_corr_err_o ) - `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o ) - `ASSERT(TdoEnIsOne_A, cio_tdo_en_o === 1'b1) // combined indication that an operation has started // This is used only for assertions diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv index 235bf9effaf..ee9c5a687f7 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv @@ -1,11 +1,15 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // // Faux Flash Prog Control // -module flash_ctrl_prog import flash_ctrl_top_specific_pkg::*; ( +module flash_ctrl_prog + import flash_ctrl_pkg::*; + import flash_ctrl_top_specific_pkg::*; +( input clk_i, input rst_ni, diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv index 719c86b4f3c..1be381e2f42 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv @@ -28,11 +28,9 @@ package flash_ctrl_reg_pkg; // Address widths within the block parameter int CoreAw = 9; - parameter int PrimAw = 7; // Number of registers for every interface parameter int NumRegsCore = 108; - parameter int NumRegsPrim = 21; // Alert indices typedef enum int { @@ -1166,387 +1164,4 @@ package flash_ctrl_reg_pkg; 4'b 0011 // index[107] FLASH_CTRL_CURR_FIFO_LVL }; - /////////////////////////////////////////////// - // Typedefs for registers for prim interface // - /////////////////////////////////////////////// - - typedef struct packed { - struct packed { - logic [4:0] q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr1_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field7; - struct packed { - logic q; - } field6; - struct packed { - logic q; - } field5; - struct packed { - logic q; - } field4; - struct packed { - logic q; - } field3; - struct packed { - logic q; - } field2; - struct packed { - logic q; - } field1; - struct packed { - logic q; - } field0; - } flash_ctrl_reg2hw_csr2_reg_t; - - typedef struct packed { - struct packed { - logic [1:0] q; - } field9; - struct packed { - logic [1:0] q; - } field8; - struct packed { - logic [2:0] q; - } field7; - struct packed { - logic q; - } field6; - struct packed { - logic [2:0] q; - } field5; - struct packed { - logic [2:0] q; - } field4; - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [2:0] q; - } field2; - struct packed { - logic [3:0] q; - } field1; - struct packed { - logic [3:0] q; - } field0; - } flash_ctrl_reg2hw_csr3_reg_t; - - typedef struct packed { - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [2:0] q; - } field2; - struct packed { - logic [2:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr4_reg_t; - - typedef struct packed { - struct packed { - logic [3:0] q; - } field4; - struct packed { - logic [4:0] q; - } field3; - struct packed { - logic [8:0] q; - } field2; - struct packed { - logic [1:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr5_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field8; - struct packed { - logic q; - } field7; - struct packed { - logic [1:0] q; - } field6; - struct packed { - logic [1:0] q; - } field5; - struct packed { - logic [1:0] q; - } field4; - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [7:0] q; - } field2; - struct packed { - logic [2:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr6_reg_t; - - typedef struct packed { - struct packed { - logic [8:0] q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr7_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr8_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr9_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr10_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr11_reg_t; - - typedef struct packed { - logic [9:0] q; - } flash_ctrl_reg2hw_csr12_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [19:0] q; - } field0; - } flash_ctrl_reg2hw_csr13_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr14_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr15_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr16_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr17_reg_t; - - typedef struct packed { - logic q; - } flash_ctrl_reg2hw_csr18_reg_t; - - typedef struct packed { - logic q; - } flash_ctrl_reg2hw_csr19_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field2; - struct packed { - logic q; - } field1; - struct packed { - logic q; - } field0; - } flash_ctrl_reg2hw_csr20_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } field7; - struct packed { - logic d; - logic de; - } field6; - struct packed { - logic d; - logic de; - } field5; - struct packed { - logic d; - logic de; - } field4; - struct packed { - logic d; - logic de; - } field3; - struct packed { - logic d; - logic de; - } field2; - struct packed { - logic d; - logic de; - } field1; - struct packed { - logic d; - logic de; - } field0; - } flash_ctrl_hw2reg_csr2_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } field2; - struct packed { - logic d; - logic de; - } field1; - struct packed { - logic d; - logic de; - } field0; - } flash_ctrl_hw2reg_csr20_reg_t; - - // Register -> HW type for prim interface - typedef struct packed { - flash_ctrl_reg2hw_csr1_reg_t csr1; // [325:313] - flash_ctrl_reg2hw_csr2_reg_t csr2; // [312:305] - flash_ctrl_reg2hw_csr3_reg_t csr3; // [304:277] - flash_ctrl_reg2hw_csr4_reg_t csr4; // [276:265] - flash_ctrl_reg2hw_csr5_reg_t csr5; // [264:242] - flash_ctrl_reg2hw_csr6_reg_t csr6; // [241:217] - flash_ctrl_reg2hw_csr7_reg_t csr7; // [216:200] - flash_ctrl_reg2hw_csr8_reg_t csr8; // [199:168] - flash_ctrl_reg2hw_csr9_reg_t csr9; // [167:136] - flash_ctrl_reg2hw_csr10_reg_t csr10; // [135:104] - flash_ctrl_reg2hw_csr11_reg_t csr11; // [103:72] - flash_ctrl_reg2hw_csr12_reg_t csr12; // [71:62] - flash_ctrl_reg2hw_csr13_reg_t csr13; // [61:41] - flash_ctrl_reg2hw_csr14_reg_t csr14; // [40:32] - flash_ctrl_reg2hw_csr15_reg_t csr15; // [31:23] - flash_ctrl_reg2hw_csr16_reg_t csr16; // [22:14] - flash_ctrl_reg2hw_csr17_reg_t csr17; // [13:5] - flash_ctrl_reg2hw_csr18_reg_t csr18; // [4:4] - flash_ctrl_reg2hw_csr19_reg_t csr19; // [3:3] - flash_ctrl_reg2hw_csr20_reg_t csr20; // [2:0] - } flash_ctrl_prim_reg2hw_t; - - // HW -> register type for prim interface - typedef struct packed { - flash_ctrl_hw2reg_csr2_reg_t csr2; // [21:6] - flash_ctrl_hw2reg_csr20_reg_t csr20; // [5:0] - } flash_ctrl_prim_hw2reg_t; - - // Register offsets for prim interface - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR0_REGWEN_OFFSET = 7'h 0; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR1_OFFSET = 7'h 4; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR2_OFFSET = 7'h 8; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR3_OFFSET = 7'h c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR4_OFFSET = 7'h 10; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR5_OFFSET = 7'h 14; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR6_OFFSET = 7'h 18; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR7_OFFSET = 7'h 1c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR8_OFFSET = 7'h 20; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR9_OFFSET = 7'h 24; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR10_OFFSET = 7'h 28; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR11_OFFSET = 7'h 2c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR12_OFFSET = 7'h 30; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR13_OFFSET = 7'h 34; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR14_OFFSET = 7'h 38; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR15_OFFSET = 7'h 3c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR16_OFFSET = 7'h 40; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR17_OFFSET = 7'h 44; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR18_OFFSET = 7'h 48; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR19_OFFSET = 7'h 4c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR20_OFFSET = 7'h 50; - - // Register index for prim interface - typedef enum int { - FLASH_CTRL_CSR0_REGWEN, - FLASH_CTRL_CSR1, - FLASH_CTRL_CSR2, - FLASH_CTRL_CSR3, - FLASH_CTRL_CSR4, - FLASH_CTRL_CSR5, - FLASH_CTRL_CSR6, - FLASH_CTRL_CSR7, - FLASH_CTRL_CSR8, - FLASH_CTRL_CSR9, - FLASH_CTRL_CSR10, - FLASH_CTRL_CSR11, - FLASH_CTRL_CSR12, - FLASH_CTRL_CSR13, - FLASH_CTRL_CSR14, - FLASH_CTRL_CSR15, - FLASH_CTRL_CSR16, - FLASH_CTRL_CSR17, - FLASH_CTRL_CSR18, - FLASH_CTRL_CSR19, - FLASH_CTRL_CSR20 - } flash_ctrl_prim_id_e; - - // Register width information to check illegal writes for prim interface - parameter logic [3:0] FLASH_CTRL_PRIM_PERMIT [21] = '{ - 4'b 0001, // index[ 0] FLASH_CTRL_CSR0_REGWEN - 4'b 0011, // index[ 1] FLASH_CTRL_CSR1 - 4'b 0001, // index[ 2] FLASH_CTRL_CSR2 - 4'b 1111, // index[ 3] FLASH_CTRL_CSR3 - 4'b 0011, // index[ 4] FLASH_CTRL_CSR4 - 4'b 0111, // index[ 5] FLASH_CTRL_CSR5 - 4'b 1111, // index[ 6] FLASH_CTRL_CSR6 - 4'b 0111, // index[ 7] FLASH_CTRL_CSR7 - 4'b 1111, // index[ 8] FLASH_CTRL_CSR8 - 4'b 1111, // index[ 9] FLASH_CTRL_CSR9 - 4'b 1111, // index[10] FLASH_CTRL_CSR10 - 4'b 1111, // index[11] FLASH_CTRL_CSR11 - 4'b 0011, // index[12] FLASH_CTRL_CSR12 - 4'b 0111, // index[13] FLASH_CTRL_CSR13 - 4'b 0011, // index[14] FLASH_CTRL_CSR14 - 4'b 0011, // index[15] FLASH_CTRL_CSR15 - 4'b 0011, // index[16] FLASH_CTRL_CSR16 - 4'b 0011, // index[17] FLASH_CTRL_CSR17 - 4'b 0001, // index[18] FLASH_CTRL_CSR18 - 4'b 0001, // index[19] FLASH_CTRL_CSR19 - 4'b 0001 // index[20] FLASH_CTRL_CSR20 - }; - endpackage diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv index ff1b882f816..8830332af03 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -14,7 +15,13 @@ package flash_ctrl_top_specific_pkg; export flash_ctrl_pkg::OwnerSeedIdx; export flash_ctrl_pkg::SeedWidth; export flash_ctrl_pkg::KeyWidth; + export flash_ctrl_pkg::FlashProgNormal; + export flash_ctrl_pkg::FlashProgRepair; export flash_ctrl_pkg::flash_key_t; + export flash_ctrl_pkg::FlashPartData; + export flash_ctrl_pkg::FlashPartInfo; + export flash_ctrl_pkg::flash_part_e; + export flash_ctrl_pkg::flash_prog_e; export flash_ctrl_pkg::keymgr_flash_t; // design parameters that can be altered through topgen @@ -328,13 +335,6 @@ package flash_ctrl_top_specific_pkg; FlashOpInvalid = 2'h3 } flash_op_e; - // Flash Program Operations Supported - typedef enum logic { - FlashProgNormal = 0, - FlashProgRepair = 1 - } flash_prog_e; - parameter int ProgTypes = 2; - // Flash Erase Operations Supported typedef enum logic { FlashErasePage = 0, @@ -354,12 +354,6 @@ package flash_ctrl_top_specific_pkg; ReadDir = 1'b1 } flash_flfo_dir_e; - // Flash partition type - typedef enum logic { - FlashPartData = 1'b0, - FlashPartInfo = 1'b1 - } flash_part_e; - // Flash controller to memory typedef struct packed { logic req; @@ -385,7 +379,6 @@ package flash_ctrl_top_specific_pkg; logic [KeyWidth-1:0] rand_data_key; logic alert_trig; logic alert_ack; - jtag_pkg::jtag_req_t jtag_req; prim_mubi_pkg::mubi4_t flash_disable; } flash_req_t; @@ -414,7 +407,6 @@ package flash_ctrl_top_specific_pkg; rand_data_key: '0, alert_trig: 1'b0, alert_ack: 1'b0, - jtag_req: '0, flash_disable: prim_mubi_pkg::MuBi4False }; @@ -427,10 +419,8 @@ package flash_ctrl_top_specific_pkg; logic rd_err; logic [BusFullWidth-1:0] rd_data; logic init_busy; - logic macro_err; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; - jtag_pkg::jtag_rsp_t jtag_rsp; logic prog_intg_err; logic storage_relbl_err; logic storage_intg_err; @@ -450,10 +440,8 @@ package flash_ctrl_top_specific_pkg; rd_err: '0, rd_data: '0, init_busy: 1'b0, - macro_err: 1'b0, ecc_single_err: '0, ecc_addr: '0, - jtag_rsp: '0, prog_intg_err: '0, storage_relbl_err: '0, storage_intg_err: '0, @@ -517,16 +505,6 @@ package flash_ctrl_top_specific_pkg; } }; - // dft_en jtag selection - typedef enum logic [2:0] { - FlashLcTckSel, - FlashLcTdiSel, - FlashLcTmsSel, - FlashLcTdoSel, - FlashBistSel, - FlashLcDftLast - } flash_lc_jtag_e; - // Error bit positioning typedef struct packed { logic invalid_op_err; diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy.sv index 8ae5f802e8f..88c6ae3633e 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -11,6 +12,7 @@ // correctly collecting the responses in order. module flash_phy + import flash_ctrl_pkg::ProgTypes; import flash_ctrl_top_specific_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -25,27 +27,14 @@ module flash_phy output logic host_req_done_o, output logic [BusFullWidth-1:0] host_rdata_o, output logic host_rderr_o, - input flash_req_t flash_ctrl_i, + input flash_req_t flash_ctrl_i, output flash_rsp_t flash_ctrl_o, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - input mubi4_t scanmode_i, - input scan_en_i, - input scan_rst_ni, - input flash_power_ready_h_i, - input flash_power_down_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - input mubi4_t flash_bist_enable_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - output logic fatal_prim_flash_alert_o, - output logic recov_prim_flash_alert_o + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_req_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_rsp_i, + input logic [ProgTypes-1:0] prog_type_avail_i, + input logic init_busy_i ); - import prim_mubi_pkg::MuBi4False; - // Flash macro outstanding refers to how many reads we allow a macro to move ahead of an // in order blocking read. Since the data cannot be returned out of order, this simply // does the reads in advance and store them in a FIFO @@ -86,8 +75,6 @@ module flash_phy logic [NumBanks-1:0] rd_done; logic [NumBanks-1:0] prog_done; logic [NumBanks-1:0] erase_done; - logic init_busy; - logic [ProgTypes-1:0] prog_type_avail; // common interface logic [BusFullWidth-1:0] rd_data_host [NumBanks]; @@ -130,13 +117,13 @@ module flash_phy assign host_rdata_o = host_rsp_data[rsp_bank_sel]; // all banks are assumed to be the same in terms of prog_type support - assign flash_ctrl_o.prog_type_avail = prog_type_avail; + assign flash_ctrl_o.prog_type_avail = prog_type_avail_i; assign flash_ctrl_o.rd_done = rd_done[ctrl_bank_sel]; assign flash_ctrl_o.prog_done = prog_done[ctrl_bank_sel]; assign flash_ctrl_o.erase_done = erase_done[ctrl_bank_sel]; assign flash_ctrl_o.rd_data = rd_data_ctrl[ctrl_bank_sel]; assign flash_ctrl_o.rd_err = rd_err[ctrl_bank_sel]; - assign flash_ctrl_o.init_busy = init_busy; + assign flash_ctrl_o.init_busy = init_busy_i; assign flash_ctrl_o.prog_intg_err = |prog_intg_err; assign flash_ctrl_o.storage_relbl_err = |relbl_ecc_err; assign flash_ctrl_o.storage_intg_err = |intg_ecc_err; @@ -202,10 +189,8 @@ module flash_phy assign host_ecc_en = mubi4_test_true_strict(mubi4_and_hi(region_cfg.ecc_en, region_cfg.en)); // Prim flash to flash_phy_core connections - flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; - flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; - flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] prim_flash_req; - flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] prim_flash_rsp; + flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; + flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; @@ -294,8 +279,8 @@ module flash_phy .flash_disable_i(flash_disable[bank]), .scramble_req_o(scramble_req[bank]), .scramble_rsp_i(scramble_rsp[bank]), - .prim_flash_req_o(prim_flash_req[bank]), - .prim_flash_rsp_i(prim_flash_rsp[bank]), + .flash_macro_req_o(flash_macro_req_o.bank_reqs[bank]), + .flash_macro_rsp_i(flash_macro_rsp_i.bank_rsps[bank]), .ecc_single_err_o(ecc_single_err[bank]), .ecc_addr_o(ecc_addr[bank][BusBankAddrW-1:0]), .fsm_err_o(fsm_err[bank]), @@ -328,72 +313,9 @@ module flash_phy .arb_err_o(scramble_arb_err) // fatal error from redundant arbiter logic ); - // life cycle handling - logic tdo; - lc_ctrl_pkg::lc_tx_t [FlashLcDftLast-1:0] lc_nvm_debug_en; - - assign flash_ctrl_o.jtag_rsp.tdo = tdo & - lc_ctrl_pkg::lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdoSel]); - - prim_lc_sync #( - .NumCopies(int'(FlashLcDftLast)) - ) u_lc_nvm_debug_en_sync ( - .clk_i, - .rst_ni, - .lc_en_i(lc_nvm_debug_en_i), - .lc_en_o(lc_nvm_debug_en) - ); - - import lc_ctrl_pkg::lc_tx_test_true_strict; - // if nvm debug is enabled, flash_bist_enable controls entry to flash test mode. - // if nvm debug is disabled, flash_bist_enable is always turned off. - mubi4_t bist_enable_qual; - assign bist_enable_qual = (lc_tx_test_true_strict(lc_nvm_debug_en[FlashBistSel])) ? - flash_bist_enable_i : - MuBi4False; - - prim_flash #( - .NumBanks(NumBanks), - .InfosPerBank(InfosPerBank), - .InfoTypes(InfoTypes), - .InfoTypesWidth(InfoTypesWidth), - .PagesPerBank(PagesPerBank), - .WordsPerPage(WordsPerPage), - .DataWidth(flash_phy_pkg::FullDataWidth) - ) u_flash ( - .clk_i, - .rst_ni, - .tl_i, - .tl_o, - .flash_req_i(prim_flash_req), - .flash_rsp_o(prim_flash_rsp), - .prog_type_avail_o(prog_type_avail), - .init_busy_o(init_busy), - .tck_i(flash_ctrl_i.jtag_req.tck & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTckSel])), - .tdi_i(flash_ctrl_i.jtag_req.tdi & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdiSel])), - .tms_i(flash_ctrl_i.jtag_req.tms & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTmsSel])), - .tdo_o(tdo), - .bist_enable_i(bist_enable_qual), - .obs_ctrl_i, - .fla_obs_o, - .scanmode_i, - .scan_en_i, - .scan_rst_ni, - .flash_power_ready_h_i, - .flash_power_down_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .flash_err_o(flash_ctrl_o.macro_err), - .fatal_alert_o(fatal_prim_flash_alert_o), - .recov_alert_o(recov_prim_flash_alert_o) - ); logic unused_alert; assign unused_alert = flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack; - logic unused_trst_n; - assign unused_trst_n = flash_ctrl_i.jtag_req.trst_n; - assign flash_ctrl_o.jtag_rsp.tdo_oe = 1'b1; - ////////////////////////////////////////////// // Assertions, Assumptions, and Coverpoints // ///////////////////////////////////////////// diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv index 576c10780fa..bc91b0f78ac 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -9,6 +10,8 @@ // scramble, ECC, security and arbitration logic. module flash_phy_core + import flash_phy_macro_pkg::flash_phy_macro_bank_req_t; + import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t; import flash_phy_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -39,8 +42,8 @@ module flash_phy_core input prim_mubi_pkg::mubi4_t flash_disable_i, output scramble_req_t scramble_req_o, input scramble_rsp_t scramble_rsp_i, - input flash_phy_prim_flash_rsp_t prim_flash_rsp_i, - output flash_phy_prim_flash_req_t prim_flash_req_o, + input flash_phy_macro_bank_rsp_t flash_macro_rsp_i, + output flash_phy_macro_bank_req_t flash_macro_req_o, output logic host_req_rdy_o, output logic host_req_done_o, output logic rd_done_o, @@ -566,7 +569,7 @@ module flash_phy_core //////////////////////// // Connections to the actual flash macro wrapper - assign prim_flash_req_o = '{ + assign flash_macro_req_o = '{ rd_req: flash_rd_req, prog_req: flash_prog_req, prog_last: prog_last, @@ -583,9 +586,9 @@ module flash_phy_core prog_full_data: prog_full_data }; - assign ack = prim_flash_rsp_i.ack; - assign done = prim_flash_rsp_i.done; - assign flash_rdata = prim_flash_rsp_i.rdata; + assign ack = flash_macro_rsp_i.ack; + assign done = flash_macro_rsp_i.done; + assign flash_rdata = flash_macro_rsp_i.rdata; ///////////////////////////////// // Assertions diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv new file mode 100644 index 00000000000..525a6179743 --- /dev/null +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Flash phy macro package +// This has the interface to the flash macro wrapper. It is top-specific, +// but all dependencies are via macro wrapper overridden parameters, so +// it is okay for the flash macro wrapper to depend on this package. + +package flash_phy_macro_pkg; + + import flash_ctrl_pkg::ProgTypes; + + parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; + parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; + parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; + parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; + parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; + parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; + parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth + + flash_ctrl_top_specific_pkg::MetaDataWidth; + parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; + parameter int TestModeWidth = 2; + + // Transaction request to flash macro + typedef struct packed { + logic rd_req; + logic prog_req; + logic prog_last; + flash_ctrl_pkg::flash_prog_e prog_type; + logic pg_erase_req; + logic bk_erase_req; + logic erase_suspend_req; + logic he; + logic [BankAddrW-1:0] addr; + flash_ctrl_pkg::flash_part_e part; + logic [InfoTypesWidth-1:0] info_sel; + logic [DataWidth-1:0] prog_full_data; + } flash_phy_macro_bank_req_t; + + typedef struct packed { + flash_phy_macro_bank_req_t [NumBanks-1:0] bank_reqs; + } flash_phy_macro_req_t; + + // Transaction response from flash macro + typedef struct packed { + logic ack; + logic done; + logic [DataWidth-1:0] rdata; + } flash_phy_macro_bank_rsp_t; + + typedef struct packed { + flash_phy_macro_bank_rsp_t [NumBanks-1:0] bank_rsps; + } flash_phy_macro_rsp_t; + + // Status of flash macro + typedef struct packed { + // What program types flash macro supports + logic [ProgTypes-1:0] prog_type_avail; + // Asserted while flash is getting initialized + logic init_busy; + // Macro error + logic flash_err; + // Alert indications for the phy to connect to alert sender + logic fatal_alert; + logic recov_alert; + } flash_macro_status_t; + +endpackage : flash_phy_macro_pkg diff --git a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv index a96f558fba3..3cb5cc6befd 100644 --- a/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv +++ b/hw/top_earlgrey/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,15 +8,26 @@ package flash_phy_pkg; + import flash_phy_macro_pkg::NumBanks; + import flash_phy_macro_pkg::InfosPerBank; + import flash_phy_macro_pkg::InfoTypes; + import flash_phy_macro_pkg::InfoTypesWidth; + import flash_phy_macro_pkg::PagesPerBank; + import flash_phy_macro_pkg::WordsPerPage; + import flash_phy_macro_pkg::BankAddrW; + + export flash_phy_macro_pkg::NumBanks; + export flash_phy_macro_pkg::InfosPerBank; + export flash_phy_macro_pkg::InfoTypes; + export flash_phy_macro_pkg::InfoTypesWidth; + export flash_phy_macro_pkg::PagesPerBank; + export flash_phy_macro_pkg::WordsPerPage; + export flash_phy_macro_pkg::BankAddrW; + // flash phy parameters - parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; - parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; - parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; - parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; parameter int unsigned BankW = flash_ctrl_top_specific_pkg::BankW; parameter int unsigned PageW = flash_ctrl_top_specific_pkg::PageW; parameter int unsigned WordW = flash_ctrl_top_specific_pkg::WordW; - parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth; parameter int unsigned EccWidth = 8; parameter int unsigned MetaDataWidth = flash_ctrl_top_specific_pkg::MetaDataWidth; @@ -25,17 +37,13 @@ package flash_phy_pkg; // will switch to this after bus widening parameter int unsigned PlainIntgWidth = MetaDataWidth - EccWidth; parameter int unsigned PlainDataWidth = DataWidth + PlainIntgWidth; - //parameter int unsigned ScrDataWidth = DataWidth + EccWidth; parameter int unsigned FullDataWidth = DataWidth + MetaDataWidth; - parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; - parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; // flash ctrl / bus parameters parameter int unsigned BusWidth = flash_ctrl_top_specific_pkg::BusWidth; parameter int unsigned BusFullWidth = flash_ctrl_top_specific_pkg::BusFullWidth; parameter int unsigned BusBankAddrW = flash_ctrl_top_specific_pkg::BusBankAddrW; parameter int unsigned BusWordW = flash_ctrl_top_specific_pkg::BusWordW; - parameter int unsigned ProgTypes = flash_ctrl_top_specific_pkg::ProgTypes; // address bits remain must be 0 parameter int unsigned AddrBitsRemain = DataWidth % BusWidth; @@ -114,28 +122,6 @@ package flash_phy_pkg; DeScrambleOp = 1'b1 } cipher_ops_e; - // Connections to prim_flash - typedef struct packed { - logic rd_req; - logic prog_req; - logic prog_last; - flash_ctrl_top_specific_pkg::flash_prog_e prog_type; - logic pg_erase_req; - logic bk_erase_req; - logic erase_suspend_req; - logic he; - logic [BankAddrW-1:0] addr; - flash_ctrl_top_specific_pkg::flash_part_e part; - logic [InfoTypesWidth-1:0] info_sel; - logic [FullDataWidth-1:0] prog_full_data; - } flash_phy_prim_flash_req_t; - - typedef struct packed { - logic ack; - logic done; - logic [FullDataWidth-1:0] rdata; - } flash_phy_prim_flash_rsp_t; - typedef struct packed { logic calc_req; logic op_req; @@ -153,4 +139,4 @@ package flash_phy_pkg; logic [DataWidth-1:0] scrambled_data; } scramble_rsp_t; -endpackage // flash_phy_pkg +endpackage : flash_phy_pkg diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md index daa8e99256c..2c3c24bef44 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_asic.md @@ -143,9 +143,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

uart2_rx

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| @@ -165,7 +165,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

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| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw310.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw310.md index 4206061a74a..d7b35e09f2d 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw310.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw310.md @@ -148,9 +148,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

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| diff --git a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md index 1b6fb7e61e3..a56cdd4acce 100644 --- a/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md +++ b/hw/top_earlgrey/ip_autogen/pinmux/doc/pinout_cw340.md @@ -147,9 +147,9 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

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flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi

|

| +|

flash_macro_wrapper_tck

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTck

|

| +|

flash_macro_wrapper_tms

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTms

|

| +|

flash_macro_wrapper_tdi

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTdi

|

| |

sysrst_ctrl_aon_ac_present

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent

|

| |

sysrst_ctrl_aon_key0_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In

|

| |

sysrst_ctrl_aon_key1_in

|

muxed

|

-

|

- / kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In

|

| @@ -169,7 +169,7 @@ util/topgen.py -t hw/top_earlgrey/data/top_earlgrey.hjson -o hw/top_earlgrey/ |

pattgen_pcl1_tx

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselPattgenPcl1Tx / -

|

| |

spi_host1_sck

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Sck / -

|

| |

spi_host1_csb

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSpiHost1Csb / -

|

| -|

flash_ctrl_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashCtrlTdo / -

|

| +|

flash_macro_wrapper_tdo

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselFlashMacroWrapperTdo / -

|

| |

sensor_ctrl_aon_ast_debug_out[0]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 / -

|

| |

sensor_ctrl_aon_ast_debug_out[1]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 / -

|

| |

sensor_ctrl_aon_ast_debug_out[2]

|

muxed

|

-

|

kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 / -

|

| diff --git a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson index 8535419e5a9..0ac0c1a93ea 100644 --- a/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson +++ b/hw/top_earlgrey/lint/top_earlgrey_lint_cfgs.hjson @@ -87,6 +87,13 @@ additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" rel_path: "hw/top_earlgrey/ip_autogen/flash_ctrl/lint/{tool}" }, + # TODO Do we need this? + # { name: flash_macro_wrapper + # fusesoc_core: lowrisc:ip:flash_macro_wrapper + # import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] + # additional_fusesoc_argument: "--mapping=lowrisc:systems:top_earlgrey:0.1" + # rel_path: "hw/ip/flash_macro_wrapper/lint/{tool}" + # }, { name: gpio fusesoc_core: lowrisc:earlgrey_ip:gpio import_cfgs: ["{proj_root}/hw/lint/tools/dvsim/common_lint_cfg.hjson"] diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv index 7c30f141743..21c9d5fee3c 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey.sv @@ -70,6 +70,7 @@ module top_earlgrey #( parameter bit SecFlashCtrlScrambleEn = 1, parameter int FlashCtrlProgFifoDepth = 4, parameter int FlashCtrlRdFifoDepth = 16, + // parameters for flash_macro_wrapper // parameters for rv_dm parameter logic [31:0] RvDmIdcodeValue = jtag_id_pkg::RV_DM_JTAG_IDCODE, parameter bit RvDmUseDmiInterface = 0, @@ -402,11 +403,12 @@ module top_earlgrey #( logic [8:0] cio_sensor_ctrl_aon_ast_debug_out_en_d2p; // sram_ctrl_ret_aon // flash_ctrl - logic cio_flash_ctrl_tck_p2d; - logic cio_flash_ctrl_tms_p2d; - logic cio_flash_ctrl_tdi_p2d; - logic cio_flash_ctrl_tdo_d2p; - logic cio_flash_ctrl_tdo_en_d2p; + // flash_macro_wrapper + logic cio_flash_macro_wrapper_tck_p2d; + logic cio_flash_macro_wrapper_tms_p2d; + logic cio_flash_macro_wrapper_tdi_p2d; + logic cio_flash_macro_wrapper_tdo_d2p; + logic cio_flash_macro_wrapper_tdo_en_d2p; // rv_dm // rv_plic // aes @@ -675,6 +677,9 @@ module top_earlgrey #( lc_ctrl_pkg::lc_tx_t lc_ctrl_lc_rma_state; otp_ctrl_macro_pkg::otp_ctrl_macro_req_t otp_ctrl_otp_macro_req; otp_ctrl_macro_pkg::otp_ctrl_macro_rsp_t otp_ctrl_otp_macro_rsp; + flash_phy_macro_pkg::flash_phy_macro_req_t flash_ctrl_flash_macro_req; + flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_ctrl_flash_macro_rsp; + flash_phy_macro_pkg::flash_macro_status_t flash_ctrl_flash_macro_status; logic rv_plic_msip; logic rv_plic_irq; logic rv_dm_debug_req; @@ -710,8 +715,8 @@ module top_earlgrey #( tlul_pkg::tl_d2h_t usbdev_tl_rsp; tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req; tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp; - tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req; - tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp; + tlul_pkg::tl_h2d_t flash_macro_wrapper_tl_req; + tlul_pkg::tl_d2h_t flash_macro_wrapper_tl_rsp; tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req; tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp; tlul_pkg::tl_h2d_t hmac_tl_req; @@ -2293,15 +2298,6 @@ module top_earlgrey #( .RdFifoDepth(FlashCtrlRdFifoDepth) ) u_flash_ctrl ( - // Input - .cio_tck_i (cio_flash_ctrl_tck_p2d), - .cio_tms_i (cio_flash_ctrl_tms_p2d), - .cio_tdi_i (cio_flash_ctrl_tdi_p2d), - - // Output - .cio_tdo_o (cio_flash_ctrl_tdo_d2p), - .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p), - // Interrupt .intr_prog_empty_o (intr_flash_ctrl_prog_empty), .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl), @@ -2320,12 +2316,6 @@ module top_earlgrey #( // Inter-module signals .otp_o(flash_ctrl_otp_req), .otp_i(flash_ctrl_otp_rsp), - .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), - .flash_bist_enable_i(flash_bist_enable_i), - .flash_power_down_h_i(flash_power_down_h_i), - .flash_power_ready_h_i(flash_power_ready_h_i), - .flash_test_mode_a_io(flash_test_mode_a_io), - .flash_test_voltage_h_io(flash_test_voltage_h_io), .lc_creator_seed_sw_rw_en_i(lc_ctrl_lc_creator_seed_sw_rw_en), .lc_owner_seed_sw_rw_en_i(lc_ctrl_lc_owner_seed_sw_rw_en), .lc_iso_part_sw_rd_en_i(lc_ctrl_lc_iso_part_sw_rd_en), @@ -2337,17 +2327,13 @@ module top_earlgrey #( .rma_seed_i(flash_ctrl_rma_seed), .pwrmgr_o(pwrmgr_aon_pwr_flash), .keymgr_o(flash_ctrl_keymgr), - .obs_ctrl_i(ast_obs_ctrl), - .fla_obs_o(flash_obs_o), + .flash_macro_o(flash_ctrl_flash_macro_req), + .flash_macro_i(flash_ctrl_flash_macro_rsp), + .flash_macro_status_i(flash_ctrl_flash_macro_status), .core_tl_i(flash_ctrl_core_tl_req), .core_tl_o(flash_ctrl_core_tl_rsp), - .prim_tl_i(flash_ctrl_prim_tl_req), - .prim_tl_o(flash_ctrl_prim_tl_rsp), .mem_tl_i(flash_ctrl_mem_tl_req), .mem_tl_o(flash_ctrl_mem_tl_rsp), - .scanmode_i, - .scan_rst_ni, - .scan_en_i, // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_main_infra), @@ -2356,6 +2342,48 @@ module top_earlgrey #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); + flash_macro_wrapper #( + .NumBanks(flash_phy_macro_pkg::NumBanks), + .InfosPerBank(flash_phy_macro_pkg::InfosPerBank), + .InfoTypes(flash_phy_macro_pkg::InfoTypes), + .InfoTypesWidth(flash_phy_macro_pkg::InfoTypesWidth), + .PagesPerBank(flash_phy_macro_pkg::PagesPerBank), + .WordsPerPage(flash_phy_macro_pkg::WordsPerPage), + .DataWidth(flash_phy_macro_pkg::DataWidth), + .TestModeWidth(flash_phy_macro_pkg::TestModeWidth) + ) u_flash_macro_wrapper ( + + // Input + .cio_tck_i (cio_flash_macro_wrapper_tck_p2d), + .cio_tms_i (cio_flash_macro_wrapper_tms_p2d), + .cio_tdi_i (cio_flash_macro_wrapper_tdi_p2d), + + // Output + .cio_tdo_o (cio_flash_macro_wrapper_tdo_d2p), + .cio_tdo_en_o (cio_flash_macro_wrapper_tdo_en_d2p), + + // Inter-module signals + .flash_i(flash_ctrl_flash_macro_req), + .flash_o(flash_ctrl_flash_macro_rsp), + .status_o(flash_ctrl_flash_macro_status), + .lc_nvm_debug_en_i(lc_ctrl_lc_nvm_debug_en), + .bist_enable_i(flash_bist_enable_i), + .power_down_h_i(flash_power_down_h_i), + .power_ready_h_i(flash_power_ready_h_i), + .test_mode_a_io(flash_test_mode_a_io), + .test_voltage_h_io(flash_test_voltage_h_io), + .obs_ctrl_i(ast_obs_ctrl), + .fla_obs_o(flash_obs_o), + .tl_i(flash_macro_wrapper_tl_req), + .tl_o(flash_macro_wrapper_tl_rsp), + .scanmode_i, + .scan_rst_ni, + .scan_en_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); rv_dm #( .AlertAsyncOn(alert_handler_reg_pkg::AsyncOn[40:40]), .AlertSkewCycles(top_pkg::AlertSkewCycles), @@ -3138,9 +3166,9 @@ module top_earlgrey #( .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req), .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp), - // port: tl_flash_ctrl__prim - .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req), - .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp), + // port: tl_flash_macro_wrapper + .tl_flash_macro_wrapper_o(flash_macro_wrapper_tl_req), + .tl_flash_macro_wrapper_i(flash_macro_wrapper_tl_rsp), // port: tl_flash_ctrl__mem .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req), @@ -3370,9 +3398,9 @@ module top_earlgrey #( assign cio_uart2_rx_p2d = mio_p2d[MioInUart2Rx]; assign cio_uart3_rx_p2d = mio_p2d[MioInUart3Rx]; assign cio_spi_device_tpm_csb_p2d = mio_p2d[MioInSpiDeviceTpmCsb]; - assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; - assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; - assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; + assign cio_flash_macro_wrapper_tck_p2d = mio_p2d[MioInFlashMacroWrapperTck]; + assign cio_flash_macro_wrapper_tms_p2d = mio_p2d[MioInFlashMacroWrapperTms]; + assign cio_flash_macro_wrapper_tdi_p2d = mio_p2d[MioInFlashMacroWrapperTdi]; assign cio_sysrst_ctrl_aon_ac_present_p2d = mio_p2d[MioInSysrstCtrlAonAcPresent]; assign cio_sysrst_ctrl_aon_key0_in_p2d = mio_p2d[MioInSysrstCtrlAonKey0In]; assign cio_sysrst_ctrl_aon_key1_in_p2d = mio_p2d[MioInSysrstCtrlAonKey1In]; @@ -3434,7 +3462,7 @@ module top_earlgrey #( assign mio_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_d2p; assign mio_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_d2p; assign mio_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_d2p; - assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p; + assign mio_d2p[MioOutFlashMacroWrapperTdo] = cio_flash_macro_wrapper_tdo_d2p; assign mio_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_d2p[0]; assign mio_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_d2p[1]; assign mio_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_d2p[2]; @@ -3511,7 +3539,7 @@ module top_earlgrey #( assign mio_en_d2p[MioOutPattgenPcl1Tx] = cio_pattgen_pcl1_tx_en_d2p; assign mio_en_d2p[MioOutSpiHost1Sck] = cio_spi_host1_sck_en_d2p; assign mio_en_d2p[MioOutSpiHost1Csb] = cio_spi_host1_csb_en_d2p; - assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p; + assign mio_en_d2p[MioOutFlashMacroWrapperTdo] = cio_flash_macro_wrapper_tdo_en_d2p; assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut0] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[0]; assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut1] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[1]; assign mio_en_d2p[MioOutSensorCtrlAonAstDebugOut2] = cio_sensor_ctrl_aon_ast_debug_out_en_d2p[2]; diff --git a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv index 227f81f0abd..195b389ce6f 100644 --- a/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv +++ b/hw/top_earlgrey/rtl/autogen/top_earlgrey_pkg.sv @@ -320,14 +320,14 @@ package top_earlgrey_pkg; parameter int unsigned TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES = 32'h200; /** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. + * Peripheral base address for flash_macro_wrapper in top earlgrey. */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR = 32'h41008000; + parameter int unsigned TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR = 32'h41008000; /** - * Peripheral size in bytes for prim device on flash_ctrl in top earlgrey. + * Peripheral size in bytes for flash_macro_wrapper in top earlgrey. */ - parameter int unsigned TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80; + parameter int unsigned TOP_EARLGREY_FLASH_MACRO_WRAPPER_SIZE_BYTES = 32'h80; /** * Peripheral base address for regs device on rv_dm in top earlgrey. @@ -897,9 +897,9 @@ package top_earlgrey_pkg; MioInUart2Rx = 44, MioInUart3Rx = 45, MioInSpiDeviceTpmCsb = 46, - MioInFlashCtrlTck = 47, - MioInFlashCtrlTms = 48, - MioInFlashCtrlTdi = 49, + MioInFlashMacroWrapperTck = 47, + MioInFlashMacroWrapperTms = 48, + MioInFlashMacroWrapperTdi = 49, MioInSysrstCtrlAonAcPresent = 50, MioInSysrstCtrlAonKey0In = 51, MioInSysrstCtrlAonKey1In = 52, @@ -963,7 +963,7 @@ package top_earlgrey_pkg; MioOutPattgenPcl1Tx = 49, MioOutSpiHost1Sck = 50, MioOutSpiHost1Csb = 51, - MioOutFlashCtrlTdo = 52, + MioOutFlashMacroWrapperTdo = 52, MioOutSensorCtrlAonAstDebugOut0 = 53, MioOutSensorCtrlAonAstDebugOut1 = 54, MioOutSensorCtrlAonAstDebugOut2 = 55, @@ -1110,6 +1110,7 @@ package top_earlgrey_pkg; PeripheralEdn1, PeripheralEntropySrc, PeripheralFlashCtrl, + PeripheralFlashMacroWrapper, PeripheralGpio, PeripheralHmac, PeripheralI2c0, diff --git a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs index d55558f09e6..dd5b3fceab6 100644 --- a/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs +++ b/hw/top_earlgrey/sw/autogen/chip/top_earlgrey.rs @@ -455,19 +455,19 @@ pub const FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000; /// `FLASH_CTRL_CORE_BASE_ADDR + FLASH_CTRL_CORE_SIZE_BYTES`. pub const FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200; -/// Peripheral base address for prim device on flash_ctrl in top earlgrey. +/// Peripheral base address for flash_macro_wrapper in top earlgrey. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped /// registers associated with the peripheral (usually via a DIF). -pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000; +pub const FLASH_MACRO_WRAPPER_BASE_ADDR: usize = 0x41008000; -/// Peripheral size for prim device on flash_ctrl in top earlgrey. +/// Peripheral size for flash_macro_wrapper in top earlgrey. /// /// This is the size (in bytes) of the peripheral's reserved memory area. All /// memory-mapped registers associated with this peripheral should have an -/// address between #FLASH_CTRL_PRIM_BASE_ADDR and -/// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`. -pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80; +/// address between #FLASH_MACRO_WRAPPER_BASE_ADDR and +/// `FLASH_MACRO_WRAPPER_BASE_ADDR + FLASH_MACRO_WRAPPER_SIZE_BYTES`. +pub const FLASH_MACRO_WRAPPER_SIZE_BYTES: usize = 0x80; /// Peripheral base address for regs device on rv_dm in top earlgrey. /// @@ -2344,11 +2344,11 @@ pub enum PinmuxPeripheralIn { /// Peripheral Input 46 SpiDeviceTpmCsb = 46, /// Peripheral Input 47 - FlashCtrlTck = 47, + FlashMacroWrapperTck = 47, /// Peripheral Input 48 - FlashCtrlTms = 48, + FlashMacroWrapperTms = 48, /// Peripheral Input 49 - FlashCtrlTdi = 49, + FlashMacroWrapperTdi = 49, /// Peripheral Input 50 SysrstCtrlAonAcPresent = 50, /// Peripheral Input 51 @@ -2416,9 +2416,9 @@ impl TryFrom for PinmuxPeripheralIn { 44 => Ok(Self::Uart2Rx), 45 => Ok(Self::Uart3Rx), 46 => Ok(Self::SpiDeviceTpmCsb), - 47 => Ok(Self::FlashCtrlTck), - 48 => Ok(Self::FlashCtrlTms), - 49 => Ok(Self::FlashCtrlTdi), + 47 => Ok(Self::FlashMacroWrapperTck), + 48 => Ok(Self::FlashMacroWrapperTms), + 49 => Ok(Self::FlashMacroWrapperTdi), 50 => Ok(Self::SysrstCtrlAonAcPresent), 51 => Ok(Self::SysrstCtrlAonKey0In), 52 => Ok(Self::SysrstCtrlAonKey1In), @@ -2864,7 +2864,7 @@ pub enum PinmuxOutsel { /// Peripheral Output 51 SpiHost1Csb = 54, /// Peripheral Output 52 - FlashCtrlTdo = 55, + FlashMacroWrapperTdo = 55, /// Peripheral Output 53 SensorCtrlAonAstDebugOut0 = 56, /// Peripheral Output 54 @@ -2970,7 +2970,7 @@ impl TryFrom for PinmuxOutsel { 52 => Ok(Self::PattgenPcl1Tx), 53 => Ok(Self::SpiHost1Sck), 54 => Ok(Self::SpiHost1Csb), - 55 => Ok(Self::FlashCtrlTdo), + 55 => Ok(Self::FlashMacroWrapperTdo), 56 => Ok(Self::SensorCtrlAonAstDebugOut0), 57 => Ok(Self::SensorCtrlAonAstDebugOut1), 58 => Ok(Self::SensorCtrlAonAstDebugOut2), diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey.h b/hw/top_earlgrey/sw/autogen/top_earlgrey.h index fc232222dd5..fbacb03ef53 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey.h @@ -589,22 +589,22 @@ extern "C" { #define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200u /** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. + * Peripheral base address for flash_macro_wrapper in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u +#define TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u /** - * Peripheral size for prim device on flash_ctrl in top earlgrey. + * Peripheral size for flash_macro_wrapper in top earlgrey. * * This is the size (in bytes) of the peripheral's reserved memory area. All * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`. + * address between #TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR and + * `TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_EARLGREY_FLASH_MACRO_WRAPPER_SIZE_BYTES`. */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u +#define TOP_EARLGREY_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u /** * Peripheral base address for regs device on rv_dm in top earlgrey. @@ -1390,9 +1390,9 @@ typedef enum top_earlgrey_pinmux_peripheral_in { kTopEarlgreyPinmuxPeripheralInUart2Rx = 44, /**< Peripheral Input 44 */ kTopEarlgreyPinmuxPeripheralInUart3Rx = 45, /**< Peripheral Input 45 */ kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb = 46, /**< Peripheral Input 46 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTck = 47, /**< Peripheral Input 47 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTms = 48, /**< Peripheral Input 48 */ - kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi = 49, /**< Peripheral Input 49 */ + kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTck = 47, /**< Peripheral Input 47 */ + kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTms = 48, /**< Peripheral Input 48 */ + kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTdi = 49, /**< Peripheral Input 49 */ kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent = 50, /**< Peripheral Input 50 */ kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In = 51, /**< Peripheral Input 51 */ kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In = 52, /**< Peripheral Input 52 */ @@ -1572,7 +1572,7 @@ typedef enum top_earlgrey_pinmux_outsel { kTopEarlgreyPinmuxOutselPattgenPcl1Tx = 52, /**< Peripheral Output 49 */ kTopEarlgreyPinmuxOutselSpiHost1Sck = 53, /**< Peripheral Output 50 */ kTopEarlgreyPinmuxOutselSpiHost1Csb = 54, /**< Peripheral Output 51 */ - kTopEarlgreyPinmuxOutselFlashCtrlTdo = 55, /**< Peripheral Output 52 */ + kTopEarlgreyPinmuxOutselFlashMacroWrapperTdo = 55, /**< Peripheral Output 52 */ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0 = 56, /**< Peripheral Output 53 */ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1 = 57, /**< Peripheral Output 54 */ kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2 = 58, /**< Peripheral Output 55 */ diff --git a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h index 23a47ee8292..431e3a45519 100644 --- a/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h +++ b/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h @@ -594,22 +594,22 @@ */ #define TOP_EARLGREY_FLASH_CTRL_CORE_SIZE_BYTES 0x200 /** - * Peripheral base address for prim device on flash_ctrl in top earlgrey. + * Peripheral base address for flash_macro_wrapper in top earlgrey. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000 +#define TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000 /** - * Peripheral size for prim device on flash_ctrl in top earlgrey. + * Peripheral size for flash_macro_wrapper in top earlgrey. * * This is the size (in bytes) of the peripheral's reserved memory area. All * memory-mapped registers associated with this peripheral should have an - * address between #TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_EARLGREY_FLASH_CTRL_PRIM_BASE_ADDR + TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES`. + * address between #TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR and + * `TOP_EARLGREY_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_EARLGREY_FLASH_MACRO_WRAPPER_SIZE_BYTES`. */ -#define TOP_EARLGREY_FLASH_CTRL_PRIM_SIZE_BYTES 0x80 +#define TOP_EARLGREY_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80 /** * Peripheral base address for regs device on rv_dm in top earlgrey. * diff --git a/hw/top_earlgrey/top_earlgrey.core b/hw/top_earlgrey/top_earlgrey.core index 90db8de8305..0a9cc4237bd 100644 --- a/hw/top_earlgrey/top_earlgrey.core +++ b/hw/top_earlgrey/top_earlgrey.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:top_earlgrey:0.1" @@ -29,7 +30,7 @@ filesets: - lowrisc:ip:kmac - lowrisc:ip:otbn - lowrisc:prim:ram_1p_scr - - lowrisc:prim:flash + - lowrisc:ip:flash_macro_wrapper - lowrisc:ip:sram_ctrl - lowrisc:ip:keymgr - lowrisc:earlgrey_constants:top_pkg @@ -111,7 +112,6 @@ mapping: "lowrisc:virtual_constants:top_pkg": "lowrisc:earlgrey_constants:top_pkg" "lowrisc:virtual_constants:top_racl_pkg": "lowrisc:earlgrey_constants:top_racl_pkg" "lowrisc:systems:ast_pkg": "lowrisc:systems:top_earlgrey_ast_pkg" - "lowrisc:virtual_ip:flash_ctrl_prim_reg_top": "lowrisc:earlgrey_ip:flash_ctrl_prim_reg_top" "lowrisc:virtual_ip:lc_ctrl_state_pkg": "lowrisc:earlgrey_constants:testing_lc_ctrl_state_pkg" "lowrisc:virtual_constants:rnd_cnst_pkg": "lowrisc:earlgrey_constants:testing_rnd_cnst_pkg" # TODO(#27347): prim_legacy_pkg is deprecated diff --git a/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl b/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl index 28951548080..813549fc56a 100644 --- a/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl +++ b/hw/top_earlgrey/util/vivado_hook_write_bitstream_pre.tcl @@ -1,4 +1,5 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -237,9 +238,9 @@ dict set memInfo otp [apply $gen_mem_info $otp_brams $mem_type_regex 0 16 "Proce # The flash banks have 76-bit wide words. 64 bits are data, and 12 bits are metadata / integrity. for {set bank 0} {$bank < 2} {incr bank} { for {set partition 0} {$partition < 3} {incr partition} { - set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[0].*"] " "] + set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_macro_wrapper*gen_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[0].*"] " "] dict set memInfo "flash${bank}_info${partition}_data" [apply $gen_mem_info $flash_info_brams $mem_type_regex 0 1 "MemoryArray"] - set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[64].*"] " "] + set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_macro_wrapper*gen_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[64].*"] " "] dict set memInfo "flash${bank}_info${partition}_intg" [apply $gen_mem_info $flash_info_brams $mem_type_regex 0 1 "MemoryArray"] } } diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core index ec19d5315ad..785dd115c75 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_cw305.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_englishbreakfast_cw305:0.1" @@ -13,12 +14,11 @@ filesets: - lowrisc:systems:top_englishbreakfast_pkg - lowrisc:systems:top_englishbreakfast_ast - lowrisc:systems:top_earlgrey_padring + - lowrisc:ip:flash_macro_wrapper_reg_top - lowrisc:earlgrey_systems:scan_role_pkg - - lowrisc:englishbreakfast_ip:flash_ctrl_prim_reg_top # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_xilinx:all - - lowrisc:prim_generic:flash files: - rtl/clkgen_xil7series.sv - rtl/usr_access_xil7series.sv diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc index 6d625877333..81bdde01f56 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc +++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.cc @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -27,8 +28,8 @@ int main(int argc, char **argv) { MemArea ram(top_scope + ".u_ram1p_ram_main." + ram1p_adv_scope, 0x20000 / 4, 4); MemArea flash0(top_scope + - ".u_flash_ctrl.u_eflash.u_flash." - "gen_prim_flash_banks[0].u_prim_flash_bank.u_mem", + ".u_flash_macro_wrapper.gen_flash_banks[0]." + "u_flash_bank.u_mem", 0x100000 / 8, 8); memutil.RegisterMemoryArea("rom", 0x8000, &rom); diff --git a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core index 0e6a88ccf13..62cbebc85c1 100644 --- a/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core +++ b/hw/top_englishbreakfast/chip_englishbreakfast_verilator.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:chip_englishbreakfast_verilator:0.1" @@ -26,12 +27,11 @@ filesets: - lowrisc:dv:sim_sram - lowrisc:dv:sw_test_status - lowrisc:dv:dv_test_status - - lowrisc:englishbreakfast_ip:flash_ctrl_prim_reg_top + - lowrisc:ip:flash_macro_wrapper_reg_top - lowrisc:prim:clock_div # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:prim_generic:all - - lowrisc:prim_generic:flash files: - rtl/chip_englishbreakfast_verilator.sv: { file_type: systemVerilogSource } diff --git a/hw/top_englishbreakfast/data/autogen/defs.bzl b/hw/top_englishbreakfast/data/autogen/defs.bzl index be04e2621e0..ab1f0d4aa7f 100644 --- a/hw/top_englishbreakfast/data/autogen/defs.bzl +++ b/hw/top_englishbreakfast/data/autogen/defs.bzl @@ -12,6 +12,7 @@ load("//hw/ip/aon_timer:defs.bzl", "AON_TIMER") load("//hw/top_englishbreakfast/ip/ast:defs.bzl", "AST") load("//hw/top_englishbreakfast/ip_autogen/clkmgr:defs.bzl", "CLKMGR") load("//hw/top_englishbreakfast/ip_autogen/flash_ctrl:defs.bzl", "FLASH_CTRL") +load("//hw/ip/flash_macro_wrapper:defs.bzl", "FLASH_MACRO_WRAPPER") load("//hw/top_englishbreakfast/ip_autogen/gpio:defs.bzl", "GPIO") load("//hw/top_englishbreakfast/ip_autogen/pinmux:defs.bzl", "PINMUX") load("//hw/top_englishbreakfast/ip_autogen/pwrmgr:defs.bzl", "PWRMGR") @@ -32,6 +33,7 @@ ENGLISHBREAKFAST_IPS = [ AST, CLKMGR, FLASH_CTRL, + FLASH_MACRO_WRAPPER, GPIO, PINMUX, PWRMGR, diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson index 50f3d29c347..6517181edbf 100644 --- a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson +++ b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson @@ -472,7 +472,7 @@ aon_timer_aon ast flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper rv_plic aes sram_ctrl_main.regs @@ -3051,10 +3051,6 @@ { hart: 0x41000000 } - prim: - { - hart: 0x41008000 - } mem: { hart: 0x20000000 @@ -3134,76 +3130,6 @@ inst_name: flash_ctrl index: -1 } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - top_signame: flash_bist_enable - conn_type: false - index: -1 - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_down_h - conn_type: false - index: -1 - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_ready_h - conn_type: false - index: -1 - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - index: -1 - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - index: -1 - } { name: lc_creator_seed_sw_rw_en struct: lc_tx @@ -3317,31 +3243,32 @@ index: -1 } { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv + name: flash_macro + desc: Data interface to the flash macro wrapper + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: req width: 1 inst_name: flash_ctrl default: "" - external: true - top_signame: obs_ctrl - conn_type: false + end_idx: -1 + top_signame: flash_ctrl_flash_macro index: -1 } { - name: fla_obs - struct: logic + name: flash_macro_status + desc: Status interface from the flash macro wrapper + struct: flash_macro_status + package: flash_phy_macro_pkg type: uni - act: req - width: 8 + act: rcv + width: 1 inst_name: flash_ctrl default: "" - package: "" - external: true - top_signame: flash_obs - conn_type: false + end_idx: -1 + top_type: broadcast + top_signame: flash_ctrl_flash_macro_status index: -1 } { @@ -3358,7 +3285,7 @@ index: -1 } { - name: prim_tl + name: mem_tl struct: tl package: tlul_pkg type: req_rsp @@ -3367,23 +3294,269 @@ inst_name: flash_ctrl default: "" end_idx: -1 - top_signame: flash_ctrl_prim_tl + top_signame: flash_ctrl_mem_tl index: -1 } + ] + generate_dif: true + domain: + [ + "0" + ] + } + { + name: flash_macro_wrapper + type: flash_macro_wrapper + clock_srcs: + { + clk_i: main + } + clock_group: infra + reset_connections: + { + rst_ni: { - name: mem_tl + name: lc + domain: "0" + } + } + param_decl: + { + NumBanks: "2" + InfosPerBank: "10" + InfoTypes: "3" + InfoTypesWidth: "2" + PagesPerBank: "16" + WordsPerPage: "256" + DataWidth: "72" + TestModeWidth: "2" + } + clock_connections: + { + clk_i: clkmgr_aon_clocks.clk_main_infra + } + memory: {} + param_list: + [ + { + name: NumBanks + desc: Number of flash banks + type: int + default: "2" + local: "false" + expose: "false" + name_top: FlashMacroWrapperNumBanks + } + { + name: InfosPerBank + desc: Info pages per bank + type: int + default: "10" + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfosPerBank + } + { + name: InfoTypes + desc: Number of different info page types per bank + type: int + default: "3" + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfoTypes + } + { + name: InfoTypesWidth + desc: Number of bits to encode the info page types + type: int + default: "2" + local: "false" + expose: "false" + name_top: FlashMacroWrapperInfoTypesWidth + } + { + name: PagesPerBank + desc: Number of data pages per bank + type: int + default: "16" + local: "false" + expose: "false" + name_top: FlashMacroWrapperPagesPerBank + } + { + name: WordsPerPage + desc: Number of words per data page + type: int + default: "256" + local: "false" + expose: "false" + name_top: FlashMacroWrapperWordsPerPage + } + { + name: DataWidth + desc: Number of bits per data word + type: int + default: "72" + local: "false" + expose: "false" + name_top: FlashMacroWrapperDataWidth + } + { + name: TestModeWidth + desc: Number of bits to encode test mode + type: int + default: "2" + local: "false" + expose: "false" + name_top: FlashMacroWrapperTestModeWidth + } + ] + inter_signal_list: + [ + { + name: flash + desc: Data interface to the flash controller + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro + index: -1 + } + { + name: status + struct: flash_macro_status + package: flash_phy_macro_pkg + type: uni + act: req + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro_status + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: bist_enable + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: flash_bist_enable + conn_type: false + index: -1 + } + { + name: power_down_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_down_h + conn_type: false + index: -1 + } + { + name: power_ready_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_ready_h + conn_type: false + index: -1 + } + { + name: test_mode_a + struct: "" + type: io + act: none + width: 2 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: test_voltage_h + struct: "" + type: io + act: none + width: 1 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: obs_ctrl + conn_type: false + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_obs + conn_type: false + index: -1 + } + { + name: tl struct: tl package: tlul_pkg type: req_rsp act: rsp width: 1 - inst_name: flash_ctrl + inst_name: flash_macro_wrapper default: "" end_idx: -1 - top_signame: flash_ctrl_mem_tl + top_signame: flash_macro_wrapper_tl index: -1 } ] + base_addrs: + { + null: + { + hart: 0x41008000 + } + } generate_dif: true domain: [ @@ -4956,6 +5129,14 @@ [ aes.idle ] + flash_ctrl.flash_macro: + [ + flash_macro_wrapper.flash + ] + flash_ctrl.flash_macro_status: + [ + flash_macro_wrapper.status + ] rv_plic.msip: [ rv_core_ibex.irq_software @@ -5014,9 +5195,9 @@ [ main.tl_flash_ctrl__core ] - flash_ctrl.prim_tl: + flash_macro_wrapper.tl: [ - main.tl_flash_ctrl__prim + main.tl_flash_macro_wrapper ] flash_ctrl.mem_tl: [ @@ -5114,11 +5295,11 @@ clkmgr_aon.all_clk_byp_ack: all_clk_byp_ack clkmgr_aon.io_clk_byp_req: io_clk_byp_req clkmgr_aon.io_clk_byp_ack: io_clk_byp_ack - flash_ctrl.flash_bist_enable: flash_bist_enable - flash_ctrl.flash_power_down_h: flash_power_down_h - flash_ctrl.flash_power_ready_h: flash_power_ready_h - flash_ctrl.obs_ctrl: obs_ctrl - flash_ctrl.fla_obs: flash_obs + flash_macro_wrapper.bist_enable: flash_bist_enable + flash_macro_wrapper.power_down_h: flash_power_down_h + flash_macro_wrapper.power_ready_h: flash_power_ready_h + flash_macro_wrapper.obs_ctrl: obs_ctrl + flash_macro_wrapper.fla_obs: flash_obs peri.tl_ast: ast_tl pinmux_aon.dft_strap_test: dft_strap_test pinmux_aon.dft_hold_tap_sel: dft_hold_tap_sel @@ -5186,7 +5367,7 @@ flash_ctrl.mem peri flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper aes rv_plic sram_ctrl_main.ram @@ -5308,13 +5489,13 @@ pipeline: true } { - name: flash_ctrl.prim + name: flash_macro_wrapper type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: true rsp_fifo_pass: false - inst_type: flash_ctrl + inst_type: flash_macro_wrapper addr_range: [ { @@ -5541,7 +5722,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -5549,7 +5730,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -7392,43 +7573,10 @@ attr: InputStd connection: direct desc: "" - glob_idx: 11 - } - { - name: uart0_rx - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - glob_idx: 32 - } - { - name: uart1_rx - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - glob_idx: 33 - } - { - name: flash_ctrl_tck - width: 1 - type: input - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - glob_idx: 34 + glob_idx: 11 } { - name: flash_ctrl_tms + name: uart0_rx width: 1 type: input idx: -1 @@ -7436,10 +7584,10 @@ attr: "" connection: muxed desc: "" - glob_idx: 35 + glob_idx: 32 } { - name: flash_ctrl_tdi + name: uart1_rx width: 1 type: input idx: -1 @@ -7447,7 +7595,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 36 + glob_idx: 33 } { name: usbdev_sense @@ -7458,7 +7606,7 @@ attr: "" connection: muxed desc: "" - glob_idx: 37 + glob_idx: 34 } { name: spi_host0_sck @@ -7504,17 +7652,6 @@ desc: "" glob_idx: 33 } - { - name: flash_ctrl_tdo - width: 1 - type: output - idx: -1 - pad: "" - attr: "" - connection: muxed - desc: "" - glob_idx: 34 - } ] io_counts: { @@ -7528,8 +7665,8 @@ muxed: { inouts: 32 - inputs: 6 - outputs: 3 + inputs: 3 + outputs: 2 pads: 47 } } @@ -8960,6 +9097,31 @@ domain: "0" } } + { + name: infra_lc_0 + clock_group: + { + name: infra + src: top + sw_cg: no + unique: no + clocks: + { + clk_main_infra: main + clk_io_div4_infra: io_div4 + clk_io_infra: io + clk_usb_infra: usb + } + } + clock_connection: clkmgr_aon_clocks.clk_main_infra + unmanaged_clock: false + unmanaged_reset: false + reset_connection: + { + name: lc + domain: "0" + } + } ] outgoing_alert_lpgs: { @@ -10978,76 +11140,6 @@ inst_name: flash_ctrl index: -1 } - { - name: lc_nvm_debug_en - struct: lc_tx - package: lc_ctrl_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - index: -1 - } - { - name: flash_bist_enable - struct: mubi4 - package: prim_mubi_pkg - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - external: true - top_signame: flash_bist_enable - conn_type: false - index: -1 - } - { - name: flash_power_down_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_down_h - conn_type: false - index: -1 - } - { - name: flash_power_ready_h - struct: logic - type: uni - act: rcv - width: 1 - inst_name: flash_ctrl - default: "" - package: "" - external: true - top_signame: flash_power_ready_h - conn_type: false - index: -1 - } - { - name: flash_test_mode_a - struct: "" - type: io - act: none - width: 2 - inst_name: flash_ctrl - index: -1 - } - { - name: flash_test_voltage_h - struct: "" - type: io - act: none - width: 1 - inst_name: flash_ctrl - index: -1 - } { name: lc_creator_seed_sw_rw_en struct: lc_tx @@ -11161,31 +11253,32 @@ index: -1 } { - name: obs_ctrl - struct: ast_obs_ctrl - package: ast_pkg - type: uni - act: rcv + name: flash_macro + desc: Data interface to the flash macro wrapper + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: req width: 1 inst_name: flash_ctrl default: "" - external: true - top_signame: obs_ctrl - conn_type: false + end_idx: -1 + top_signame: flash_ctrl_flash_macro index: -1 } { - name: fla_obs - struct: logic + name: flash_macro_status + desc: Status interface from the flash macro wrapper + struct: flash_macro_status + package: flash_phy_macro_pkg type: uni - act: req - width: 8 + act: rcv + width: 1 inst_name: flash_ctrl default: "" - package: "" - external: true - top_signame: flash_obs - conn_type: false + end_idx: -1 + top_type: broadcast + top_signame: flash_ctrl_flash_macro_status index: -1 } { @@ -11202,7 +11295,7 @@ index: -1 } { - name: prim_tl + name: mem_tl struct: tl package: tlul_pkg type: req_rsp @@ -11211,20 +11304,143 @@ inst_name: flash_ctrl default: "" end_idx: -1 - top_signame: flash_ctrl_prim_tl + top_signame: flash_ctrl_mem_tl index: -1 } { - name: mem_tl + name: flash + desc: Data interface to the flash controller + struct: flash_phy_macro + package: flash_phy_macro_pkg + type: req_rsp + act: rsp + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro + index: -1 + } + { + name: status + struct: flash_macro_status + package: flash_phy_macro_pkg + type: uni + act: req + width: 1 + inst_name: flash_macro_wrapper + default: "" + top_signame: flash_ctrl_flash_macro_status + index: -1 + } + { + name: lc_nvm_debug_en + struct: lc_tx + package: lc_ctrl_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: bist_enable + struct: mubi4 + package: prim_mubi_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: flash_bist_enable + conn_type: false + index: -1 + } + { + name: power_down_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_down_h + conn_type: false + index: -1 + } + { + name: power_ready_h + struct: logic + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_power_ready_h + conn_type: false + index: -1 + } + { + name: test_mode_a + struct: "" + type: io + act: none + width: 2 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: test_voltage_h + struct: "" + type: io + act: none + width: 1 + inst_name: flash_macro_wrapper + index: -1 + } + { + name: obs_ctrl + struct: ast_obs_ctrl + package: ast_pkg + type: uni + act: rcv + width: 1 + inst_name: flash_macro_wrapper + default: "" + external: true + top_signame: obs_ctrl + conn_type: false + index: -1 + } + { + name: fla_obs + struct: logic + type: uni + act: req + width: 8 + inst_name: flash_macro_wrapper + default: "" + package: "" + external: true + top_signame: flash_obs + conn_type: false + index: -1 + } + { + name: tl struct: tl package: tlul_pkg type: req_rsp act: rsp width: 1 - inst_name: flash_ctrl + inst_name: flash_macro_wrapper default: "" end_idx: -1 - top_signame: flash_ctrl_mem_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -11913,7 +12129,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -11921,7 +12137,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { @@ -12864,6 +13080,39 @@ suffix: "" default: prim_mubi_pkg::MUBI4_DEFAULT } + { + package: flash_phy_macro_pkg + struct: flash_phy_macro_req + signame: flash_ctrl_flash_macro_req + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: req + default: "" + } + { + package: flash_phy_macro_pkg + struct: flash_phy_macro_rsp + signame: flash_ctrl_flash_macro_rsp + width: 1 + type: req_rsp + end_idx: -1 + act: req + suffix: rsp + default: flash_phy_macro_pkg::FLASH_PHY_MACRO_RSP_DEFAULT + } + { + package: flash_phy_macro_pkg + struct: flash_macro_status + signame: flash_ctrl_flash_macro_status + width: 1 + type: uni + end_idx: -1 + act: rcv + suffix: "" + default: flash_phy_macro_pkg::FLASH_MACRO_STATUS_DEFAULT + } { package: "" struct: logic @@ -13098,7 +13347,7 @@ { package: tlul_pkg struct: tl_h2d - signame: flash_ctrl_prim_tl_req + signame: flash_macro_wrapper_tl_req width: 1 type: req_rsp end_idx: -1 @@ -13109,7 +13358,7 @@ { package: tlul_pkg struct: tl_d2h - signame: flash_ctrl_prim_tl_rsp + signame: flash_macro_wrapper_tl_rsp width: 1 type: req_rsp end_idx: -1 diff --git a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.secrets.testing.gen.hjson b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.secrets.testing.gen.hjson index 0e6871ab146..b6cbbdb2502 100644 --- a/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.secrets.testing.gen.hjson +++ b/hw/top_englishbreakfast/data/autogen/top_englishbreakfast.secrets.testing.gen.hjson @@ -26,10 +26,6 @@ { hart: 0x41000000 } - prim: - { - hart: 0x41008000 - } mem: { hart: 0x20000000 diff --git a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson index ef17b05be62..1c395a95708 100644 --- a/hw/top_englishbreakfast/data/top_englishbreakfast.hjson +++ b/hw/top_englishbreakfast/data/top_englishbreakfast.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -235,7 +236,7 @@ "aon_timer_aon", "ast", "flash_ctrl.core", - "flash_ctrl.prim", + "flash_macro_wrapper", "rv_plic", "aes", "sram_ctrl_main.regs" @@ -491,7 +492,6 @@ reset_connections: {rst_ni: "lc", rst_otp_ni: "lc_io_div4"}, base_addrs: { core: {hart: "0x41000000"}, - prim: {hart: "0x41008000"}, mem: {hart: "0x20000000"} } param_decl: { @@ -514,6 +514,26 @@ attr: "ipgen", outgoing_alert: "englishbreakfast", }, + { name: "flash_macro_wrapper", + type: "flash_macro_wrapper", + clock_srcs: {clk_i: "main"}, + clock_group: "infra", + reset_connections: {rst_ni: "lc"}, + base_addr: { + hart: "0x41008000", + }, + param_decl: { + // Change these to be from package + NumBanks: "2", + InfosPerBank: "10", + InfoTypes: "3", + InfoTypesWidth: "2", + PagesPerBank: "16", + WordsPerPage: "256", + DataWidth: "72", + TestModeWidth: "2", + }, + }, { name: "rv_plic", type: "rv_plic", template_type: "rv_plic", @@ -725,7 +745,11 @@ // The idle connection is automatically connected through topgen. // The user does not need to explicitly declare anything other than // an empty list. - 'clkmgr_aon.idle' : [], + 'clkmgr_aon.idle' : [], + + // FLASH_CTRL FLASH_MACRO_WRAPPER connections + 'flash_ctrl.flash_macro' : ['flash_macro_wrapper.flash'], + 'flash_ctrl.flash_macro_status' : ['flash_macro_wrapper.status'], // rv_plic connections 'rv_plic.msip' : ['rv_core_ibex.irq_software'], @@ -794,11 +818,11 @@ 'clkmgr_aon.all_clk_byp_ack' : 'all_clk_byp_ack', 'clkmgr_aon.io_clk_byp_req' : 'io_clk_byp_req', 'clkmgr_aon.io_clk_byp_ack' : 'io_clk_byp_ack', - 'flash_ctrl.flash_bist_enable' : 'flash_bist_enable', - 'flash_ctrl.flash_power_down_h' : 'flash_power_down_h', - 'flash_ctrl.flash_power_ready_h' : 'flash_power_ready_h', - 'flash_ctrl.obs_ctrl' : 'obs_ctrl', - 'flash_ctrl.fla_obs' : 'flash_obs', + 'flash_macro_wrapper.bist_enable' : 'flash_bist_enable', + 'flash_macro_wrapper.power_down_h' : 'flash_power_down_h', + 'flash_macro_wrapper.power_ready_h': 'flash_power_ready_h', + 'flash_macro_wrapper.obs_ctrl' : 'obs_ctrl', + 'flash_macro_wrapper.fla_obs' : 'flash_obs', # 'entropy_src.entropy_src_rng' : '', # 'entropy_src.rng_fips' : '', 'peri.tl_ast' : 'ast_tl', diff --git a/hw/top_englishbreakfast/data/xbar_main.hjson b/hw/top_englishbreakfast/data/xbar_main.hjson index 9dec20b953f..1b80f9669be 100644 --- a/hw/top_englishbreakfast/data/xbar_main.hjson +++ b/hw/top_englishbreakfast/data/xbar_main.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 { name: "main", @@ -49,7 +50,7 @@ req_fifo_pass: true, rsp_fifo_pass: false, }, - { name: "flash_ctrl.prim", + { name: "flash_macro_wrapper", type: "device", clock: "clk_main_i", reset: "rst_main_ni", @@ -99,7 +100,7 @@ rv_core_ibex.corei: ["rom_ctrl.rom", "sram_ctrl_main.ram", "flash_ctrl.mem"], rv_core_ibex.cored: [ "rom_ctrl.rom", "rom_ctrl.regs", - "sram_ctrl_main.ram", "flash_ctrl.mem", "peri", "flash_ctrl.core", "flash_ctrl.prim", + "sram_ctrl_main.ram", "flash_ctrl.mem", "peri", "flash_ctrl.core", "flash_macro_wrapper", "aes", "rv_plic", "sram_ctrl_main.ram", "sram_ctrl_main.regs", "rv_core_ibex.cfg" diff --git a/hw/top_englishbreakfast/dv/autogen/tb__xbar_connect.sv b/hw/top_englishbreakfast/dv/autogen/tb__xbar_connect.sv index 09f9b8bca38..6a4f26cbb20 100644 --- a/hw/top_englishbreakfast/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_englishbreakfast/dv/autogen/tb__xbar_connect.sv @@ -41,7 +41,7 @@ tl_if rv_core_ibex__cored_tl_if(clk_main, rst_n); tl_if rom_ctrl__rom_tl_if(clk_main, rst_n); tl_if rom_ctrl__regs_tl_if(clk_main, rst_n); tl_if flash_ctrl__core_tl_if(clk_main, rst_n); -tl_if flash_ctrl__prim_tl_if(clk_main, rst_n); +tl_if flash_macro_wrapper_tl_if(clk_main, rst_n); tl_if flash_ctrl__mem_tl_if(clk_main, rst_n); tl_if aes_tl_if(clk_main, rst_n); tl_if rv_plic_tl_if(clk_main, rst_n); @@ -92,7 +92,7 @@ initial begin `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__rom, rom_ctrl, rom_tl) `DRIVE_CHIP_TL_DEVICE_IF(rom_ctrl__regs, rom_ctrl, regs_tl) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__core, flash_ctrl, core_tl) - `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__prim, flash_ctrl, prim_tl) + `DRIVE_CHIP_TL_DEVICE_IF(flash_macro_wrapper, flash_macro_wrapper, tl) `DRIVE_CHIP_TL_DEVICE_IF(flash_ctrl__mem, flash_ctrl, mem_tl) `DRIVE_CHIP_TL_DEVICE_IF(aes, aes, tl) `DRIVE_CHIP_TL_DEVICE_IF(rv_plic, rv_plic, tl) diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv index 4067393df73..4f08e78eecb 100644 --- a/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_englishbreakfast/dv/autogen/xbar_env_pkg__params.sv @@ -16,7 +16,7 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__core", '{ '{32'h41000000, 32'h410001ff} }}, - '{"flash_ctrl__prim", '{ + '{"flash_macro_wrapper", '{ '{32'h41008000, 32'h4100807f} }}, '{"flash_ctrl__mem", '{ @@ -99,7 +99,7 @@ tl_host_t xbar_hosts[$] = '{ "pinmux_aon", "ast", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "aes", "rv_plic", "sram_ctrl_main__ram", diff --git a/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg b/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg index fdcaef860d8..b2bef2b6c68 100644 --- a/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg +++ b/hw/top_englishbreakfast/dv/autogen/xbar_tgl_excl.cfg @@ -33,10 +33,10 @@ -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[23:9] -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[29:25] -node tb.dut*.u_flash_ctrl core_tl_*i.a_address[31:31] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[14:7] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[23:16] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[29:25] --node tb.dut*.u_flash_ctrl prim_tl_*i.a_address[31:31] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[14:7] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[23:16] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[29:25] +-node tb.dut*.u_flash_macro_wrapper tl_*i.a_address[31:31] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[28:16] -node tb.dut*.u_flash_ctrl mem_tl_*i.a_address[31:30] -node tb.dut*.u_aes tl_*i.a_address[19:8] diff --git a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson index aede9f4ed0e..c9975161f16 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson +++ b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.gen.hjson @@ -53,7 +53,7 @@ flash_ctrl.mem peri flash_ctrl.core - flash_ctrl.prim + flash_macro_wrapper aes rv_plic sram_ctrl_main.ram @@ -175,13 +175,13 @@ pipeline: true } { - name: flash_ctrl.prim + name: flash_macro_wrapper type: device clock: clk_main_i reset: rst_main_ni req_fifo_pass: true rsp_fifo_pass: false - inst_type: flash_ctrl + inst_type: flash_macro_wrapper addr_range: [ { @@ -408,7 +408,7 @@ index: -1 } { - name: tl_flash_ctrl__prim + name: tl_flash_macro_wrapper struct: tl package: tlul_pkg type: req_rsp @@ -416,7 +416,7 @@ inst_name: main width: 1 default: "" - top_signame: flash_ctrl_prim_tl + top_signame: flash_macro_wrapper_tl index: -1 } { diff --git a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.hjson b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.hjson index cad263d455c..92cbb545123 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.hjson +++ b/hw/top_englishbreakfast/ip/xbar_main/data/autogen/xbar_main.hjson @@ -51,7 +51,7 @@ } { struct: "tl" type: "req_rsp" - name: "tl_flash_ctrl__prim" + name: "tl_flash_macro_wrapper" act: "req" package: "tlul_pkg" } diff --git a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/tb__xbar_connect.sv b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/tb__xbar_connect.sv index 459034d5868..fa21007cae3 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/tb__xbar_connect.sv +++ b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/tb__xbar_connect.sv @@ -25,7 +25,7 @@ initial force dut.rst_fixed_ni = rst_n; `CONNECT_TL_DEVICE_IF(rom_ctrl__regs, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(peri, dut, clk_fixed_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__core, dut, clk_main_i, rst_n) -`CONNECT_TL_DEVICE_IF(flash_ctrl__prim, dut, clk_main_i, rst_n) +`CONNECT_TL_DEVICE_IF(flash_macro_wrapper, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(flash_ctrl__mem, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(aes, dut, clk_main_i, rst_n) `CONNECT_TL_DEVICE_IF(rv_plic, dut, clk_main_i, rst_n) diff --git a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_cover.cfg b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_cover.cfg index b7e05ce8d6d..e68e4bb1f1f 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_cover.cfg +++ b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_cover.cfg @@ -31,10 +31,10 @@ -node tb.dut tl_flash_ctrl__core_o.a_address[23:9] -node tb.dut tl_flash_ctrl__core_o.a_address[29:25] -node tb.dut tl_flash_ctrl__core_o.a_address[31:31] --node tb.dut tl_flash_ctrl__prim_o.a_address[14:7] --node tb.dut tl_flash_ctrl__prim_o.a_address[23:16] --node tb.dut tl_flash_ctrl__prim_o.a_address[29:25] --node tb.dut tl_flash_ctrl__prim_o.a_address[31:31] +-node tb.dut tl_flash_macro_wrapper_o.a_address[14:7] +-node tb.dut tl_flash_macro_wrapper_o.a_address[23:16] +-node tb.dut tl_flash_macro_wrapper_o.a_address[29:25] +-node tb.dut tl_flash_macro_wrapper_o.a_address[31:31] -node tb.dut tl_flash_ctrl__mem_o.a_address[28:16] -node tb.dut tl_flash_ctrl__mem_o.a_address[31:30] -node tb.dut tl_aes_o.a_address[19:8] diff --git a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv index c726067b1e6..30435318e6d 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv +++ b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv @@ -19,7 +19,7 @@ tl_device_t xbar_devices[$] = '{ '{"flash_ctrl__core", '{ '{32'h41000000, 32'h410001ff} }}, - '{"flash_ctrl__prim", '{ + '{"flash_macro_wrapper", '{ '{32'h41008000, 32'h4100807f} }}, '{"flash_ctrl__mem", '{ @@ -55,7 +55,7 @@ tl_host_t xbar_hosts[$] = '{ "flash_ctrl__mem", "peri", "flash_ctrl__core", - "flash_ctrl__prim", + "flash_macro_wrapper", "aes", "rv_plic", "sram_ctrl_main__regs", diff --git a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_main_bind.sv b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_main_bind.sv index d3264fb17c8..789ce453f4c 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_main_bind.sv +++ b/hw/top_englishbreakfast/ip/xbar_main/dv/autogen/xbar_main_bind.sv @@ -44,11 +44,11 @@ module xbar_main_bind; .h2d (tl_flash_ctrl__core_o), .d2h (tl_flash_ctrl__core_i) ); - bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__prim ( + bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_macro_wrapper ( .clk_i (clk_main_i), .rst_ni (rst_main_ni), - .h2d (tl_flash_ctrl__prim_o), - .d2h (tl_flash_ctrl__prim_i) + .h2d (tl_flash_macro_wrapper_o), + .d2h (tl_flash_macro_wrapper_i) ); bind xbar_main tlul_assert #(.EndpointType("Host")) tlul_assert_device_flash_ctrl__mem ( .clk_i (clk_main_i), diff --git a/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/tl_main_pkg.sv index 893a33d267a..c3363cfd051 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/tl_main_pkg.sv +++ b/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/tl_main_pkg.sv @@ -12,7 +12,7 @@ package tl_main_pkg; 32'h 40000000 }; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__CORE = 32'h 41000000; - localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__PRIM = 32'h 41008000; + localparam logic [31:0] ADDR_SPACE_FLASH_MACRO_WRAPPER = 32'h 41008000; localparam logic [31:0] ADDR_SPACE_FLASH_CTRL__MEM = 32'h 20000000; localparam logic [31:0] ADDR_SPACE_AES = 32'h 41100000; localparam logic [31:0] ADDR_SPACE_RV_PLIC = 32'h 48000000; @@ -26,7 +26,7 @@ package tl_main_pkg; 32'h 007fffff }; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__CORE = 32'h 000001ff; - localparam logic [31:0] ADDR_MASK_FLASH_CTRL__PRIM = 32'h 0000007f; + localparam logic [31:0] ADDR_MASK_FLASH_MACRO_WRAPPER = 32'h 0000007f; localparam logic [31:0] ADDR_MASK_FLASH_CTRL__MEM = 32'h 0000ffff; localparam logic [31:0] ADDR_MASK_AES = 32'h 000000ff; localparam logic [31:0] ADDR_MASK_RV_PLIC = 32'h 07ffffff; @@ -42,7 +42,7 @@ package tl_main_pkg; TlRomCtrlRegs = 1, TlPeri = 2, TlFlashCtrlCore = 3, - TlFlashCtrlPrim = 4, + TlFlashMacroWrapper = 4, TlFlashCtrlMem = 5, TlAes = 6, TlRvPlic = 7, diff --git a/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/xbar_main.sv index a4d10b50039..b8547fe4735 100644 --- a/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/xbar_main.sv +++ b/hw/top_englishbreakfast/ip/xbar_main/rtl/autogen/xbar_main.sv @@ -26,7 +26,7 @@ // -> asf_18 // -> peri // -> flash_ctrl.core -// -> flash_ctrl.prim +// -> flash_macro_wrapper // -> aes // -> rv_plic // -> sram_ctrl_main.regs @@ -53,8 +53,8 @@ module xbar_main ( input tlul_pkg::tl_d2h_t tl_peri_i, output tlul_pkg::tl_h2d_t tl_flash_ctrl__core_o, input tlul_pkg::tl_d2h_t tl_flash_ctrl__core_i, - output tlul_pkg::tl_h2d_t tl_flash_ctrl__prim_o, - input tlul_pkg::tl_d2h_t tl_flash_ctrl__prim_i, + output tlul_pkg::tl_h2d_t tl_flash_macro_wrapper_o, + input tlul_pkg::tl_d2h_t tl_flash_macro_wrapper_i, output tlul_pkg::tl_h2d_t tl_flash_ctrl__mem_o, input tlul_pkg::tl_d2h_t tl_flash_ctrl__mem_i, output tlul_pkg::tl_h2d_t tl_aes_o, @@ -154,8 +154,8 @@ module xbar_main ( assign tl_flash_ctrl__core_o = tl_s1n_17_ds_h2d[5]; assign tl_s1n_17_ds_d2h[5] = tl_flash_ctrl__core_i; - assign tl_flash_ctrl__prim_o = tl_s1n_17_ds_h2d[6]; - assign tl_s1n_17_ds_d2h[6] = tl_flash_ctrl__prim_i; + assign tl_flash_macro_wrapper_o = tl_s1n_17_ds_h2d[6]; + assign tl_s1n_17_ds_d2h[6] = tl_flash_macro_wrapper_i; assign tl_aes_o = tl_s1n_17_ds_h2d[7]; assign tl_s1n_17_ds_d2h[7] = tl_aes_i; @@ -232,7 +232,7 @@ end dev_sel_s1n_17 = 4'd5; end else if ((tl_s1n_17_us_h2d.a_address & - ~(ADDR_MASK_FLASH_CTRL__PRIM)) == ADDR_SPACE_FLASH_CTRL__PRIM) begin + ~(ADDR_MASK_FLASH_MACRO_WRAPPER)) == ADDR_SPACE_FLASH_MACRO_WRAPPER) begin dev_sel_s1n_17 = 4'd6; end else if ((tl_s1n_17_us_h2d.a_address & diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/README.md b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/README.md index 79259c44551..240f0719b60 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/README.md +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/README.md @@ -193,3 +193,14 @@ During production and RMA states, the isolated page is also readable. * Both `lc_iso_part_sw_wr_en` and `lc_iso_part_sw_rd_en` are set. See [life cycle](../../../ip/lc_ctrl/README.md#iso_part_sw_rd_en-and-iso_part_sw_wr_en) for more details + +## IP Blocks Organization + +The flash macro wrapper is provided by a separate IP block that is directly instantiated under the top level. +As such it has its own IP documentation (https://opentitan.org/book/hw/ip/flash_macro_wrapper/index.html). +This split allows the controller to be independent of low level testing and vendor specific interfaces to the Flash Macro. +It makes it simpler to make changes for different vendor flash macros. + +In terms of the top generation (https://opentitan.org/book/util/topgen/index.html#overview), the controller is an ipgen peripheral, while the macro is generic. +The controller can be generated with different parameters that directly affect the macro. +The macro wrapper is parameterized at the top-level so that it matches the controller's configuration. diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/flash_ctrl.hjson b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/flash_ctrl.hjson index 70cb8e35efb..5e6dd9a5490 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/flash_ctrl.hjson +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/data/flash_ctrl.hjson @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -10,7 +11,7 @@ one_line_desc: "Interfaces and manages integrated non-volatile flash memory; supports scrambling, integrity, and secure wipe", one_paragraph_desc: ''' Flash Controller interfaces the integrated, non-volatile flash memory with software and other hardware components in the system, such as Life Cycle Controller, Key Manager, and OTP Controller. - It consists of the open source flash controller that interfaces with a third party flash module. + It consists of the open source flash controller that interfaces with a third party flash macro. The protocol controller handles read, program, and erase requests, as well as life cycle RMA entry. It supports differentiation between informational and data flash partitions, flash memory protection at page boundaries, and the handling of key manager secrets inaccessible to software. The actual physical controller is highly parameterized (number of banks, number of pages for each bank, number of words and word size for each page, and number of read buffers) and supports XEX scrambling configurable by software, as well as two types of ECC support configurable on a page boundary. @@ -43,17 +44,9 @@ ] bus_interfaces: [ { protocol: "tlul", direction: "device", name: "core" } - { protocol: "tlul", direction: "device", name: "prim" , hier_path: "u_eflash.u_flash.u_reg_top"} { protocol: "tlul", direction: "device", name: "mem" } ], - available_input_list: [ - { name: "tck", desc: "jtag clock" }, - { name: "tms", desc: "jtag tms" }, - { name: "tdi", desc: "jtag input" }, - ], - available_output_list: [ - { name: "tdo", desc: "jtag output" }, - ], + interrupt_list: [ // The first two status interrupts assert by default, since the FIFO is empty. // This is captured in the Hjson via the `default` key so that automatically generated tests can incorporate this information. @@ -100,46 +93,6 @@ package: "otp_ctrl_pkg" }, - { struct: "lc_tx", - package: "lc_ctrl_pkg", - type: "uni" - act: "rcv" - name: "lc_nvm_debug_en" - }, - - { struct: "mubi4" - package: "prim_mubi_pkg" - type: "uni" - act: "rcv" - name: "flash_bist_enable" - }, - - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_down_h" - }, - { struct: "logic" - package: "" - type: "uni" - act: "rcv" - name: "flash_power_ready_h" - }, - { struct: "", - package: "", - width: "2", - type: "io" - act: "none" - name: "flash_test_mode_a" - }, - { struct: "", - package: "", - type: "io" - act: "none" - name: "flash_test_voltage_h" - }, - { struct: "lc_tx" type: "uni" name: "lc_creator_seed_sw_rw_en" @@ -215,24 +168,25 @@ name: "keymgr", act: "req", package: "flash_ctrl_pkg" - } - - { struct: "ast_obs_ctrl", - type: "uni", - name: "obs_ctrl", - act: "rcv", - package: "ast_pkg" - } + }, - { struct: "logic", - type: "uni", - name: "fla_obs", - act: "req", - width: "8", - package: "" - } + { struct: "flash_phy_macro", + type: "req_rsp", + name: "flash_macro", + act: "req", + package: "flash_phy_macro_pkg", + desc: "Data interface to the flash macro wrapper" + }, + { struct: "flash_macro_status", + type: "uni", + name: "flash_macro_status", + act: "rcv", + package: "flash_phy_macro_pkg", + desc: "Status interface from the flash macro wrapper" + }, ], + countermeasures: [ { name: "REG.BUS.INTEGRITY", desc: ''' @@ -386,9 +340,6 @@ } ] - scan: "true", // Enable `scanmode_i` port - scan_en: "true", // Enable `scan_en_i` port - scan_reset: "true", // Enable `scan_rst_ni` port param_list: [ // The reg parameters can be modified directly through top_*.hjson. // The template will automatically propagate the appropriate values. @@ -2357,867 +2308,6 @@ }, ], - prim: [ - { - name: "CSR0_REGWEN", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw0c", - hwaccess: "none", - resval: "1", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR1", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "12:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR2", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "3", - name: "field3", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4", - name: "field4", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5", - name: "field5", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "6", - name: "field6", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7", - name: "field7", - swaccess: "rw", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - }, - { - name: "CSR3", - desc: "", - fields: [ - { - bits: "3:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "7:4", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "10:8", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:11", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "19:17", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23:21", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "25:24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "27:26", - name: "field9", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR4", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "11:9", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR5", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "4:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:5", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:19", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR6", - desc: "", - fields: [ - { - bits: "2:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "5:3", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "13:6", - name: "field2", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:14", - name: "field3", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "18:17", - name: "field4", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20:19", - name: "field5", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "22:21", - name: "field6", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "23", - name: "field7", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "24", - name: "field8", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR7", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "16:8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR8", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR9", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR10", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR11", - desc: "", - fields: [ - { - bits: "31:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR12", - desc: "", - fields: [ - { - bits: "9:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR13", - desc: "", - fields: [ - { - bits: "19:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "20", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR14", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR15", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR16", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR17", - desc: "", - fields: [ - { - bits: "7:0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "8", - name: "field1", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR18", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR19", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw", - hwaccess: "hro", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False", - regwen: "CSR0_REGWEN" - }, - { - name: "CSR20", - desc: "", - fields: [ - { - bits: "0", - name: "field0", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "1", - name: "field1", - swaccess: "rw1c", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - }, - { - bits: "2", - name: "field2", - swaccess: "ro", - hwaccess: "hrw", - resval: "0", - tags: [], - desc: "", - enum: [] - } - ], - hwext: "False", - hwqe: "False", - hwre: "False", - tags: [], - shadowed: "False" - } - ], } memory: { mem: {} diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/interfaces.md b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/interfaces.md index f62996934e7..454e9002135 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/interfaces.md +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/interfaces.md @@ -4,45 +4,30 @@ Referring to the [Comportable guideline for peripheral device functionality](https://opentitan.org/book/doc/contributing/hw/comportability), the module **`flash_ctrl`** has the following hardware interfaces defined - Primary Clock: **`clk_i`** - Other Clocks: **`clk_otp_i`** -- Bus Device Interfaces (TL-UL): **`core_tl`**, **`prim_tl`**, **`mem_tl`** +- Bus Device Interfaces (TL-UL): **`core_tl`**, **`mem_tl`** - Bus Host Interfaces (TL-UL): *none* - -## Peripheral Pins for Chip IO - -| Pin name | Direction | Description | -|:-----------|:------------|:--------------| -| tck | input | jtag clock | -| tms | input | jtag tms | -| tdi | input | jtag input | -| tdo | output | jtag output | +- Peripheral Pins for Chip IO: *none* ## [Inter-Module Signals](https://opentitan.org/book/doc/contributing/hw/comportability/index.html#inter-signal-handling) -| Port Name | Package::Struct | Type | Act | Width | Description | -|:-------------------------|:-------------------------------|:--------|:------|--------:|:--------------| -| otp | otp_ctrl_pkg::flash_otp_key | req_rsp | req | 1 | | -| lc_nvm_debug_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| flash_bist_enable | prim_mubi_pkg::mubi4 | uni | rcv | 1 | | -| flash_power_down_h | logic | uni | rcv | 1 | | -| flash_power_ready_h | logic | uni | rcv | 1 | | -| flash_test_mode_a | | io | none | 2 | | -| flash_test_voltage_h | | io | none | 1 | | -| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | -| rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | -| rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | rcv | 1 | | -| pwrmgr | pwrmgr_pkg::pwr_flash | uni | req | 1 | | -| keymgr | flash_ctrl_pkg::keymgr_flash | uni | req | 1 | | -| obs_ctrl | ast_pkg::ast_obs_ctrl | uni | rcv | 1 | | -| fla_obs | logic | uni | req | 8 | | -| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| prim_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | -| mem_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| Port Name | Package::Struct | Type | Act | Width | Description | +|:-------------------------|:----------------------------------------|:--------|:------|--------:|:----------------------------------------------| +| otp | otp_ctrl_pkg::flash_otp_key | req_rsp | req | 1 | | +| lc_creator_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_owner_seed_sw_rw_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_iso_part_sw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_iso_part_sw_wr_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_seed_hw_rd_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| lc_escalate_en | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| rma_req | lc_ctrl_pkg::lc_tx | uni | rcv | 1 | | +| rma_ack | lc_ctrl_pkg::lc_tx | uni | req | 1 | | +| rma_seed | lc_ctrl_pkg::lc_flash_rma_seed | uni | rcv | 1 | | +| pwrmgr | pwrmgr_pkg::pwr_flash | uni | req | 1 | | +| keymgr | flash_ctrl_pkg::keymgr_flash | uni | req | 1 | | +| flash_macro | flash_phy_macro_pkg::flash_phy_macro | req_rsp | req | 1 | Data interface to the flash macro wrapper | +| flash_macro_status | flash_phy_macro_pkg::flash_macro_status | uni | rcv | 1 | Status interface from the flash macro wrapper | +| core_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | +| mem_tl | tlul_pkg::tl | req_rsp | rsp | 1 | | ## Interrupts diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/registers.md b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/registers.md index 3734c6d2a38..61024aca8a3 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/registers.md +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/doc/registers.md @@ -4,7 +4,7 @@ The flash protocol controller maintains two separate access windows for the FIFO It is implemented this way because the access window supports transaction back-pressure should the FIFO become full (in case of write) or empty (in case of read). -## Summary of the **`core`** interface's registers +## Summary | Name | Offset | Length | Description | |:-------------------------------------------------------------|:---------|---------:|:--------------------------------------------------------------------| @@ -1437,686 +1437,5 @@ The FIFO is 16 entries of 4B flash words - Access: `ro` - Byte writes are *not* supported. -## Summary of the **`prim`** interface's registers - -| Name | Offset | Length | Description | -|:-----------------------------------------|:---------|---------:|:--------------| -| flash_ctrl.[`CSR0_REGWEN`](#csr0_regwen) | 0x0 | 4 | | -| flash_ctrl.[`CSR1`](#csr1) | 0x4 | 4 | | -| flash_ctrl.[`CSR2`](#csr2) | 0x8 | 4 | | -| flash_ctrl.[`CSR3`](#csr3) | 0xc | 4 | | -| flash_ctrl.[`CSR4`](#csr4) | 0x10 | 4 | | -| flash_ctrl.[`CSR5`](#csr5) | 0x14 | 4 | | -| flash_ctrl.[`CSR6`](#csr6) | 0x18 | 4 | | -| flash_ctrl.[`CSR7`](#csr7) | 0x1c | 4 | | -| flash_ctrl.[`CSR8`](#csr8) | 0x20 | 4 | | -| flash_ctrl.[`CSR9`](#csr9) | 0x24 | 4 | | -| flash_ctrl.[`CSR10`](#csr10) | 0x28 | 4 | | -| flash_ctrl.[`CSR11`](#csr11) | 0x2c | 4 | | -| flash_ctrl.[`CSR12`](#csr12) | 0x30 | 4 | | -| flash_ctrl.[`CSR13`](#csr13) | 0x34 | 4 | | -| flash_ctrl.[`CSR14`](#csr14) | 0x38 | 4 | | -| flash_ctrl.[`CSR15`](#csr15) | 0x3c | 4 | | -| flash_ctrl.[`CSR16`](#csr16) | 0x40 | 4 | | -| flash_ctrl.[`CSR17`](#csr17) | 0x44 | 4 | | -| flash_ctrl.[`CSR18`](#csr18) | 0x48 | 4 | | -| flash_ctrl.[`CSR19`](#csr19) | 0x4c | 4 | | -| flash_ctrl.[`CSR20`](#csr20) | 0x50 | 4 | | - -## CSR0_REGWEN - -- Offset: `0x0` -- Reset default: `0x1` -- Reset mask: `0x1` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw0c"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------------| -| 31:1 | | | Reserved | -| 0 | rw0c | 0x1 | [field0](#csr0_regwen--field0) | - -### CSR0_REGWEN . field0 - -All values are reserved. - -## CSR1 - -- Offset: `0x4` -- Reset default: `0x0` -- Reset mask: `0x1fff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 5, "attr": ["rw"], "rotate": 0}, {"bits": 19}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:13 | | | Reserved | -| 12:8 | rw | 0x0 | [field1](#csr1--field1) | -| 7:0 | rw | 0x0 | [field0](#csr1--field0) | - -### CSR1 . field1 - -All values are reserved. - -### CSR1 . field0 - -All values are reserved. - -## CSR2 - -- Offset: `0x8` -- Reset default: `0x0` -- Reset mask: `0xff` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field3", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field5", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 24}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:8 | | | Reserved | -| 7 | rw | 0x0 | [field7](#csr2--field7) | -| 6 | rw1c | 0x0 | [field6](#csr2--field6) | -| 5 | rw1c | 0x0 | [field5](#csr2--field5) | -| 4 | rw1c | 0x0 | [field4](#csr2--field4) | -| 3 | rw | 0x0 | [field3](#csr2--field3) | -| 2 | rw1c | 0x0 | [field2](#csr2--field2) | -| 1 | rw1c | 0x0 | [field1](#csr2--field1) | -| 0 | rw1c | 0x0 | [field0](#csr2--field0) | - -### CSR2 . field7 - -All values are reserved. - -### CSR2 . field6 - -All values are reserved. - -### CSR2 . field5 - -All values are reserved. - -### CSR2 . field4 - -All values are reserved. - -### CSR2 . field3 - -All values are reserved. - -### CSR2 . field2 - -All values are reserved. - -### CSR2 . field1 - -All values are reserved. - -### CSR2 . field0 - -All values are reserved. - -## CSR3 - -- Offset: `0xc` -- Reset default: `0x0` -- Reset mask: `0xfffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 4, "attr": ["rw"], "rotate": 0}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field9", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 4}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:28 | | | Reserved | -| 27:26 | rw | 0x0 | [field9](#csr3--field9) | -| 25:24 | rw | 0x0 | [field8](#csr3--field8) | -| 23:21 | rw | 0x0 | [field7](#csr3--field7) | -| 20 | rw | 0x0 | [field6](#csr3--field6) | -| 19:17 | rw | 0x0 | [field5](#csr3--field5) | -| 16:14 | rw | 0x0 | [field4](#csr3--field4) | -| 13:11 | rw | 0x0 | [field3](#csr3--field3) | -| 10:8 | rw | 0x0 | [field2](#csr3--field2) | -| 7:4 | rw | 0x0 | [field1](#csr3--field1) | -| 3:0 | rw | 0x0 | [field0](#csr3--field0) | - -### CSR3 . field9 - -All values are reserved. - -### CSR3 . field8 - -All values are reserved. - -### CSR3 . field7 - -All values are reserved. - -### CSR3 . field6 - -All values are reserved. - -### CSR3 . field5 - -All values are reserved. - -### CSR3 . field4 - -All values are reserved. - -### CSR3 . field3 - -All values are reserved. - -### CSR3 . field2 - -All values are reserved. - -### CSR3 . field1 - -All values are reserved. - -### CSR3 . field0 - -All values are reserved. - -## CSR4 - -- Offset: `0x10` -- Reset default: `0x0` -- Reset mask: `0xfff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"bits": 20}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:12 | | | Reserved | -| 11:9 | rw | 0x0 | [field3](#csr4--field3) | -| 8:6 | rw | 0x0 | [field2](#csr4--field2) | -| 5:3 | rw | 0x0 | [field1](#csr4--field1) | -| 2:0 | rw | 0x0 | [field0](#csr4--field0) | - -### CSR4 . field3 - -All values are reserved. - -### CSR4 . field2 - -All values are reserved. - -### CSR4 . field1 - -All values are reserved. - -### CSR4 . field0 - -All values are reserved. - -## CSR5 - -- Offset: `0x14` -- Reset default: `0x0` -- Reset mask: `0x7fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 9, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 5, "attr": ["rw"], "rotate": 0}, {"name": "field4", "bits": 4, "attr": ["rw"], "rotate": 0}, {"bits": 9}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:23 | | | Reserved | -| 22:19 | rw | 0x0 | [field4](#csr5--field4) | -| 18:14 | rw | 0x0 | [field3](#csr5--field3) | -| 13:5 | rw | 0x0 | [field2](#csr5--field2) | -| 4:3 | rw | 0x0 | [field1](#csr5--field1) | -| 2:0 | rw | 0x0 | [field0](#csr5--field0) | - -### CSR5 . field4 - -All values are reserved. - -### CSR5 . field3 - -All values are reserved. - -### CSR5 . field2 - -All values are reserved. - -### CSR5 . field1 - -All values are reserved. - -### CSR5 . field0 - -All values are reserved. - -## CSR6 - -- Offset: `0x18` -- Reset default: `0x0` -- Reset mask: `0x1ffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field1", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field2", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field3", "bits": 3, "attr": ["rw"], "rotate": -90}, {"name": "field4", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field5", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field6", "bits": 2, "attr": ["rw"], "rotate": -90}, {"name": "field7", "bits": 1, "attr": ["rw"], "rotate": -90}, {"name": "field8", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 7}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:25 | | | Reserved | -| 24 | rw | 0x0 | [field8](#csr6--field8) | -| 23 | rw | 0x0 | [field7](#csr6--field7) | -| 22:21 | rw | 0x0 | [field6](#csr6--field6) | -| 20:19 | rw | 0x0 | [field5](#csr6--field5) | -| 18:17 | rw | 0x0 | [field4](#csr6--field4) | -| 16:14 | rw | 0x0 | [field3](#csr6--field3) | -| 13:6 | rw | 0x0 | [field2](#csr6--field2) | -| 5:3 | rw | 0x0 | [field1](#csr6--field1) | -| 2:0 | rw | 0x0 | [field0](#csr6--field0) | - -### CSR6 . field8 - -All values are reserved. - -### CSR6 . field7 - -All values are reserved. - -### CSR6 . field6 - -All values are reserved. - -### CSR6 . field5 - -All values are reserved. - -### CSR6 . field4 - -All values are reserved. - -### CSR6 . field3 - -All values are reserved. - -### CSR6 . field2 - -All values are reserved. - -### CSR6 . field1 - -All values are reserved. - -### CSR6 . field0 - -All values are reserved. - -## CSR7 - -- Offset: `0x1c` -- Reset default: `0x0` -- Reset mask: `0x1ffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 9, "attr": ["rw"], "rotate": 0}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:17 | | | Reserved | -| 16:8 | rw | 0x0 | [field1](#csr7--field1) | -| 7:0 | rw | 0x0 | [field0](#csr7--field0) | - -### CSR7 . field1 - -All values are reserved. - -### CSR7 . field0 - -All values are reserved. - -## CSR8 - -- Offset: `0x20` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr8--field0) | - -### CSR8 . field0 - -All values are reserved. - -## CSR9 - -- Offset: `0x24` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:------------------------| -| 31:0 | rw | 0x0 | [field0](#csr9--field0) | - -### CSR9 . field0 - -All values are reserved. - -## CSR10 - -- Offset: `0x28` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr10--field0) | - -### CSR10 . field0 - -All values are reserved. - -## CSR11 - -- Offset: `0x2c` -- Reset default: `0x0` -- Reset mask: `0xffffffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:0 | rw | 0x0 | [field0](#csr11--field0) | - -### CSR11 . field0 - -All values are reserved. - -## CSR12 - -- Offset: `0x30` -- Reset default: `0x0` -- Reset mask: `0x3ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 10, "attr": ["rw"], "rotate": 0}, {"bits": 22}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:10 | | | Reserved | -| 9:0 | rw | 0x0 | [field0](#csr12--field0) | - -### CSR12 . field0 - -All values are reserved. - -## CSR13 - -- Offset: `0x34` -- Reset default: `0x0` -- Reset mask: `0x1fffff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 20, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 11}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:21 | | | Reserved | -| 20 | rw | 0x0 | [field1](#csr13--field1) | -| 19:0 | rw | 0x0 | [field0](#csr13--field0) | - -### CSR13 . field1 - -All values are reserved. - -### CSR13 . field0 - -All values are reserved. - -## CSR14 - -- Offset: `0x38` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr14--field1) | -| 7:0 | rw | 0x0 | [field0](#csr14--field0) | - -### CSR14 . field1 - -All values are reserved. - -### CSR14 . field0 - -All values are reserved. - -## CSR15 - -- Offset: `0x3c` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr15--field1) | -| 7:0 | rw | 0x0 | [field0](#csr15--field0) | - -### CSR15 . field1 - -All values are reserved. - -### CSR15 . field0 - -All values are reserved. - -## CSR16 - -- Offset: `0x40` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr16--field1) | -| 7:0 | rw | 0x0 | [field0](#csr16--field0) | - -### CSR16 . field1 - -All values are reserved. - -### CSR16 . field0 - -All values are reserved. - -## CSR17 - -- Offset: `0x44` -- Reset default: `0x0` -- Reset mask: `0x1ff` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 8, "attr": ["rw"], "rotate": 0}, {"name": "field1", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 23}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:9 | | | Reserved | -| 8 | rw | 0x0 | [field1](#csr17--field1) | -| 7:0 | rw | 0x0 | [field0](#csr17--field0) | - -### CSR17 . field1 - -All values are reserved. - -### CSR17 . field0 - -All values are reserved. - -## CSR18 - -- Offset: `0x48` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr18--field0) | - -### CSR18 . field0 - -All values are reserved. - -## CSR19 - -- Offset: `0x4c` -- Reset default: `0x0` -- Reset mask: `0x1` -- Register enable: [`CSR0_REGWEN`](#csr0_regwen) - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:1 | | | Reserved | -| 0 | rw | 0x0 | [field0](#csr19--field0) | - -### CSR19 . field0 - -All values are reserved. - -## CSR20 - -- Offset: `0x50` -- Reset default: `0x0` -- Reset mask: `0x7` - -### Fields - -```wavejson -{"reg": [{"name": "field0", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field1", "bits": 1, "attr": ["rw1c"], "rotate": -90}, {"name": "field2", "bits": 1, "attr": ["ro"], "rotate": -90}, {"bits": 29}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} -``` - -| Bits | Type | Reset | Name | -|:------:|:------:|:-------:|:-------------------------| -| 31:3 | | | Reserved | -| 2 | ro | 0x0 | [field2](#csr20--field2) | -| 1 | rw1c | 0x0 | [field1](#csr20--field1) | -| 0 | rw1c | 0x0 | [field0](#csr20--field0) | - -### CSR20 . field2 - -All values are reserved. - -### CSR20 . field1 - -All values are reserved. - -### CSR20 . field0 - -All values are reserved. - diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core index 73e3e30377c..bd20a008037 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:englishbreakfast_dv:flash_ctrl_cov @@ -9,6 +10,7 @@ filesets: files_dv: depend: - lowrisc:dv:dv_utils + - lowrisc:ip:flash_macro_wrapper - lowrisc:englishbreakfast_ip:flash_ctrl files: - flash_ctrl_cov_bind.sv diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv index 4c20c8dd914..2de0af16b01 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/cov/flash_ctrl_cov_bind.sv @@ -1,25 +1,33 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // -// Binds FLASH_CTRL functional coverage interface to the top level FLASH_CTRL module. -`define FLASH_COV_LC_TX_BIND(__name) \ +// Binds LC_TX functional coverage interface to the top level FLASH_CTRL module. +`define FLASH_CTRL_COV_LC_TX_BIND(__name) \ bind flash_ctrl cip_lc_tx_cov_if u_``__name``_cov_if( \ .rst_ni (rst_ni), \ .val (``__name``_i) \ ); +// Binds LC_TX functional coverage interface to the top level FLASH_MACRO_WRAPPER module. +`define FLASH_MACRO_COV_LC_TX_BIND(__name) \ + bind flash_macro_wrapper cip_lc_tx_cov_if u_``__name``_cov_if( \ + .rst_ni (rst_ni), \ + .val (``__name``_i) \ + ); + module flash_ctrl_cov_bind; - `FLASH_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) - `FLASH_COV_LC_TX_BIND(lc_seed_hw_rd_en) - `FLASH_COV_LC_TX_BIND(lc_escalate_en) - `FLASH_COV_LC_TX_BIND(lc_nvm_debug_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_creator_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_owner_seed_sw_rw_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_iso_part_sw_wr_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_seed_hw_rd_en) + `FLASH_CTRL_COV_LC_TX_BIND(lc_escalate_en) + `FLASH_MACRO_COV_LC_TX_BIND(lc_nvm_debug_en) - bind prim_generic_flash_bank flash_ctrl_phy_cov_if u_phy_cov_if + bind flash_macro_bank flash_ctrl_phy_cov_if u_phy_cov_if ( .clk_i(clk_i), .rst_ni(rst_ni), diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core index fb2cb0c012c..c4a0056d937 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:englishbreakfast_dv:flash_ctrl_env:0.1 @@ -16,6 +17,7 @@ filesets: - lowrisc:dv:mem_bkdr_util - lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg - lowrisc:englishbreakfast_constants:top_pkg + - lowrisc:dv:flash_macro_wrapper_env files: - flash_ctrl_eflash_ral_pkg.sv - flash_ctrl_env_pkg.sv diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv index 23f71cb546e..300019d23c6 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_cfg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 typedef class flash_ctrl_scoreboard; @@ -28,7 +29,6 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( // interface virtual flash_ctrl_if flash_ctrl_vif; virtual clk_rst_if clk_rst_vif_flash_ctrl_eflash_reg_block; - virtual clk_rst_if clk_rst_vif_flash_ctrl_prim_reg_block; virtual flash_ctrl_mem_if flash_ctrl_mem_vif[NumBanks]; // knobs @@ -283,7 +283,7 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( endfunction // get_region_from_info virtual function void initialize(addr_t csr_base_addr = '1); - string prim_ral_name = "flash_ctrl_prim_reg_block"; + string prim_ral_name = "flash_macro_wrapper_reg_block"; string fast_rcvr_name = ""; list_of_alerts = flash_ctrl_env_pkg::LIST_OF_ALERTS; @@ -594,13 +594,13 @@ class flash_ctrl_env_cfg extends cip_base_env_cfg #( data_4s_t loc_data = (scheme == FlashMemInitCustom) ? data[i] : (scheme == FlashMemInitRandomize) ? $urandom() : wr_data; - _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); `uvm_info(`gfn, $sformatf( "flash_mem_bkdr_write: partition = %s, {%s} = 0x%0h", flash_op.partition.name(), addr_attrs.sprint(), loc_data - ), UVM_HIGH) + ), UVM_MEDIUM) + _flash_full_write(flash_op.partition, addr_attrs.bank, addr_attrs.bank_addr, loc_data); // update the scoreboard on backdoor-programs as well mem_data[0] = loc_data; diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv index ae9842cc4e0..4cebe708137 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_env_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -15,7 +16,7 @@ package flash_ctrl_env_pkg; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_core_ral_pkg::*; import flash_ctrl_eflash_ral_pkg::*; - import flash_ctrl_prim_ral_pkg::*; + import flash_macro_wrapper_ral_pkg::*; import flash_ctrl_bkdr_util_pkg::*; import mem_bkdr_util_pkg::*; import prim_mubi_pkg::*; @@ -441,7 +442,9 @@ package flash_ctrl_env_pkg; end endfunction // flash_otf_print_data64 - function automatic flash_dv_part_e get_part_name(flash_phy_pkg::flash_phy_prim_flash_req_t req); + function automatic flash_dv_part_e get_part_name( + input flash_phy_macro_pkg::flash_phy_macro_bank_req_t req + ); flash_dv_part_e part; if (req.part == 0) return FlashPartData; diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv index 33bdf2f7a37..ea8904d3366 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/env/flash_ctrl_mem_if.sv @@ -1,16 +1,17 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -import flash_ctrl_top_specific_pkg::*; + interface flash_ctrl_mem_if ( input logic clk_i, input logic rst_ni, input logic data_mem_req, input logic mem_wr, - input logic [BankAddrW-1:0] mem_addr, - input logic [flash_phy_pkg::FullDataWidth-1:0] mem_wdata, - input flash_part_e mem_part, - input logic [InfoTypesWidth-1:0] mem_info_sel, + input logic [flash_phy_macro_pkg::BankAddrW-1:0] mem_addr, + input logic [flash_phy_macro_pkg::DataWidth-1:0] mem_wdata, + input flash_ctrl_pkg::flash_part_e mem_part, + input logic [flash_phy_macro_pkg::InfoTypesWidth-1:0] mem_info_sel, input logic info0_mem_req, input logic info1_mem_req, input logic info2_mem_req diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/tb/tb.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/tb/tb.sv index c6a53be8537..e415644116e 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/tb/tb.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/dv/tb/tb.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,10 +8,14 @@ module tb; import uvm_pkg::*; import top_pkg::*; import dv_utils_pkg::*; + import flash_ctrl_pkg::*; import flash_ctrl_top_specific_pkg::*; import flash_ctrl_env_pkg::*; import flash_ctrl_test_pkg::*; import flash_ctrl_bkdr_util_pkg::flash_ctrl_bkdr_util; + import flash_phy_macro_pkg::flash_phy_macro_req_t; + import flash_phy_macro_pkg::flash_phy_macro_rsp_t; + import flash_phy_macro_pkg::flash_macro_status_t; // macro includes `include "uvm_macros.svh" @@ -39,6 +44,9 @@ module tb; wire intr_op_done; wire intr_err; wire [NUM_MAX_INTERRUPTS-1:0] interrupts; + flash_phy_macro_req_t flash_macro_req; + flash_phy_macro_rsp_t flash_macro_rsp; + flash_macro_status_t flash_macro_status; ast_pkg::ast_obs_ctrl_t obs_ctrl; @@ -73,9 +81,9 @@ module tb; .rst_n(rst_n) ); - `define FLASH_DEVICE_HIER tb.dut.u_eflash.u_flash - assign fpp_if.req = `FLASH_DEVICE_HIER.flash_req_i; - assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_rsp_o; + `define FLASH_DEVICE_HIER tb.flash_macro_wrapper + assign fpp_if.req = `FLASH_DEVICE_HIER.flash_i; + assign fpp_if.rsp = `FLASH_DEVICE_HIER.flash_o; for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_bank_loop assign fpp_if.rreq[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.req_i; assign fpp_if.rdy[i] = tb.dut.u_eflash.gen_flash_cores[i].u_core.u_rd.rdy_o; @@ -142,11 +150,9 @@ module tb; .clk_otp_i (clk), .rst_otp_ni (rst_n), - // various tlul interfaces + // tlul interfaces .core_tl_i(tl_if.h2d), .core_tl_o(tl_if.d2h), - .prim_tl_i(prim_tl_if.h2d), - .prim_tl_o(prim_tl_if.d2h), .mem_tl_i (eflash_tl_if.h2d), .mem_tl_o (eflash_tl_if.d2h), @@ -160,7 +166,6 @@ module tb; .lc_iso_part_sw_rd_en_i (flash_ctrl_if.lc_iso_part_sw_rd_en), .lc_iso_part_sw_wr_en_i (flash_ctrl_if.lc_iso_part_sw_wr_en), .lc_seed_hw_rd_en_i (flash_ctrl_if.lc_seed_hw_rd_en), - .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), .lc_escalate_en_i (flash_ctrl_if.lc_escalate_en), // life cycle rma handling @@ -173,23 +178,9 @@ module tb; .keymgr_o(flash_ctrl_if.keymgr), // flash prim signals - .flash_power_ready_h_i (flash_ctrl_if.power_ready_h), - .flash_power_down_h_i (flash_power_down_h), - .flash_bist_enable_i (prim_mubi_pkg::MuBi4False), - .flash_test_mode_a_io (flash_test_mode_a), - .flash_test_voltage_h_io(flash_test_v), - - // test - .scanmode_i (prim_mubi_pkg::MuBi4False), - .scan_rst_ni('0), - .scan_en_i ('0), - - // JTAG - .cio_tck_i (flash_ctrl_if.cio_tck), - .cio_tms_i (flash_ctrl_if.cio_tms), - .cio_tdi_i (flash_ctrl_if.cio_tdi), - .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), - .cio_tdo_o (flash_ctrl_if.cio_tdo), + .flash_macro_o (flash_macro_req), + .flash_macro_i (flash_macro_rsp), + .flash_macro_status_i (flash_macro_status), // alerts and interrupts .intr_prog_empty_o(intr_prog_empty), @@ -199,12 +190,43 @@ module tb; .intr_op_done_o (intr_op_done), .intr_corr_err_o (intr_err), .alert_rx_i (alert_rx), - .alert_tx_o (alert_tx), + .alert_tx_o (alert_tx) - // Observability - .obs_ctrl_i(obs_ctrl), - .fla_obs_o ( ) + ); + flash_macro_wrapper #( + .NumBanks(flash_phy_macro_pkg::NumBanks), + .InfosPerBank(flash_phy_macro_pkg::InfosPerBank), + .InfoTypes(flash_phy_macro_pkg::InfoTypes), + .InfoTypesWidth(flash_phy_macro_pkg::InfoTypesWidth), + .PagesPerBank(flash_phy_macro_pkg::PagesPerBank), + .WordsPerPage(flash_phy_macro_pkg::WordsPerPage), + .DataWidth(flash_phy_pkg::FullDataWidth) + ) flash_macro_wrapper ( + .clk_i (clk), + .rst_ni (rst_n), + .tl_i (prim_tl_if.h2d), + .tl_o (prim_tl_if.d2h), + .lc_nvm_debug_en_i (flash_ctrl_if.lc_nvm_debug_en), + .flash_i (flash_macro_req), + .flash_o (flash_macro_rsp), + .status_o (flash_macro_status), + // JTAG + .cio_tck_i (flash_ctrl_if.cio_tck), + .cio_tms_i (flash_ctrl_if.cio_tms), + .cio_tdi_i (flash_ctrl_if.cio_tdi), + .cio_tdo_en_o(flash_ctrl_if.cio_tdo_en), + .cio_tdo_o (flash_ctrl_if.cio_tdo), + .bist_enable_i(prim_mubi_pkg::MuBi4False), + .obs_ctrl_i (obs_ctrl), + .fla_obs_o ( ), + .scanmode_i (prim_mubi_pkg::MuBi4False), + .scan_en_i ('0), + .scan_rst_ni ('0), + .power_ready_h_i (flash_ctrl_if.power_ready_h), + .power_down_h_i (flash_power_down_h), + .test_mode_a_io (flash_test_mode_a), + .test_voltage_h_io (flash_test_v) ); // Create edge in flash_power_down_h_i, whenever reset is asserted @@ -243,25 +265,22 @@ module tb; // // For eflash of a specific vendor implementation, set the hierarchy to the memory element // correctly when creating these instances in the extended testbench. - `define FLASH_BANK_HIER(i) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank + `define FLASH_BANK_HIER(i) \ + tb.flash_macro_wrapper.gen_flash_banks[i].u_flash_macro_bank - `define FLASH_DATA_MEM_HIER(i) \ + `define FLASH_DATA_MEM_HIER(i) \ `FLASH_BANK_HIER(i).u_mem.mem - `define FLASH_DATA_MEM_HIER_STR(i) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.u_mem.mem"}, i) + `define FLASH_DATA_MEM_HIER_STR(i) \ + $sformatf("tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.u_mem.mem", i) - `define FLASH_INFO_MEM_HIER(i, j) \ - tb.dut.u_eflash.u_flash.gen_prim_flash_banks[i]. \ - u_prim_flash_bank.gen_info_types[j].u_info_mem.mem + `define FLASH_INFO_MEM_HIER(i, j) \ + tb.flash_macro_wrapper.gen_flash_banks[i]. \ + u_flash_macro_bank.gen_info_types[j].u_info_mem.mem - `define FLASH_INFO_MEM_HIER_STR(i, j) \ - $sformatf({"tb.dut.u_eflash.u_flash.", \ - "gen_prim_flash_banks[%0d].u_prim_flash_bank.gen_info_types[%0d].", \ - "u_info_mem.mem"}, i, j) + `define FLASH_INFO_MEM_HIER_STR(i, j) \ + $sformatf({"tb.flash_macro_wrapper.gen_flash_banks[%0d].u_flash_macro_bank.", \ + "gen_info_types[%0d].u_info_mem.mem"}, i, j) if (`PRIM_DEFAULT_IMPL == prim_pkg::ImplGeneric) begin : gen_generic for (genvar i = 0; i < flash_ctrl_top_specific_pkg::NumBanks; i++) begin : gen_each_bank @@ -276,6 +295,9 @@ module tb; .n_bits($bits(`FLASH_DATA_MEM_HIER(i))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d part=%s fails", i, part.name()), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -291,6 +313,9 @@ module tb; .n_bits($bits(`FLASH_INFO_MEM_HIER(i, j))), .err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68) ); + `DV_CHECK(m_mem_bkdr_util, $sformatf( + "mem_bkdr_util bank=%0d, part=%s, info=%0d fails", i, part.name(), j), , + "flash_ctrl tb") uvm_config_db#(flash_ctrl_bkdr_util)::set(null, "*.env", m_mem_bkdr_util.get_name(), m_mem_bkdr_util); part = part.next(); @@ -337,7 +362,8 @@ module tb; uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", "clk_rst_vif_flash_ctrl_eflash_reg_block", clk_rst_if); uvm_config_db#(virtual clk_rst_if)::set(null, "*.env", - "clk_rst_vif_flash_ctrl_prim_reg_block", clk_rst_if); + "clk_rst_vif_flash_macro_wrapper_reg_block", + clk_rst_if); uvm_config_db#(virtual rst_shadowed_if)::set(null, "*.env", "rst_shadowed_vif", rst_shadowed_if); @@ -346,8 +372,8 @@ module tb; tl_if); uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_eflash_reg_block*", "vif", eflash_tl_if); - uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_ctrl_prim_reg_block*", "vif", - prim_tl_if); + uvm_config_db#(virtual tl_if)::set(null, "*.env.m_tl_agent_flash_macro_wrapper_reg_block*", + "vif", prim_tl_if); uvm_config_db#(virtual flash_ctrl_if)::set(null, "*.env", "flash_ctrl_vif", flash_ctrl_if); uvm_config_db#(virtual flash_phy_prim_if)::set(null, "*.env.m_fpp_agent*", "vif", fpp_if); $timeformat(-9, 1, " ns", 9); diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core index 5acec0c3d19..9c5e52a33f9 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:englishbreakfast_ip:flash_ctrl:0.1 @@ -8,11 +9,14 @@ description: "Flash Controller" filesets: files_rtl: depend: + - lowrisc:englishbreakfast_ip:flash_phy_macro_pkg + - lowrisc:englishbreakfast_ip:flash_phy_pkg + - lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg - lowrisc:ip:tlul + - lowrisc:ip:flash_macro_wrapper - lowrisc:prim:all - lowrisc:prim:count - lowrisc:prim:edge_detector - - lowrisc:prim:flash - lowrisc:prim:flop_2sync - lowrisc:prim:gf_mult - lowrisc:prim:lc_sync @@ -22,7 +26,6 @@ filesets: # TODO(#27347): prim_legacy_pkg is deprecated - lowrisc:prim:prim_legacy_pkg - lowrisc:ip:otp_ctrl_pkg - - lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg - lowrisc:englishbreakfast_ip:flash_ctrl_reg - lowrisc:englishbreakfast_constants:top_pkg - lowrisc:ip:jtag_pkg diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core index eda10e9f4c6..750e468ef0e 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_top_specific_pkg.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg:0.1 @@ -17,13 +18,11 @@ filesets: - lowrisc:ip:jtag_pkg - lowrisc:ip:edn_pkg - lowrisc:tlul:headers - - lowrisc:ip:flash_ctrl_pkg - "fileset_partner ? (partner:systems:ast_pkg)" - "!fileset_partner ? (lowrisc:systems:ast_pkg)" files: - rtl/flash_ctrl_reg_pkg.sv - rtl/flash_ctrl_top_specific_pkg.sv - - rtl/flash_phy_pkg.sv file_type: systemVerilogSource files_verilator_waiver: diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core similarity index 51% rename from hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core rename to hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core index 898b73277f6..b81ca0b018c 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_ctrl_prim_reg_top.core +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_macro_pkg.core @@ -1,30 +1,24 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 -name: lowrisc:englishbreakfast_ip:flash_ctrl_prim_reg_top:1.0 -description: "Generic register top for the FLASH wrapper" +name: lowrisc:englishbreakfast_ip:flash_phy_macro_pkg:0.1 +description: "Flash phy interface to flash macro" virtual: - - lowrisc:virtual_ip:flash_ctrl_prim_reg_top + - lowrisc:virtual_ip:flash_phy_macro_pkg filesets: files_rtl: depend: + - lowrisc:ip:tlul - lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg - - lowrisc:prim:subreg +# - lowrisc:englishbreakfast_ip:flash_phy_pkg files: - - rtl/flash_ctrl_prim_reg_top.sv + - rtl/flash_phy_macro_pkg.sv file_type: systemVerilogSource - -parameters: - SYNTHESIS: - datatype: bool - paramtype: vlogdefine - - targets: - default: &default_target + default: filesets: - files_rtl - toplevel: lc_ctrl diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_pkg.core b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_pkg.core new file mode 100644 index 00000000000..9a75a246b09 --- /dev/null +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/flash_phy_pkg.core @@ -0,0 +1,22 @@ +CAPI=2: +# Copyright zeroRISC Inc. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 +name: lowrisc:englishbreakfast_ip:flash_phy_pkg:0.1 +description: "Top specific flash phy package" +virtual: + - lowrisc:virtual_ip:flash_phy_pkg + +filesets: + files_rtl: + depend: + - lowrisc:englishbreakfast_ip:flash_ctrl_top_specific_pkg + - lowrisc:englishbreakfast_ip:flash_phy_macro_pkg + files: + - rtl/flash_phy_pkg.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_rtl diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv index 32263ee71ac..d9393c8cafa 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -39,13 +40,10 @@ module flash_ctrl input lc_ctrl_pkg::lc_tx_t lc_iso_part_sw_wr_en_i, input lc_ctrl_pkg::lc_tx_t lc_seed_hw_rd_en_i, input lc_ctrl_pkg::lc_tx_t lc_escalate_en_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, // Bus Interface input tlul_pkg::tl_h2d_t core_tl_i, output tlul_pkg::tl_d2h_t core_tl_o, - input tlul_pkg::tl_h2d_t prim_tl_i, - output tlul_pkg::tl_d2h_t prim_tl_o, input tlul_pkg::tl_h2d_t mem_tl_i, output tlul_pkg::tl_d2h_t mem_tl_o, @@ -59,13 +57,6 @@ module flash_ctrl output pwrmgr_pkg::pwr_flash_t pwrmgr_o, output keymgr_flash_t keymgr_o, - // IOs - input cio_tck_i, - input cio_tms_i, - input cio_tdi_i, - output logic cio_tdo_en_o, - output logic cio_tdo_o, - // Interrupts output logic intr_corr_err_o, // Correctable errors encountered output logic intr_prog_empty_o, // Program fifo is empty @@ -74,23 +65,14 @@ module flash_ctrl output logic intr_rd_lvl_o, // Read fifo is full output logic intr_op_done_o, // Requested flash operation (wr/erase) done + // Flash macro interface + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_i, + input flash_phy_macro_pkg::flash_macro_status_t flash_macro_status_i, + // Alerts input prim_alert_pkg::alert_rx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_rx_i, - output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o, - - // Observability - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - - // Flash test interface - input scan_en_i, - input prim_mubi_pkg::mubi4_t scanmode_i, - input scan_rst_ni, - input prim_mubi_pkg::mubi4_t flash_bist_enable_i, - input flash_power_down_h_i, - input flash_power_ready_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io + output prim_alert_pkg::alert_tx_t [flash_ctrl_reg_pkg::NumAlerts-1:0] alert_tx_o ); ////////////////////////////////////////////////////////// @@ -901,12 +883,6 @@ module flash_ctrl assign flash_phy_req.rand_data_key = rand_data_key; assign flash_phy_req.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q; assign flash_phy_req.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q; - assign flash_phy_req.jtag_req.tck = cio_tck_i; - assign flash_phy_req.jtag_req.tms = cio_tms_i; - assign flash_phy_req.jtag_req.tdi = cio_tdi_i; - assign flash_phy_req.jtag_req.trst_n = '0; - assign cio_tdo_o = flash_phy_rsp.jtag_rsp.tdo; - assign cio_tdo_en_o = flash_phy_rsp.jtag_rsp.tdo_oe; assign flash_rd_err = flash_phy_rsp.rd_err; assign flash_rd_data = flash_phy_rsp.rd_data; assign flash_phy_busy = flash_phy_rsp.init_busy; @@ -935,12 +911,11 @@ module flash_ctrl logic [NumAlerts-1:0] alert_srcs; logic [NumAlerts-1:0] alert_tests; - logic fatal_prim_flash_alert, recov_prim_flash_alert; // An excessive number of recoverable errors may also indicate an attack logic recov_err; assign recov_err = (sw_ctrl_done & |sw_ctrl_err) | - flash_phy_rsp.macro_err | + flash_macro_status_i.flash_err | update_err; logic fatal_err; @@ -953,8 +928,8 @@ module flash_ctrl assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err); assign alert_srcs = { - recov_prim_flash_alert, - fatal_prim_flash_alert, + flash_macro_status_i.recov_alert, + flash_macro_status_i.fatal_alert, fatal_err, fatal_std_err, recov_err @@ -1085,7 +1060,7 @@ module flash_ctrl assign hw2reg.err_code.prog_win_err.de = sw_ctrl_err.prog_win_err; assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err; assign hw2reg.err_code.update_err.de = update_err; - assign hw2reg.err_code.macro_err.de = flash_phy_rsp.macro_err; + assign hw2reg.err_code.macro_err.de = flash_macro_status_i.flash_err; assign hw2reg.err_addr.d = {ctrl_err_addr, {BusByteWidth{1'h0}}}; assign hw2reg.err_addr.de = sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | @@ -1356,21 +1331,10 @@ module flash_ctrl .host_rdata_o (flash_host_rdata), .flash_ctrl_i (flash_phy_req), .flash_ctrl_o (flash_phy_rsp), - .tl_i (prim_tl_i), - .tl_o (prim_tl_o), - .obs_ctrl_i, - .fla_obs_o, - .lc_nvm_debug_en_i, - .flash_bist_enable_i, - .flash_power_down_h_i, - .flash_power_ready_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .fatal_prim_flash_alert_o(fatal_prim_flash_alert), - .recov_prim_flash_alert_o(recov_prim_flash_alert), - .scanmode_i, - .scan_en_i, - .scan_rst_ni + .flash_macro_req_o (flash_macro_o), + .flash_macro_rsp_i (flash_macro_i), + .prog_type_avail_i (flash_macro_status_i.prog_type_avail), + .init_busy_i (flash_macro_status_i.init_busy) ); ///////////////////////////////// @@ -1380,9 +1344,6 @@ module flash_ctrl `ASSERT_KNOWN(TlDValidKnownO_A, core_tl_o.d_valid ) `ASSERT_KNOWN(TlAReadyKnownO_A, core_tl_o.a_ready ) `ASSERT_KNOWN_IF(RspPayLoad_A, core_tl_o, core_tl_o.d_valid) - `ASSERT_KNOWN(PrimTlDValidKnownO_A, prim_tl_o.d_valid ) - `ASSERT_KNOWN(PrimTlAReadyKnownO_A, prim_tl_o.a_ready ) - `ASSERT_KNOWN_IF(PrimRspPayLoad_A, prim_tl_o, prim_tl_o.d_valid) `ASSERT_KNOWN(MemTlDValidKnownO_A, mem_tl_o.d_valid ) `ASSERT_KNOWN(MemTlAReadyKnownO_A, mem_tl_o.a_ready ) `ASSERT_KNOWN_IF(MemRspPayLoad_A, mem_tl_o, mem_tl_o.d_valid) @@ -1398,8 +1359,6 @@ module flash_ctrl `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o ) `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o ) `ASSERT_KNOWN(IntrErrO_A, intr_corr_err_o ) - `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o ) - `ASSERT(TdoEnIsOne_A, cio_tdo_en_o === 1'b1) // combined indication that an operation has started // This is used only for assertions diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv deleted file mode 100644 index 873559c1c81..00000000000 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prim_reg_top.sv +++ /dev/null @@ -1,2387 +0,0 @@ -// Copyright lowRISC contributors (OpenTitan project). -// Licensed under the Apache License, Version 2.0, see LICENSE for details. -// SPDX-License-Identifier: Apache-2.0 -// -// Register Top module auto-generated by `reggen` - -`include "prim_assert.sv" - -module flash_ctrl_prim_reg_top ( - input clk_i, - input rst_ni, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - // To HW - output flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw, // Write - input flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg, // Read - - // Integrity check errors - output logic intg_err_o -); - - import flash_ctrl_reg_pkg::* ; - - localparam int AW = 7; - localparam int DW = 32; - localparam int DBW = DW/8; // Byte Width - - // register signals - logic reg_we; - logic reg_re; - logic [AW-1:0] reg_addr; - logic [DW-1:0] reg_wdata; - logic [DBW-1:0] reg_be; - logic [DW-1:0] reg_rdata; - logic reg_error; - - logic addrmiss, wr_err; - - logic [DW-1:0] reg_rdata_next; - logic reg_busy; - - tlul_pkg::tl_h2d_t tl_reg_h2d; - tlul_pkg::tl_d2h_t tl_reg_d2h; - - - // incoming payload check - logic intg_err; - tlul_cmd_intg_chk u_chk ( - .tl_i(tl_i), - .err_o(intg_err) - ); - - // also check for spurious write enables - logic reg_we_err; - logic [20:0] reg_we_check; - prim_reg_we_check #( - .OneHotWidth(21) - ) u_prim_reg_we_check ( - .clk_i(clk_i), - .rst_ni(rst_ni), - .oh_i (reg_we_check), - .en_i (reg_we && !addrmiss), - .err_o (reg_we_err) - ); - - logic err_q; - always_ff @(posedge clk_i or negedge rst_ni) begin - if (!rst_ni) begin - err_q <= '0; - end else if (intg_err || reg_we_err) begin - err_q <= 1'b1; - end - end - - // integrity error output is permanent and should be used for alert generation - // register errors are transactional - assign intg_err_o = err_q | intg_err | reg_we_err; - - // outgoing integrity generation - tlul_pkg::tl_d2h_t tl_o_pre; - tlul_rsp_intg_gen #( - .EnableRspIntgGen(1), - .EnableDataIntgGen(1) - ) u_rsp_intg_gen ( - .tl_i(tl_o_pre), - .tl_o(tl_o) - ); - - assign tl_reg_h2d = tl_i; - assign tl_o_pre = tl_reg_d2h; - - tlul_adapter_reg #( - .RegAw(AW), - .RegDw(DW), - .EnableDataIntgGen(0) - ) u_reg_if ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - .tl_i (tl_reg_h2d), - .tl_o (tl_reg_d2h), - - .en_ifetch_i(prim_mubi_pkg::MuBi4False), - .intg_error_o(), - - .we_o (reg_we), - .re_o (reg_re), - .addr_o (reg_addr), - .wdata_o (reg_wdata), - .be_o (reg_be), - .busy_i (reg_busy), - .rdata_i (reg_rdata), - .error_i (reg_error) - ); - - // cdc oversampling signals - - assign reg_rdata = reg_rdata_next ; - assign reg_error = addrmiss | wr_err | intg_err; - - // Define SW related signals - // Format: __{wd|we|qs} - // or _{wd|we|qs} if field == 1 or 0 - logic csr0_regwen_we; - logic csr0_regwen_qs; - logic csr0_regwen_wd; - logic csr1_we; - logic [7:0] csr1_field0_qs; - logic [7:0] csr1_field0_wd; - logic [4:0] csr1_field1_qs; - logic [4:0] csr1_field1_wd; - logic csr2_we; - logic csr2_field0_qs; - logic csr2_field0_wd; - logic csr2_field1_qs; - logic csr2_field1_wd; - logic csr2_field2_qs; - logic csr2_field2_wd; - logic csr2_field3_qs; - logic csr2_field3_wd; - logic csr2_field4_qs; - logic csr2_field4_wd; - logic csr2_field5_qs; - logic csr2_field5_wd; - logic csr2_field6_qs; - logic csr2_field6_wd; - logic csr2_field7_qs; - logic csr2_field7_wd; - logic csr3_we; - logic [3:0] csr3_field0_qs; - logic [3:0] csr3_field0_wd; - logic [3:0] csr3_field1_qs; - logic [3:0] csr3_field1_wd; - logic [2:0] csr3_field2_qs; - logic [2:0] csr3_field2_wd; - logic [2:0] csr3_field3_qs; - logic [2:0] csr3_field3_wd; - logic [2:0] csr3_field4_qs; - logic [2:0] csr3_field4_wd; - logic [2:0] csr3_field5_qs; - logic [2:0] csr3_field5_wd; - logic csr3_field6_qs; - logic csr3_field6_wd; - logic [2:0] csr3_field7_qs; - logic [2:0] csr3_field7_wd; - logic [1:0] csr3_field8_qs; - logic [1:0] csr3_field8_wd; - logic [1:0] csr3_field9_qs; - logic [1:0] csr3_field9_wd; - logic csr4_we; - logic [2:0] csr4_field0_qs; - logic [2:0] csr4_field0_wd; - logic [2:0] csr4_field1_qs; - logic [2:0] csr4_field1_wd; - logic [2:0] csr4_field2_qs; - logic [2:0] csr4_field2_wd; - logic [2:0] csr4_field3_qs; - logic [2:0] csr4_field3_wd; - logic csr5_we; - logic [2:0] csr5_field0_qs; - logic [2:0] csr5_field0_wd; - logic [1:0] csr5_field1_qs; - logic [1:0] csr5_field1_wd; - logic [8:0] csr5_field2_qs; - logic [8:0] csr5_field2_wd; - logic [4:0] csr5_field3_qs; - logic [4:0] csr5_field3_wd; - logic [3:0] csr5_field4_qs; - logic [3:0] csr5_field4_wd; - logic csr6_we; - logic [2:0] csr6_field0_qs; - logic [2:0] csr6_field0_wd; - logic [2:0] csr6_field1_qs; - logic [2:0] csr6_field1_wd; - logic [7:0] csr6_field2_qs; - logic [7:0] csr6_field2_wd; - logic [2:0] csr6_field3_qs; - logic [2:0] csr6_field3_wd; - logic [1:0] csr6_field4_qs; - logic [1:0] csr6_field4_wd; - logic [1:0] csr6_field5_qs; - logic [1:0] csr6_field5_wd; - logic [1:0] csr6_field6_qs; - logic [1:0] csr6_field6_wd; - logic csr6_field7_qs; - logic csr6_field7_wd; - logic csr6_field8_qs; - logic csr6_field8_wd; - logic csr7_we; - logic [7:0] csr7_field0_qs; - logic [7:0] csr7_field0_wd; - logic [8:0] csr7_field1_qs; - logic [8:0] csr7_field1_wd; - logic csr8_we; - logic [31:0] csr8_qs; - logic [31:0] csr8_wd; - logic csr9_we; - logic [31:0] csr9_qs; - logic [31:0] csr9_wd; - logic csr10_we; - logic [31:0] csr10_qs; - logic [31:0] csr10_wd; - logic csr11_we; - logic [31:0] csr11_qs; - logic [31:0] csr11_wd; - logic csr12_we; - logic [9:0] csr12_qs; - logic [9:0] csr12_wd; - logic csr13_we; - logic [19:0] csr13_field0_qs; - logic [19:0] csr13_field0_wd; - logic csr13_field1_qs; - logic csr13_field1_wd; - logic csr14_we; - logic [7:0] csr14_field0_qs; - logic [7:0] csr14_field0_wd; - logic csr14_field1_qs; - logic csr14_field1_wd; - logic csr15_we; - logic [7:0] csr15_field0_qs; - logic [7:0] csr15_field0_wd; - logic csr15_field1_qs; - logic csr15_field1_wd; - logic csr16_we; - logic [7:0] csr16_field0_qs; - logic [7:0] csr16_field0_wd; - logic csr16_field1_qs; - logic csr16_field1_wd; - logic csr17_we; - logic [7:0] csr17_field0_qs; - logic [7:0] csr17_field0_wd; - logic csr17_field1_qs; - logic csr17_field1_wd; - logic csr18_we; - logic csr18_qs; - logic csr18_wd; - logic csr19_we; - logic csr19_qs; - logic csr19_wd; - logic csr20_we; - logic csr20_field0_qs; - logic csr20_field0_wd; - logic csr20_field1_qs; - logic csr20_field1_wd; - logic csr20_field2_qs; - - // Register instances - // R[csr0_regwen]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_csr0_regwen ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr0_regwen_we), - .wd (csr0_regwen_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (csr0_regwen_qs) - ); - - - // R[csr1]: V(False) - // Create REGWEN-gated WE signal - logic csr1_gated_we; - assign csr1_gated_we = csr1_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr1_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr1_gated_we), - .wd (csr1_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr1.field0.q), - .ds (), - - // to register interface (read) - .qs (csr1_field0_qs) - ); - - // F[field1]: 12:8 - prim_subreg #( - .DW (5), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (5'h0), - .Mubi (1'b0) - ) u_csr1_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr1_gated_we), - .wd (csr1_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr1.field1.q), - .ds (), - - // to register interface (read) - .qs (csr1_field1_qs) - ); - - - // R[csr2]: V(False) - // F[field0]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field0_wd), - - // from internal hardware - .de (hw2reg.csr2.field0.de), - .d (hw2reg.csr2.field0.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field0.q), - .ds (), - - // to register interface (read) - .qs (csr2_field0_qs) - ); - - // F[field1]: 1:1 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field1_wd), - - // from internal hardware - .de (hw2reg.csr2.field1.de), - .d (hw2reg.csr2.field1.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field1.q), - .ds (), - - // to register interface (read) - .qs (csr2_field1_qs) - ); - - // F[field2]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field2_wd), - - // from internal hardware - .de (hw2reg.csr2.field2.de), - .d (hw2reg.csr2.field2.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field2.q), - .ds (), - - // to register interface (read) - .qs (csr2_field2_qs) - ); - - // F[field3]: 3:3 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field3_wd), - - // from internal hardware - .de (hw2reg.csr2.field3.de), - .d (hw2reg.csr2.field3.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field3.q), - .ds (), - - // to register interface (read) - .qs (csr2_field3_qs) - ); - - // F[field4]: 4:4 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field4 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field4_wd), - - // from internal hardware - .de (hw2reg.csr2.field4.de), - .d (hw2reg.csr2.field4.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field4.q), - .ds (), - - // to register interface (read) - .qs (csr2_field4_qs) - ); - - // F[field5]: 5:5 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field5 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field5_wd), - - // from internal hardware - .de (hw2reg.csr2.field5.de), - .d (hw2reg.csr2.field5.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field5.q), - .ds (), - - // to register interface (read) - .qs (csr2_field5_qs) - ); - - // F[field6]: 6:6 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field6 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field6_wd), - - // from internal hardware - .de (hw2reg.csr2.field6.de), - .d (hw2reg.csr2.field6.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field6.q), - .ds (), - - // to register interface (read) - .qs (csr2_field6_qs) - ); - - // F[field7]: 7:7 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr2_field7 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr2_we), - .wd (csr2_field7_wd), - - // from internal hardware - .de (hw2reg.csr2.field7.de), - .d (hw2reg.csr2.field7.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr2.field7.q), - .ds (), - - // to register interface (read) - .qs (csr2_field7_qs) - ); - - - // R[csr3]: V(False) - // Create REGWEN-gated WE signal - logic csr3_gated_we; - assign csr3_gated_we = csr3_we & csr0_regwen_qs; - // F[field0]: 3:0 - prim_subreg #( - .DW (4), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (4'h0), - .Mubi (1'b0) - ) u_csr3_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field0.q), - .ds (), - - // to register interface (read) - .qs (csr3_field0_qs) - ); - - // F[field1]: 7:4 - prim_subreg #( - .DW (4), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (4'h0), - .Mubi (1'b0) - ) u_csr3_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field1.q), - .ds (), - - // to register interface (read) - .qs (csr3_field1_qs) - ); - - // F[field2]: 10:8 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr3_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field2_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field2.q), - .ds (), - - // to register interface (read) - .qs (csr3_field2_qs) - ); - - // F[field3]: 13:11 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr3_field3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field3_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field3.q), - .ds (), - - // to register interface (read) - .qs (csr3_field3_qs) - ); - - // F[field4]: 16:14 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr3_field4 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field4_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field4.q), - .ds (), - - // to register interface (read) - .qs (csr3_field4_qs) - ); - - // F[field5]: 19:17 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr3_field5 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field5_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field5.q), - .ds (), - - // to register interface (read) - .qs (csr3_field5_qs) - ); - - // F[field6]: 20:20 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr3_field6 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field6_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field6.q), - .ds (), - - // to register interface (read) - .qs (csr3_field6_qs) - ); - - // F[field7]: 23:21 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr3_field7 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field7_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field7.q), - .ds (), - - // to register interface (read) - .qs (csr3_field7_qs) - ); - - // F[field8]: 25:24 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr3_field8 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field8_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field8.q), - .ds (), - - // to register interface (read) - .qs (csr3_field8_qs) - ); - - // F[field9]: 27:26 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr3_field9 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr3_gated_we), - .wd (csr3_field9_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr3.field9.q), - .ds (), - - // to register interface (read) - .qs (csr3_field9_qs) - ); - - - // R[csr4]: V(False) - // Create REGWEN-gated WE signal - logic csr4_gated_we; - assign csr4_gated_we = csr4_we & csr0_regwen_qs; - // F[field0]: 2:0 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr4_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr4_gated_we), - .wd (csr4_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr4.field0.q), - .ds (), - - // to register interface (read) - .qs (csr4_field0_qs) - ); - - // F[field1]: 5:3 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr4_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr4_gated_we), - .wd (csr4_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr4.field1.q), - .ds (), - - // to register interface (read) - .qs (csr4_field1_qs) - ); - - // F[field2]: 8:6 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr4_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr4_gated_we), - .wd (csr4_field2_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr4.field2.q), - .ds (), - - // to register interface (read) - .qs (csr4_field2_qs) - ); - - // F[field3]: 11:9 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr4_field3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr4_gated_we), - .wd (csr4_field3_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr4.field3.q), - .ds (), - - // to register interface (read) - .qs (csr4_field3_qs) - ); - - - // R[csr5]: V(False) - // Create REGWEN-gated WE signal - logic csr5_gated_we; - assign csr5_gated_we = csr5_we & csr0_regwen_qs; - // F[field0]: 2:0 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr5_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr5_gated_we), - .wd (csr5_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr5.field0.q), - .ds (), - - // to register interface (read) - .qs (csr5_field0_qs) - ); - - // F[field1]: 4:3 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr5_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr5_gated_we), - .wd (csr5_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr5.field1.q), - .ds (), - - // to register interface (read) - .qs (csr5_field1_qs) - ); - - // F[field2]: 13:5 - prim_subreg #( - .DW (9), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (9'h0), - .Mubi (1'b0) - ) u_csr5_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr5_gated_we), - .wd (csr5_field2_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr5.field2.q), - .ds (), - - // to register interface (read) - .qs (csr5_field2_qs) - ); - - // F[field3]: 18:14 - prim_subreg #( - .DW (5), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (5'h0), - .Mubi (1'b0) - ) u_csr5_field3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr5_gated_we), - .wd (csr5_field3_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr5.field3.q), - .ds (), - - // to register interface (read) - .qs (csr5_field3_qs) - ); - - // F[field4]: 22:19 - prim_subreg #( - .DW (4), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (4'h0), - .Mubi (1'b0) - ) u_csr5_field4 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr5_gated_we), - .wd (csr5_field4_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr5.field4.q), - .ds (), - - // to register interface (read) - .qs (csr5_field4_qs) - ); - - - // R[csr6]: V(False) - // Create REGWEN-gated WE signal - logic csr6_gated_we; - assign csr6_gated_we = csr6_we & csr0_regwen_qs; - // F[field0]: 2:0 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr6_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field0.q), - .ds (), - - // to register interface (read) - .qs (csr6_field0_qs) - ); - - // F[field1]: 5:3 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr6_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field1.q), - .ds (), - - // to register interface (read) - .qs (csr6_field1_qs) - ); - - // F[field2]: 13:6 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr6_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field2_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field2.q), - .ds (), - - // to register interface (read) - .qs (csr6_field2_qs) - ); - - // F[field3]: 16:14 - prim_subreg #( - .DW (3), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (3'h0), - .Mubi (1'b0) - ) u_csr6_field3 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field3_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field3.q), - .ds (), - - // to register interface (read) - .qs (csr6_field3_qs) - ); - - // F[field4]: 18:17 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr6_field4 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field4_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field4.q), - .ds (), - - // to register interface (read) - .qs (csr6_field4_qs) - ); - - // F[field5]: 20:19 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr6_field5 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field5_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field5.q), - .ds (), - - // to register interface (read) - .qs (csr6_field5_qs) - ); - - // F[field6]: 22:21 - prim_subreg #( - .DW (2), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (2'h0), - .Mubi (1'b0) - ) u_csr6_field6 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field6_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field6.q), - .ds (), - - // to register interface (read) - .qs (csr6_field6_qs) - ); - - // F[field7]: 23:23 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr6_field7 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field7_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field7.q), - .ds (), - - // to register interface (read) - .qs (csr6_field7_qs) - ); - - // F[field8]: 24:24 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr6_field8 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr6_gated_we), - .wd (csr6_field8_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr6.field8.q), - .ds (), - - // to register interface (read) - .qs (csr6_field8_qs) - ); - - - // R[csr7]: V(False) - // Create REGWEN-gated WE signal - logic csr7_gated_we; - assign csr7_gated_we = csr7_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr7_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr7_gated_we), - .wd (csr7_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr7.field0.q), - .ds (), - - // to register interface (read) - .qs (csr7_field0_qs) - ); - - // F[field1]: 16:8 - prim_subreg #( - .DW (9), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (9'h0), - .Mubi (1'b0) - ) u_csr7_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr7_gated_we), - .wd (csr7_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr7.field1.q), - .ds (), - - // to register interface (read) - .qs (csr7_field1_qs) - ); - - - // R[csr8]: V(False) - // Create REGWEN-gated WE signal - logic csr8_gated_we; - assign csr8_gated_we = csr8_we & csr0_regwen_qs; - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_csr8 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr8_gated_we), - .wd (csr8_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr8.q), - .ds (), - - // to register interface (read) - .qs (csr8_qs) - ); - - - // R[csr9]: V(False) - // Create REGWEN-gated WE signal - logic csr9_gated_we; - assign csr9_gated_we = csr9_we & csr0_regwen_qs; - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_csr9 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr9_gated_we), - .wd (csr9_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr9.q), - .ds (), - - // to register interface (read) - .qs (csr9_qs) - ); - - - // R[csr10]: V(False) - // Create REGWEN-gated WE signal - logic csr10_gated_we; - assign csr10_gated_we = csr10_we & csr0_regwen_qs; - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_csr10 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr10_gated_we), - .wd (csr10_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr10.q), - .ds (), - - // to register interface (read) - .qs (csr10_qs) - ); - - - // R[csr11]: V(False) - // Create REGWEN-gated WE signal - logic csr11_gated_we; - assign csr11_gated_we = csr11_we & csr0_regwen_qs; - prim_subreg #( - .DW (32), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (32'h0), - .Mubi (1'b0) - ) u_csr11 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr11_gated_we), - .wd (csr11_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr11.q), - .ds (), - - // to register interface (read) - .qs (csr11_qs) - ); - - - // R[csr12]: V(False) - // Create REGWEN-gated WE signal - logic csr12_gated_we; - assign csr12_gated_we = csr12_we & csr0_regwen_qs; - prim_subreg #( - .DW (10), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (10'h0), - .Mubi (1'b0) - ) u_csr12 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr12_gated_we), - .wd (csr12_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr12.q), - .ds (), - - // to register interface (read) - .qs (csr12_qs) - ); - - - // R[csr13]: V(False) - // Create REGWEN-gated WE signal - logic csr13_gated_we; - assign csr13_gated_we = csr13_we & csr0_regwen_qs; - // F[field0]: 19:0 - prim_subreg #( - .DW (20), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (20'h0), - .Mubi (1'b0) - ) u_csr13_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr13_gated_we), - .wd (csr13_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr13.field0.q), - .ds (), - - // to register interface (read) - .qs (csr13_field0_qs) - ); - - // F[field1]: 20:20 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr13_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr13_gated_we), - .wd (csr13_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr13.field1.q), - .ds (), - - // to register interface (read) - .qs (csr13_field1_qs) - ); - - - // R[csr14]: V(False) - // Create REGWEN-gated WE signal - logic csr14_gated_we; - assign csr14_gated_we = csr14_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr14_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr14_gated_we), - .wd (csr14_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr14.field0.q), - .ds (), - - // to register interface (read) - .qs (csr14_field0_qs) - ); - - // F[field1]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr14_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr14_gated_we), - .wd (csr14_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr14.field1.q), - .ds (), - - // to register interface (read) - .qs (csr14_field1_qs) - ); - - - // R[csr15]: V(False) - // Create REGWEN-gated WE signal - logic csr15_gated_we; - assign csr15_gated_we = csr15_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr15_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr15_gated_we), - .wd (csr15_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr15.field0.q), - .ds (), - - // to register interface (read) - .qs (csr15_field0_qs) - ); - - // F[field1]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr15_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr15_gated_we), - .wd (csr15_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr15.field1.q), - .ds (), - - // to register interface (read) - .qs (csr15_field1_qs) - ); - - - // R[csr16]: V(False) - // Create REGWEN-gated WE signal - logic csr16_gated_we; - assign csr16_gated_we = csr16_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr16_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr16_gated_we), - .wd (csr16_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr16.field0.q), - .ds (), - - // to register interface (read) - .qs (csr16_field0_qs) - ); - - // F[field1]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr16_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr16_gated_we), - .wd (csr16_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr16.field1.q), - .ds (), - - // to register interface (read) - .qs (csr16_field1_qs) - ); - - - // R[csr17]: V(False) - // Create REGWEN-gated WE signal - logic csr17_gated_we; - assign csr17_gated_we = csr17_we & csr0_regwen_qs; - // F[field0]: 7:0 - prim_subreg #( - .DW (8), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (8'h0), - .Mubi (1'b0) - ) u_csr17_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr17_gated_we), - .wd (csr17_field0_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr17.field0.q), - .ds (), - - // to register interface (read) - .qs (csr17_field0_qs) - ); - - // F[field1]: 8:8 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr17_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr17_gated_we), - .wd (csr17_field1_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr17.field1.q), - .ds (), - - // to register interface (read) - .qs (csr17_field1_qs) - ); - - - // R[csr18]: V(False) - // Create REGWEN-gated WE signal - logic csr18_gated_we; - assign csr18_gated_we = csr18_we & csr0_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr18 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr18_gated_we), - .wd (csr18_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr18.q), - .ds (), - - // to register interface (read) - .qs (csr18_qs) - ); - - - // R[csr19]: V(False) - // Create REGWEN-gated WE signal - logic csr19_gated_we; - assign csr19_gated_we = csr19_we & csr0_regwen_qs; - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr19 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr19_gated_we), - .wd (csr19_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.csr19.q), - .ds (), - - // to register interface (read) - .qs (csr19_qs) - ); - - - // R[csr20]: V(False) - // F[field0]: 0:0 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr20_field0 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr20_we), - .wd (csr20_field0_wd), - - // from internal hardware - .de (hw2reg.csr20.field0.de), - .d (hw2reg.csr20.field0.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr20.field0.q), - .ds (), - - // to register interface (read) - .qs (csr20_field0_qs) - ); - - // F[field1]: 1:1 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW1C), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr20_field1 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (csr20_we), - .wd (csr20_field1_wd), - - // from internal hardware - .de (hw2reg.csr20.field1.de), - .d (hw2reg.csr20.field1.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr20.field1.q), - .ds (), - - // to register interface (read) - .qs (csr20_field1_qs) - ); - - // F[field2]: 2:2 - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessRO), - .RESVAL (1'h0), - .Mubi (1'b0) - ) u_csr20_field2 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (1'b0), - .wd ('0), - - // from internal hardware - .de (hw2reg.csr20.field2.de), - .d (hw2reg.csr20.field2.d), - - // to internal hardware - .qe (), - .q (reg2hw.csr20.field2.q), - .ds (), - - // to register interface (read) - .qs (csr20_field2_qs) - ); - - - - logic [20:0] addr_hit; - always_comb begin - addr_hit[ 0] = (reg_addr == FLASH_CTRL_CSR0_REGWEN_OFFSET); - addr_hit[ 1] = (reg_addr == FLASH_CTRL_CSR1_OFFSET); - addr_hit[ 2] = (reg_addr == FLASH_CTRL_CSR2_OFFSET); - addr_hit[ 3] = (reg_addr == FLASH_CTRL_CSR3_OFFSET); - addr_hit[ 4] = (reg_addr == FLASH_CTRL_CSR4_OFFSET); - addr_hit[ 5] = (reg_addr == FLASH_CTRL_CSR5_OFFSET); - addr_hit[ 6] = (reg_addr == FLASH_CTRL_CSR6_OFFSET); - addr_hit[ 7] = (reg_addr == FLASH_CTRL_CSR7_OFFSET); - addr_hit[ 8] = (reg_addr == FLASH_CTRL_CSR8_OFFSET); - addr_hit[ 9] = (reg_addr == FLASH_CTRL_CSR9_OFFSET); - addr_hit[10] = (reg_addr == FLASH_CTRL_CSR10_OFFSET); - addr_hit[11] = (reg_addr == FLASH_CTRL_CSR11_OFFSET); - addr_hit[12] = (reg_addr == FLASH_CTRL_CSR12_OFFSET); - addr_hit[13] = (reg_addr == FLASH_CTRL_CSR13_OFFSET); - addr_hit[14] = (reg_addr == FLASH_CTRL_CSR14_OFFSET); - addr_hit[15] = (reg_addr == FLASH_CTRL_CSR15_OFFSET); - addr_hit[16] = (reg_addr == FLASH_CTRL_CSR16_OFFSET); - addr_hit[17] = (reg_addr == FLASH_CTRL_CSR17_OFFSET); - addr_hit[18] = (reg_addr == FLASH_CTRL_CSR18_OFFSET); - addr_hit[19] = (reg_addr == FLASH_CTRL_CSR19_OFFSET); - addr_hit[20] = (reg_addr == FLASH_CTRL_CSR20_OFFSET); - end - - assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; - - // Check sub-word write is permitted - always_comb begin - wr_err = (reg_we & - ((addr_hit[ 0] & (|(FLASH_CTRL_PRIM_PERMIT[ 0] & ~reg_be))) | - (addr_hit[ 1] & (|(FLASH_CTRL_PRIM_PERMIT[ 1] & ~reg_be))) | - (addr_hit[ 2] & (|(FLASH_CTRL_PRIM_PERMIT[ 2] & ~reg_be))) | - (addr_hit[ 3] & (|(FLASH_CTRL_PRIM_PERMIT[ 3] & ~reg_be))) | - (addr_hit[ 4] & (|(FLASH_CTRL_PRIM_PERMIT[ 4] & ~reg_be))) | - (addr_hit[ 5] & (|(FLASH_CTRL_PRIM_PERMIT[ 5] & ~reg_be))) | - (addr_hit[ 6] & (|(FLASH_CTRL_PRIM_PERMIT[ 6] & ~reg_be))) | - (addr_hit[ 7] & (|(FLASH_CTRL_PRIM_PERMIT[ 7] & ~reg_be))) | - (addr_hit[ 8] & (|(FLASH_CTRL_PRIM_PERMIT[ 8] & ~reg_be))) | - (addr_hit[ 9] & (|(FLASH_CTRL_PRIM_PERMIT[ 9] & ~reg_be))) | - (addr_hit[10] & (|(FLASH_CTRL_PRIM_PERMIT[10] & ~reg_be))) | - (addr_hit[11] & (|(FLASH_CTRL_PRIM_PERMIT[11] & ~reg_be))) | - (addr_hit[12] & (|(FLASH_CTRL_PRIM_PERMIT[12] & ~reg_be))) | - (addr_hit[13] & (|(FLASH_CTRL_PRIM_PERMIT[13] & ~reg_be))) | - (addr_hit[14] & (|(FLASH_CTRL_PRIM_PERMIT[14] & ~reg_be))) | - (addr_hit[15] & (|(FLASH_CTRL_PRIM_PERMIT[15] & ~reg_be))) | - (addr_hit[16] & (|(FLASH_CTRL_PRIM_PERMIT[16] & ~reg_be))) | - (addr_hit[17] & (|(FLASH_CTRL_PRIM_PERMIT[17] & ~reg_be))) | - (addr_hit[18] & (|(FLASH_CTRL_PRIM_PERMIT[18] & ~reg_be))) | - (addr_hit[19] & (|(FLASH_CTRL_PRIM_PERMIT[19] & ~reg_be))) | - (addr_hit[20] & (|(FLASH_CTRL_PRIM_PERMIT[20] & ~reg_be))))); - end - - // Generate write-enables - assign csr0_regwen_we = addr_hit[0] & reg_we & !reg_error; - - assign csr0_regwen_wd = reg_wdata[0]; - assign csr1_we = addr_hit[1] & reg_we & !reg_error; - - assign csr1_field0_wd = reg_wdata[7:0]; - - assign csr1_field1_wd = reg_wdata[12:8]; - assign csr2_we = addr_hit[2] & reg_we & !reg_error; - - assign csr2_field0_wd = reg_wdata[0]; - - assign csr2_field1_wd = reg_wdata[1]; - - assign csr2_field2_wd = reg_wdata[2]; - - assign csr2_field3_wd = reg_wdata[3]; - - assign csr2_field4_wd = reg_wdata[4]; - - assign csr2_field5_wd = reg_wdata[5]; - - assign csr2_field6_wd = reg_wdata[6]; - - assign csr2_field7_wd = reg_wdata[7]; - assign csr3_we = addr_hit[3] & reg_we & !reg_error; - - assign csr3_field0_wd = reg_wdata[3:0]; - - assign csr3_field1_wd = reg_wdata[7:4]; - - assign csr3_field2_wd = reg_wdata[10:8]; - - assign csr3_field3_wd = reg_wdata[13:11]; - - assign csr3_field4_wd = reg_wdata[16:14]; - - assign csr3_field5_wd = reg_wdata[19:17]; - - assign csr3_field6_wd = reg_wdata[20]; - - assign csr3_field7_wd = reg_wdata[23:21]; - - assign csr3_field8_wd = reg_wdata[25:24]; - - assign csr3_field9_wd = reg_wdata[27:26]; - assign csr4_we = addr_hit[4] & reg_we & !reg_error; - - assign csr4_field0_wd = reg_wdata[2:0]; - - assign csr4_field1_wd = reg_wdata[5:3]; - - assign csr4_field2_wd = reg_wdata[8:6]; - - assign csr4_field3_wd = reg_wdata[11:9]; - assign csr5_we = addr_hit[5] & reg_we & !reg_error; - - assign csr5_field0_wd = reg_wdata[2:0]; - - assign csr5_field1_wd = reg_wdata[4:3]; - - assign csr5_field2_wd = reg_wdata[13:5]; - - assign csr5_field3_wd = reg_wdata[18:14]; - - assign csr5_field4_wd = reg_wdata[22:19]; - assign csr6_we = addr_hit[6] & reg_we & !reg_error; - - assign csr6_field0_wd = reg_wdata[2:0]; - - assign csr6_field1_wd = reg_wdata[5:3]; - - assign csr6_field2_wd = reg_wdata[13:6]; - - assign csr6_field3_wd = reg_wdata[16:14]; - - assign csr6_field4_wd = reg_wdata[18:17]; - - assign csr6_field5_wd = reg_wdata[20:19]; - - assign csr6_field6_wd = reg_wdata[22:21]; - - assign csr6_field7_wd = reg_wdata[23]; - - assign csr6_field8_wd = reg_wdata[24]; - assign csr7_we = addr_hit[7] & reg_we & !reg_error; - - assign csr7_field0_wd = reg_wdata[7:0]; - - assign csr7_field1_wd = reg_wdata[16:8]; - assign csr8_we = addr_hit[8] & reg_we & !reg_error; - - assign csr8_wd = reg_wdata[31:0]; - assign csr9_we = addr_hit[9] & reg_we & !reg_error; - - assign csr9_wd = reg_wdata[31:0]; - assign csr10_we = addr_hit[10] & reg_we & !reg_error; - - assign csr10_wd = reg_wdata[31:0]; - assign csr11_we = addr_hit[11] & reg_we & !reg_error; - - assign csr11_wd = reg_wdata[31:0]; - assign csr12_we = addr_hit[12] & reg_we & !reg_error; - - assign csr12_wd = reg_wdata[9:0]; - assign csr13_we = addr_hit[13] & reg_we & !reg_error; - - assign csr13_field0_wd = reg_wdata[19:0]; - - assign csr13_field1_wd = reg_wdata[20]; - assign csr14_we = addr_hit[14] & reg_we & !reg_error; - - assign csr14_field0_wd = reg_wdata[7:0]; - - assign csr14_field1_wd = reg_wdata[8]; - assign csr15_we = addr_hit[15] & reg_we & !reg_error; - - assign csr15_field0_wd = reg_wdata[7:0]; - - assign csr15_field1_wd = reg_wdata[8]; - assign csr16_we = addr_hit[16] & reg_we & !reg_error; - - assign csr16_field0_wd = reg_wdata[7:0]; - - assign csr16_field1_wd = reg_wdata[8]; - assign csr17_we = addr_hit[17] & reg_we & !reg_error; - - assign csr17_field0_wd = reg_wdata[7:0]; - - assign csr17_field1_wd = reg_wdata[8]; - assign csr18_we = addr_hit[18] & reg_we & !reg_error; - - assign csr18_wd = reg_wdata[0]; - assign csr19_we = addr_hit[19] & reg_we & !reg_error; - - assign csr19_wd = reg_wdata[0]; - assign csr20_we = addr_hit[20] & reg_we & !reg_error; - - assign csr20_field0_wd = reg_wdata[0]; - - assign csr20_field1_wd = reg_wdata[1]; - - // Assign write-enables to checker logic vector. - always_comb begin - reg_we_check[0] = csr0_regwen_we; - reg_we_check[1] = csr1_gated_we; - reg_we_check[2] = csr2_we; - reg_we_check[3] = csr3_gated_we; - reg_we_check[4] = csr4_gated_we; - reg_we_check[5] = csr5_gated_we; - reg_we_check[6] = csr6_gated_we; - reg_we_check[7] = csr7_gated_we; - reg_we_check[8] = csr8_gated_we; - reg_we_check[9] = csr9_gated_we; - reg_we_check[10] = csr10_gated_we; - reg_we_check[11] = csr11_gated_we; - reg_we_check[12] = csr12_gated_we; - reg_we_check[13] = csr13_gated_we; - reg_we_check[14] = csr14_gated_we; - reg_we_check[15] = csr15_gated_we; - reg_we_check[16] = csr16_gated_we; - reg_we_check[17] = csr17_gated_we; - reg_we_check[18] = csr18_gated_we; - reg_we_check[19] = csr19_gated_we; - reg_we_check[20] = csr20_we; - end - - // Read data return - always_comb begin - reg_rdata_next = '0; - unique case (1'b1) - addr_hit[0]: begin - reg_rdata_next[0] = csr0_regwen_qs; - end - - addr_hit[1]: begin - reg_rdata_next[7:0] = csr1_field0_qs; - reg_rdata_next[12:8] = csr1_field1_qs; - end - - addr_hit[2]: begin - reg_rdata_next[0] = csr2_field0_qs; - reg_rdata_next[1] = csr2_field1_qs; - reg_rdata_next[2] = csr2_field2_qs; - reg_rdata_next[3] = csr2_field3_qs; - reg_rdata_next[4] = csr2_field4_qs; - reg_rdata_next[5] = csr2_field5_qs; - reg_rdata_next[6] = csr2_field6_qs; - reg_rdata_next[7] = csr2_field7_qs; - end - - addr_hit[3]: begin - reg_rdata_next[3:0] = csr3_field0_qs; - reg_rdata_next[7:4] = csr3_field1_qs; - reg_rdata_next[10:8] = csr3_field2_qs; - reg_rdata_next[13:11] = csr3_field3_qs; - reg_rdata_next[16:14] = csr3_field4_qs; - reg_rdata_next[19:17] = csr3_field5_qs; - reg_rdata_next[20] = csr3_field6_qs; - reg_rdata_next[23:21] = csr3_field7_qs; - reg_rdata_next[25:24] = csr3_field8_qs; - reg_rdata_next[27:26] = csr3_field9_qs; - end - - addr_hit[4]: begin - reg_rdata_next[2:0] = csr4_field0_qs; - reg_rdata_next[5:3] = csr4_field1_qs; - reg_rdata_next[8:6] = csr4_field2_qs; - reg_rdata_next[11:9] = csr4_field3_qs; - end - - addr_hit[5]: begin - reg_rdata_next[2:0] = csr5_field0_qs; - reg_rdata_next[4:3] = csr5_field1_qs; - reg_rdata_next[13:5] = csr5_field2_qs; - reg_rdata_next[18:14] = csr5_field3_qs; - reg_rdata_next[22:19] = csr5_field4_qs; - end - - addr_hit[6]: begin - reg_rdata_next[2:0] = csr6_field0_qs; - reg_rdata_next[5:3] = csr6_field1_qs; - reg_rdata_next[13:6] = csr6_field2_qs; - reg_rdata_next[16:14] = csr6_field3_qs; - reg_rdata_next[18:17] = csr6_field4_qs; - reg_rdata_next[20:19] = csr6_field5_qs; - reg_rdata_next[22:21] = csr6_field6_qs; - reg_rdata_next[23] = csr6_field7_qs; - reg_rdata_next[24] = csr6_field8_qs; - end - - addr_hit[7]: begin - reg_rdata_next[7:0] = csr7_field0_qs; - reg_rdata_next[16:8] = csr7_field1_qs; - end - - addr_hit[8]: begin - reg_rdata_next[31:0] = csr8_qs; - end - - addr_hit[9]: begin - reg_rdata_next[31:0] = csr9_qs; - end - - addr_hit[10]: begin - reg_rdata_next[31:0] = csr10_qs; - end - - addr_hit[11]: begin - reg_rdata_next[31:0] = csr11_qs; - end - - addr_hit[12]: begin - reg_rdata_next[9:0] = csr12_qs; - end - - addr_hit[13]: begin - reg_rdata_next[19:0] = csr13_field0_qs; - reg_rdata_next[20] = csr13_field1_qs; - end - - addr_hit[14]: begin - reg_rdata_next[7:0] = csr14_field0_qs; - reg_rdata_next[8] = csr14_field1_qs; - end - - addr_hit[15]: begin - reg_rdata_next[7:0] = csr15_field0_qs; - reg_rdata_next[8] = csr15_field1_qs; - end - - addr_hit[16]: begin - reg_rdata_next[7:0] = csr16_field0_qs; - reg_rdata_next[8] = csr16_field1_qs; - end - - addr_hit[17]: begin - reg_rdata_next[7:0] = csr17_field0_qs; - reg_rdata_next[8] = csr17_field1_qs; - end - - addr_hit[18]: begin - reg_rdata_next[0] = csr18_qs; - end - - addr_hit[19]: begin - reg_rdata_next[0] = csr19_qs; - end - - addr_hit[20]: begin - reg_rdata_next[0] = csr20_field0_qs; - reg_rdata_next[1] = csr20_field1_qs; - reg_rdata_next[2] = csr20_field2_qs; - end - - default: begin - reg_rdata_next = '1; - end - endcase - end - - // shadow busy - logic shadow_busy; - assign shadow_busy = 1'b0; - - // register busy - assign reg_busy = shadow_busy; - - // Unused signal tieoff - - // wdata / byte enable are not always fully used - // add a blanket unused statement to handle lint waivers - logic unused_wdata; - logic unused_be; - assign unused_wdata = ^reg_wdata; - assign unused_be = ^reg_be; - - // Assertions for Register Interface - `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni) - `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni) - - `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o_pre.d_valid, clk_i, !rst_ni) - - `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni) - - // this is formulated as an assumption such that the FPV testbenches do disprove this - // property by mistake - //`ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.chk_en == tlul_pkg::CheckDis) - -endmodule diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv index 235bf9effaf..ee9c5a687f7 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_prog.sv @@ -1,11 +1,15 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // // Faux Flash Prog Control // -module flash_ctrl_prog import flash_ctrl_top_specific_pkg::*; ( +module flash_ctrl_prog + import flash_ctrl_pkg::*; + import flash_ctrl_top_specific_pkg::*; +( input clk_i, input rst_ni, diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv index ae3ab5e901a..4a943c945f1 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_reg_pkg.sv @@ -28,11 +28,9 @@ package flash_ctrl_reg_pkg; // Address widths within the block parameter int CoreAw = 9; - parameter int PrimAw = 7; // Number of registers for every interface parameter int NumRegsCore = 108; - parameter int NumRegsPrim = 21; // Alert indices typedef enum int { @@ -1166,387 +1164,4 @@ package flash_ctrl_reg_pkg; 4'b 0011 // index[107] FLASH_CTRL_CURR_FIFO_LVL }; - /////////////////////////////////////////////// - // Typedefs for registers for prim interface // - /////////////////////////////////////////////// - - typedef struct packed { - struct packed { - logic [4:0] q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr1_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field7; - struct packed { - logic q; - } field6; - struct packed { - logic q; - } field5; - struct packed { - logic q; - } field4; - struct packed { - logic q; - } field3; - struct packed { - logic q; - } field2; - struct packed { - logic q; - } field1; - struct packed { - logic q; - } field0; - } flash_ctrl_reg2hw_csr2_reg_t; - - typedef struct packed { - struct packed { - logic [1:0] q; - } field9; - struct packed { - logic [1:0] q; - } field8; - struct packed { - logic [2:0] q; - } field7; - struct packed { - logic q; - } field6; - struct packed { - logic [2:0] q; - } field5; - struct packed { - logic [2:0] q; - } field4; - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [2:0] q; - } field2; - struct packed { - logic [3:0] q; - } field1; - struct packed { - logic [3:0] q; - } field0; - } flash_ctrl_reg2hw_csr3_reg_t; - - typedef struct packed { - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [2:0] q; - } field2; - struct packed { - logic [2:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr4_reg_t; - - typedef struct packed { - struct packed { - logic [3:0] q; - } field4; - struct packed { - logic [4:0] q; - } field3; - struct packed { - logic [8:0] q; - } field2; - struct packed { - logic [1:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr5_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field8; - struct packed { - logic q; - } field7; - struct packed { - logic [1:0] q; - } field6; - struct packed { - logic [1:0] q; - } field5; - struct packed { - logic [1:0] q; - } field4; - struct packed { - logic [2:0] q; - } field3; - struct packed { - logic [7:0] q; - } field2; - struct packed { - logic [2:0] q; - } field1; - struct packed { - logic [2:0] q; - } field0; - } flash_ctrl_reg2hw_csr6_reg_t; - - typedef struct packed { - struct packed { - logic [8:0] q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr7_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr8_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr9_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr10_reg_t; - - typedef struct packed { - logic [31:0] q; - } flash_ctrl_reg2hw_csr11_reg_t; - - typedef struct packed { - logic [9:0] q; - } flash_ctrl_reg2hw_csr12_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [19:0] q; - } field0; - } flash_ctrl_reg2hw_csr13_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr14_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr15_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr16_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field1; - struct packed { - logic [7:0] q; - } field0; - } flash_ctrl_reg2hw_csr17_reg_t; - - typedef struct packed { - logic q; - } flash_ctrl_reg2hw_csr18_reg_t; - - typedef struct packed { - logic q; - } flash_ctrl_reg2hw_csr19_reg_t; - - typedef struct packed { - struct packed { - logic q; - } field2; - struct packed { - logic q; - } field1; - struct packed { - logic q; - } field0; - } flash_ctrl_reg2hw_csr20_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } field7; - struct packed { - logic d; - logic de; - } field6; - struct packed { - logic d; - logic de; - } field5; - struct packed { - logic d; - logic de; - } field4; - struct packed { - logic d; - logic de; - } field3; - struct packed { - logic d; - logic de; - } field2; - struct packed { - logic d; - logic de; - } field1; - struct packed { - logic d; - logic de; - } field0; - } flash_ctrl_hw2reg_csr2_reg_t; - - typedef struct packed { - struct packed { - logic d; - logic de; - } field2; - struct packed { - logic d; - logic de; - } field1; - struct packed { - logic d; - logic de; - } field0; - } flash_ctrl_hw2reg_csr20_reg_t; - - // Register -> HW type for prim interface - typedef struct packed { - flash_ctrl_reg2hw_csr1_reg_t csr1; // [325:313] - flash_ctrl_reg2hw_csr2_reg_t csr2; // [312:305] - flash_ctrl_reg2hw_csr3_reg_t csr3; // [304:277] - flash_ctrl_reg2hw_csr4_reg_t csr4; // [276:265] - flash_ctrl_reg2hw_csr5_reg_t csr5; // [264:242] - flash_ctrl_reg2hw_csr6_reg_t csr6; // [241:217] - flash_ctrl_reg2hw_csr7_reg_t csr7; // [216:200] - flash_ctrl_reg2hw_csr8_reg_t csr8; // [199:168] - flash_ctrl_reg2hw_csr9_reg_t csr9; // [167:136] - flash_ctrl_reg2hw_csr10_reg_t csr10; // [135:104] - flash_ctrl_reg2hw_csr11_reg_t csr11; // [103:72] - flash_ctrl_reg2hw_csr12_reg_t csr12; // [71:62] - flash_ctrl_reg2hw_csr13_reg_t csr13; // [61:41] - flash_ctrl_reg2hw_csr14_reg_t csr14; // [40:32] - flash_ctrl_reg2hw_csr15_reg_t csr15; // [31:23] - flash_ctrl_reg2hw_csr16_reg_t csr16; // [22:14] - flash_ctrl_reg2hw_csr17_reg_t csr17; // [13:5] - flash_ctrl_reg2hw_csr18_reg_t csr18; // [4:4] - flash_ctrl_reg2hw_csr19_reg_t csr19; // [3:3] - flash_ctrl_reg2hw_csr20_reg_t csr20; // [2:0] - } flash_ctrl_prim_reg2hw_t; - - // HW -> register type for prim interface - typedef struct packed { - flash_ctrl_hw2reg_csr2_reg_t csr2; // [21:6] - flash_ctrl_hw2reg_csr20_reg_t csr20; // [5:0] - } flash_ctrl_prim_hw2reg_t; - - // Register offsets for prim interface - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR0_REGWEN_OFFSET = 7'h 0; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR1_OFFSET = 7'h 4; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR2_OFFSET = 7'h 8; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR3_OFFSET = 7'h c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR4_OFFSET = 7'h 10; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR5_OFFSET = 7'h 14; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR6_OFFSET = 7'h 18; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR7_OFFSET = 7'h 1c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR8_OFFSET = 7'h 20; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR9_OFFSET = 7'h 24; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR10_OFFSET = 7'h 28; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR11_OFFSET = 7'h 2c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR12_OFFSET = 7'h 30; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR13_OFFSET = 7'h 34; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR14_OFFSET = 7'h 38; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR15_OFFSET = 7'h 3c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR16_OFFSET = 7'h 40; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR17_OFFSET = 7'h 44; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR18_OFFSET = 7'h 48; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR19_OFFSET = 7'h 4c; - parameter logic [PrimAw-1:0] FLASH_CTRL_CSR20_OFFSET = 7'h 50; - - // Register index for prim interface - typedef enum int { - FLASH_CTRL_CSR0_REGWEN, - FLASH_CTRL_CSR1, - FLASH_CTRL_CSR2, - FLASH_CTRL_CSR3, - FLASH_CTRL_CSR4, - FLASH_CTRL_CSR5, - FLASH_CTRL_CSR6, - FLASH_CTRL_CSR7, - FLASH_CTRL_CSR8, - FLASH_CTRL_CSR9, - FLASH_CTRL_CSR10, - FLASH_CTRL_CSR11, - FLASH_CTRL_CSR12, - FLASH_CTRL_CSR13, - FLASH_CTRL_CSR14, - FLASH_CTRL_CSR15, - FLASH_CTRL_CSR16, - FLASH_CTRL_CSR17, - FLASH_CTRL_CSR18, - FLASH_CTRL_CSR19, - FLASH_CTRL_CSR20 - } flash_ctrl_prim_id_e; - - // Register width information to check illegal writes for prim interface - parameter logic [3:0] FLASH_CTRL_PRIM_PERMIT [21] = '{ - 4'b 0001, // index[ 0] FLASH_CTRL_CSR0_REGWEN - 4'b 0011, // index[ 1] FLASH_CTRL_CSR1 - 4'b 0001, // index[ 2] FLASH_CTRL_CSR2 - 4'b 1111, // index[ 3] FLASH_CTRL_CSR3 - 4'b 0011, // index[ 4] FLASH_CTRL_CSR4 - 4'b 0111, // index[ 5] FLASH_CTRL_CSR5 - 4'b 1111, // index[ 6] FLASH_CTRL_CSR6 - 4'b 0111, // index[ 7] FLASH_CTRL_CSR7 - 4'b 1111, // index[ 8] FLASH_CTRL_CSR8 - 4'b 1111, // index[ 9] FLASH_CTRL_CSR9 - 4'b 1111, // index[10] FLASH_CTRL_CSR10 - 4'b 1111, // index[11] FLASH_CTRL_CSR11 - 4'b 0011, // index[12] FLASH_CTRL_CSR12 - 4'b 0111, // index[13] FLASH_CTRL_CSR13 - 4'b 0011, // index[14] FLASH_CTRL_CSR14 - 4'b 0011, // index[15] FLASH_CTRL_CSR15 - 4'b 0011, // index[16] FLASH_CTRL_CSR16 - 4'b 0011, // index[17] FLASH_CTRL_CSR17 - 4'b 0001, // index[18] FLASH_CTRL_CSR18 - 4'b 0001, // index[19] FLASH_CTRL_CSR19 - 4'b 0001 // index[20] FLASH_CTRL_CSR20 - }; - endpackage diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv index ff1b882f816..8830332af03 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_ctrl_top_specific_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -14,7 +15,13 @@ package flash_ctrl_top_specific_pkg; export flash_ctrl_pkg::OwnerSeedIdx; export flash_ctrl_pkg::SeedWidth; export flash_ctrl_pkg::KeyWidth; + export flash_ctrl_pkg::FlashProgNormal; + export flash_ctrl_pkg::FlashProgRepair; export flash_ctrl_pkg::flash_key_t; + export flash_ctrl_pkg::FlashPartData; + export flash_ctrl_pkg::FlashPartInfo; + export flash_ctrl_pkg::flash_part_e; + export flash_ctrl_pkg::flash_prog_e; export flash_ctrl_pkg::keymgr_flash_t; // design parameters that can be altered through topgen @@ -328,13 +335,6 @@ package flash_ctrl_top_specific_pkg; FlashOpInvalid = 2'h3 } flash_op_e; - // Flash Program Operations Supported - typedef enum logic { - FlashProgNormal = 0, - FlashProgRepair = 1 - } flash_prog_e; - parameter int ProgTypes = 2; - // Flash Erase Operations Supported typedef enum logic { FlashErasePage = 0, @@ -354,12 +354,6 @@ package flash_ctrl_top_specific_pkg; ReadDir = 1'b1 } flash_flfo_dir_e; - // Flash partition type - typedef enum logic { - FlashPartData = 1'b0, - FlashPartInfo = 1'b1 - } flash_part_e; - // Flash controller to memory typedef struct packed { logic req; @@ -385,7 +379,6 @@ package flash_ctrl_top_specific_pkg; logic [KeyWidth-1:0] rand_data_key; logic alert_trig; logic alert_ack; - jtag_pkg::jtag_req_t jtag_req; prim_mubi_pkg::mubi4_t flash_disable; } flash_req_t; @@ -414,7 +407,6 @@ package flash_ctrl_top_specific_pkg; rand_data_key: '0, alert_trig: 1'b0, alert_ack: 1'b0, - jtag_req: '0, flash_disable: prim_mubi_pkg::MuBi4False }; @@ -427,10 +419,8 @@ package flash_ctrl_top_specific_pkg; logic rd_err; logic [BusFullWidth-1:0] rd_data; logic init_busy; - logic macro_err; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; - jtag_pkg::jtag_rsp_t jtag_rsp; logic prog_intg_err; logic storage_relbl_err; logic storage_intg_err; @@ -450,10 +440,8 @@ package flash_ctrl_top_specific_pkg; rd_err: '0, rd_data: '0, init_busy: 1'b0, - macro_err: 1'b0, ecc_single_err: '0, ecc_addr: '0, - jtag_rsp: '0, prog_intg_err: '0, storage_relbl_err: '0, storage_intg_err: '0, @@ -517,16 +505,6 @@ package flash_ctrl_top_specific_pkg; } }; - // dft_en jtag selection - typedef enum logic [2:0] { - FlashLcTckSel, - FlashLcTdiSel, - FlashLcTmsSel, - FlashLcTdoSel, - FlashBistSel, - FlashLcDftLast - } flash_lc_jtag_e; - // Error bit positioning typedef struct packed { logic invalid_op_err; diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy.sv index 8ae5f802e8f..88c6ae3633e 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -11,6 +12,7 @@ // correctly collecting the responses in order. module flash_phy + import flash_ctrl_pkg::ProgTypes; import flash_ctrl_top_specific_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -25,27 +27,14 @@ module flash_phy output logic host_req_done_o, output logic [BusFullWidth-1:0] host_rdata_o, output logic host_rderr_o, - input flash_req_t flash_ctrl_i, + input flash_req_t flash_ctrl_i, output flash_rsp_t flash_ctrl_o, - input tlul_pkg::tl_h2d_t tl_i, - output tlul_pkg::tl_d2h_t tl_o, - input mubi4_t scanmode_i, - input scan_en_i, - input scan_rst_ni, - input flash_power_ready_h_i, - input flash_power_down_h_i, - inout [1:0] flash_test_mode_a_io, - inout flash_test_voltage_h_io, - input mubi4_t flash_bist_enable_i, - input lc_ctrl_pkg::lc_tx_t lc_nvm_debug_en_i, - input ast_pkg::ast_obs_ctrl_t obs_ctrl_i, - output logic [7:0] fla_obs_o, - output logic fatal_prim_flash_alert_o, - output logic recov_prim_flash_alert_o + output flash_phy_macro_pkg::flash_phy_macro_req_t flash_macro_req_o, + input flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_macro_rsp_i, + input logic [ProgTypes-1:0] prog_type_avail_i, + input logic init_busy_i ); - import prim_mubi_pkg::MuBi4False; - // Flash macro outstanding refers to how many reads we allow a macro to move ahead of an // in order blocking read. Since the data cannot be returned out of order, this simply // does the reads in advance and store them in a FIFO @@ -86,8 +75,6 @@ module flash_phy logic [NumBanks-1:0] rd_done; logic [NumBanks-1:0] prog_done; logic [NumBanks-1:0] erase_done; - logic init_busy; - logic [ProgTypes-1:0] prog_type_avail; // common interface logic [BusFullWidth-1:0] rd_data_host [NumBanks]; @@ -130,13 +117,13 @@ module flash_phy assign host_rdata_o = host_rsp_data[rsp_bank_sel]; // all banks are assumed to be the same in terms of prog_type support - assign flash_ctrl_o.prog_type_avail = prog_type_avail; + assign flash_ctrl_o.prog_type_avail = prog_type_avail_i; assign flash_ctrl_o.rd_done = rd_done[ctrl_bank_sel]; assign flash_ctrl_o.prog_done = prog_done[ctrl_bank_sel]; assign flash_ctrl_o.erase_done = erase_done[ctrl_bank_sel]; assign flash_ctrl_o.rd_data = rd_data_ctrl[ctrl_bank_sel]; assign flash_ctrl_o.rd_err = rd_err[ctrl_bank_sel]; - assign flash_ctrl_o.init_busy = init_busy; + assign flash_ctrl_o.init_busy = init_busy_i; assign flash_ctrl_o.prog_intg_err = |prog_intg_err; assign flash_ctrl_o.storage_relbl_err = |relbl_ecc_err; assign flash_ctrl_o.storage_intg_err = |intg_ecc_err; @@ -202,10 +189,8 @@ module flash_phy assign host_ecc_en = mubi4_test_true_strict(mubi4_and_hi(region_cfg.ecc_en, region_cfg.en)); // Prim flash to flash_phy_core connections - flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; - flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; - flash_phy_pkg::flash_phy_prim_flash_req_t [NumBanks-1:0] prim_flash_req; - flash_phy_pkg::flash_phy_prim_flash_rsp_t [NumBanks-1:0] prim_flash_rsp; + flash_phy_pkg::scramble_req_t [NumBanks-1:0] scramble_req; + flash_phy_pkg::scramble_rsp_t [NumBanks-1:0] scramble_rsp; logic [NumBanks-1:0] ecc_single_err; logic [NumBanks-1:0][BusAddrW-1:0] ecc_addr; @@ -294,8 +279,8 @@ module flash_phy .flash_disable_i(flash_disable[bank]), .scramble_req_o(scramble_req[bank]), .scramble_rsp_i(scramble_rsp[bank]), - .prim_flash_req_o(prim_flash_req[bank]), - .prim_flash_rsp_i(prim_flash_rsp[bank]), + .flash_macro_req_o(flash_macro_req_o.bank_reqs[bank]), + .flash_macro_rsp_i(flash_macro_rsp_i.bank_rsps[bank]), .ecc_single_err_o(ecc_single_err[bank]), .ecc_addr_o(ecc_addr[bank][BusBankAddrW-1:0]), .fsm_err_o(fsm_err[bank]), @@ -328,72 +313,9 @@ module flash_phy .arb_err_o(scramble_arb_err) // fatal error from redundant arbiter logic ); - // life cycle handling - logic tdo; - lc_ctrl_pkg::lc_tx_t [FlashLcDftLast-1:0] lc_nvm_debug_en; - - assign flash_ctrl_o.jtag_rsp.tdo = tdo & - lc_ctrl_pkg::lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdoSel]); - - prim_lc_sync #( - .NumCopies(int'(FlashLcDftLast)) - ) u_lc_nvm_debug_en_sync ( - .clk_i, - .rst_ni, - .lc_en_i(lc_nvm_debug_en_i), - .lc_en_o(lc_nvm_debug_en) - ); - - import lc_ctrl_pkg::lc_tx_test_true_strict; - // if nvm debug is enabled, flash_bist_enable controls entry to flash test mode. - // if nvm debug is disabled, flash_bist_enable is always turned off. - mubi4_t bist_enable_qual; - assign bist_enable_qual = (lc_tx_test_true_strict(lc_nvm_debug_en[FlashBistSel])) ? - flash_bist_enable_i : - MuBi4False; - - prim_flash #( - .NumBanks(NumBanks), - .InfosPerBank(InfosPerBank), - .InfoTypes(InfoTypes), - .InfoTypesWidth(InfoTypesWidth), - .PagesPerBank(PagesPerBank), - .WordsPerPage(WordsPerPage), - .DataWidth(flash_phy_pkg::FullDataWidth) - ) u_flash ( - .clk_i, - .rst_ni, - .tl_i, - .tl_o, - .flash_req_i(prim_flash_req), - .flash_rsp_o(prim_flash_rsp), - .prog_type_avail_o(prog_type_avail), - .init_busy_o(init_busy), - .tck_i(flash_ctrl_i.jtag_req.tck & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTckSel])), - .tdi_i(flash_ctrl_i.jtag_req.tdi & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTdiSel])), - .tms_i(flash_ctrl_i.jtag_req.tms & lc_tx_test_true_strict(lc_nvm_debug_en[FlashLcTmsSel])), - .tdo_o(tdo), - .bist_enable_i(bist_enable_qual), - .obs_ctrl_i, - .fla_obs_o, - .scanmode_i, - .scan_en_i, - .scan_rst_ni, - .flash_power_ready_h_i, - .flash_power_down_h_i, - .flash_test_mode_a_io, - .flash_test_voltage_h_io, - .flash_err_o(flash_ctrl_o.macro_err), - .fatal_alert_o(fatal_prim_flash_alert_o), - .recov_alert_o(recov_prim_flash_alert_o) - ); logic unused_alert; assign unused_alert = flash_ctrl_i.alert_trig & flash_ctrl_i.alert_ack; - logic unused_trst_n; - assign unused_trst_n = flash_ctrl_i.jtag_req.trst_n; - assign flash_ctrl_o.jtag_rsp.tdo_oe = 1'b1; - ////////////////////////////////////////////// // Assertions, Assumptions, and Coverpoints // ///////////////////////////////////////////// diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv index 576c10780fa..bc91b0f78ac 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_core.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -9,6 +10,8 @@ // scramble, ECC, security and arbitration logic. module flash_phy_core + import flash_phy_macro_pkg::flash_phy_macro_bank_req_t; + import flash_phy_macro_pkg::flash_phy_macro_bank_rsp_t; import flash_phy_pkg::*; import prim_mubi_pkg::mubi4_t; #( @@ -39,8 +42,8 @@ module flash_phy_core input prim_mubi_pkg::mubi4_t flash_disable_i, output scramble_req_t scramble_req_o, input scramble_rsp_t scramble_rsp_i, - input flash_phy_prim_flash_rsp_t prim_flash_rsp_i, - output flash_phy_prim_flash_req_t prim_flash_req_o, + input flash_phy_macro_bank_rsp_t flash_macro_rsp_i, + output flash_phy_macro_bank_req_t flash_macro_req_o, output logic host_req_rdy_o, output logic host_req_done_o, output logic rd_done_o, @@ -566,7 +569,7 @@ module flash_phy_core //////////////////////// // Connections to the actual flash macro wrapper - assign prim_flash_req_o = '{ + assign flash_macro_req_o = '{ rd_req: flash_rd_req, prog_req: flash_prog_req, prog_last: prog_last, @@ -583,9 +586,9 @@ module flash_phy_core prog_full_data: prog_full_data }; - assign ack = prim_flash_rsp_i.ack; - assign done = prim_flash_rsp_i.done; - assign flash_rdata = prim_flash_rsp_i.rdata; + assign ack = flash_macro_rsp_i.ack; + assign done = flash_macro_rsp_i.done; + assign flash_rdata = flash_macro_rsp_i.rdata; ///////////////////////////////// // Assertions diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv new file mode 100644 index 00000000000..525a6179743 --- /dev/null +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_macro_pkg.sv @@ -0,0 +1,70 @@ +// Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Flash phy macro package +// This has the interface to the flash macro wrapper. It is top-specific, +// but all dependencies are via macro wrapper overridden parameters, so +// it is okay for the flash macro wrapper to depend on this package. + +package flash_phy_macro_pkg; + + import flash_ctrl_pkg::ProgTypes; + + parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; + parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; + parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; + parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; + parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; + parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; + parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth + + flash_ctrl_top_specific_pkg::MetaDataWidth; + parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; + parameter int TestModeWidth = 2; + + // Transaction request to flash macro + typedef struct packed { + logic rd_req; + logic prog_req; + logic prog_last; + flash_ctrl_pkg::flash_prog_e prog_type; + logic pg_erase_req; + logic bk_erase_req; + logic erase_suspend_req; + logic he; + logic [BankAddrW-1:0] addr; + flash_ctrl_pkg::flash_part_e part; + logic [InfoTypesWidth-1:0] info_sel; + logic [DataWidth-1:0] prog_full_data; + } flash_phy_macro_bank_req_t; + + typedef struct packed { + flash_phy_macro_bank_req_t [NumBanks-1:0] bank_reqs; + } flash_phy_macro_req_t; + + // Transaction response from flash macro + typedef struct packed { + logic ack; + logic done; + logic [DataWidth-1:0] rdata; + } flash_phy_macro_bank_rsp_t; + + typedef struct packed { + flash_phy_macro_bank_rsp_t [NumBanks-1:0] bank_rsps; + } flash_phy_macro_rsp_t; + + // Status of flash macro + typedef struct packed { + // What program types flash macro supports + logic [ProgTypes-1:0] prog_type_avail; + // Asserted while flash is getting initialized + logic init_busy; + // Macro error + logic flash_err; + // Alert indications for the phy to connect to alert sender + logic fatal_alert; + logic recov_alert; + } flash_macro_status_t; + +endpackage : flash_phy_macro_pkg diff --git a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv index a96f558fba3..3cb5cc6befd 100644 --- a/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/flash_ctrl/rtl/flash_phy_pkg.sv @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 // @@ -7,15 +8,26 @@ package flash_phy_pkg; + import flash_phy_macro_pkg::NumBanks; + import flash_phy_macro_pkg::InfosPerBank; + import flash_phy_macro_pkg::InfoTypes; + import flash_phy_macro_pkg::InfoTypesWidth; + import flash_phy_macro_pkg::PagesPerBank; + import flash_phy_macro_pkg::WordsPerPage; + import flash_phy_macro_pkg::BankAddrW; + + export flash_phy_macro_pkg::NumBanks; + export flash_phy_macro_pkg::InfosPerBank; + export flash_phy_macro_pkg::InfoTypes; + export flash_phy_macro_pkg::InfoTypesWidth; + export flash_phy_macro_pkg::PagesPerBank; + export flash_phy_macro_pkg::WordsPerPage; + export flash_phy_macro_pkg::BankAddrW; + // flash phy parameters - parameter int unsigned NumBanks = flash_ctrl_top_specific_pkg::NumBanks; - parameter int unsigned InfosPerBank = flash_ctrl_top_specific_pkg::InfosPerBank; - parameter int unsigned PagesPerBank = flash_ctrl_top_specific_pkg::PagesPerBank; - parameter int unsigned WordsPerPage = flash_ctrl_top_specific_pkg::WordsPerPage; parameter int unsigned BankW = flash_ctrl_top_specific_pkg::BankW; parameter int unsigned PageW = flash_ctrl_top_specific_pkg::PageW; parameter int unsigned WordW = flash_ctrl_top_specific_pkg::WordW; - parameter int unsigned BankAddrW = flash_ctrl_top_specific_pkg::BankAddrW; parameter int unsigned DataWidth = flash_ctrl_top_specific_pkg::DataWidth; parameter int unsigned EccWidth = 8; parameter int unsigned MetaDataWidth = flash_ctrl_top_specific_pkg::MetaDataWidth; @@ -25,17 +37,13 @@ package flash_phy_pkg; // will switch to this after bus widening parameter int unsigned PlainIntgWidth = MetaDataWidth - EccWidth; parameter int unsigned PlainDataWidth = DataWidth + PlainIntgWidth; - //parameter int unsigned ScrDataWidth = DataWidth + EccWidth; parameter int unsigned FullDataWidth = DataWidth + MetaDataWidth; - parameter int unsigned InfoTypes = flash_ctrl_top_specific_pkg::InfoTypes; - parameter int unsigned InfoTypesWidth = flash_ctrl_top_specific_pkg::InfoTypesWidth; // flash ctrl / bus parameters parameter int unsigned BusWidth = flash_ctrl_top_specific_pkg::BusWidth; parameter int unsigned BusFullWidth = flash_ctrl_top_specific_pkg::BusFullWidth; parameter int unsigned BusBankAddrW = flash_ctrl_top_specific_pkg::BusBankAddrW; parameter int unsigned BusWordW = flash_ctrl_top_specific_pkg::BusWordW; - parameter int unsigned ProgTypes = flash_ctrl_top_specific_pkg::ProgTypes; // address bits remain must be 0 parameter int unsigned AddrBitsRemain = DataWidth % BusWidth; @@ -114,28 +122,6 @@ package flash_phy_pkg; DeScrambleOp = 1'b1 } cipher_ops_e; - // Connections to prim_flash - typedef struct packed { - logic rd_req; - logic prog_req; - logic prog_last; - flash_ctrl_top_specific_pkg::flash_prog_e prog_type; - logic pg_erase_req; - logic bk_erase_req; - logic erase_suspend_req; - logic he; - logic [BankAddrW-1:0] addr; - flash_ctrl_top_specific_pkg::flash_part_e part; - logic [InfoTypesWidth-1:0] info_sel; - logic [FullDataWidth-1:0] prog_full_data; - } flash_phy_prim_flash_req_t; - - typedef struct packed { - logic ack; - logic done; - logic [FullDataWidth-1:0] rdata; - } flash_phy_prim_flash_rsp_t; - typedef struct packed { logic calc_req; logic op_req; @@ -153,4 +139,4 @@ package flash_phy_pkg; logic [DataWidth-1:0] scrambled_data; } scramble_rsp_t; -endpackage // flash_phy_pkg +endpackage : flash_phy_pkg diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/data/pinmux.hjson b/hw/top_englishbreakfast/ip_autogen/pinmux/data/pinmux.hjson index 93069ea18de..6954908a2a5 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/data/pinmux.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/data/pinmux.hjson @@ -349,13 +349,13 @@ { name: "NMioPeriphIn", desc: "Number of muxed peripheral inputs", type: "int", - default: "38", + default: "35", local: "true" }, { name: "NMioPeriphOut", desc: "Number of muxed peripheral outputs", type: "int", - default: "35", + default: "34", local: "true" }, { name: "NMioPads", diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson b/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson index 1e9919110ce..9c878de6695 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/data/top_englishbreakfast_pinmux.ipconfig.hjson @@ -8,8 +8,8 @@ n_wkup_detect: 8 wkup_cnt_width: 8 n_mio_pads: 47 - n_mio_periph_in: 38 - n_mio_periph_out: 35 + n_mio_periph_in: 35 + n_mio_periph_out: 34 n_dio_pads: 14 n_dio_periph_in: 12 n_dio_periph_out: 12 diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/doc/pinout_cw305.md b/hw/top_englishbreakfast/ip_autogen/pinmux/doc/pinout_cw305.md index 2f753506fc9..048c11f5b21 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/doc/pinout_cw305.md +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/doc/pinout_cw305.md @@ -96,12 +96,8 @@ util/topgen.py -t hw/top_englishbreakfast/data/top_englishbreakfast.hjson -o hw/ |

spi_device_csb

|

direct

|

SPI_DEV_CS_L

|

- / -

|

| |

uart0_rx

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInUart0Rx

|

| |

uart1_rx

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInUart1Rx

|

| -|

flash_ctrl_tck

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTck

|

| -|

flash_ctrl_tms

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTms

|

| -|

flash_ctrl_tdi

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTdi

|

| |

usbdev_sense

|

muxed

|

-

|

- / kTopEnglishbreakfastPinmuxPeripheralInUsbdevSense

|

| |

spi_host0_sck

|

direct

|

SPI_HOST_CLK

|

- / -

|

| |

spi_host0_csb

|

direct

|

SPI_HOST_CS_L

|

- / -

|

| |

uart0_tx

|

muxed

|

-

|

kTopEnglishbreakfastPinmuxOutselUart0Tx / -

|

| |

uart1_tx

|

muxed

|

-

|

kTopEnglishbreakfastPinmuxOutselUart1Tx / -

|

| -|

flash_ctrl_tdo

|

muxed

|

-

|

kTopEnglishbreakfastPinmuxOutselFlashCtrlTdo / -

|

| diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/doc/registers.md b/hw/top_englishbreakfast/ip_autogen/pinmux/doc/registers.md index 4bafc92883e..3dbbc6ddd95 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/doc/registers.md +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/doc/registers.md @@ -41,490 +41,484 @@ | pinmux.[`MIO_PERIPH_INSEL_REGWEN_32`](#mio_periph_insel_regwen) | 0x84 | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_33`](#mio_periph_insel_regwen) | 0x88 | 4 | Register write enable for MIO peripheral input selects. | | pinmux.[`MIO_PERIPH_INSEL_REGWEN_34`](#mio_periph_insel_regwen) | 0x8c | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_35`](#mio_periph_insel_regwen) | 0x90 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_36`](#mio_periph_insel_regwen) | 0x94 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_REGWEN_37`](#mio_periph_insel_regwen) | 0x98 | 4 | Register write enable for MIO peripheral input selects. | -| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0x9c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0xa0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0xa4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0xa8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0xac | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0xb0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0xb4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0xb8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0xbc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0xc0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0xc4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0xc8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0xcc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0xd0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0xd4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0xd8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0xdc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0xe0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0xe4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0xe8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0xec | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x11c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x120 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x124 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_35`](#mio_periph_insel) | 0x128 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_36`](#mio_periph_insel) | 0x12c | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_PERIPH_INSEL_37`](#mio_periph_insel) | 0x130 | 4 | For each peripheral input, this selects the muxable pad input. | -| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x134 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x138 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x13c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x140 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x144 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x148 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x14c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x150 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x154 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x158 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x15c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x160 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x164 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x168 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x16c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x170 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x174 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x178 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x17c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x180 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x184 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x188 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x18c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x190 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x194 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x198 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x19c | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x1a0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x1a4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x1a8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x1ac | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x1b0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x1b4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x1b8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x1bc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x1c0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x1c4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x1c8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x1cc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x1d0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x1d4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x1d8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x1dc | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x1e0 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x1e4 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x1e8 | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x1ec | 4 | Register write enable for MIO output selects. | -| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x1f0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x1f4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x1f8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x1fc | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x200 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x204 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x208 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x20c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x210 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x214 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x218 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x21c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x220 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x224 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x228 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x22c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x230 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x234 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x238 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x23c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x240 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x244 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x248 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x24c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x250 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x254 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x258 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x25c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x260 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x264 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x268 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x26c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x270 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x274 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x278 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x27c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x280 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x284 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x288 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x28c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x290 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x294 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x298 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x29c | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x2a0 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x2a4 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x2a8 | 4 | For each muxable pad, this selects the peripheral output. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x2ac | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x2b0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x2b4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x2b8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x2bc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x2c0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x2c4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x2c8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x2cc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x2d0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x2d4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x2d8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x2dc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x2e0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x2e4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x2e8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x2ec | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x2f0 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x2f4 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x2f8 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x2fc | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x300 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x304 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x308 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x30c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x310 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x314 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x318 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x31c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x320 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x324 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x328 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x32c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x330 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x334 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x338 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x33c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x340 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x344 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x348 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x34c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x350 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x354 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x358 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x35c | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x360 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x364 | 4 | Register write enable for MIO PAD attributes. | -| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x368 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x36c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x370 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x374 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x378 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x37c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x380 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x384 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x388 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x38c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x390 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x394 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x398 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x39c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x3a0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x3a4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x3a8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x3ac | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x3b0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x3b4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x3b8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x3bc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x3c0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x3c4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x3c8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x3cc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x3d0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x3d4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x3d8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x3dc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x3e0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x3e4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x3e8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x3ec | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x3f0 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x3f4 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x3f8 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x3fc | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x400 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x404 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x408 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x40c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x410 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x414 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x418 | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x41c | 4 | Muxed pad attributes. | -| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x420 | 4 | Muxed pad attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x424 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x428 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x42c | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x430 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x434 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x438 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x43c | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x440 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x444 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x448 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x44c | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x450 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x454 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x458 | 4 | Register write enable for DIO PAD attributes. | -| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x45c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x460 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x464 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x468 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x46c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x470 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x474 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x478 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x47c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x480 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x484 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x488 | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x48c | 4 | Dedicated pad attributes. | -| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x490 | 4 | Dedicated pad attributes. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x494 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x498 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x49c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x4a0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x4a4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x4a8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x4ac | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x4b0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x4b4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x4b8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x4bc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x4c0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x4c4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x4c8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x4cc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x4d0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x4d4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x4d8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x4dc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x4e0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x4e4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x4e8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x4ec | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x4f0 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x4f4 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x4f8 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x4fc | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x500 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x504 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x508 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x50c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x510 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x514 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x518 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x51c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x520 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x524 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x528 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x52c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x530 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x534 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x538 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x53c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x540 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x544 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x548 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x54c | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x550 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x554 | 4 | Register write enable for MIO sleep value configuration. | -| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x558 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x55c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x560 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x564 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x568 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x56c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x570 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x574 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x578 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x57c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x580 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x584 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x588 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x58c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x590 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x594 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x598 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x59c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x5a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x5a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x5a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x5ac | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x5b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x5b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x5b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x5bc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x5c0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x5c4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x5c8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x5cc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x5d0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x5d4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x5d8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x5dc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x5e0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x5e4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x5e8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x5ec | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x5f0 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x5f4 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x5f8 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x5fc | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x600 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x604 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x608 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x60c | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x610 | 4 | Enables the sleep mode of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x614 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x618 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x61c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x620 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x624 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x628 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x62c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x630 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x634 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x638 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x63c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x640 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x644 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x648 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x64c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x650 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x654 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x658 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x65c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x660 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x664 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x668 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x66c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x670 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x674 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x678 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x67c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x680 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x684 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x688 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x68c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x690 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x694 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x698 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x69c | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x6a0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x6a4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x6a8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x6ac | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x6b0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x6b4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x6b8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x6bc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x6c0 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x6c4 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x6c8 | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x6cc | 4 | Defines sleep behavior of the corresponding muxed pad. | -| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x6d0 | 4 | Register indicating whether the corresponding pad is in sleep mode. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x6d4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x6d8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x6dc | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x6e0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x6e4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x6e8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x6ec | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x6f0 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x6f4 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x6f8 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x6fc | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x700 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x704 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x708 | 4 | Register write enable for DIO sleep value configuration. | -| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x70c | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x710 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x714 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x718 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x71c | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x720 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x724 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x728 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x72c | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x730 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x734 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x738 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x73c | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x740 | 4 | Enables the sleep mode of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x764 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x768 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x76c | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x770 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x774 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x778 | 4 | Defines sleep behavior of the corresponding dedicated pad. | -| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x77c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x780 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x784 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x788 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x78c | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x790 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x794 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x798 | 4 | Register write enable for wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x79c | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x7a0 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x7a4 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x7a8 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x7ac | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x7b0 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x7b4 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x7b8 | 4 | Enables for the wakeup detectors. | -| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x7bc | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x7c0 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x7c4 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x7c8 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x7cc | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x7d0 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x7d4 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x7d8 | 4 | Configuration of wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x7dc | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x7e0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x7e4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x7e8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x7ec | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x7f0 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x7f4 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x7f8 | 4 | Counter thresholds for wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x7fc | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x800 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x804 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x808 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x80c | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x810 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x814 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x818 | 4 | Pad selects for pad wakeup condition detectors. | -| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x81c | 4 | Cause registers for wakeup detectors. | +| pinmux.[`MIO_PERIPH_INSEL_0`](#mio_periph_insel) | 0x90 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_1`](#mio_periph_insel) | 0x94 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_2`](#mio_periph_insel) | 0x98 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_3`](#mio_periph_insel) | 0x9c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_4`](#mio_periph_insel) | 0xa0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_5`](#mio_periph_insel) | 0xa4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_6`](#mio_periph_insel) | 0xa8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_7`](#mio_periph_insel) | 0xac | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_8`](#mio_periph_insel) | 0xb0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_9`](#mio_periph_insel) | 0xb4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_10`](#mio_periph_insel) | 0xb8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_11`](#mio_periph_insel) | 0xbc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_12`](#mio_periph_insel) | 0xc0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_13`](#mio_periph_insel) | 0xc4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_14`](#mio_periph_insel) | 0xc8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_15`](#mio_periph_insel) | 0xcc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_16`](#mio_periph_insel) | 0xd0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_17`](#mio_periph_insel) | 0xd4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_18`](#mio_periph_insel) | 0xd8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_19`](#mio_periph_insel) | 0xdc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_20`](#mio_periph_insel) | 0xe0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_21`](#mio_periph_insel) | 0xe4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_22`](#mio_periph_insel) | 0xe8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_23`](#mio_periph_insel) | 0xec | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_24`](#mio_periph_insel) | 0xf0 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_25`](#mio_periph_insel) | 0xf4 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_26`](#mio_periph_insel) | 0xf8 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_27`](#mio_periph_insel) | 0xfc | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_28`](#mio_periph_insel) | 0x100 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_29`](#mio_periph_insel) | 0x104 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_30`](#mio_periph_insel) | 0x108 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_31`](#mio_periph_insel) | 0x10c | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_32`](#mio_periph_insel) | 0x110 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_33`](#mio_periph_insel) | 0x114 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_PERIPH_INSEL_34`](#mio_periph_insel) | 0x118 | 4 | For each peripheral input, this selects the muxable pad input. | +| pinmux.[`MIO_OUTSEL_REGWEN_0`](#mio_outsel_regwen) | 0x11c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_1`](#mio_outsel_regwen) | 0x120 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_2`](#mio_outsel_regwen) | 0x124 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_3`](#mio_outsel_regwen) | 0x128 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_4`](#mio_outsel_regwen) | 0x12c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_5`](#mio_outsel_regwen) | 0x130 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_6`](#mio_outsel_regwen) | 0x134 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_7`](#mio_outsel_regwen) | 0x138 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_8`](#mio_outsel_regwen) | 0x13c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_9`](#mio_outsel_regwen) | 0x140 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_10`](#mio_outsel_regwen) | 0x144 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_11`](#mio_outsel_regwen) | 0x148 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_12`](#mio_outsel_regwen) | 0x14c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_13`](#mio_outsel_regwen) | 0x150 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_14`](#mio_outsel_regwen) | 0x154 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_15`](#mio_outsel_regwen) | 0x158 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_16`](#mio_outsel_regwen) | 0x15c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_17`](#mio_outsel_regwen) | 0x160 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_18`](#mio_outsel_regwen) | 0x164 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_19`](#mio_outsel_regwen) | 0x168 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_20`](#mio_outsel_regwen) | 0x16c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_21`](#mio_outsel_regwen) | 0x170 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_22`](#mio_outsel_regwen) | 0x174 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_23`](#mio_outsel_regwen) | 0x178 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_24`](#mio_outsel_regwen) | 0x17c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_25`](#mio_outsel_regwen) | 0x180 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_26`](#mio_outsel_regwen) | 0x184 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_27`](#mio_outsel_regwen) | 0x188 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_28`](#mio_outsel_regwen) | 0x18c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_29`](#mio_outsel_regwen) | 0x190 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_30`](#mio_outsel_regwen) | 0x194 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_31`](#mio_outsel_regwen) | 0x198 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_32`](#mio_outsel_regwen) | 0x19c | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_33`](#mio_outsel_regwen) | 0x1a0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_34`](#mio_outsel_regwen) | 0x1a4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_35`](#mio_outsel_regwen) | 0x1a8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_36`](#mio_outsel_regwen) | 0x1ac | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_37`](#mio_outsel_regwen) | 0x1b0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_38`](#mio_outsel_regwen) | 0x1b4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_39`](#mio_outsel_regwen) | 0x1b8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_40`](#mio_outsel_regwen) | 0x1bc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_41`](#mio_outsel_regwen) | 0x1c0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_42`](#mio_outsel_regwen) | 0x1c4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_43`](#mio_outsel_regwen) | 0x1c8 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_44`](#mio_outsel_regwen) | 0x1cc | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_45`](#mio_outsel_regwen) | 0x1d0 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_REGWEN_46`](#mio_outsel_regwen) | 0x1d4 | 4 | Register write enable for MIO output selects. | +| pinmux.[`MIO_OUTSEL_0`](#mio_outsel) | 0x1d8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_1`](#mio_outsel) | 0x1dc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_2`](#mio_outsel) | 0x1e0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_3`](#mio_outsel) | 0x1e4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_4`](#mio_outsel) | 0x1e8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_5`](#mio_outsel) | 0x1ec | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_6`](#mio_outsel) | 0x1f0 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_7`](#mio_outsel) | 0x1f4 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_8`](#mio_outsel) | 0x1f8 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_9`](#mio_outsel) | 0x1fc | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_10`](#mio_outsel) | 0x200 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_11`](#mio_outsel) | 0x204 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_12`](#mio_outsel) | 0x208 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_13`](#mio_outsel) | 0x20c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_14`](#mio_outsel) | 0x210 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_15`](#mio_outsel) | 0x214 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_16`](#mio_outsel) | 0x218 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_17`](#mio_outsel) | 0x21c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_18`](#mio_outsel) | 0x220 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_19`](#mio_outsel) | 0x224 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_20`](#mio_outsel) | 0x228 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_21`](#mio_outsel) | 0x22c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_22`](#mio_outsel) | 0x230 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_23`](#mio_outsel) | 0x234 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_24`](#mio_outsel) | 0x238 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_25`](#mio_outsel) | 0x23c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_26`](#mio_outsel) | 0x240 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_27`](#mio_outsel) | 0x244 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_28`](#mio_outsel) | 0x248 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_29`](#mio_outsel) | 0x24c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_30`](#mio_outsel) | 0x250 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_31`](#mio_outsel) | 0x254 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_32`](#mio_outsel) | 0x258 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_33`](#mio_outsel) | 0x25c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_34`](#mio_outsel) | 0x260 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_35`](#mio_outsel) | 0x264 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_36`](#mio_outsel) | 0x268 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_37`](#mio_outsel) | 0x26c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_38`](#mio_outsel) | 0x270 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_39`](#mio_outsel) | 0x274 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_40`](#mio_outsel) | 0x278 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_41`](#mio_outsel) | 0x27c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_42`](#mio_outsel) | 0x280 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_43`](#mio_outsel) | 0x284 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_44`](#mio_outsel) | 0x288 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_45`](#mio_outsel) | 0x28c | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_OUTSEL_46`](#mio_outsel) | 0x290 | 4 | For each muxable pad, this selects the peripheral output. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_0`](#mio_pad_attr_regwen) | 0x294 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_1`](#mio_pad_attr_regwen) | 0x298 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_2`](#mio_pad_attr_regwen) | 0x29c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_3`](#mio_pad_attr_regwen) | 0x2a0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_4`](#mio_pad_attr_regwen) | 0x2a4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_5`](#mio_pad_attr_regwen) | 0x2a8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_6`](#mio_pad_attr_regwen) | 0x2ac | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_7`](#mio_pad_attr_regwen) | 0x2b0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_8`](#mio_pad_attr_regwen) | 0x2b4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_9`](#mio_pad_attr_regwen) | 0x2b8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_10`](#mio_pad_attr_regwen) | 0x2bc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_11`](#mio_pad_attr_regwen) | 0x2c0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_12`](#mio_pad_attr_regwen) | 0x2c4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_13`](#mio_pad_attr_regwen) | 0x2c8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_14`](#mio_pad_attr_regwen) | 0x2cc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_15`](#mio_pad_attr_regwen) | 0x2d0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_16`](#mio_pad_attr_regwen) | 0x2d4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_17`](#mio_pad_attr_regwen) | 0x2d8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_18`](#mio_pad_attr_regwen) | 0x2dc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_19`](#mio_pad_attr_regwen) | 0x2e0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_20`](#mio_pad_attr_regwen) | 0x2e4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_21`](#mio_pad_attr_regwen) | 0x2e8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_22`](#mio_pad_attr_regwen) | 0x2ec | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_23`](#mio_pad_attr_regwen) | 0x2f0 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_24`](#mio_pad_attr_regwen) | 0x2f4 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_25`](#mio_pad_attr_regwen) | 0x2f8 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_26`](#mio_pad_attr_regwen) | 0x2fc | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_27`](#mio_pad_attr_regwen) | 0x300 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_28`](#mio_pad_attr_regwen) | 0x304 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_29`](#mio_pad_attr_regwen) | 0x308 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_30`](#mio_pad_attr_regwen) | 0x30c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_31`](#mio_pad_attr_regwen) | 0x310 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_32`](#mio_pad_attr_regwen) | 0x314 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_33`](#mio_pad_attr_regwen) | 0x318 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_34`](#mio_pad_attr_regwen) | 0x31c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_35`](#mio_pad_attr_regwen) | 0x320 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_36`](#mio_pad_attr_regwen) | 0x324 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_37`](#mio_pad_attr_regwen) | 0x328 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_38`](#mio_pad_attr_regwen) | 0x32c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_39`](#mio_pad_attr_regwen) | 0x330 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_40`](#mio_pad_attr_regwen) | 0x334 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_41`](#mio_pad_attr_regwen) | 0x338 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_42`](#mio_pad_attr_regwen) | 0x33c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_43`](#mio_pad_attr_regwen) | 0x340 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_44`](#mio_pad_attr_regwen) | 0x344 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_45`](#mio_pad_attr_regwen) | 0x348 | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_REGWEN_46`](#mio_pad_attr_regwen) | 0x34c | 4 | Register write enable for MIO PAD attributes. | +| pinmux.[`MIO_PAD_ATTR_0`](#mio_pad_attr) | 0x350 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_1`](#mio_pad_attr) | 0x354 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_2`](#mio_pad_attr) | 0x358 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_3`](#mio_pad_attr) | 0x35c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_4`](#mio_pad_attr) | 0x360 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_5`](#mio_pad_attr) | 0x364 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_6`](#mio_pad_attr) | 0x368 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_7`](#mio_pad_attr) | 0x36c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_8`](#mio_pad_attr) | 0x370 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_9`](#mio_pad_attr) | 0x374 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_10`](#mio_pad_attr) | 0x378 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_11`](#mio_pad_attr) | 0x37c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_12`](#mio_pad_attr) | 0x380 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_13`](#mio_pad_attr) | 0x384 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_14`](#mio_pad_attr) | 0x388 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_15`](#mio_pad_attr) | 0x38c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_16`](#mio_pad_attr) | 0x390 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_17`](#mio_pad_attr) | 0x394 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_18`](#mio_pad_attr) | 0x398 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_19`](#mio_pad_attr) | 0x39c | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_20`](#mio_pad_attr) | 0x3a0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_21`](#mio_pad_attr) | 0x3a4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_22`](#mio_pad_attr) | 0x3a8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_23`](#mio_pad_attr) | 0x3ac | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_24`](#mio_pad_attr) | 0x3b0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_25`](#mio_pad_attr) | 0x3b4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_26`](#mio_pad_attr) | 0x3b8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_27`](#mio_pad_attr) | 0x3bc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_28`](#mio_pad_attr) | 0x3c0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_29`](#mio_pad_attr) | 0x3c4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_30`](#mio_pad_attr) | 0x3c8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_31`](#mio_pad_attr) | 0x3cc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_32`](#mio_pad_attr) | 0x3d0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_33`](#mio_pad_attr) | 0x3d4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_34`](#mio_pad_attr) | 0x3d8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_35`](#mio_pad_attr) | 0x3dc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_36`](#mio_pad_attr) | 0x3e0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_37`](#mio_pad_attr) | 0x3e4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_38`](#mio_pad_attr) | 0x3e8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_39`](#mio_pad_attr) | 0x3ec | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_40`](#mio_pad_attr) | 0x3f0 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_41`](#mio_pad_attr) | 0x3f4 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_42`](#mio_pad_attr) | 0x3f8 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_43`](#mio_pad_attr) | 0x3fc | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_44`](#mio_pad_attr) | 0x400 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_45`](#mio_pad_attr) | 0x404 | 4 | Muxed pad attributes. | +| pinmux.[`MIO_PAD_ATTR_46`](#mio_pad_attr) | 0x408 | 4 | Muxed pad attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_0`](#dio_pad_attr_regwen) | 0x40c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_1`](#dio_pad_attr_regwen) | 0x410 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_2`](#dio_pad_attr_regwen) | 0x414 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_3`](#dio_pad_attr_regwen) | 0x418 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_4`](#dio_pad_attr_regwen) | 0x41c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_5`](#dio_pad_attr_regwen) | 0x420 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_6`](#dio_pad_attr_regwen) | 0x424 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_7`](#dio_pad_attr_regwen) | 0x428 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_8`](#dio_pad_attr_regwen) | 0x42c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_9`](#dio_pad_attr_regwen) | 0x430 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_10`](#dio_pad_attr_regwen) | 0x434 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_11`](#dio_pad_attr_regwen) | 0x438 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_12`](#dio_pad_attr_regwen) | 0x43c | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_REGWEN_13`](#dio_pad_attr_regwen) | 0x440 | 4 | Register write enable for DIO PAD attributes. | +| pinmux.[`DIO_PAD_ATTR_0`](#dio_pad_attr) | 0x444 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_1`](#dio_pad_attr) | 0x448 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_2`](#dio_pad_attr) | 0x44c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_3`](#dio_pad_attr) | 0x450 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_4`](#dio_pad_attr) | 0x454 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_5`](#dio_pad_attr) | 0x458 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_6`](#dio_pad_attr) | 0x45c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_7`](#dio_pad_attr) | 0x460 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_8`](#dio_pad_attr) | 0x464 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_9`](#dio_pad_attr) | 0x468 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_10`](#dio_pad_attr) | 0x46c | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_11`](#dio_pad_attr) | 0x470 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_12`](#dio_pad_attr) | 0x474 | 4 | Dedicated pad attributes. | +| pinmux.[`DIO_PAD_ATTR_13`](#dio_pad_attr) | 0x478 | 4 | Dedicated pad attributes. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_0`](#mio_pad_sleep_status_0) | 0x47c | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_STATUS_1`](#mio_pad_sleep_status_1) | 0x480 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_0`](#mio_pad_sleep_regwen) | 0x484 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_1`](#mio_pad_sleep_regwen) | 0x488 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_2`](#mio_pad_sleep_regwen) | 0x48c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_3`](#mio_pad_sleep_regwen) | 0x490 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_4`](#mio_pad_sleep_regwen) | 0x494 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_5`](#mio_pad_sleep_regwen) | 0x498 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_6`](#mio_pad_sleep_regwen) | 0x49c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_7`](#mio_pad_sleep_regwen) | 0x4a0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_8`](#mio_pad_sleep_regwen) | 0x4a4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_9`](#mio_pad_sleep_regwen) | 0x4a8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_10`](#mio_pad_sleep_regwen) | 0x4ac | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_11`](#mio_pad_sleep_regwen) | 0x4b0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_12`](#mio_pad_sleep_regwen) | 0x4b4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_13`](#mio_pad_sleep_regwen) | 0x4b8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_14`](#mio_pad_sleep_regwen) | 0x4bc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_15`](#mio_pad_sleep_regwen) | 0x4c0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_16`](#mio_pad_sleep_regwen) | 0x4c4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_17`](#mio_pad_sleep_regwen) | 0x4c8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_18`](#mio_pad_sleep_regwen) | 0x4cc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_19`](#mio_pad_sleep_regwen) | 0x4d0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_20`](#mio_pad_sleep_regwen) | 0x4d4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_21`](#mio_pad_sleep_regwen) | 0x4d8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_22`](#mio_pad_sleep_regwen) | 0x4dc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_23`](#mio_pad_sleep_regwen) | 0x4e0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_24`](#mio_pad_sleep_regwen) | 0x4e4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_25`](#mio_pad_sleep_regwen) | 0x4e8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_26`](#mio_pad_sleep_regwen) | 0x4ec | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_27`](#mio_pad_sleep_regwen) | 0x4f0 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_28`](#mio_pad_sleep_regwen) | 0x4f4 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_29`](#mio_pad_sleep_regwen) | 0x4f8 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_30`](#mio_pad_sleep_regwen) | 0x4fc | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_31`](#mio_pad_sleep_regwen) | 0x500 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_32`](#mio_pad_sleep_regwen) | 0x504 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_33`](#mio_pad_sleep_regwen) | 0x508 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_34`](#mio_pad_sleep_regwen) | 0x50c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_35`](#mio_pad_sleep_regwen) | 0x510 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_36`](#mio_pad_sleep_regwen) | 0x514 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_37`](#mio_pad_sleep_regwen) | 0x518 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_38`](#mio_pad_sleep_regwen) | 0x51c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_39`](#mio_pad_sleep_regwen) | 0x520 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_40`](#mio_pad_sleep_regwen) | 0x524 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_41`](#mio_pad_sleep_regwen) | 0x528 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_42`](#mio_pad_sleep_regwen) | 0x52c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_43`](#mio_pad_sleep_regwen) | 0x530 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_44`](#mio_pad_sleep_regwen) | 0x534 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_45`](#mio_pad_sleep_regwen) | 0x538 | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_REGWEN_46`](#mio_pad_sleep_regwen) | 0x53c | 4 | Register write enable for MIO sleep value configuration. | +| pinmux.[`MIO_PAD_SLEEP_EN_0`](#mio_pad_sleep_en) | 0x540 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_1`](#mio_pad_sleep_en) | 0x544 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_2`](#mio_pad_sleep_en) | 0x548 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_3`](#mio_pad_sleep_en) | 0x54c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_4`](#mio_pad_sleep_en) | 0x550 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_5`](#mio_pad_sleep_en) | 0x554 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_6`](#mio_pad_sleep_en) | 0x558 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_7`](#mio_pad_sleep_en) | 0x55c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_8`](#mio_pad_sleep_en) | 0x560 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_9`](#mio_pad_sleep_en) | 0x564 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_10`](#mio_pad_sleep_en) | 0x568 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_11`](#mio_pad_sleep_en) | 0x56c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_12`](#mio_pad_sleep_en) | 0x570 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_13`](#mio_pad_sleep_en) | 0x574 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_14`](#mio_pad_sleep_en) | 0x578 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_15`](#mio_pad_sleep_en) | 0x57c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_16`](#mio_pad_sleep_en) | 0x580 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_17`](#mio_pad_sleep_en) | 0x584 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_18`](#mio_pad_sleep_en) | 0x588 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_19`](#mio_pad_sleep_en) | 0x58c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_20`](#mio_pad_sleep_en) | 0x590 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_21`](#mio_pad_sleep_en) | 0x594 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_22`](#mio_pad_sleep_en) | 0x598 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_23`](#mio_pad_sleep_en) | 0x59c | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_24`](#mio_pad_sleep_en) | 0x5a0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_25`](#mio_pad_sleep_en) | 0x5a4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_26`](#mio_pad_sleep_en) | 0x5a8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_27`](#mio_pad_sleep_en) | 0x5ac | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_28`](#mio_pad_sleep_en) | 0x5b0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_29`](#mio_pad_sleep_en) | 0x5b4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_30`](#mio_pad_sleep_en) | 0x5b8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_31`](#mio_pad_sleep_en) | 0x5bc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_32`](#mio_pad_sleep_en) | 0x5c0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_33`](#mio_pad_sleep_en) | 0x5c4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_34`](#mio_pad_sleep_en) | 0x5c8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_35`](#mio_pad_sleep_en) | 0x5cc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_36`](#mio_pad_sleep_en) | 0x5d0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_37`](#mio_pad_sleep_en) | 0x5d4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_38`](#mio_pad_sleep_en) | 0x5d8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_39`](#mio_pad_sleep_en) | 0x5dc | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_40`](#mio_pad_sleep_en) | 0x5e0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_41`](#mio_pad_sleep_en) | 0x5e4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_42`](#mio_pad_sleep_en) | 0x5e8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_43`](#mio_pad_sleep_en) | 0x5ec | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_44`](#mio_pad_sleep_en) | 0x5f0 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_45`](#mio_pad_sleep_en) | 0x5f4 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_EN_46`](#mio_pad_sleep_en) | 0x5f8 | 4 | Enables the sleep mode of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_0`](#mio_pad_sleep_mode) | 0x5fc | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_1`](#mio_pad_sleep_mode) | 0x600 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_2`](#mio_pad_sleep_mode) | 0x604 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_3`](#mio_pad_sleep_mode) | 0x608 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_4`](#mio_pad_sleep_mode) | 0x60c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_5`](#mio_pad_sleep_mode) | 0x610 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_6`](#mio_pad_sleep_mode) | 0x614 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_7`](#mio_pad_sleep_mode) | 0x618 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_8`](#mio_pad_sleep_mode) | 0x61c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_9`](#mio_pad_sleep_mode) | 0x620 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_10`](#mio_pad_sleep_mode) | 0x624 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_11`](#mio_pad_sleep_mode) | 0x628 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_12`](#mio_pad_sleep_mode) | 0x62c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_13`](#mio_pad_sleep_mode) | 0x630 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_14`](#mio_pad_sleep_mode) | 0x634 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_15`](#mio_pad_sleep_mode) | 0x638 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_16`](#mio_pad_sleep_mode) | 0x63c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_17`](#mio_pad_sleep_mode) | 0x640 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_18`](#mio_pad_sleep_mode) | 0x644 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_19`](#mio_pad_sleep_mode) | 0x648 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_20`](#mio_pad_sleep_mode) | 0x64c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_21`](#mio_pad_sleep_mode) | 0x650 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_22`](#mio_pad_sleep_mode) | 0x654 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_23`](#mio_pad_sleep_mode) | 0x658 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_24`](#mio_pad_sleep_mode) | 0x65c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_25`](#mio_pad_sleep_mode) | 0x660 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_26`](#mio_pad_sleep_mode) | 0x664 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_27`](#mio_pad_sleep_mode) | 0x668 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_28`](#mio_pad_sleep_mode) | 0x66c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_29`](#mio_pad_sleep_mode) | 0x670 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_30`](#mio_pad_sleep_mode) | 0x674 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_31`](#mio_pad_sleep_mode) | 0x678 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_32`](#mio_pad_sleep_mode) | 0x67c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_33`](#mio_pad_sleep_mode) | 0x680 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_34`](#mio_pad_sleep_mode) | 0x684 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_35`](#mio_pad_sleep_mode) | 0x688 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_36`](#mio_pad_sleep_mode) | 0x68c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_37`](#mio_pad_sleep_mode) | 0x690 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_38`](#mio_pad_sleep_mode) | 0x694 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_39`](#mio_pad_sleep_mode) | 0x698 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_40`](#mio_pad_sleep_mode) | 0x69c | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_41`](#mio_pad_sleep_mode) | 0x6a0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_42`](#mio_pad_sleep_mode) | 0x6a4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_43`](#mio_pad_sleep_mode) | 0x6a8 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_44`](#mio_pad_sleep_mode) | 0x6ac | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_45`](#mio_pad_sleep_mode) | 0x6b0 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`MIO_PAD_SLEEP_MODE_46`](#mio_pad_sleep_mode) | 0x6b4 | 4 | Defines sleep behavior of the corresponding muxed pad. | +| pinmux.[`DIO_PAD_SLEEP_STATUS`](#dio_pad_sleep_status) | 0x6b8 | 4 | Register indicating whether the corresponding pad is in sleep mode. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_0`](#dio_pad_sleep_regwen) | 0x6bc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_1`](#dio_pad_sleep_regwen) | 0x6c0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_2`](#dio_pad_sleep_regwen) | 0x6c4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_3`](#dio_pad_sleep_regwen) | 0x6c8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_4`](#dio_pad_sleep_regwen) | 0x6cc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_5`](#dio_pad_sleep_regwen) | 0x6d0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_6`](#dio_pad_sleep_regwen) | 0x6d4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_7`](#dio_pad_sleep_regwen) | 0x6d8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_8`](#dio_pad_sleep_regwen) | 0x6dc | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_9`](#dio_pad_sleep_regwen) | 0x6e0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_10`](#dio_pad_sleep_regwen) | 0x6e4 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_11`](#dio_pad_sleep_regwen) | 0x6e8 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_12`](#dio_pad_sleep_regwen) | 0x6ec | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_REGWEN_13`](#dio_pad_sleep_regwen) | 0x6f0 | 4 | Register write enable for DIO sleep value configuration. | +| pinmux.[`DIO_PAD_SLEEP_EN_0`](#dio_pad_sleep_en) | 0x6f4 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_1`](#dio_pad_sleep_en) | 0x6f8 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_2`](#dio_pad_sleep_en) | 0x6fc | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_3`](#dio_pad_sleep_en) | 0x700 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_4`](#dio_pad_sleep_en) | 0x704 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_5`](#dio_pad_sleep_en) | 0x708 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_6`](#dio_pad_sleep_en) | 0x70c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_7`](#dio_pad_sleep_en) | 0x710 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_8`](#dio_pad_sleep_en) | 0x714 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_9`](#dio_pad_sleep_en) | 0x718 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_10`](#dio_pad_sleep_en) | 0x71c | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_11`](#dio_pad_sleep_en) | 0x720 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_12`](#dio_pad_sleep_en) | 0x724 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_EN_13`](#dio_pad_sleep_en) | 0x728 | 4 | Enables the sleep mode of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_0`](#dio_pad_sleep_mode) | 0x72c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_1`](#dio_pad_sleep_mode) | 0x730 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_2`](#dio_pad_sleep_mode) | 0x734 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_3`](#dio_pad_sleep_mode) | 0x738 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_4`](#dio_pad_sleep_mode) | 0x73c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_5`](#dio_pad_sleep_mode) | 0x740 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_6`](#dio_pad_sleep_mode) | 0x744 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_7`](#dio_pad_sleep_mode) | 0x748 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_8`](#dio_pad_sleep_mode) | 0x74c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_9`](#dio_pad_sleep_mode) | 0x750 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_10`](#dio_pad_sleep_mode) | 0x754 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_11`](#dio_pad_sleep_mode) | 0x758 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_12`](#dio_pad_sleep_mode) | 0x75c | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`DIO_PAD_SLEEP_MODE_13`](#dio_pad_sleep_mode) | 0x760 | 4 | Defines sleep behavior of the corresponding dedicated pad. | +| pinmux.[`WKUP_DETECTOR_REGWEN_0`](#wkup_detector_regwen) | 0x764 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_1`](#wkup_detector_regwen) | 0x768 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_2`](#wkup_detector_regwen) | 0x76c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_3`](#wkup_detector_regwen) | 0x770 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_4`](#wkup_detector_regwen) | 0x774 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_5`](#wkup_detector_regwen) | 0x778 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_6`](#wkup_detector_regwen) | 0x77c | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_REGWEN_7`](#wkup_detector_regwen) | 0x780 | 4 | Register write enable for wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_0`](#wkup_detector_en) | 0x784 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_1`](#wkup_detector_en) | 0x788 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_2`](#wkup_detector_en) | 0x78c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_3`](#wkup_detector_en) | 0x790 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_4`](#wkup_detector_en) | 0x794 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_5`](#wkup_detector_en) | 0x798 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_6`](#wkup_detector_en) | 0x79c | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_EN_7`](#wkup_detector_en) | 0x7a0 | 4 | Enables for the wakeup detectors. | +| pinmux.[`WKUP_DETECTOR_0`](#wkup_detector) | 0x7a4 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_1`](#wkup_detector) | 0x7a8 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_2`](#wkup_detector) | 0x7ac | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_3`](#wkup_detector) | 0x7b0 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_4`](#wkup_detector) | 0x7b4 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_5`](#wkup_detector) | 0x7b8 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_6`](#wkup_detector) | 0x7bc | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_7`](#wkup_detector) | 0x7c0 | 4 | Configuration of wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_0`](#wkup_detector_cnt_th) | 0x7c4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_1`](#wkup_detector_cnt_th) | 0x7c8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_2`](#wkup_detector_cnt_th) | 0x7cc | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_3`](#wkup_detector_cnt_th) | 0x7d0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_4`](#wkup_detector_cnt_th) | 0x7d4 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_5`](#wkup_detector_cnt_th) | 0x7d8 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_6`](#wkup_detector_cnt_th) | 0x7dc | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_CNT_TH_7`](#wkup_detector_cnt_th) | 0x7e0 | 4 | Counter thresholds for wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_0`](#wkup_detector_padsel) | 0x7e4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_1`](#wkup_detector_padsel) | 0x7e8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_2`](#wkup_detector_padsel) | 0x7ec | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_3`](#wkup_detector_padsel) | 0x7f0 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_4`](#wkup_detector_padsel) | 0x7f4 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_5`](#wkup_detector_padsel) | 0x7f8 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_6`](#wkup_detector_padsel) | 0x7fc | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_DETECTOR_PADSEL_7`](#wkup_detector_padsel) | 0x800 | 4 | Pad selects for pad wakeup condition detectors. | +| pinmux.[`WKUP_CAUSE`](#wkup_cause) | 0x804 | 4 | Cause registers for wakeup detectors. | ## ALERT_TEST Alert Test Register @@ -587,9 +581,6 @@ Register write enable for MIO peripheral input selects. | MIO_PERIPH_INSEL_REGWEN_32 | 0x84 | | MIO_PERIPH_INSEL_REGWEN_33 | 0x88 | | MIO_PERIPH_INSEL_REGWEN_34 | 0x8c | -| MIO_PERIPH_INSEL_REGWEN_35 | 0x90 | -| MIO_PERIPH_INSEL_REGWEN_36 | 0x94 | -| MIO_PERIPH_INSEL_REGWEN_37 | 0x98 | ### Fields @@ -613,44 +604,41 @@ For each peripheral input, this selects the muxable pad input. | Name | Offset | |:--------------------|:---------| -| MIO_PERIPH_INSEL_0 | 0x9c | -| MIO_PERIPH_INSEL_1 | 0xa0 | -| MIO_PERIPH_INSEL_2 | 0xa4 | -| MIO_PERIPH_INSEL_3 | 0xa8 | -| MIO_PERIPH_INSEL_4 | 0xac | -| MIO_PERIPH_INSEL_5 | 0xb0 | -| MIO_PERIPH_INSEL_6 | 0xb4 | -| MIO_PERIPH_INSEL_7 | 0xb8 | -| MIO_PERIPH_INSEL_8 | 0xbc | -| MIO_PERIPH_INSEL_9 | 0xc0 | -| MIO_PERIPH_INSEL_10 | 0xc4 | -| MIO_PERIPH_INSEL_11 | 0xc8 | -| MIO_PERIPH_INSEL_12 | 0xcc | -| MIO_PERIPH_INSEL_13 | 0xd0 | -| MIO_PERIPH_INSEL_14 | 0xd4 | -| MIO_PERIPH_INSEL_15 | 0xd8 | -| MIO_PERIPH_INSEL_16 | 0xdc | -| MIO_PERIPH_INSEL_17 | 0xe0 | -| MIO_PERIPH_INSEL_18 | 0xe4 | -| MIO_PERIPH_INSEL_19 | 0xe8 | -| MIO_PERIPH_INSEL_20 | 0xec | -| MIO_PERIPH_INSEL_21 | 0xf0 | -| MIO_PERIPH_INSEL_22 | 0xf4 | -| MIO_PERIPH_INSEL_23 | 0xf8 | -| MIO_PERIPH_INSEL_24 | 0xfc | -| MIO_PERIPH_INSEL_25 | 0x100 | -| MIO_PERIPH_INSEL_26 | 0x104 | -| MIO_PERIPH_INSEL_27 | 0x108 | -| MIO_PERIPH_INSEL_28 | 0x10c | -| MIO_PERIPH_INSEL_29 | 0x110 | -| MIO_PERIPH_INSEL_30 | 0x114 | -| MIO_PERIPH_INSEL_31 | 0x118 | -| MIO_PERIPH_INSEL_32 | 0x11c | -| MIO_PERIPH_INSEL_33 | 0x120 | -| MIO_PERIPH_INSEL_34 | 0x124 | -| MIO_PERIPH_INSEL_35 | 0x128 | -| MIO_PERIPH_INSEL_36 | 0x12c | -| MIO_PERIPH_INSEL_37 | 0x130 | +| MIO_PERIPH_INSEL_0 | 0x90 | +| MIO_PERIPH_INSEL_1 | 0x94 | +| MIO_PERIPH_INSEL_2 | 0x98 | +| MIO_PERIPH_INSEL_3 | 0x9c | +| MIO_PERIPH_INSEL_4 | 0xa0 | +| MIO_PERIPH_INSEL_5 | 0xa4 | +| MIO_PERIPH_INSEL_6 | 0xa8 | +| MIO_PERIPH_INSEL_7 | 0xac | +| MIO_PERIPH_INSEL_8 | 0xb0 | +| MIO_PERIPH_INSEL_9 | 0xb4 | +| MIO_PERIPH_INSEL_10 | 0xb8 | +| MIO_PERIPH_INSEL_11 | 0xbc | +| MIO_PERIPH_INSEL_12 | 0xc0 | +| MIO_PERIPH_INSEL_13 | 0xc4 | +| MIO_PERIPH_INSEL_14 | 0xc8 | +| MIO_PERIPH_INSEL_15 | 0xcc | +| MIO_PERIPH_INSEL_16 | 0xd0 | +| MIO_PERIPH_INSEL_17 | 0xd4 | +| MIO_PERIPH_INSEL_18 | 0xd8 | +| MIO_PERIPH_INSEL_19 | 0xdc | +| MIO_PERIPH_INSEL_20 | 0xe0 | +| MIO_PERIPH_INSEL_21 | 0xe4 | +| MIO_PERIPH_INSEL_22 | 0xe8 | +| MIO_PERIPH_INSEL_23 | 0xec | +| MIO_PERIPH_INSEL_24 | 0xf0 | +| MIO_PERIPH_INSEL_25 | 0xf4 | +| MIO_PERIPH_INSEL_26 | 0xf8 | +| MIO_PERIPH_INSEL_27 | 0xfc | +| MIO_PERIPH_INSEL_28 | 0x100 | +| MIO_PERIPH_INSEL_29 | 0x104 | +| MIO_PERIPH_INSEL_30 | 0x108 | +| MIO_PERIPH_INSEL_31 | 0x10c | +| MIO_PERIPH_INSEL_32 | 0x110 | +| MIO_PERIPH_INSEL_33 | 0x114 | +| MIO_PERIPH_INSEL_34 | 0x118 | ### Fields @@ -673,53 +661,53 @@ Register write enable for MIO output selects. | Name | Offset | |:---------------------|:---------| -| MIO_OUTSEL_REGWEN_0 | 0x134 | -| MIO_OUTSEL_REGWEN_1 | 0x138 | -| MIO_OUTSEL_REGWEN_2 | 0x13c | -| MIO_OUTSEL_REGWEN_3 | 0x140 | -| MIO_OUTSEL_REGWEN_4 | 0x144 | -| MIO_OUTSEL_REGWEN_5 | 0x148 | -| MIO_OUTSEL_REGWEN_6 | 0x14c | -| MIO_OUTSEL_REGWEN_7 | 0x150 | -| MIO_OUTSEL_REGWEN_8 | 0x154 | -| MIO_OUTSEL_REGWEN_9 | 0x158 | -| MIO_OUTSEL_REGWEN_10 | 0x15c | -| MIO_OUTSEL_REGWEN_11 | 0x160 | -| MIO_OUTSEL_REGWEN_12 | 0x164 | -| MIO_OUTSEL_REGWEN_13 | 0x168 | -| MIO_OUTSEL_REGWEN_14 | 0x16c | -| MIO_OUTSEL_REGWEN_15 | 0x170 | -| MIO_OUTSEL_REGWEN_16 | 0x174 | -| MIO_OUTSEL_REGWEN_17 | 0x178 | -| MIO_OUTSEL_REGWEN_18 | 0x17c | -| MIO_OUTSEL_REGWEN_19 | 0x180 | -| MIO_OUTSEL_REGWEN_20 | 0x184 | -| MIO_OUTSEL_REGWEN_21 | 0x188 | -| MIO_OUTSEL_REGWEN_22 | 0x18c | -| MIO_OUTSEL_REGWEN_23 | 0x190 | -| MIO_OUTSEL_REGWEN_24 | 0x194 | -| MIO_OUTSEL_REGWEN_25 | 0x198 | -| MIO_OUTSEL_REGWEN_26 | 0x19c | -| MIO_OUTSEL_REGWEN_27 | 0x1a0 | -| MIO_OUTSEL_REGWEN_28 | 0x1a4 | -| MIO_OUTSEL_REGWEN_29 | 0x1a8 | -| MIO_OUTSEL_REGWEN_30 | 0x1ac | -| MIO_OUTSEL_REGWEN_31 | 0x1b0 | -| MIO_OUTSEL_REGWEN_32 | 0x1b4 | -| MIO_OUTSEL_REGWEN_33 | 0x1b8 | -| MIO_OUTSEL_REGWEN_34 | 0x1bc | -| MIO_OUTSEL_REGWEN_35 | 0x1c0 | -| MIO_OUTSEL_REGWEN_36 | 0x1c4 | -| MIO_OUTSEL_REGWEN_37 | 0x1c8 | -| MIO_OUTSEL_REGWEN_38 | 0x1cc | -| MIO_OUTSEL_REGWEN_39 | 0x1d0 | -| MIO_OUTSEL_REGWEN_40 | 0x1d4 | -| MIO_OUTSEL_REGWEN_41 | 0x1d8 | -| MIO_OUTSEL_REGWEN_42 | 0x1dc | -| MIO_OUTSEL_REGWEN_43 | 0x1e0 | -| MIO_OUTSEL_REGWEN_44 | 0x1e4 | -| MIO_OUTSEL_REGWEN_45 | 0x1e8 | -| MIO_OUTSEL_REGWEN_46 | 0x1ec | +| MIO_OUTSEL_REGWEN_0 | 0x11c | +| MIO_OUTSEL_REGWEN_1 | 0x120 | +| MIO_OUTSEL_REGWEN_2 | 0x124 | +| MIO_OUTSEL_REGWEN_3 | 0x128 | +| MIO_OUTSEL_REGWEN_4 | 0x12c | +| MIO_OUTSEL_REGWEN_5 | 0x130 | +| MIO_OUTSEL_REGWEN_6 | 0x134 | +| MIO_OUTSEL_REGWEN_7 | 0x138 | +| MIO_OUTSEL_REGWEN_8 | 0x13c | +| MIO_OUTSEL_REGWEN_9 | 0x140 | +| MIO_OUTSEL_REGWEN_10 | 0x144 | +| MIO_OUTSEL_REGWEN_11 | 0x148 | +| MIO_OUTSEL_REGWEN_12 | 0x14c | +| MIO_OUTSEL_REGWEN_13 | 0x150 | +| MIO_OUTSEL_REGWEN_14 | 0x154 | +| MIO_OUTSEL_REGWEN_15 | 0x158 | +| MIO_OUTSEL_REGWEN_16 | 0x15c | +| MIO_OUTSEL_REGWEN_17 | 0x160 | +| MIO_OUTSEL_REGWEN_18 | 0x164 | +| MIO_OUTSEL_REGWEN_19 | 0x168 | +| MIO_OUTSEL_REGWEN_20 | 0x16c | +| MIO_OUTSEL_REGWEN_21 | 0x170 | +| MIO_OUTSEL_REGWEN_22 | 0x174 | +| MIO_OUTSEL_REGWEN_23 | 0x178 | +| MIO_OUTSEL_REGWEN_24 | 0x17c | +| MIO_OUTSEL_REGWEN_25 | 0x180 | +| MIO_OUTSEL_REGWEN_26 | 0x184 | +| MIO_OUTSEL_REGWEN_27 | 0x188 | +| MIO_OUTSEL_REGWEN_28 | 0x18c | +| MIO_OUTSEL_REGWEN_29 | 0x190 | +| MIO_OUTSEL_REGWEN_30 | 0x194 | +| MIO_OUTSEL_REGWEN_31 | 0x198 | +| MIO_OUTSEL_REGWEN_32 | 0x19c | +| MIO_OUTSEL_REGWEN_33 | 0x1a0 | +| MIO_OUTSEL_REGWEN_34 | 0x1a4 | +| MIO_OUTSEL_REGWEN_35 | 0x1a8 | +| MIO_OUTSEL_REGWEN_36 | 0x1ac | +| MIO_OUTSEL_REGWEN_37 | 0x1b0 | +| MIO_OUTSEL_REGWEN_38 | 0x1b4 | +| MIO_OUTSEL_REGWEN_39 | 0x1b8 | +| MIO_OUTSEL_REGWEN_40 | 0x1bc | +| MIO_OUTSEL_REGWEN_41 | 0x1c0 | +| MIO_OUTSEL_REGWEN_42 | 0x1c4 | +| MIO_OUTSEL_REGWEN_43 | 0x1c8 | +| MIO_OUTSEL_REGWEN_44 | 0x1cc | +| MIO_OUTSEL_REGWEN_45 | 0x1d0 | +| MIO_OUTSEL_REGWEN_46 | 0x1d4 | ### Fields @@ -743,53 +731,53 @@ For each muxable pad, this selects the peripheral output. | Name | Offset | |:--------------|:---------| -| MIO_OUTSEL_0 | 0x1f0 | -| MIO_OUTSEL_1 | 0x1f4 | -| MIO_OUTSEL_2 | 0x1f8 | -| MIO_OUTSEL_3 | 0x1fc | -| MIO_OUTSEL_4 | 0x200 | -| MIO_OUTSEL_5 | 0x204 | -| MIO_OUTSEL_6 | 0x208 | -| MIO_OUTSEL_7 | 0x20c | -| MIO_OUTSEL_8 | 0x210 | -| MIO_OUTSEL_9 | 0x214 | -| MIO_OUTSEL_10 | 0x218 | -| MIO_OUTSEL_11 | 0x21c | -| MIO_OUTSEL_12 | 0x220 | -| MIO_OUTSEL_13 | 0x224 | -| MIO_OUTSEL_14 | 0x228 | -| MIO_OUTSEL_15 | 0x22c | -| MIO_OUTSEL_16 | 0x230 | -| MIO_OUTSEL_17 | 0x234 | -| MIO_OUTSEL_18 | 0x238 | -| MIO_OUTSEL_19 | 0x23c | -| MIO_OUTSEL_20 | 0x240 | -| MIO_OUTSEL_21 | 0x244 | -| MIO_OUTSEL_22 | 0x248 | -| MIO_OUTSEL_23 | 0x24c | -| MIO_OUTSEL_24 | 0x250 | -| MIO_OUTSEL_25 | 0x254 | -| MIO_OUTSEL_26 | 0x258 | -| MIO_OUTSEL_27 | 0x25c | -| MIO_OUTSEL_28 | 0x260 | -| MIO_OUTSEL_29 | 0x264 | -| MIO_OUTSEL_30 | 0x268 | -| MIO_OUTSEL_31 | 0x26c | -| MIO_OUTSEL_32 | 0x270 | -| MIO_OUTSEL_33 | 0x274 | -| MIO_OUTSEL_34 | 0x278 | -| MIO_OUTSEL_35 | 0x27c | -| MIO_OUTSEL_36 | 0x280 | -| MIO_OUTSEL_37 | 0x284 | -| MIO_OUTSEL_38 | 0x288 | -| MIO_OUTSEL_39 | 0x28c | -| MIO_OUTSEL_40 | 0x290 | -| MIO_OUTSEL_41 | 0x294 | -| MIO_OUTSEL_42 | 0x298 | -| MIO_OUTSEL_43 | 0x29c | -| MIO_OUTSEL_44 | 0x2a0 | -| MIO_OUTSEL_45 | 0x2a4 | -| MIO_OUTSEL_46 | 0x2a8 | +| MIO_OUTSEL_0 | 0x1d8 | +| MIO_OUTSEL_1 | 0x1dc | +| MIO_OUTSEL_2 | 0x1e0 | +| MIO_OUTSEL_3 | 0x1e4 | +| MIO_OUTSEL_4 | 0x1e8 | +| MIO_OUTSEL_5 | 0x1ec | +| MIO_OUTSEL_6 | 0x1f0 | +| MIO_OUTSEL_7 | 0x1f4 | +| MIO_OUTSEL_8 | 0x1f8 | +| MIO_OUTSEL_9 | 0x1fc | +| MIO_OUTSEL_10 | 0x200 | +| MIO_OUTSEL_11 | 0x204 | +| MIO_OUTSEL_12 | 0x208 | +| MIO_OUTSEL_13 | 0x20c | +| MIO_OUTSEL_14 | 0x210 | +| MIO_OUTSEL_15 | 0x214 | +| MIO_OUTSEL_16 | 0x218 | +| MIO_OUTSEL_17 | 0x21c | +| MIO_OUTSEL_18 | 0x220 | +| MIO_OUTSEL_19 | 0x224 | +| MIO_OUTSEL_20 | 0x228 | +| MIO_OUTSEL_21 | 0x22c | +| MIO_OUTSEL_22 | 0x230 | +| MIO_OUTSEL_23 | 0x234 | +| MIO_OUTSEL_24 | 0x238 | +| MIO_OUTSEL_25 | 0x23c | +| MIO_OUTSEL_26 | 0x240 | +| MIO_OUTSEL_27 | 0x244 | +| MIO_OUTSEL_28 | 0x248 | +| MIO_OUTSEL_29 | 0x24c | +| MIO_OUTSEL_30 | 0x250 | +| MIO_OUTSEL_31 | 0x254 | +| MIO_OUTSEL_32 | 0x258 | +| MIO_OUTSEL_33 | 0x25c | +| MIO_OUTSEL_34 | 0x260 | +| MIO_OUTSEL_35 | 0x264 | +| MIO_OUTSEL_36 | 0x268 | +| MIO_OUTSEL_37 | 0x26c | +| MIO_OUTSEL_38 | 0x270 | +| MIO_OUTSEL_39 | 0x274 | +| MIO_OUTSEL_40 | 0x278 | +| MIO_OUTSEL_41 | 0x27c | +| MIO_OUTSEL_42 | 0x280 | +| MIO_OUTSEL_43 | 0x284 | +| MIO_OUTSEL_44 | 0x288 | +| MIO_OUTSEL_45 | 0x28c | +| MIO_OUTSEL_46 | 0x290 | ### Fields @@ -812,53 +800,53 @@ Register write enable for MIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| MIO_PAD_ATTR_REGWEN_0 | 0x2ac | -| MIO_PAD_ATTR_REGWEN_1 | 0x2b0 | -| MIO_PAD_ATTR_REGWEN_2 | 0x2b4 | -| MIO_PAD_ATTR_REGWEN_3 | 0x2b8 | -| MIO_PAD_ATTR_REGWEN_4 | 0x2bc | -| MIO_PAD_ATTR_REGWEN_5 | 0x2c0 | -| MIO_PAD_ATTR_REGWEN_6 | 0x2c4 | -| MIO_PAD_ATTR_REGWEN_7 | 0x2c8 | -| MIO_PAD_ATTR_REGWEN_8 | 0x2cc | -| MIO_PAD_ATTR_REGWEN_9 | 0x2d0 | -| MIO_PAD_ATTR_REGWEN_10 | 0x2d4 | -| MIO_PAD_ATTR_REGWEN_11 | 0x2d8 | -| MIO_PAD_ATTR_REGWEN_12 | 0x2dc | -| MIO_PAD_ATTR_REGWEN_13 | 0x2e0 | -| MIO_PAD_ATTR_REGWEN_14 | 0x2e4 | -| MIO_PAD_ATTR_REGWEN_15 | 0x2e8 | -| MIO_PAD_ATTR_REGWEN_16 | 0x2ec | -| MIO_PAD_ATTR_REGWEN_17 | 0x2f0 | -| MIO_PAD_ATTR_REGWEN_18 | 0x2f4 | -| MIO_PAD_ATTR_REGWEN_19 | 0x2f8 | -| MIO_PAD_ATTR_REGWEN_20 | 0x2fc | -| MIO_PAD_ATTR_REGWEN_21 | 0x300 | -| MIO_PAD_ATTR_REGWEN_22 | 0x304 | -| MIO_PAD_ATTR_REGWEN_23 | 0x308 | -| MIO_PAD_ATTR_REGWEN_24 | 0x30c | -| MIO_PAD_ATTR_REGWEN_25 | 0x310 | -| MIO_PAD_ATTR_REGWEN_26 | 0x314 | -| MIO_PAD_ATTR_REGWEN_27 | 0x318 | -| MIO_PAD_ATTR_REGWEN_28 | 0x31c | -| MIO_PAD_ATTR_REGWEN_29 | 0x320 | -| MIO_PAD_ATTR_REGWEN_30 | 0x324 | -| MIO_PAD_ATTR_REGWEN_31 | 0x328 | -| MIO_PAD_ATTR_REGWEN_32 | 0x32c | -| MIO_PAD_ATTR_REGWEN_33 | 0x330 | -| MIO_PAD_ATTR_REGWEN_34 | 0x334 | -| MIO_PAD_ATTR_REGWEN_35 | 0x338 | -| MIO_PAD_ATTR_REGWEN_36 | 0x33c | -| MIO_PAD_ATTR_REGWEN_37 | 0x340 | -| MIO_PAD_ATTR_REGWEN_38 | 0x344 | -| MIO_PAD_ATTR_REGWEN_39 | 0x348 | -| MIO_PAD_ATTR_REGWEN_40 | 0x34c | -| MIO_PAD_ATTR_REGWEN_41 | 0x350 | -| MIO_PAD_ATTR_REGWEN_42 | 0x354 | -| MIO_PAD_ATTR_REGWEN_43 | 0x358 | -| MIO_PAD_ATTR_REGWEN_44 | 0x35c | -| MIO_PAD_ATTR_REGWEN_45 | 0x360 | -| MIO_PAD_ATTR_REGWEN_46 | 0x364 | +| MIO_PAD_ATTR_REGWEN_0 | 0x294 | +| MIO_PAD_ATTR_REGWEN_1 | 0x298 | +| MIO_PAD_ATTR_REGWEN_2 | 0x29c | +| MIO_PAD_ATTR_REGWEN_3 | 0x2a0 | +| MIO_PAD_ATTR_REGWEN_4 | 0x2a4 | +| MIO_PAD_ATTR_REGWEN_5 | 0x2a8 | +| MIO_PAD_ATTR_REGWEN_6 | 0x2ac | +| MIO_PAD_ATTR_REGWEN_7 | 0x2b0 | +| MIO_PAD_ATTR_REGWEN_8 | 0x2b4 | +| MIO_PAD_ATTR_REGWEN_9 | 0x2b8 | +| MIO_PAD_ATTR_REGWEN_10 | 0x2bc | +| MIO_PAD_ATTR_REGWEN_11 | 0x2c0 | +| MIO_PAD_ATTR_REGWEN_12 | 0x2c4 | +| MIO_PAD_ATTR_REGWEN_13 | 0x2c8 | +| MIO_PAD_ATTR_REGWEN_14 | 0x2cc | +| MIO_PAD_ATTR_REGWEN_15 | 0x2d0 | +| MIO_PAD_ATTR_REGWEN_16 | 0x2d4 | +| MIO_PAD_ATTR_REGWEN_17 | 0x2d8 | +| MIO_PAD_ATTR_REGWEN_18 | 0x2dc | +| MIO_PAD_ATTR_REGWEN_19 | 0x2e0 | +| MIO_PAD_ATTR_REGWEN_20 | 0x2e4 | +| MIO_PAD_ATTR_REGWEN_21 | 0x2e8 | +| MIO_PAD_ATTR_REGWEN_22 | 0x2ec | +| MIO_PAD_ATTR_REGWEN_23 | 0x2f0 | +| MIO_PAD_ATTR_REGWEN_24 | 0x2f4 | +| MIO_PAD_ATTR_REGWEN_25 | 0x2f8 | +| MIO_PAD_ATTR_REGWEN_26 | 0x2fc | +| MIO_PAD_ATTR_REGWEN_27 | 0x300 | +| MIO_PAD_ATTR_REGWEN_28 | 0x304 | +| MIO_PAD_ATTR_REGWEN_29 | 0x308 | +| MIO_PAD_ATTR_REGWEN_30 | 0x30c | +| MIO_PAD_ATTR_REGWEN_31 | 0x310 | +| MIO_PAD_ATTR_REGWEN_32 | 0x314 | +| MIO_PAD_ATTR_REGWEN_33 | 0x318 | +| MIO_PAD_ATTR_REGWEN_34 | 0x31c | +| MIO_PAD_ATTR_REGWEN_35 | 0x320 | +| MIO_PAD_ATTR_REGWEN_36 | 0x324 | +| MIO_PAD_ATTR_REGWEN_37 | 0x328 | +| MIO_PAD_ATTR_REGWEN_38 | 0x32c | +| MIO_PAD_ATTR_REGWEN_39 | 0x330 | +| MIO_PAD_ATTR_REGWEN_40 | 0x334 | +| MIO_PAD_ATTR_REGWEN_41 | 0x338 | +| MIO_PAD_ATTR_REGWEN_42 | 0x33c | +| MIO_PAD_ATTR_REGWEN_43 | 0x340 | +| MIO_PAD_ATTR_REGWEN_44 | 0x344 | +| MIO_PAD_ATTR_REGWEN_45 | 0x348 | +| MIO_PAD_ATTR_REGWEN_46 | 0x34c | ### Fields @@ -885,53 +873,53 @@ The muxed pad that is used for TAP strap 0 has a different reset value, with `pu | Name | Offset | |:----------------|:---------| -| MIO_PAD_ATTR_0 | 0x368 | -| MIO_PAD_ATTR_1 | 0x36c | -| MIO_PAD_ATTR_2 | 0x370 | -| MIO_PAD_ATTR_3 | 0x374 | -| MIO_PAD_ATTR_4 | 0x378 | -| MIO_PAD_ATTR_5 | 0x37c | -| MIO_PAD_ATTR_6 | 0x380 | -| MIO_PAD_ATTR_7 | 0x384 | -| MIO_PAD_ATTR_8 | 0x388 | -| MIO_PAD_ATTR_9 | 0x38c | -| MIO_PAD_ATTR_10 | 0x390 | -| MIO_PAD_ATTR_11 | 0x394 | -| MIO_PAD_ATTR_12 | 0x398 | -| MIO_PAD_ATTR_13 | 0x39c | -| MIO_PAD_ATTR_14 | 0x3a0 | -| MIO_PAD_ATTR_15 | 0x3a4 | -| MIO_PAD_ATTR_16 | 0x3a8 | -| MIO_PAD_ATTR_17 | 0x3ac | -| MIO_PAD_ATTR_18 | 0x3b0 | -| MIO_PAD_ATTR_19 | 0x3b4 | -| MIO_PAD_ATTR_20 | 0x3b8 | -| MIO_PAD_ATTR_21 | 0x3bc | -| MIO_PAD_ATTR_22 | 0x3c0 | -| MIO_PAD_ATTR_23 | 0x3c4 | -| MIO_PAD_ATTR_24 | 0x3c8 | -| MIO_PAD_ATTR_25 | 0x3cc | -| MIO_PAD_ATTR_26 | 0x3d0 | -| MIO_PAD_ATTR_27 | 0x3d4 | -| MIO_PAD_ATTR_28 | 0x3d8 | -| MIO_PAD_ATTR_29 | 0x3dc | -| MIO_PAD_ATTR_30 | 0x3e0 | -| MIO_PAD_ATTR_31 | 0x3e4 | -| MIO_PAD_ATTR_32 | 0x3e8 | -| MIO_PAD_ATTR_33 | 0x3ec | -| MIO_PAD_ATTR_34 | 0x3f0 | -| MIO_PAD_ATTR_35 | 0x3f4 | -| MIO_PAD_ATTR_36 | 0x3f8 | -| MIO_PAD_ATTR_37 | 0x3fc | -| MIO_PAD_ATTR_38 | 0x400 | -| MIO_PAD_ATTR_39 | 0x404 | -| MIO_PAD_ATTR_40 | 0x408 | -| MIO_PAD_ATTR_41 | 0x40c | -| MIO_PAD_ATTR_42 | 0x410 | -| MIO_PAD_ATTR_43 | 0x414 | -| MIO_PAD_ATTR_44 | 0x418 | -| MIO_PAD_ATTR_45 | 0x41c | -| MIO_PAD_ATTR_46 | 0x420 | +| MIO_PAD_ATTR_0 | 0x350 | +| MIO_PAD_ATTR_1 | 0x354 | +| MIO_PAD_ATTR_2 | 0x358 | +| MIO_PAD_ATTR_3 | 0x35c | +| MIO_PAD_ATTR_4 | 0x360 | +| MIO_PAD_ATTR_5 | 0x364 | +| MIO_PAD_ATTR_6 | 0x368 | +| MIO_PAD_ATTR_7 | 0x36c | +| MIO_PAD_ATTR_8 | 0x370 | +| MIO_PAD_ATTR_9 | 0x374 | +| MIO_PAD_ATTR_10 | 0x378 | +| MIO_PAD_ATTR_11 | 0x37c | +| MIO_PAD_ATTR_12 | 0x380 | +| MIO_PAD_ATTR_13 | 0x384 | +| MIO_PAD_ATTR_14 | 0x388 | +| MIO_PAD_ATTR_15 | 0x38c | +| MIO_PAD_ATTR_16 | 0x390 | +| MIO_PAD_ATTR_17 | 0x394 | +| MIO_PAD_ATTR_18 | 0x398 | +| MIO_PAD_ATTR_19 | 0x39c | +| MIO_PAD_ATTR_20 | 0x3a0 | +| MIO_PAD_ATTR_21 | 0x3a4 | +| MIO_PAD_ATTR_22 | 0x3a8 | +| MIO_PAD_ATTR_23 | 0x3ac | +| MIO_PAD_ATTR_24 | 0x3b0 | +| MIO_PAD_ATTR_25 | 0x3b4 | +| MIO_PAD_ATTR_26 | 0x3b8 | +| MIO_PAD_ATTR_27 | 0x3bc | +| MIO_PAD_ATTR_28 | 0x3c0 | +| MIO_PAD_ATTR_29 | 0x3c4 | +| MIO_PAD_ATTR_30 | 0x3c8 | +| MIO_PAD_ATTR_31 | 0x3cc | +| MIO_PAD_ATTR_32 | 0x3d0 | +| MIO_PAD_ATTR_33 | 0x3d4 | +| MIO_PAD_ATTR_34 | 0x3d8 | +| MIO_PAD_ATTR_35 | 0x3dc | +| MIO_PAD_ATTR_36 | 0x3e0 | +| MIO_PAD_ATTR_37 | 0x3e4 | +| MIO_PAD_ATTR_38 | 0x3e8 | +| MIO_PAD_ATTR_39 | 0x3ec | +| MIO_PAD_ATTR_40 | 0x3f0 | +| MIO_PAD_ATTR_41 | 0x3f4 | +| MIO_PAD_ATTR_42 | 0x3f8 | +| MIO_PAD_ATTR_43 | 0x3fc | +| MIO_PAD_ATTR_44 | 0x400 | +| MIO_PAD_ATTR_45 | 0x404 | +| MIO_PAD_ATTR_46 | 0x408 | ### Fields @@ -1002,20 +990,20 @@ Register write enable for DIO PAD attributes. | Name | Offset | |:-----------------------|:---------| -| DIO_PAD_ATTR_REGWEN_0 | 0x424 | -| DIO_PAD_ATTR_REGWEN_1 | 0x428 | -| DIO_PAD_ATTR_REGWEN_2 | 0x42c | -| DIO_PAD_ATTR_REGWEN_3 | 0x430 | -| DIO_PAD_ATTR_REGWEN_4 | 0x434 | -| DIO_PAD_ATTR_REGWEN_5 | 0x438 | -| DIO_PAD_ATTR_REGWEN_6 | 0x43c | -| DIO_PAD_ATTR_REGWEN_7 | 0x440 | -| DIO_PAD_ATTR_REGWEN_8 | 0x444 | -| DIO_PAD_ATTR_REGWEN_9 | 0x448 | -| DIO_PAD_ATTR_REGWEN_10 | 0x44c | -| DIO_PAD_ATTR_REGWEN_11 | 0x450 | -| DIO_PAD_ATTR_REGWEN_12 | 0x454 | -| DIO_PAD_ATTR_REGWEN_13 | 0x458 | +| DIO_PAD_ATTR_REGWEN_0 | 0x40c | +| DIO_PAD_ATTR_REGWEN_1 | 0x410 | +| DIO_PAD_ATTR_REGWEN_2 | 0x414 | +| DIO_PAD_ATTR_REGWEN_3 | 0x418 | +| DIO_PAD_ATTR_REGWEN_4 | 0x41c | +| DIO_PAD_ATTR_REGWEN_5 | 0x420 | +| DIO_PAD_ATTR_REGWEN_6 | 0x424 | +| DIO_PAD_ATTR_REGWEN_7 | 0x428 | +| DIO_PAD_ATTR_REGWEN_8 | 0x42c | +| DIO_PAD_ATTR_REGWEN_9 | 0x430 | +| DIO_PAD_ATTR_REGWEN_10 | 0x434 | +| DIO_PAD_ATTR_REGWEN_11 | 0x438 | +| DIO_PAD_ATTR_REGWEN_12 | 0x43c | +| DIO_PAD_ATTR_REGWEN_13 | 0x440 | ### Fields @@ -1041,20 +1029,20 @@ all attributes. | Name | Offset | |:----------------|:---------| -| DIO_PAD_ATTR_0 | 0x45c | -| DIO_PAD_ATTR_1 | 0x460 | -| DIO_PAD_ATTR_2 | 0x464 | -| DIO_PAD_ATTR_3 | 0x468 | -| DIO_PAD_ATTR_4 | 0x46c | -| DIO_PAD_ATTR_5 | 0x470 | -| DIO_PAD_ATTR_6 | 0x474 | -| DIO_PAD_ATTR_7 | 0x478 | -| DIO_PAD_ATTR_8 | 0x47c | -| DIO_PAD_ATTR_9 | 0x480 | -| DIO_PAD_ATTR_10 | 0x484 | -| DIO_PAD_ATTR_11 | 0x488 | -| DIO_PAD_ATTR_12 | 0x48c | -| DIO_PAD_ATTR_13 | 0x490 | +| DIO_PAD_ATTR_0 | 0x444 | +| DIO_PAD_ATTR_1 | 0x448 | +| DIO_PAD_ATTR_2 | 0x44c | +| DIO_PAD_ATTR_3 | 0x450 | +| DIO_PAD_ATTR_4 | 0x454 | +| DIO_PAD_ATTR_5 | 0x458 | +| DIO_PAD_ATTR_6 | 0x45c | +| DIO_PAD_ATTR_7 | 0x460 | +| DIO_PAD_ATTR_8 | 0x464 | +| DIO_PAD_ATTR_9 | 0x468 | +| DIO_PAD_ATTR_10 | 0x46c | +| DIO_PAD_ATTR_11 | 0x470 | +| DIO_PAD_ATTR_12 | 0x474 | +| DIO_PAD_ATTR_13 | 0x478 | ### Fields @@ -1118,7 +1106,7 @@ Invert input and output levels. ## MIO_PAD_SLEEP_STATUS_0 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x494` +- Offset: `0x47c` - Reset default: `0x0` - Reset mask: `0xffffffff` @@ -1165,7 +1153,7 @@ Register indicating whether the corresponding pad is in sleep mode. ## MIO_PAD_SLEEP_STATUS_1 Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x498` +- Offset: `0x480` - Reset default: `0x0` - Reset mask: `0x7fff` @@ -1203,53 +1191,53 @@ Register write enable for MIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| MIO_PAD_SLEEP_REGWEN_0 | 0x49c | -| MIO_PAD_SLEEP_REGWEN_1 | 0x4a0 | -| MIO_PAD_SLEEP_REGWEN_2 | 0x4a4 | -| MIO_PAD_SLEEP_REGWEN_3 | 0x4a8 | -| MIO_PAD_SLEEP_REGWEN_4 | 0x4ac | -| MIO_PAD_SLEEP_REGWEN_5 | 0x4b0 | -| MIO_PAD_SLEEP_REGWEN_6 | 0x4b4 | -| MIO_PAD_SLEEP_REGWEN_7 | 0x4b8 | -| MIO_PAD_SLEEP_REGWEN_8 | 0x4bc | -| MIO_PAD_SLEEP_REGWEN_9 | 0x4c0 | -| MIO_PAD_SLEEP_REGWEN_10 | 0x4c4 | -| MIO_PAD_SLEEP_REGWEN_11 | 0x4c8 | -| MIO_PAD_SLEEP_REGWEN_12 | 0x4cc | -| MIO_PAD_SLEEP_REGWEN_13 | 0x4d0 | -| MIO_PAD_SLEEP_REGWEN_14 | 0x4d4 | -| MIO_PAD_SLEEP_REGWEN_15 | 0x4d8 | -| MIO_PAD_SLEEP_REGWEN_16 | 0x4dc | -| MIO_PAD_SLEEP_REGWEN_17 | 0x4e0 | -| MIO_PAD_SLEEP_REGWEN_18 | 0x4e4 | -| MIO_PAD_SLEEP_REGWEN_19 | 0x4e8 | -| MIO_PAD_SLEEP_REGWEN_20 | 0x4ec | -| MIO_PAD_SLEEP_REGWEN_21 | 0x4f0 | -| MIO_PAD_SLEEP_REGWEN_22 | 0x4f4 | -| MIO_PAD_SLEEP_REGWEN_23 | 0x4f8 | -| MIO_PAD_SLEEP_REGWEN_24 | 0x4fc | -| MIO_PAD_SLEEP_REGWEN_25 | 0x500 | -| MIO_PAD_SLEEP_REGWEN_26 | 0x504 | -| MIO_PAD_SLEEP_REGWEN_27 | 0x508 | -| MIO_PAD_SLEEP_REGWEN_28 | 0x50c | -| MIO_PAD_SLEEP_REGWEN_29 | 0x510 | -| MIO_PAD_SLEEP_REGWEN_30 | 0x514 | -| MIO_PAD_SLEEP_REGWEN_31 | 0x518 | -| MIO_PAD_SLEEP_REGWEN_32 | 0x51c | -| MIO_PAD_SLEEP_REGWEN_33 | 0x520 | -| MIO_PAD_SLEEP_REGWEN_34 | 0x524 | -| MIO_PAD_SLEEP_REGWEN_35 | 0x528 | -| MIO_PAD_SLEEP_REGWEN_36 | 0x52c | -| MIO_PAD_SLEEP_REGWEN_37 | 0x530 | -| MIO_PAD_SLEEP_REGWEN_38 | 0x534 | -| MIO_PAD_SLEEP_REGWEN_39 | 0x538 | -| MIO_PAD_SLEEP_REGWEN_40 | 0x53c | -| MIO_PAD_SLEEP_REGWEN_41 | 0x540 | -| MIO_PAD_SLEEP_REGWEN_42 | 0x544 | -| MIO_PAD_SLEEP_REGWEN_43 | 0x548 | -| MIO_PAD_SLEEP_REGWEN_44 | 0x54c | -| MIO_PAD_SLEEP_REGWEN_45 | 0x550 | -| MIO_PAD_SLEEP_REGWEN_46 | 0x554 | +| MIO_PAD_SLEEP_REGWEN_0 | 0x484 | +| MIO_PAD_SLEEP_REGWEN_1 | 0x488 | +| MIO_PAD_SLEEP_REGWEN_2 | 0x48c | +| MIO_PAD_SLEEP_REGWEN_3 | 0x490 | +| MIO_PAD_SLEEP_REGWEN_4 | 0x494 | +| MIO_PAD_SLEEP_REGWEN_5 | 0x498 | +| MIO_PAD_SLEEP_REGWEN_6 | 0x49c | +| MIO_PAD_SLEEP_REGWEN_7 | 0x4a0 | +| MIO_PAD_SLEEP_REGWEN_8 | 0x4a4 | +| MIO_PAD_SLEEP_REGWEN_9 | 0x4a8 | +| MIO_PAD_SLEEP_REGWEN_10 | 0x4ac | +| MIO_PAD_SLEEP_REGWEN_11 | 0x4b0 | +| MIO_PAD_SLEEP_REGWEN_12 | 0x4b4 | +| MIO_PAD_SLEEP_REGWEN_13 | 0x4b8 | +| MIO_PAD_SLEEP_REGWEN_14 | 0x4bc | +| MIO_PAD_SLEEP_REGWEN_15 | 0x4c0 | +| MIO_PAD_SLEEP_REGWEN_16 | 0x4c4 | +| MIO_PAD_SLEEP_REGWEN_17 | 0x4c8 | +| MIO_PAD_SLEEP_REGWEN_18 | 0x4cc | +| MIO_PAD_SLEEP_REGWEN_19 | 0x4d0 | +| MIO_PAD_SLEEP_REGWEN_20 | 0x4d4 | +| MIO_PAD_SLEEP_REGWEN_21 | 0x4d8 | +| MIO_PAD_SLEEP_REGWEN_22 | 0x4dc | +| MIO_PAD_SLEEP_REGWEN_23 | 0x4e0 | +| MIO_PAD_SLEEP_REGWEN_24 | 0x4e4 | +| MIO_PAD_SLEEP_REGWEN_25 | 0x4e8 | +| MIO_PAD_SLEEP_REGWEN_26 | 0x4ec | +| MIO_PAD_SLEEP_REGWEN_27 | 0x4f0 | +| MIO_PAD_SLEEP_REGWEN_28 | 0x4f4 | +| MIO_PAD_SLEEP_REGWEN_29 | 0x4f8 | +| MIO_PAD_SLEEP_REGWEN_30 | 0x4fc | +| MIO_PAD_SLEEP_REGWEN_31 | 0x500 | +| MIO_PAD_SLEEP_REGWEN_32 | 0x504 | +| MIO_PAD_SLEEP_REGWEN_33 | 0x508 | +| MIO_PAD_SLEEP_REGWEN_34 | 0x50c | +| MIO_PAD_SLEEP_REGWEN_35 | 0x510 | +| MIO_PAD_SLEEP_REGWEN_36 | 0x514 | +| MIO_PAD_SLEEP_REGWEN_37 | 0x518 | +| MIO_PAD_SLEEP_REGWEN_38 | 0x51c | +| MIO_PAD_SLEEP_REGWEN_39 | 0x520 | +| MIO_PAD_SLEEP_REGWEN_40 | 0x524 | +| MIO_PAD_SLEEP_REGWEN_41 | 0x528 | +| MIO_PAD_SLEEP_REGWEN_42 | 0x52c | +| MIO_PAD_SLEEP_REGWEN_43 | 0x530 | +| MIO_PAD_SLEEP_REGWEN_44 | 0x534 | +| MIO_PAD_SLEEP_REGWEN_45 | 0x538 | +| MIO_PAD_SLEEP_REGWEN_46 | 0x53c | ### Fields @@ -1273,53 +1261,53 @@ Enables the sleep mode of the corresponding muxed pad. | Name | Offset | |:--------------------|:---------| -| MIO_PAD_SLEEP_EN_0 | 0x558 | -| MIO_PAD_SLEEP_EN_1 | 0x55c | -| MIO_PAD_SLEEP_EN_2 | 0x560 | -| MIO_PAD_SLEEP_EN_3 | 0x564 | -| MIO_PAD_SLEEP_EN_4 | 0x568 | -| MIO_PAD_SLEEP_EN_5 | 0x56c | -| MIO_PAD_SLEEP_EN_6 | 0x570 | -| MIO_PAD_SLEEP_EN_7 | 0x574 | -| MIO_PAD_SLEEP_EN_8 | 0x578 | -| MIO_PAD_SLEEP_EN_9 | 0x57c | -| MIO_PAD_SLEEP_EN_10 | 0x580 | -| MIO_PAD_SLEEP_EN_11 | 0x584 | -| MIO_PAD_SLEEP_EN_12 | 0x588 | -| MIO_PAD_SLEEP_EN_13 | 0x58c | -| MIO_PAD_SLEEP_EN_14 | 0x590 | -| MIO_PAD_SLEEP_EN_15 | 0x594 | -| MIO_PAD_SLEEP_EN_16 | 0x598 | -| MIO_PAD_SLEEP_EN_17 | 0x59c | -| MIO_PAD_SLEEP_EN_18 | 0x5a0 | -| MIO_PAD_SLEEP_EN_19 | 0x5a4 | -| MIO_PAD_SLEEP_EN_20 | 0x5a8 | -| MIO_PAD_SLEEP_EN_21 | 0x5ac | -| MIO_PAD_SLEEP_EN_22 | 0x5b0 | -| MIO_PAD_SLEEP_EN_23 | 0x5b4 | -| MIO_PAD_SLEEP_EN_24 | 0x5b8 | -| MIO_PAD_SLEEP_EN_25 | 0x5bc | -| MIO_PAD_SLEEP_EN_26 | 0x5c0 | -| MIO_PAD_SLEEP_EN_27 | 0x5c4 | -| MIO_PAD_SLEEP_EN_28 | 0x5c8 | -| MIO_PAD_SLEEP_EN_29 | 0x5cc | -| MIO_PAD_SLEEP_EN_30 | 0x5d0 | -| MIO_PAD_SLEEP_EN_31 | 0x5d4 | -| MIO_PAD_SLEEP_EN_32 | 0x5d8 | -| MIO_PAD_SLEEP_EN_33 | 0x5dc | -| MIO_PAD_SLEEP_EN_34 | 0x5e0 | -| MIO_PAD_SLEEP_EN_35 | 0x5e4 | -| MIO_PAD_SLEEP_EN_36 | 0x5e8 | -| MIO_PAD_SLEEP_EN_37 | 0x5ec | -| MIO_PAD_SLEEP_EN_38 | 0x5f0 | -| MIO_PAD_SLEEP_EN_39 | 0x5f4 | -| MIO_PAD_SLEEP_EN_40 | 0x5f8 | -| MIO_PAD_SLEEP_EN_41 | 0x5fc | -| MIO_PAD_SLEEP_EN_42 | 0x600 | -| MIO_PAD_SLEEP_EN_43 | 0x604 | -| MIO_PAD_SLEEP_EN_44 | 0x608 | -| MIO_PAD_SLEEP_EN_45 | 0x60c | -| MIO_PAD_SLEEP_EN_46 | 0x610 | +| MIO_PAD_SLEEP_EN_0 | 0x540 | +| MIO_PAD_SLEEP_EN_1 | 0x544 | +| MIO_PAD_SLEEP_EN_2 | 0x548 | +| MIO_PAD_SLEEP_EN_3 | 0x54c | +| MIO_PAD_SLEEP_EN_4 | 0x550 | +| MIO_PAD_SLEEP_EN_5 | 0x554 | +| MIO_PAD_SLEEP_EN_6 | 0x558 | +| MIO_PAD_SLEEP_EN_7 | 0x55c | +| MIO_PAD_SLEEP_EN_8 | 0x560 | +| MIO_PAD_SLEEP_EN_9 | 0x564 | +| MIO_PAD_SLEEP_EN_10 | 0x568 | +| MIO_PAD_SLEEP_EN_11 | 0x56c | +| MIO_PAD_SLEEP_EN_12 | 0x570 | +| MIO_PAD_SLEEP_EN_13 | 0x574 | +| MIO_PAD_SLEEP_EN_14 | 0x578 | +| MIO_PAD_SLEEP_EN_15 | 0x57c | +| MIO_PAD_SLEEP_EN_16 | 0x580 | +| MIO_PAD_SLEEP_EN_17 | 0x584 | +| MIO_PAD_SLEEP_EN_18 | 0x588 | +| MIO_PAD_SLEEP_EN_19 | 0x58c | +| MIO_PAD_SLEEP_EN_20 | 0x590 | +| MIO_PAD_SLEEP_EN_21 | 0x594 | +| MIO_PAD_SLEEP_EN_22 | 0x598 | +| MIO_PAD_SLEEP_EN_23 | 0x59c | +| MIO_PAD_SLEEP_EN_24 | 0x5a0 | +| MIO_PAD_SLEEP_EN_25 | 0x5a4 | +| MIO_PAD_SLEEP_EN_26 | 0x5a8 | +| MIO_PAD_SLEEP_EN_27 | 0x5ac | +| MIO_PAD_SLEEP_EN_28 | 0x5b0 | +| MIO_PAD_SLEEP_EN_29 | 0x5b4 | +| MIO_PAD_SLEEP_EN_30 | 0x5b8 | +| MIO_PAD_SLEEP_EN_31 | 0x5bc | +| MIO_PAD_SLEEP_EN_32 | 0x5c0 | +| MIO_PAD_SLEEP_EN_33 | 0x5c4 | +| MIO_PAD_SLEEP_EN_34 | 0x5c8 | +| MIO_PAD_SLEEP_EN_35 | 0x5cc | +| MIO_PAD_SLEEP_EN_36 | 0x5d0 | +| MIO_PAD_SLEEP_EN_37 | 0x5d4 | +| MIO_PAD_SLEEP_EN_38 | 0x5d8 | +| MIO_PAD_SLEEP_EN_39 | 0x5dc | +| MIO_PAD_SLEEP_EN_40 | 0x5e0 | +| MIO_PAD_SLEEP_EN_41 | 0x5e4 | +| MIO_PAD_SLEEP_EN_42 | 0x5e8 | +| MIO_PAD_SLEEP_EN_43 | 0x5ec | +| MIO_PAD_SLEEP_EN_44 | 0x5f0 | +| MIO_PAD_SLEEP_EN_45 | 0x5f4 | +| MIO_PAD_SLEEP_EN_46 | 0x5f8 | ### Fields @@ -1353,53 +1341,53 @@ Defines sleep behavior of the corresponding muxed pad. | Name | Offset | |:----------------------|:---------| -| MIO_PAD_SLEEP_MODE_0 | 0x614 | -| MIO_PAD_SLEEP_MODE_1 | 0x618 | -| MIO_PAD_SLEEP_MODE_2 | 0x61c | -| MIO_PAD_SLEEP_MODE_3 | 0x620 | -| MIO_PAD_SLEEP_MODE_4 | 0x624 | -| MIO_PAD_SLEEP_MODE_5 | 0x628 | -| MIO_PAD_SLEEP_MODE_6 | 0x62c | -| MIO_PAD_SLEEP_MODE_7 | 0x630 | -| MIO_PAD_SLEEP_MODE_8 | 0x634 | -| MIO_PAD_SLEEP_MODE_9 | 0x638 | -| MIO_PAD_SLEEP_MODE_10 | 0x63c | -| MIO_PAD_SLEEP_MODE_11 | 0x640 | -| MIO_PAD_SLEEP_MODE_12 | 0x644 | -| MIO_PAD_SLEEP_MODE_13 | 0x648 | -| MIO_PAD_SLEEP_MODE_14 | 0x64c | -| MIO_PAD_SLEEP_MODE_15 | 0x650 | -| MIO_PAD_SLEEP_MODE_16 | 0x654 | -| MIO_PAD_SLEEP_MODE_17 | 0x658 | -| MIO_PAD_SLEEP_MODE_18 | 0x65c | -| MIO_PAD_SLEEP_MODE_19 | 0x660 | -| MIO_PAD_SLEEP_MODE_20 | 0x664 | -| MIO_PAD_SLEEP_MODE_21 | 0x668 | -| MIO_PAD_SLEEP_MODE_22 | 0x66c | -| MIO_PAD_SLEEP_MODE_23 | 0x670 | -| MIO_PAD_SLEEP_MODE_24 | 0x674 | -| MIO_PAD_SLEEP_MODE_25 | 0x678 | -| MIO_PAD_SLEEP_MODE_26 | 0x67c | -| MIO_PAD_SLEEP_MODE_27 | 0x680 | -| MIO_PAD_SLEEP_MODE_28 | 0x684 | -| MIO_PAD_SLEEP_MODE_29 | 0x688 | -| MIO_PAD_SLEEP_MODE_30 | 0x68c | -| MIO_PAD_SLEEP_MODE_31 | 0x690 | -| MIO_PAD_SLEEP_MODE_32 | 0x694 | -| MIO_PAD_SLEEP_MODE_33 | 0x698 | -| MIO_PAD_SLEEP_MODE_34 | 0x69c | -| MIO_PAD_SLEEP_MODE_35 | 0x6a0 | -| MIO_PAD_SLEEP_MODE_36 | 0x6a4 | -| MIO_PAD_SLEEP_MODE_37 | 0x6a8 | -| MIO_PAD_SLEEP_MODE_38 | 0x6ac | -| MIO_PAD_SLEEP_MODE_39 | 0x6b0 | -| MIO_PAD_SLEEP_MODE_40 | 0x6b4 | -| MIO_PAD_SLEEP_MODE_41 | 0x6b8 | -| MIO_PAD_SLEEP_MODE_42 | 0x6bc | -| MIO_PAD_SLEEP_MODE_43 | 0x6c0 | -| MIO_PAD_SLEEP_MODE_44 | 0x6c4 | -| MIO_PAD_SLEEP_MODE_45 | 0x6c8 | -| MIO_PAD_SLEEP_MODE_46 | 0x6cc | +| MIO_PAD_SLEEP_MODE_0 | 0x5fc | +| MIO_PAD_SLEEP_MODE_1 | 0x600 | +| MIO_PAD_SLEEP_MODE_2 | 0x604 | +| MIO_PAD_SLEEP_MODE_3 | 0x608 | +| MIO_PAD_SLEEP_MODE_4 | 0x60c | +| MIO_PAD_SLEEP_MODE_5 | 0x610 | +| MIO_PAD_SLEEP_MODE_6 | 0x614 | +| MIO_PAD_SLEEP_MODE_7 | 0x618 | +| MIO_PAD_SLEEP_MODE_8 | 0x61c | +| MIO_PAD_SLEEP_MODE_9 | 0x620 | +| MIO_PAD_SLEEP_MODE_10 | 0x624 | +| MIO_PAD_SLEEP_MODE_11 | 0x628 | +| MIO_PAD_SLEEP_MODE_12 | 0x62c | +| MIO_PAD_SLEEP_MODE_13 | 0x630 | +| MIO_PAD_SLEEP_MODE_14 | 0x634 | +| MIO_PAD_SLEEP_MODE_15 | 0x638 | +| MIO_PAD_SLEEP_MODE_16 | 0x63c | +| MIO_PAD_SLEEP_MODE_17 | 0x640 | +| MIO_PAD_SLEEP_MODE_18 | 0x644 | +| MIO_PAD_SLEEP_MODE_19 | 0x648 | +| MIO_PAD_SLEEP_MODE_20 | 0x64c | +| MIO_PAD_SLEEP_MODE_21 | 0x650 | +| MIO_PAD_SLEEP_MODE_22 | 0x654 | +| MIO_PAD_SLEEP_MODE_23 | 0x658 | +| MIO_PAD_SLEEP_MODE_24 | 0x65c | +| MIO_PAD_SLEEP_MODE_25 | 0x660 | +| MIO_PAD_SLEEP_MODE_26 | 0x664 | +| MIO_PAD_SLEEP_MODE_27 | 0x668 | +| MIO_PAD_SLEEP_MODE_28 | 0x66c | +| MIO_PAD_SLEEP_MODE_29 | 0x670 | +| MIO_PAD_SLEEP_MODE_30 | 0x674 | +| MIO_PAD_SLEEP_MODE_31 | 0x678 | +| MIO_PAD_SLEEP_MODE_32 | 0x67c | +| MIO_PAD_SLEEP_MODE_33 | 0x680 | +| MIO_PAD_SLEEP_MODE_34 | 0x684 | +| MIO_PAD_SLEEP_MODE_35 | 0x688 | +| MIO_PAD_SLEEP_MODE_36 | 0x68c | +| MIO_PAD_SLEEP_MODE_37 | 0x690 | +| MIO_PAD_SLEEP_MODE_38 | 0x694 | +| MIO_PAD_SLEEP_MODE_39 | 0x698 | +| MIO_PAD_SLEEP_MODE_40 | 0x69c | +| MIO_PAD_SLEEP_MODE_41 | 0x6a0 | +| MIO_PAD_SLEEP_MODE_42 | 0x6a4 | +| MIO_PAD_SLEEP_MODE_43 | 0x6a8 | +| MIO_PAD_SLEEP_MODE_44 | 0x6ac | +| MIO_PAD_SLEEP_MODE_45 | 0x6b0 | +| MIO_PAD_SLEEP_MODE_46 | 0x6b4 | ### Fields @@ -1426,7 +1414,7 @@ Value to drive in deep sleep. ## DIO_PAD_SLEEP_STATUS Register indicating whether the corresponding pad is in sleep mode. -- Offset: `0x6d0` +- Offset: `0x6b8` - Reset default: `0x0` - Reset mask: `0x3fff` @@ -1463,20 +1451,20 @@ Register write enable for DIO sleep value configuration. | Name | Offset | |:------------------------|:---------| -| DIO_PAD_SLEEP_REGWEN_0 | 0x6d4 | -| DIO_PAD_SLEEP_REGWEN_1 | 0x6d8 | -| DIO_PAD_SLEEP_REGWEN_2 | 0x6dc | -| DIO_PAD_SLEEP_REGWEN_3 | 0x6e0 | -| DIO_PAD_SLEEP_REGWEN_4 | 0x6e4 | -| DIO_PAD_SLEEP_REGWEN_5 | 0x6e8 | -| DIO_PAD_SLEEP_REGWEN_6 | 0x6ec | -| DIO_PAD_SLEEP_REGWEN_7 | 0x6f0 | -| DIO_PAD_SLEEP_REGWEN_8 | 0x6f4 | -| DIO_PAD_SLEEP_REGWEN_9 | 0x6f8 | -| DIO_PAD_SLEEP_REGWEN_10 | 0x6fc | -| DIO_PAD_SLEEP_REGWEN_11 | 0x700 | -| DIO_PAD_SLEEP_REGWEN_12 | 0x704 | -| DIO_PAD_SLEEP_REGWEN_13 | 0x708 | +| DIO_PAD_SLEEP_REGWEN_0 | 0x6bc | +| DIO_PAD_SLEEP_REGWEN_1 | 0x6c0 | +| DIO_PAD_SLEEP_REGWEN_2 | 0x6c4 | +| DIO_PAD_SLEEP_REGWEN_3 | 0x6c8 | +| DIO_PAD_SLEEP_REGWEN_4 | 0x6cc | +| DIO_PAD_SLEEP_REGWEN_5 | 0x6d0 | +| DIO_PAD_SLEEP_REGWEN_6 | 0x6d4 | +| DIO_PAD_SLEEP_REGWEN_7 | 0x6d8 | +| DIO_PAD_SLEEP_REGWEN_8 | 0x6dc | +| DIO_PAD_SLEEP_REGWEN_9 | 0x6e0 | +| DIO_PAD_SLEEP_REGWEN_10 | 0x6e4 | +| DIO_PAD_SLEEP_REGWEN_11 | 0x6e8 | +| DIO_PAD_SLEEP_REGWEN_12 | 0x6ec | +| DIO_PAD_SLEEP_REGWEN_13 | 0x6f0 | ### Fields @@ -1500,20 +1488,20 @@ Enables the sleep mode of the corresponding dedicated pad. | Name | Offset | |:--------------------|:---------| -| DIO_PAD_SLEEP_EN_0 | 0x70c | -| DIO_PAD_SLEEP_EN_1 | 0x710 | -| DIO_PAD_SLEEP_EN_2 | 0x714 | -| DIO_PAD_SLEEP_EN_3 | 0x718 | -| DIO_PAD_SLEEP_EN_4 | 0x71c | -| DIO_PAD_SLEEP_EN_5 | 0x720 | -| DIO_PAD_SLEEP_EN_6 | 0x724 | -| DIO_PAD_SLEEP_EN_7 | 0x728 | -| DIO_PAD_SLEEP_EN_8 | 0x72c | -| DIO_PAD_SLEEP_EN_9 | 0x730 | -| DIO_PAD_SLEEP_EN_10 | 0x734 | -| DIO_PAD_SLEEP_EN_11 | 0x738 | -| DIO_PAD_SLEEP_EN_12 | 0x73c | -| DIO_PAD_SLEEP_EN_13 | 0x740 | +| DIO_PAD_SLEEP_EN_0 | 0x6f4 | +| DIO_PAD_SLEEP_EN_1 | 0x6f8 | +| DIO_PAD_SLEEP_EN_2 | 0x6fc | +| DIO_PAD_SLEEP_EN_3 | 0x700 | +| DIO_PAD_SLEEP_EN_4 | 0x704 | +| DIO_PAD_SLEEP_EN_5 | 0x708 | +| DIO_PAD_SLEEP_EN_6 | 0x70c | +| DIO_PAD_SLEEP_EN_7 | 0x710 | +| DIO_PAD_SLEEP_EN_8 | 0x714 | +| DIO_PAD_SLEEP_EN_9 | 0x718 | +| DIO_PAD_SLEEP_EN_10 | 0x71c | +| DIO_PAD_SLEEP_EN_11 | 0x720 | +| DIO_PAD_SLEEP_EN_12 | 0x724 | +| DIO_PAD_SLEEP_EN_13 | 0x728 | ### Fields @@ -1547,20 +1535,20 @@ Defines sleep behavior of the corresponding dedicated pad. | Name | Offset | |:----------------------|:---------| -| DIO_PAD_SLEEP_MODE_0 | 0x744 | -| DIO_PAD_SLEEP_MODE_1 | 0x748 | -| DIO_PAD_SLEEP_MODE_2 | 0x74c | -| DIO_PAD_SLEEP_MODE_3 | 0x750 | -| DIO_PAD_SLEEP_MODE_4 | 0x754 | -| DIO_PAD_SLEEP_MODE_5 | 0x758 | -| DIO_PAD_SLEEP_MODE_6 | 0x75c | -| DIO_PAD_SLEEP_MODE_7 | 0x760 | -| DIO_PAD_SLEEP_MODE_8 | 0x764 | -| DIO_PAD_SLEEP_MODE_9 | 0x768 | -| DIO_PAD_SLEEP_MODE_10 | 0x76c | -| DIO_PAD_SLEEP_MODE_11 | 0x770 | -| DIO_PAD_SLEEP_MODE_12 | 0x774 | -| DIO_PAD_SLEEP_MODE_13 | 0x778 | +| DIO_PAD_SLEEP_MODE_0 | 0x72c | +| DIO_PAD_SLEEP_MODE_1 | 0x730 | +| DIO_PAD_SLEEP_MODE_2 | 0x734 | +| DIO_PAD_SLEEP_MODE_3 | 0x738 | +| DIO_PAD_SLEEP_MODE_4 | 0x73c | +| DIO_PAD_SLEEP_MODE_5 | 0x740 | +| DIO_PAD_SLEEP_MODE_6 | 0x744 | +| DIO_PAD_SLEEP_MODE_7 | 0x748 | +| DIO_PAD_SLEEP_MODE_8 | 0x74c | +| DIO_PAD_SLEEP_MODE_9 | 0x750 | +| DIO_PAD_SLEEP_MODE_10 | 0x754 | +| DIO_PAD_SLEEP_MODE_11 | 0x758 | +| DIO_PAD_SLEEP_MODE_12 | 0x75c | +| DIO_PAD_SLEEP_MODE_13 | 0x760 | ### Fields @@ -1594,14 +1582,14 @@ Register write enable for wakeup detectors. | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_REGWEN_0 | 0x77c | -| WKUP_DETECTOR_REGWEN_1 | 0x780 | -| WKUP_DETECTOR_REGWEN_2 | 0x784 | -| WKUP_DETECTOR_REGWEN_3 | 0x788 | -| WKUP_DETECTOR_REGWEN_4 | 0x78c | -| WKUP_DETECTOR_REGWEN_5 | 0x790 | -| WKUP_DETECTOR_REGWEN_6 | 0x794 | -| WKUP_DETECTOR_REGWEN_7 | 0x798 | +| WKUP_DETECTOR_REGWEN_0 | 0x764 | +| WKUP_DETECTOR_REGWEN_1 | 0x768 | +| WKUP_DETECTOR_REGWEN_2 | 0x76c | +| WKUP_DETECTOR_REGWEN_3 | 0x770 | +| WKUP_DETECTOR_REGWEN_4 | 0x774 | +| WKUP_DETECTOR_REGWEN_5 | 0x778 | +| WKUP_DETECTOR_REGWEN_6 | 0x77c | +| WKUP_DETECTOR_REGWEN_7 | 0x780 | ### Fields @@ -1628,14 +1616,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-------------------|:---------| -| WKUP_DETECTOR_EN_0 | 0x79c | -| WKUP_DETECTOR_EN_1 | 0x7a0 | -| WKUP_DETECTOR_EN_2 | 0x7a4 | -| WKUP_DETECTOR_EN_3 | 0x7a8 | -| WKUP_DETECTOR_EN_4 | 0x7ac | -| WKUP_DETECTOR_EN_5 | 0x7b0 | -| WKUP_DETECTOR_EN_6 | 0x7b4 | -| WKUP_DETECTOR_EN_7 | 0x7b8 | +| WKUP_DETECTOR_EN_0 | 0x784 | +| WKUP_DETECTOR_EN_1 | 0x788 | +| WKUP_DETECTOR_EN_2 | 0x78c | +| WKUP_DETECTOR_EN_3 | 0x790 | +| WKUP_DETECTOR_EN_4 | 0x794 | +| WKUP_DETECTOR_EN_5 | 0x798 | +| WKUP_DETECTOR_EN_6 | 0x79c | +| WKUP_DETECTOR_EN_7 | 0x7a0 | ### Fields @@ -1665,14 +1653,14 @@ The reason for that is that the pulse width counter is NOT cleared upon a mode c | Name | Offset | |:----------------|:---------| -| WKUP_DETECTOR_0 | 0x7bc | -| WKUP_DETECTOR_1 | 0x7c0 | -| WKUP_DETECTOR_2 | 0x7c4 | -| WKUP_DETECTOR_3 | 0x7c8 | -| WKUP_DETECTOR_4 | 0x7cc | -| WKUP_DETECTOR_5 | 0x7d0 | -| WKUP_DETECTOR_6 | 0x7d4 | -| WKUP_DETECTOR_7 | 0x7d8 | +| WKUP_DETECTOR_0 | 0x7a4 | +| WKUP_DETECTOR_1 | 0x7a8 | +| WKUP_DETECTOR_2 | 0x7ac | +| WKUP_DETECTOR_3 | 0x7b0 | +| WKUP_DETECTOR_4 | 0x7b4 | +| WKUP_DETECTOR_5 | 0x7b8 | +| WKUP_DETECTOR_6 | 0x7bc | +| WKUP_DETECTOR_7 | 0x7c0 | ### Fields @@ -1723,14 +1711,14 @@ However, read/write accesses following a write will block until that write has c | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_CNT_TH_0 | 0x7dc | -| WKUP_DETECTOR_CNT_TH_1 | 0x7e0 | -| WKUP_DETECTOR_CNT_TH_2 | 0x7e4 | -| WKUP_DETECTOR_CNT_TH_3 | 0x7e8 | -| WKUP_DETECTOR_CNT_TH_4 | 0x7ec | -| WKUP_DETECTOR_CNT_TH_5 | 0x7f0 | -| WKUP_DETECTOR_CNT_TH_6 | 0x7f4 | -| WKUP_DETECTOR_CNT_TH_7 | 0x7f8 | +| WKUP_DETECTOR_CNT_TH_0 | 0x7c4 | +| WKUP_DETECTOR_CNT_TH_1 | 0x7c8 | +| WKUP_DETECTOR_CNT_TH_2 | 0x7cc | +| WKUP_DETECTOR_CNT_TH_3 | 0x7d0 | +| WKUP_DETECTOR_CNT_TH_4 | 0x7d4 | +| WKUP_DETECTOR_CNT_TH_5 | 0x7d8 | +| WKUP_DETECTOR_CNT_TH_6 | 0x7dc | +| WKUP_DETECTOR_CNT_TH_7 | 0x7e0 | ### Fields @@ -1755,14 +1743,14 @@ This register is NOT synced to the AON domain since the muxing mechanism is impl | Name | Offset | |:-----------------------|:---------| -| WKUP_DETECTOR_PADSEL_0 | 0x7fc | -| WKUP_DETECTOR_PADSEL_1 | 0x800 | -| WKUP_DETECTOR_PADSEL_2 | 0x804 | -| WKUP_DETECTOR_PADSEL_3 | 0x808 | -| WKUP_DETECTOR_PADSEL_4 | 0x80c | -| WKUP_DETECTOR_PADSEL_5 | 0x810 | -| WKUP_DETECTOR_PADSEL_6 | 0x814 | -| WKUP_DETECTOR_PADSEL_7 | 0x818 | +| WKUP_DETECTOR_PADSEL_0 | 0x7e4 | +| WKUP_DETECTOR_PADSEL_1 | 0x7e8 | +| WKUP_DETECTOR_PADSEL_2 | 0x7ec | +| WKUP_DETECTOR_PADSEL_3 | 0x7f0 | +| WKUP_DETECTOR_PADSEL_4 | 0x7f4 | +| WKUP_DETECTOR_PADSEL_5 | 0x7f8 | +| WKUP_DETECTOR_PADSEL_6 | 0x7fc | +| WKUP_DETECTOR_PADSEL_7 | 0x800 | ### Fields @@ -1787,7 +1775,7 @@ Cause registers for wakeup detectors. Note that these registers are synced to the always-on clock. The first write access always completes immediately. However, read/write accesses following a write will block until that write has completed. -- Offset: `0x81c` +- Offset: `0x804` - Reset default: `0x0` - Reset mask: `0xff` diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv b/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv index 94867aee09c..8c7ddd00ee7 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_pkg.sv @@ -7,8 +7,8 @@ package pinmux_reg_pkg; // Param list - parameter int NMioPeriphIn = 38; - parameter int NMioPeriphOut = 35; + parameter int NMioPeriphIn = 35; + parameter int NMioPeriphOut = 34; parameter int NMioPads = 47; parameter int NDioPads = 14; parameter int NWkupDetect = 8; @@ -19,7 +19,7 @@ package pinmux_reg_pkg; parameter int BlockAw = 12; // Number of registers for every interface - parameter int NumRegs = 520; + parameter int NumRegs = 514; // Alert indices typedef enum int { @@ -264,8 +264,8 @@ package pinmux_reg_pkg; // Register -> HW type typedef struct packed { - pinmux_reg2hw_alert_test_reg_t alert_test; // [2387:2386] - pinmux_reg2hw_mio_periph_insel_mreg_t [37:0] mio_periph_insel; // [2385:2158] + pinmux_reg2hw_alert_test_reg_t alert_test; // [2369:2368] + pinmux_reg2hw_mio_periph_insel_mreg_t [34:0] mio_periph_insel; // [2367:2158] pinmux_reg2hw_mio_outsel_mreg_t [46:0] mio_outsel; // [2157:1876] pinmux_reg2hw_mio_pad_attr_mreg_t [46:0] mio_pad_attr; // [1875:748] pinmux_reg2hw_dio_pad_attr_mreg_t [13:0] dio_pad_attr; // [747:412] @@ -328,490 +328,484 @@ package pinmux_reg_pkg; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET = 12'h 84; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET = 12'h 88; parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET = 12'h 8c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET = 12'h 90; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET = 12'h 94; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET = 12'h 98; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h 9c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h 100; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h 104; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h 108; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 10c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 110; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 114; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 118; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 11c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 120; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 124; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_35_OFFSET = 12'h 128; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_36_OFFSET = 12'h 12c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_37_OFFSET = 12'h 130; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 134; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 138; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 13c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 140; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 144; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 148; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 14c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 150; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 154; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 158; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 15c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 160; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 164; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 168; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 16c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 170; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 174; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 178; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 17c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 180; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 184; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 188; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 18c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 190; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 194; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 198; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 19c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 1a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 1a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 1a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 1ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 1b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 1b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 1b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 1bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 1c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 1c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 1c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 1cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 1d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 1d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 1d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 1dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 1e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 1e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 1e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 1ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 1f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 1f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 1f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 1fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 200; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 204; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 208; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 20c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 210; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 214; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 218; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 21c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 220; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 224; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 228; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 22c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 230; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 234; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 238; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 23c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 240; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 244; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 248; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 24c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 250; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 254; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 258; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 25c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 260; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 264; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 268; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 26c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 270; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 274; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 278; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 27c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 280; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 284; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 288; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 28c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 290; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 294; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 298; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 29c; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 2a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 2a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 2a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 2ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 2b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 2b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 2b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 2bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 2c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 2c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 2c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 2cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 2d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 2d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 2d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 2dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 2e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 2e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 2e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 2ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 2f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 2f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 2f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 2fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 300; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 304; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 308; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 30c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 310; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 314; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 318; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 31c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 320; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 324; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 328; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 32c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 330; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 334; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 338; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 33c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 340; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 344; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 348; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 34c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 350; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 354; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 358; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 35c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 360; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 364; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 368; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 36c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 370; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 374; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 378; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 37c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 380; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 384; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 388; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 38c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 390; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 394; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 398; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 39c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 3a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 3a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 3a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 3ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 3b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 3b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 3b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 3bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 3c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 3c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 3c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 3cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 3d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 3d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 3d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 3dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 3e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 3e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 3e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 3ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 3f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 3f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 3f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 3fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 400; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 404; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 408; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 40c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 410; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 414; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 418; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 41c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 420; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 424; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 428; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 42c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 430; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 434; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 438; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 43c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 440; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 444; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 448; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 44c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 450; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 454; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 458; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 45c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 460; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 464; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 468; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 46c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 470; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 474; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 478; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 47c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 480; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 484; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 488; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 48c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 490; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 494; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 498; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 49c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 4a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 4a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 4a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 4ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 4b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 4b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 4b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 4bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 4c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 4c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 4c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 4cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 4d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 4d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 4d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 4dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 4e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 4e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 4e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 4ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 4f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 4f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 4f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 4fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 500; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 504; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 508; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 50c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 510; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 514; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 518; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 51c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 520; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 524; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 528; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 52c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 530; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 534; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 538; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 53c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 540; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 544; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 548; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 54c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 550; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 554; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 558; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 55c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 560; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 564; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 568; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 56c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 570; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 574; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 578; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 57c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 580; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 584; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 588; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 58c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 590; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 594; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 598; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 59c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 5a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 5a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 5a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 5ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 5b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 5b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 5b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 5bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 5c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 5c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 5c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 5cc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 5d0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 5d4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 5d8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 5dc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 5e0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 5e4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 5e8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 5ec; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 5f0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 5f4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 5f8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 5fc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 600; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 604; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 608; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 60c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 610; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 614; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 618; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 61c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 620; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 624; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 628; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 62c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 630; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 634; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 638; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 63c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 640; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 644; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 648; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 64c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 650; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 654; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 658; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 65c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 660; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 664; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 668; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 66c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 670; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 674; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 678; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 67c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 680; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 684; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 688; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 68c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 690; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 694; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 698; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 69c; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 6a0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 6a4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 6a8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 6ac; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 6b0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 6b4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 6b8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 6bc; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 6c0; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 6c4; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 6c8; - parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 6cc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 6d0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 6d4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 6d8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 6dc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 6e0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 6e4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 6e8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 6ec; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 6f0; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 6f4; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 6f8; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 6fc; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 700; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 704; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 708; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 70c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 710; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 714; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 718; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 71c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 720; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 724; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 728; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 72c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 730; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 734; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 738; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 73c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 740; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 744; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 748; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 74c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 750; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 754; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 758; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 75c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 760; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 764; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 768; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 76c; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 770; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 774; - parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 778; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 77c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 780; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 784; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 788; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 78c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 790; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 794; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 798; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 79c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 7a0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 7a4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 7a8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 7ac; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 7b0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 7b4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 7b8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 7bc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 7c0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 7c4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 7c8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 7cc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 7d0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 7d4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 7d8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 7dc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 7e0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 7e4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 7e8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 7ec; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 7f0; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 7f4; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 7f8; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 7fc; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 800; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 804; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 808; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 80c; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 810; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 814; - parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 818; - parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 81c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_0_OFFSET = 12'h 90; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_1_OFFSET = 12'h 94; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_2_OFFSET = 12'h 98; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_3_OFFSET = 12'h 9c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_4_OFFSET = 12'h a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_5_OFFSET = 12'h a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_6_OFFSET = 12'h a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_7_OFFSET = 12'h ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_8_OFFSET = 12'h b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_9_OFFSET = 12'h b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_10_OFFSET = 12'h b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_11_OFFSET = 12'h bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_12_OFFSET = 12'h c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_13_OFFSET = 12'h c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_14_OFFSET = 12'h c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_15_OFFSET = 12'h cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_16_OFFSET = 12'h d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_17_OFFSET = 12'h d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_18_OFFSET = 12'h d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_19_OFFSET = 12'h dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_20_OFFSET = 12'h e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_21_OFFSET = 12'h e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_22_OFFSET = 12'h e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_23_OFFSET = 12'h ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_24_OFFSET = 12'h f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_25_OFFSET = 12'h f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_26_OFFSET = 12'h f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_27_OFFSET = 12'h fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_28_OFFSET = 12'h 100; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_29_OFFSET = 12'h 104; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_30_OFFSET = 12'h 108; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_31_OFFSET = 12'h 10c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_32_OFFSET = 12'h 110; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_33_OFFSET = 12'h 114; + parameter logic [BlockAw-1:0] PINMUX_MIO_PERIPH_INSEL_34_OFFSET = 12'h 118; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET = 12'h 11c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET = 12'h 120; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET = 12'h 124; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET = 12'h 128; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET = 12'h 12c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET = 12'h 130; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET = 12'h 134; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET = 12'h 138; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET = 12'h 13c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET = 12'h 140; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET = 12'h 144; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET = 12'h 148; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET = 12'h 14c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET = 12'h 150; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET = 12'h 154; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET = 12'h 158; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET = 12'h 15c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET = 12'h 160; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET = 12'h 164; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET = 12'h 168; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET = 12'h 16c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET = 12'h 170; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET = 12'h 174; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET = 12'h 178; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET = 12'h 17c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET = 12'h 180; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET = 12'h 184; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET = 12'h 188; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET = 12'h 18c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET = 12'h 190; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET = 12'h 194; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET = 12'h 198; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET = 12'h 19c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET = 12'h 1a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET = 12'h 1a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET = 12'h 1a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET = 12'h 1ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET = 12'h 1b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET = 12'h 1b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET = 12'h 1b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET = 12'h 1bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET = 12'h 1c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET = 12'h 1c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET = 12'h 1c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET = 12'h 1cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET = 12'h 1d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET = 12'h 1d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_0_OFFSET = 12'h 1d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_1_OFFSET = 12'h 1dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_2_OFFSET = 12'h 1e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_3_OFFSET = 12'h 1e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_4_OFFSET = 12'h 1e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_5_OFFSET = 12'h 1ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_6_OFFSET = 12'h 1f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_7_OFFSET = 12'h 1f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_8_OFFSET = 12'h 1f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_9_OFFSET = 12'h 1fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_10_OFFSET = 12'h 200; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_11_OFFSET = 12'h 204; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_12_OFFSET = 12'h 208; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_13_OFFSET = 12'h 20c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_14_OFFSET = 12'h 210; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_15_OFFSET = 12'h 214; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_16_OFFSET = 12'h 218; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_17_OFFSET = 12'h 21c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_18_OFFSET = 12'h 220; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_19_OFFSET = 12'h 224; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_20_OFFSET = 12'h 228; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_21_OFFSET = 12'h 22c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_22_OFFSET = 12'h 230; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_23_OFFSET = 12'h 234; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_24_OFFSET = 12'h 238; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_25_OFFSET = 12'h 23c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_26_OFFSET = 12'h 240; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_27_OFFSET = 12'h 244; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_28_OFFSET = 12'h 248; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_29_OFFSET = 12'h 24c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_30_OFFSET = 12'h 250; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_31_OFFSET = 12'h 254; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_32_OFFSET = 12'h 258; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_33_OFFSET = 12'h 25c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_34_OFFSET = 12'h 260; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_35_OFFSET = 12'h 264; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_36_OFFSET = 12'h 268; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_37_OFFSET = 12'h 26c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_38_OFFSET = 12'h 270; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_39_OFFSET = 12'h 274; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_40_OFFSET = 12'h 278; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_41_OFFSET = 12'h 27c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_42_OFFSET = 12'h 280; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_43_OFFSET = 12'h 284; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_44_OFFSET = 12'h 288; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_45_OFFSET = 12'h 28c; + parameter logic [BlockAw-1:0] PINMUX_MIO_OUTSEL_46_OFFSET = 12'h 290; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 294; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 298; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 29c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 2a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 2a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 2a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 2ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 2b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 2b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 2b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 2bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 2c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 2c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 2c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET = 12'h 2cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET = 12'h 2d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET = 12'h 2d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET = 12'h 2d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET = 12'h 2dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET = 12'h 2e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET = 12'h 2e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET = 12'h 2e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET = 12'h 2ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET = 12'h 2f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET = 12'h 2f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET = 12'h 2f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET = 12'h 2fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET = 12'h 300; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET = 12'h 304; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET = 12'h 308; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET = 12'h 30c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET = 12'h 310; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET = 12'h 314; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET = 12'h 318; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET = 12'h 31c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET = 12'h 320; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET = 12'h 324; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET = 12'h 328; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET = 12'h 32c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET = 12'h 330; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET = 12'h 334; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET = 12'h 338; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET = 12'h 33c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET = 12'h 340; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET = 12'h 344; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET = 12'h 348; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET = 12'h 34c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_0_OFFSET = 12'h 350; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_1_OFFSET = 12'h 354; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_2_OFFSET = 12'h 358; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_3_OFFSET = 12'h 35c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_4_OFFSET = 12'h 360; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_5_OFFSET = 12'h 364; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_6_OFFSET = 12'h 368; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_7_OFFSET = 12'h 36c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_8_OFFSET = 12'h 370; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_9_OFFSET = 12'h 374; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_10_OFFSET = 12'h 378; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_11_OFFSET = 12'h 37c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_12_OFFSET = 12'h 380; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_13_OFFSET = 12'h 384; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_14_OFFSET = 12'h 388; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_15_OFFSET = 12'h 38c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_16_OFFSET = 12'h 390; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_17_OFFSET = 12'h 394; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_18_OFFSET = 12'h 398; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_19_OFFSET = 12'h 39c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_20_OFFSET = 12'h 3a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_21_OFFSET = 12'h 3a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_22_OFFSET = 12'h 3a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_23_OFFSET = 12'h 3ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_24_OFFSET = 12'h 3b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_25_OFFSET = 12'h 3b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_26_OFFSET = 12'h 3b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_27_OFFSET = 12'h 3bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_28_OFFSET = 12'h 3c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_29_OFFSET = 12'h 3c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_30_OFFSET = 12'h 3c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_31_OFFSET = 12'h 3cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_32_OFFSET = 12'h 3d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_33_OFFSET = 12'h 3d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_34_OFFSET = 12'h 3d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_35_OFFSET = 12'h 3dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_36_OFFSET = 12'h 3e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_37_OFFSET = 12'h 3e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_38_OFFSET = 12'h 3e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_39_OFFSET = 12'h 3ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_40_OFFSET = 12'h 3f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_41_OFFSET = 12'h 3f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_42_OFFSET = 12'h 3f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_43_OFFSET = 12'h 3fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_44_OFFSET = 12'h 400; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_45_OFFSET = 12'h 404; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_ATTR_46_OFFSET = 12'h 408; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET = 12'h 40c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET = 12'h 410; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET = 12'h 414; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET = 12'h 418; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET = 12'h 41c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET = 12'h 420; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET = 12'h 424; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET = 12'h 428; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET = 12'h 42c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET = 12'h 430; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET = 12'h 434; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET = 12'h 438; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET = 12'h 43c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET = 12'h 440; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_0_OFFSET = 12'h 444; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_1_OFFSET = 12'h 448; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_2_OFFSET = 12'h 44c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_3_OFFSET = 12'h 450; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_4_OFFSET = 12'h 454; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_5_OFFSET = 12'h 458; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_6_OFFSET = 12'h 45c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_7_OFFSET = 12'h 460; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_8_OFFSET = 12'h 464; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_9_OFFSET = 12'h 468; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_10_OFFSET = 12'h 46c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_11_OFFSET = 12'h 470; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_12_OFFSET = 12'h 474; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_ATTR_13_OFFSET = 12'h 478; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET = 12'h 47c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET = 12'h 480; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 484; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 488; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 48c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 490; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 494; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 498; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 49c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 4a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 4a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 4a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 4ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 4b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 4b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 4b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET = 12'h 4bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET = 12'h 4c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET = 12'h 4c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET = 12'h 4c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET = 12'h 4cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET = 12'h 4d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET = 12'h 4d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET = 12'h 4d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET = 12'h 4dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET = 12'h 4e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET = 12'h 4e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET = 12'h 4e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET = 12'h 4ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET = 12'h 4f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET = 12'h 4f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET = 12'h 4f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET = 12'h 4fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET = 12'h 500; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET = 12'h 504; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET = 12'h 508; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET = 12'h 50c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET = 12'h 510; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET = 12'h 514; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET = 12'h 518; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET = 12'h 51c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET = 12'h 520; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET = 12'h 524; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET = 12'h 528; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET = 12'h 52c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET = 12'h 530; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET = 12'h 534; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET = 12'h 538; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET = 12'h 53c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET = 12'h 540; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET = 12'h 544; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET = 12'h 548; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET = 12'h 54c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET = 12'h 550; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET = 12'h 554; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET = 12'h 558; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET = 12'h 55c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET = 12'h 560; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET = 12'h 564; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET = 12'h 568; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET = 12'h 56c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET = 12'h 570; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET = 12'h 574; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET = 12'h 578; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET = 12'h 57c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET = 12'h 580; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET = 12'h 584; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET = 12'h 588; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET = 12'h 58c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET = 12'h 590; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET = 12'h 594; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET = 12'h 598; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET = 12'h 59c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET = 12'h 5a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET = 12'h 5a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET = 12'h 5a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET = 12'h 5ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET = 12'h 5b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET = 12'h 5b4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET = 12'h 5b8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET = 12'h 5bc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET = 12'h 5c0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET = 12'h 5c4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET = 12'h 5c8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET = 12'h 5cc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET = 12'h 5d0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET = 12'h 5d4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET = 12'h 5d8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET = 12'h 5dc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET = 12'h 5e0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET = 12'h 5e4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET = 12'h 5e8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET = 12'h 5ec; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET = 12'h 5f0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET = 12'h 5f4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET = 12'h 5f8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 5fc; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 600; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 604; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 608; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 60c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 610; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 614; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 618; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 61c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 620; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 624; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 628; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 62c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 630; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET = 12'h 634; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET = 12'h 638; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET = 12'h 63c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET = 12'h 640; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET = 12'h 644; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET = 12'h 648; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET = 12'h 64c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET = 12'h 650; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET = 12'h 654; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET = 12'h 658; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET = 12'h 65c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET = 12'h 660; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET = 12'h 664; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET = 12'h 668; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET = 12'h 66c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET = 12'h 670; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET = 12'h 674; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET = 12'h 678; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET = 12'h 67c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET = 12'h 680; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET = 12'h 684; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET = 12'h 688; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET = 12'h 68c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET = 12'h 690; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET = 12'h 694; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET = 12'h 698; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET = 12'h 69c; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET = 12'h 6a0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET = 12'h 6a4; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET = 12'h 6a8; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET = 12'h 6ac; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET = 12'h 6b0; + parameter logic [BlockAw-1:0] PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET = 12'h 6b4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET = 12'h 6b8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET = 12'h 6bc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET = 12'h 6c0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET = 12'h 6c4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET = 12'h 6c8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET = 12'h 6cc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET = 12'h 6d0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET = 12'h 6d4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET = 12'h 6d8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET = 12'h 6dc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET = 12'h 6e0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET = 12'h 6e4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET = 12'h 6e8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET = 12'h 6ec; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET = 12'h 6f0; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET = 12'h 6f4; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET = 12'h 6f8; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET = 12'h 6fc; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET = 12'h 700; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET = 12'h 704; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET = 12'h 708; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET = 12'h 70c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET = 12'h 710; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET = 12'h 714; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET = 12'h 718; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET = 12'h 71c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET = 12'h 720; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET = 12'h 724; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET = 12'h 728; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET = 12'h 72c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET = 12'h 730; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET = 12'h 734; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET = 12'h 738; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET = 12'h 73c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET = 12'h 740; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET = 12'h 744; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET = 12'h 748; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET = 12'h 74c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET = 12'h 750; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET = 12'h 754; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET = 12'h 758; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET = 12'h 75c; + parameter logic [BlockAw-1:0] PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET = 12'h 760; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET = 12'h 764; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET = 12'h 768; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET = 12'h 76c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET = 12'h 770; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET = 12'h 774; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET = 12'h 778; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET = 12'h 77c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET = 12'h 780; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_0_OFFSET = 12'h 784; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_1_OFFSET = 12'h 788; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_2_OFFSET = 12'h 78c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_3_OFFSET = 12'h 790; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_4_OFFSET = 12'h 794; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_5_OFFSET = 12'h 798; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_6_OFFSET = 12'h 79c; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_EN_7_OFFSET = 12'h 7a0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_0_OFFSET = 12'h 7a4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_1_OFFSET = 12'h 7a8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_2_OFFSET = 12'h 7ac; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_3_OFFSET = 12'h 7b0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_4_OFFSET = 12'h 7b4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_5_OFFSET = 12'h 7b8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_6_OFFSET = 12'h 7bc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_7_OFFSET = 12'h 7c0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET = 12'h 7c4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET = 12'h 7c8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET = 12'h 7cc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET = 12'h 7d0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET = 12'h 7d4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET = 12'h 7d8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET = 12'h 7dc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET = 12'h 7e0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET = 12'h 7e4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET = 12'h 7e8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET = 12'h 7ec; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET = 12'h 7f0; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET = 12'h 7f4; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET = 12'h 7f8; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET = 12'h 7fc; + parameter logic [BlockAw-1:0] PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET = 12'h 800; + parameter logic [BlockAw-1:0] PINMUX_WKUP_CAUSE_OFFSET = 12'h 804; // Reset values for hwext registers and their fields parameter logic [0:0] PINMUX_ALERT_TEST_RESVAL = 1'h 0; @@ -1526,9 +1520,6 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_REGWEN_32, PINMUX_MIO_PERIPH_INSEL_REGWEN_33, PINMUX_MIO_PERIPH_INSEL_REGWEN_34, - PINMUX_MIO_PERIPH_INSEL_REGWEN_35, - PINMUX_MIO_PERIPH_INSEL_REGWEN_36, - PINMUX_MIO_PERIPH_INSEL_REGWEN_37, PINMUX_MIO_PERIPH_INSEL_0, PINMUX_MIO_PERIPH_INSEL_1, PINMUX_MIO_PERIPH_INSEL_2, @@ -1564,9 +1555,6 @@ package pinmux_reg_pkg; PINMUX_MIO_PERIPH_INSEL_32, PINMUX_MIO_PERIPH_INSEL_33, PINMUX_MIO_PERIPH_INSEL_34, - PINMUX_MIO_PERIPH_INSEL_35, - PINMUX_MIO_PERIPH_INSEL_36, - PINMUX_MIO_PERIPH_INSEL_37, PINMUX_MIO_OUTSEL_REGWEN_0, PINMUX_MIO_OUTSEL_REGWEN_1, PINMUX_MIO_OUTSEL_REGWEN_2, @@ -2013,7 +2001,7 @@ package pinmux_reg_pkg; } pinmux_id_e; // Register width information to check illegal writes - parameter logic [3:0] PINMUX_PERMIT [520] = '{ + parameter logic [3:0] PINMUX_PERMIT [514] = '{ 4'b 0001, // index[ 0] PINMUX_ALERT_TEST 4'b 0001, // index[ 1] PINMUX_MIO_PERIPH_INSEL_REGWEN_0 4'b 0001, // index[ 2] PINMUX_MIO_PERIPH_INSEL_REGWEN_1 @@ -2050,490 +2038,484 @@ package pinmux_reg_pkg; 4'b 0001, // index[ 33] PINMUX_MIO_PERIPH_INSEL_REGWEN_32 4'b 0001, // index[ 34] PINMUX_MIO_PERIPH_INSEL_REGWEN_33 4'b 0001, // index[ 35] PINMUX_MIO_PERIPH_INSEL_REGWEN_34 - 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_REGWEN_35 - 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_REGWEN_36 - 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_REGWEN_37 - 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_0 - 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_1 - 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_2 - 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_3 - 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_4 - 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_5 - 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_6 - 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_7 - 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_8 - 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_9 - 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_10 - 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_11 - 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_12 - 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_13 - 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_14 - 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_15 - 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_16 - 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_17 - 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_18 - 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_19 - 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_20 - 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_21 - 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_22 - 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_23 - 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_24 - 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_25 - 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_26 - 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_27 - 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_28 - 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_29 - 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_30 - 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_31 - 4'b 0001, // index[ 71] PINMUX_MIO_PERIPH_INSEL_32 - 4'b 0001, // index[ 72] PINMUX_MIO_PERIPH_INSEL_33 - 4'b 0001, // index[ 73] PINMUX_MIO_PERIPH_INSEL_34 - 4'b 0001, // index[ 74] PINMUX_MIO_PERIPH_INSEL_35 - 4'b 0001, // index[ 75] PINMUX_MIO_PERIPH_INSEL_36 - 4'b 0001, // index[ 76] PINMUX_MIO_PERIPH_INSEL_37 - 4'b 0001, // index[ 77] PINMUX_MIO_OUTSEL_REGWEN_0 - 4'b 0001, // index[ 78] PINMUX_MIO_OUTSEL_REGWEN_1 - 4'b 0001, // index[ 79] PINMUX_MIO_OUTSEL_REGWEN_2 - 4'b 0001, // index[ 80] PINMUX_MIO_OUTSEL_REGWEN_3 - 4'b 0001, // index[ 81] PINMUX_MIO_OUTSEL_REGWEN_4 - 4'b 0001, // index[ 82] PINMUX_MIO_OUTSEL_REGWEN_5 - 4'b 0001, // index[ 83] PINMUX_MIO_OUTSEL_REGWEN_6 - 4'b 0001, // index[ 84] PINMUX_MIO_OUTSEL_REGWEN_7 - 4'b 0001, // index[ 85] PINMUX_MIO_OUTSEL_REGWEN_8 - 4'b 0001, // index[ 86] PINMUX_MIO_OUTSEL_REGWEN_9 - 4'b 0001, // index[ 87] PINMUX_MIO_OUTSEL_REGWEN_10 - 4'b 0001, // index[ 88] PINMUX_MIO_OUTSEL_REGWEN_11 - 4'b 0001, // index[ 89] PINMUX_MIO_OUTSEL_REGWEN_12 - 4'b 0001, // index[ 90] PINMUX_MIO_OUTSEL_REGWEN_13 - 4'b 0001, // index[ 91] PINMUX_MIO_OUTSEL_REGWEN_14 - 4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_15 - 4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_16 - 4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_17 - 4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_18 - 4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_19 - 4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_20 - 4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_REGWEN_21 - 4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_REGWEN_22 - 4'b 0001, // index[100] PINMUX_MIO_OUTSEL_REGWEN_23 - 4'b 0001, // index[101] PINMUX_MIO_OUTSEL_REGWEN_24 - 4'b 0001, // index[102] PINMUX_MIO_OUTSEL_REGWEN_25 - 4'b 0001, // index[103] PINMUX_MIO_OUTSEL_REGWEN_26 - 4'b 0001, // index[104] PINMUX_MIO_OUTSEL_REGWEN_27 - 4'b 0001, // index[105] PINMUX_MIO_OUTSEL_REGWEN_28 - 4'b 0001, // index[106] PINMUX_MIO_OUTSEL_REGWEN_29 - 4'b 0001, // index[107] PINMUX_MIO_OUTSEL_REGWEN_30 - 4'b 0001, // index[108] PINMUX_MIO_OUTSEL_REGWEN_31 - 4'b 0001, // index[109] PINMUX_MIO_OUTSEL_REGWEN_32 - 4'b 0001, // index[110] PINMUX_MIO_OUTSEL_REGWEN_33 - 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_34 - 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_35 - 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_36 - 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_REGWEN_37 - 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_38 - 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_39 - 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_40 - 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_REGWEN_41 - 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_REGWEN_42 - 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_REGWEN_43 - 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_REGWEN_44 - 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_REGWEN_45 - 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_REGWEN_46 - 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_0 - 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_1 - 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_2 - 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_3 - 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_4 - 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_5 - 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_6 - 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_7 - 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_8 - 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_9 - 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_10 - 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_11 - 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_12 - 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_13 - 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_14 - 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_15 - 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_16 - 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_17 - 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_18 - 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_19 - 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_20 - 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_21 - 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_22 - 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_23 - 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_24 - 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_25 - 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_26 - 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_27 - 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_28 - 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_29 - 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_30 - 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_31 - 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_32 - 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_33 - 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_34 - 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_35 - 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_36 - 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_37 - 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_38 - 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_39 - 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_40 - 4'b 0001, // index[165] PINMUX_MIO_OUTSEL_41 - 4'b 0001, // index[166] PINMUX_MIO_OUTSEL_42 - 4'b 0001, // index[167] PINMUX_MIO_OUTSEL_43 - 4'b 0001, // index[168] PINMUX_MIO_OUTSEL_44 - 4'b 0001, // index[169] PINMUX_MIO_OUTSEL_45 - 4'b 0001, // index[170] PINMUX_MIO_OUTSEL_46 - 4'b 0001, // index[171] PINMUX_MIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[172] PINMUX_MIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[173] PINMUX_MIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[174] PINMUX_MIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[175] PINMUX_MIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[176] PINMUX_MIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[177] PINMUX_MIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[178] PINMUX_MIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[179] PINMUX_MIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[180] PINMUX_MIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[181] PINMUX_MIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[182] PINMUX_MIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[183] PINMUX_MIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[184] PINMUX_MIO_PAD_ATTR_REGWEN_13 - 4'b 0001, // index[185] PINMUX_MIO_PAD_ATTR_REGWEN_14 - 4'b 0001, // index[186] PINMUX_MIO_PAD_ATTR_REGWEN_15 - 4'b 0001, // index[187] PINMUX_MIO_PAD_ATTR_REGWEN_16 - 4'b 0001, // index[188] PINMUX_MIO_PAD_ATTR_REGWEN_17 - 4'b 0001, // index[189] PINMUX_MIO_PAD_ATTR_REGWEN_18 - 4'b 0001, // index[190] PINMUX_MIO_PAD_ATTR_REGWEN_19 - 4'b 0001, // index[191] PINMUX_MIO_PAD_ATTR_REGWEN_20 - 4'b 0001, // index[192] PINMUX_MIO_PAD_ATTR_REGWEN_21 - 4'b 0001, // index[193] PINMUX_MIO_PAD_ATTR_REGWEN_22 - 4'b 0001, // index[194] PINMUX_MIO_PAD_ATTR_REGWEN_23 - 4'b 0001, // index[195] PINMUX_MIO_PAD_ATTR_REGWEN_24 - 4'b 0001, // index[196] PINMUX_MIO_PAD_ATTR_REGWEN_25 - 4'b 0001, // index[197] PINMUX_MIO_PAD_ATTR_REGWEN_26 - 4'b 0001, // index[198] PINMUX_MIO_PAD_ATTR_REGWEN_27 - 4'b 0001, // index[199] PINMUX_MIO_PAD_ATTR_REGWEN_28 - 4'b 0001, // index[200] PINMUX_MIO_PAD_ATTR_REGWEN_29 - 4'b 0001, // index[201] PINMUX_MIO_PAD_ATTR_REGWEN_30 - 4'b 0001, // index[202] PINMUX_MIO_PAD_ATTR_REGWEN_31 - 4'b 0001, // index[203] PINMUX_MIO_PAD_ATTR_REGWEN_32 - 4'b 0001, // index[204] PINMUX_MIO_PAD_ATTR_REGWEN_33 - 4'b 0001, // index[205] PINMUX_MIO_PAD_ATTR_REGWEN_34 - 4'b 0001, // index[206] PINMUX_MIO_PAD_ATTR_REGWEN_35 - 4'b 0001, // index[207] PINMUX_MIO_PAD_ATTR_REGWEN_36 - 4'b 0001, // index[208] PINMUX_MIO_PAD_ATTR_REGWEN_37 - 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_38 - 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_39 - 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_40 - 4'b 0001, // index[212] PINMUX_MIO_PAD_ATTR_REGWEN_41 - 4'b 0001, // index[213] PINMUX_MIO_PAD_ATTR_REGWEN_42 - 4'b 0001, // index[214] PINMUX_MIO_PAD_ATTR_REGWEN_43 - 4'b 0001, // index[215] PINMUX_MIO_PAD_ATTR_REGWEN_44 - 4'b 0001, // index[216] PINMUX_MIO_PAD_ATTR_REGWEN_45 - 4'b 0001, // index[217] PINMUX_MIO_PAD_ATTR_REGWEN_46 - 4'b 0111, // index[218] PINMUX_MIO_PAD_ATTR_0 - 4'b 0111, // index[219] PINMUX_MIO_PAD_ATTR_1 - 4'b 0111, // index[220] PINMUX_MIO_PAD_ATTR_2 - 4'b 0111, // index[221] PINMUX_MIO_PAD_ATTR_3 - 4'b 0111, // index[222] PINMUX_MIO_PAD_ATTR_4 - 4'b 0111, // index[223] PINMUX_MIO_PAD_ATTR_5 - 4'b 0111, // index[224] PINMUX_MIO_PAD_ATTR_6 - 4'b 0111, // index[225] PINMUX_MIO_PAD_ATTR_7 - 4'b 0111, // index[226] PINMUX_MIO_PAD_ATTR_8 - 4'b 0111, // index[227] PINMUX_MIO_PAD_ATTR_9 - 4'b 0111, // index[228] PINMUX_MIO_PAD_ATTR_10 - 4'b 0111, // index[229] PINMUX_MIO_PAD_ATTR_11 - 4'b 0111, // index[230] PINMUX_MIO_PAD_ATTR_12 - 4'b 0111, // index[231] PINMUX_MIO_PAD_ATTR_13 - 4'b 0111, // index[232] PINMUX_MIO_PAD_ATTR_14 - 4'b 0111, // index[233] PINMUX_MIO_PAD_ATTR_15 - 4'b 0111, // index[234] PINMUX_MIO_PAD_ATTR_16 - 4'b 0111, // index[235] PINMUX_MIO_PAD_ATTR_17 - 4'b 0111, // index[236] PINMUX_MIO_PAD_ATTR_18 - 4'b 0111, // index[237] PINMUX_MIO_PAD_ATTR_19 - 4'b 0111, // index[238] PINMUX_MIO_PAD_ATTR_20 - 4'b 0111, // index[239] PINMUX_MIO_PAD_ATTR_21 - 4'b 0111, // index[240] PINMUX_MIO_PAD_ATTR_22 - 4'b 0111, // index[241] PINMUX_MIO_PAD_ATTR_23 - 4'b 0111, // index[242] PINMUX_MIO_PAD_ATTR_24 - 4'b 0111, // index[243] PINMUX_MIO_PAD_ATTR_25 - 4'b 0111, // index[244] PINMUX_MIO_PAD_ATTR_26 - 4'b 0111, // index[245] PINMUX_MIO_PAD_ATTR_27 - 4'b 0111, // index[246] PINMUX_MIO_PAD_ATTR_28 - 4'b 0111, // index[247] PINMUX_MIO_PAD_ATTR_29 - 4'b 0111, // index[248] PINMUX_MIO_PAD_ATTR_30 - 4'b 0111, // index[249] PINMUX_MIO_PAD_ATTR_31 - 4'b 0111, // index[250] PINMUX_MIO_PAD_ATTR_32 - 4'b 0111, // index[251] PINMUX_MIO_PAD_ATTR_33 - 4'b 0111, // index[252] PINMUX_MIO_PAD_ATTR_34 - 4'b 0111, // index[253] PINMUX_MIO_PAD_ATTR_35 - 4'b 0111, // index[254] PINMUX_MIO_PAD_ATTR_36 - 4'b 0111, // index[255] PINMUX_MIO_PAD_ATTR_37 - 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_38 - 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_39 - 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_40 - 4'b 0111, // index[259] PINMUX_MIO_PAD_ATTR_41 - 4'b 0111, // index[260] PINMUX_MIO_PAD_ATTR_42 - 4'b 0111, // index[261] PINMUX_MIO_PAD_ATTR_43 - 4'b 0111, // index[262] PINMUX_MIO_PAD_ATTR_44 - 4'b 0111, // index[263] PINMUX_MIO_PAD_ATTR_45 - 4'b 0111, // index[264] PINMUX_MIO_PAD_ATTR_46 - 4'b 0001, // index[265] PINMUX_DIO_PAD_ATTR_REGWEN_0 - 4'b 0001, // index[266] PINMUX_DIO_PAD_ATTR_REGWEN_1 - 4'b 0001, // index[267] PINMUX_DIO_PAD_ATTR_REGWEN_2 - 4'b 0001, // index[268] PINMUX_DIO_PAD_ATTR_REGWEN_3 - 4'b 0001, // index[269] PINMUX_DIO_PAD_ATTR_REGWEN_4 - 4'b 0001, // index[270] PINMUX_DIO_PAD_ATTR_REGWEN_5 - 4'b 0001, // index[271] PINMUX_DIO_PAD_ATTR_REGWEN_6 - 4'b 0001, // index[272] PINMUX_DIO_PAD_ATTR_REGWEN_7 - 4'b 0001, // index[273] PINMUX_DIO_PAD_ATTR_REGWEN_8 - 4'b 0001, // index[274] PINMUX_DIO_PAD_ATTR_REGWEN_9 - 4'b 0001, // index[275] PINMUX_DIO_PAD_ATTR_REGWEN_10 - 4'b 0001, // index[276] PINMUX_DIO_PAD_ATTR_REGWEN_11 - 4'b 0001, // index[277] PINMUX_DIO_PAD_ATTR_REGWEN_12 - 4'b 0001, // index[278] PINMUX_DIO_PAD_ATTR_REGWEN_13 - 4'b 0111, // index[279] PINMUX_DIO_PAD_ATTR_0 - 4'b 0111, // index[280] PINMUX_DIO_PAD_ATTR_1 - 4'b 0111, // index[281] PINMUX_DIO_PAD_ATTR_2 - 4'b 0111, // index[282] PINMUX_DIO_PAD_ATTR_3 - 4'b 0111, // index[283] PINMUX_DIO_PAD_ATTR_4 - 4'b 0111, // index[284] PINMUX_DIO_PAD_ATTR_5 - 4'b 0111, // index[285] PINMUX_DIO_PAD_ATTR_6 - 4'b 0111, // index[286] PINMUX_DIO_PAD_ATTR_7 - 4'b 0111, // index[287] PINMUX_DIO_PAD_ATTR_8 - 4'b 0111, // index[288] PINMUX_DIO_PAD_ATTR_9 - 4'b 0111, // index[289] PINMUX_DIO_PAD_ATTR_10 - 4'b 0111, // index[290] PINMUX_DIO_PAD_ATTR_11 - 4'b 0111, // index[291] PINMUX_DIO_PAD_ATTR_12 - 4'b 0111, // index[292] PINMUX_DIO_PAD_ATTR_13 - 4'b 1111, // index[293] PINMUX_MIO_PAD_SLEEP_STATUS_0 - 4'b 0011, // index[294] PINMUX_MIO_PAD_SLEEP_STATUS_1 - 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_REGWEN_14 - 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_REGWEN_15 - 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_REGWEN_16 - 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_REGWEN_17 - 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_REGWEN_18 - 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_REGWEN_19 - 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_REGWEN_20 - 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_REGWEN_21 - 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_REGWEN_22 - 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_REGWEN_23 - 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_REGWEN_24 - 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_REGWEN_25 - 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_REGWEN_26 - 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_REGWEN_27 - 4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_REGWEN_28 - 4'b 0001, // index[324] PINMUX_MIO_PAD_SLEEP_REGWEN_29 - 4'b 0001, // index[325] PINMUX_MIO_PAD_SLEEP_REGWEN_30 - 4'b 0001, // index[326] PINMUX_MIO_PAD_SLEEP_REGWEN_31 - 4'b 0001, // index[327] PINMUX_MIO_PAD_SLEEP_REGWEN_32 - 4'b 0001, // index[328] PINMUX_MIO_PAD_SLEEP_REGWEN_33 - 4'b 0001, // index[329] PINMUX_MIO_PAD_SLEEP_REGWEN_34 - 4'b 0001, // index[330] PINMUX_MIO_PAD_SLEEP_REGWEN_35 - 4'b 0001, // index[331] PINMUX_MIO_PAD_SLEEP_REGWEN_36 - 4'b 0001, // index[332] PINMUX_MIO_PAD_SLEEP_REGWEN_37 - 4'b 0001, // index[333] PINMUX_MIO_PAD_SLEEP_REGWEN_38 - 4'b 0001, // index[334] PINMUX_MIO_PAD_SLEEP_REGWEN_39 - 4'b 0001, // index[335] PINMUX_MIO_PAD_SLEEP_REGWEN_40 - 4'b 0001, // index[336] PINMUX_MIO_PAD_SLEEP_REGWEN_41 - 4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_REGWEN_42 - 4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_REGWEN_43 - 4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_REGWEN_44 - 4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_REGWEN_45 - 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_REGWEN_46 - 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_EN_14 - 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_EN_15 - 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_EN_16 - 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_EN_17 - 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_EN_18 - 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_EN_19 - 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_EN_20 - 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_EN_21 - 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_EN_22 - 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_EN_23 - 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_EN_24 - 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_EN_25 - 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_EN_26 - 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_EN_27 - 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_EN_28 - 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_EN_29 - 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_EN_30 - 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_EN_31 - 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_EN_32 - 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_EN_33 - 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_EN_34 - 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_EN_35 - 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_EN_36 - 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_EN_37 - 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_EN_38 - 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_EN_39 - 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_EN_40 - 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_EN_41 - 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_EN_42 - 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_EN_43 - 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_EN_44 - 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_EN_45 - 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_EN_46 - 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_MODE_14 - 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_MODE_15 - 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_MODE_16 - 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_MODE_17 - 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_MODE_18 - 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_MODE_19 - 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_MODE_20 - 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_MODE_21 - 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_MODE_22 - 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_MODE_23 - 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_MODE_24 - 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_MODE_25 - 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_MODE_26 - 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_MODE_27 - 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_MODE_28 - 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_MODE_29 - 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_MODE_30 - 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_MODE_31 - 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_MODE_32 - 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_MODE_33 - 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_MODE_34 - 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_MODE_35 - 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_MODE_36 - 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_MODE_37 - 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_MODE_38 - 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_MODE_39 - 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_MODE_40 - 4'b 0001, // index[430] PINMUX_MIO_PAD_SLEEP_MODE_41 - 4'b 0001, // index[431] PINMUX_MIO_PAD_SLEEP_MODE_42 - 4'b 0001, // index[432] PINMUX_MIO_PAD_SLEEP_MODE_43 - 4'b 0001, // index[433] PINMUX_MIO_PAD_SLEEP_MODE_44 - 4'b 0001, // index[434] PINMUX_MIO_PAD_SLEEP_MODE_45 - 4'b 0001, // index[435] PINMUX_MIO_PAD_SLEEP_MODE_46 - 4'b 0011, // index[436] PINMUX_DIO_PAD_SLEEP_STATUS - 4'b 0001, // index[437] PINMUX_DIO_PAD_SLEEP_REGWEN_0 - 4'b 0001, // index[438] PINMUX_DIO_PAD_SLEEP_REGWEN_1 - 4'b 0001, // index[439] PINMUX_DIO_PAD_SLEEP_REGWEN_2 - 4'b 0001, // index[440] PINMUX_DIO_PAD_SLEEP_REGWEN_3 - 4'b 0001, // index[441] PINMUX_DIO_PAD_SLEEP_REGWEN_4 - 4'b 0001, // index[442] PINMUX_DIO_PAD_SLEEP_REGWEN_5 - 4'b 0001, // index[443] PINMUX_DIO_PAD_SLEEP_REGWEN_6 - 4'b 0001, // index[444] PINMUX_DIO_PAD_SLEEP_REGWEN_7 - 4'b 0001, // index[445] PINMUX_DIO_PAD_SLEEP_REGWEN_8 - 4'b 0001, // index[446] PINMUX_DIO_PAD_SLEEP_REGWEN_9 - 4'b 0001, // index[447] PINMUX_DIO_PAD_SLEEP_REGWEN_10 - 4'b 0001, // index[448] PINMUX_DIO_PAD_SLEEP_REGWEN_11 - 4'b 0001, // index[449] PINMUX_DIO_PAD_SLEEP_REGWEN_12 - 4'b 0001, // index[450] PINMUX_DIO_PAD_SLEEP_REGWEN_13 - 4'b 0001, // index[451] PINMUX_DIO_PAD_SLEEP_EN_0 - 4'b 0001, // index[452] PINMUX_DIO_PAD_SLEEP_EN_1 - 4'b 0001, // index[453] PINMUX_DIO_PAD_SLEEP_EN_2 - 4'b 0001, // index[454] PINMUX_DIO_PAD_SLEEP_EN_3 - 4'b 0001, // index[455] PINMUX_DIO_PAD_SLEEP_EN_4 - 4'b 0001, // index[456] PINMUX_DIO_PAD_SLEEP_EN_5 - 4'b 0001, // index[457] PINMUX_DIO_PAD_SLEEP_EN_6 - 4'b 0001, // index[458] PINMUX_DIO_PAD_SLEEP_EN_7 - 4'b 0001, // index[459] PINMUX_DIO_PAD_SLEEP_EN_8 - 4'b 0001, // index[460] PINMUX_DIO_PAD_SLEEP_EN_9 - 4'b 0001, // index[461] PINMUX_DIO_PAD_SLEEP_EN_10 - 4'b 0001, // index[462] PINMUX_DIO_PAD_SLEEP_EN_11 - 4'b 0001, // index[463] PINMUX_DIO_PAD_SLEEP_EN_12 - 4'b 0001, // index[464] PINMUX_DIO_PAD_SLEEP_EN_13 - 4'b 0001, // index[465] PINMUX_DIO_PAD_SLEEP_MODE_0 - 4'b 0001, // index[466] PINMUX_DIO_PAD_SLEEP_MODE_1 - 4'b 0001, // index[467] PINMUX_DIO_PAD_SLEEP_MODE_2 - 4'b 0001, // index[468] PINMUX_DIO_PAD_SLEEP_MODE_3 - 4'b 0001, // index[469] PINMUX_DIO_PAD_SLEEP_MODE_4 - 4'b 0001, // index[470] PINMUX_DIO_PAD_SLEEP_MODE_5 - 4'b 0001, // index[471] PINMUX_DIO_PAD_SLEEP_MODE_6 - 4'b 0001, // index[472] PINMUX_DIO_PAD_SLEEP_MODE_7 - 4'b 0001, // index[473] PINMUX_DIO_PAD_SLEEP_MODE_8 - 4'b 0001, // index[474] PINMUX_DIO_PAD_SLEEP_MODE_9 - 4'b 0001, // index[475] PINMUX_DIO_PAD_SLEEP_MODE_10 - 4'b 0001, // index[476] PINMUX_DIO_PAD_SLEEP_MODE_11 - 4'b 0001, // index[477] PINMUX_DIO_PAD_SLEEP_MODE_12 - 4'b 0001, // index[478] PINMUX_DIO_PAD_SLEEP_MODE_13 - 4'b 0001, // index[479] PINMUX_WKUP_DETECTOR_REGWEN_0 - 4'b 0001, // index[480] PINMUX_WKUP_DETECTOR_REGWEN_1 - 4'b 0001, // index[481] PINMUX_WKUP_DETECTOR_REGWEN_2 - 4'b 0001, // index[482] PINMUX_WKUP_DETECTOR_REGWEN_3 - 4'b 0001, // index[483] PINMUX_WKUP_DETECTOR_REGWEN_4 - 4'b 0001, // index[484] PINMUX_WKUP_DETECTOR_REGWEN_5 - 4'b 0001, // index[485] PINMUX_WKUP_DETECTOR_REGWEN_6 - 4'b 0001, // index[486] PINMUX_WKUP_DETECTOR_REGWEN_7 - 4'b 0001, // index[487] PINMUX_WKUP_DETECTOR_EN_0 - 4'b 0001, // index[488] PINMUX_WKUP_DETECTOR_EN_1 - 4'b 0001, // index[489] PINMUX_WKUP_DETECTOR_EN_2 - 4'b 0001, // index[490] PINMUX_WKUP_DETECTOR_EN_3 - 4'b 0001, // index[491] PINMUX_WKUP_DETECTOR_EN_4 - 4'b 0001, // index[492] PINMUX_WKUP_DETECTOR_EN_5 - 4'b 0001, // index[493] PINMUX_WKUP_DETECTOR_EN_6 - 4'b 0001, // index[494] PINMUX_WKUP_DETECTOR_EN_7 - 4'b 0001, // index[495] PINMUX_WKUP_DETECTOR_0 - 4'b 0001, // index[496] PINMUX_WKUP_DETECTOR_1 - 4'b 0001, // index[497] PINMUX_WKUP_DETECTOR_2 - 4'b 0001, // index[498] PINMUX_WKUP_DETECTOR_3 - 4'b 0001, // index[499] PINMUX_WKUP_DETECTOR_4 - 4'b 0001, // index[500] PINMUX_WKUP_DETECTOR_5 - 4'b 0001, // index[501] PINMUX_WKUP_DETECTOR_6 - 4'b 0001, // index[502] PINMUX_WKUP_DETECTOR_7 - 4'b 0001, // index[503] PINMUX_WKUP_DETECTOR_CNT_TH_0 - 4'b 0001, // index[504] PINMUX_WKUP_DETECTOR_CNT_TH_1 - 4'b 0001, // index[505] PINMUX_WKUP_DETECTOR_CNT_TH_2 - 4'b 0001, // index[506] PINMUX_WKUP_DETECTOR_CNT_TH_3 - 4'b 0001, // index[507] PINMUX_WKUP_DETECTOR_CNT_TH_4 - 4'b 0001, // index[508] PINMUX_WKUP_DETECTOR_CNT_TH_5 - 4'b 0001, // index[509] PINMUX_WKUP_DETECTOR_CNT_TH_6 - 4'b 0001, // index[510] PINMUX_WKUP_DETECTOR_CNT_TH_7 - 4'b 0001, // index[511] PINMUX_WKUP_DETECTOR_PADSEL_0 - 4'b 0001, // index[512] PINMUX_WKUP_DETECTOR_PADSEL_1 - 4'b 0001, // index[513] PINMUX_WKUP_DETECTOR_PADSEL_2 - 4'b 0001, // index[514] PINMUX_WKUP_DETECTOR_PADSEL_3 - 4'b 0001, // index[515] PINMUX_WKUP_DETECTOR_PADSEL_4 - 4'b 0001, // index[516] PINMUX_WKUP_DETECTOR_PADSEL_5 - 4'b 0001, // index[517] PINMUX_WKUP_DETECTOR_PADSEL_6 - 4'b 0001, // index[518] PINMUX_WKUP_DETECTOR_PADSEL_7 - 4'b 0001 // index[519] PINMUX_WKUP_CAUSE + 4'b 0001, // index[ 36] PINMUX_MIO_PERIPH_INSEL_0 + 4'b 0001, // index[ 37] PINMUX_MIO_PERIPH_INSEL_1 + 4'b 0001, // index[ 38] PINMUX_MIO_PERIPH_INSEL_2 + 4'b 0001, // index[ 39] PINMUX_MIO_PERIPH_INSEL_3 + 4'b 0001, // index[ 40] PINMUX_MIO_PERIPH_INSEL_4 + 4'b 0001, // index[ 41] PINMUX_MIO_PERIPH_INSEL_5 + 4'b 0001, // index[ 42] PINMUX_MIO_PERIPH_INSEL_6 + 4'b 0001, // index[ 43] PINMUX_MIO_PERIPH_INSEL_7 + 4'b 0001, // index[ 44] PINMUX_MIO_PERIPH_INSEL_8 + 4'b 0001, // index[ 45] PINMUX_MIO_PERIPH_INSEL_9 + 4'b 0001, // index[ 46] PINMUX_MIO_PERIPH_INSEL_10 + 4'b 0001, // index[ 47] PINMUX_MIO_PERIPH_INSEL_11 + 4'b 0001, // index[ 48] PINMUX_MIO_PERIPH_INSEL_12 + 4'b 0001, // index[ 49] PINMUX_MIO_PERIPH_INSEL_13 + 4'b 0001, // index[ 50] PINMUX_MIO_PERIPH_INSEL_14 + 4'b 0001, // index[ 51] PINMUX_MIO_PERIPH_INSEL_15 + 4'b 0001, // index[ 52] PINMUX_MIO_PERIPH_INSEL_16 + 4'b 0001, // index[ 53] PINMUX_MIO_PERIPH_INSEL_17 + 4'b 0001, // index[ 54] PINMUX_MIO_PERIPH_INSEL_18 + 4'b 0001, // index[ 55] PINMUX_MIO_PERIPH_INSEL_19 + 4'b 0001, // index[ 56] PINMUX_MIO_PERIPH_INSEL_20 + 4'b 0001, // index[ 57] PINMUX_MIO_PERIPH_INSEL_21 + 4'b 0001, // index[ 58] PINMUX_MIO_PERIPH_INSEL_22 + 4'b 0001, // index[ 59] PINMUX_MIO_PERIPH_INSEL_23 + 4'b 0001, // index[ 60] PINMUX_MIO_PERIPH_INSEL_24 + 4'b 0001, // index[ 61] PINMUX_MIO_PERIPH_INSEL_25 + 4'b 0001, // index[ 62] PINMUX_MIO_PERIPH_INSEL_26 + 4'b 0001, // index[ 63] PINMUX_MIO_PERIPH_INSEL_27 + 4'b 0001, // index[ 64] PINMUX_MIO_PERIPH_INSEL_28 + 4'b 0001, // index[ 65] PINMUX_MIO_PERIPH_INSEL_29 + 4'b 0001, // index[ 66] PINMUX_MIO_PERIPH_INSEL_30 + 4'b 0001, // index[ 67] PINMUX_MIO_PERIPH_INSEL_31 + 4'b 0001, // index[ 68] PINMUX_MIO_PERIPH_INSEL_32 + 4'b 0001, // index[ 69] PINMUX_MIO_PERIPH_INSEL_33 + 4'b 0001, // index[ 70] PINMUX_MIO_PERIPH_INSEL_34 + 4'b 0001, // index[ 71] PINMUX_MIO_OUTSEL_REGWEN_0 + 4'b 0001, // index[ 72] PINMUX_MIO_OUTSEL_REGWEN_1 + 4'b 0001, // index[ 73] PINMUX_MIO_OUTSEL_REGWEN_2 + 4'b 0001, // index[ 74] PINMUX_MIO_OUTSEL_REGWEN_3 + 4'b 0001, // index[ 75] PINMUX_MIO_OUTSEL_REGWEN_4 + 4'b 0001, // index[ 76] PINMUX_MIO_OUTSEL_REGWEN_5 + 4'b 0001, // index[ 77] PINMUX_MIO_OUTSEL_REGWEN_6 + 4'b 0001, // index[ 78] PINMUX_MIO_OUTSEL_REGWEN_7 + 4'b 0001, // index[ 79] PINMUX_MIO_OUTSEL_REGWEN_8 + 4'b 0001, // index[ 80] PINMUX_MIO_OUTSEL_REGWEN_9 + 4'b 0001, // index[ 81] PINMUX_MIO_OUTSEL_REGWEN_10 + 4'b 0001, // index[ 82] PINMUX_MIO_OUTSEL_REGWEN_11 + 4'b 0001, // index[ 83] PINMUX_MIO_OUTSEL_REGWEN_12 + 4'b 0001, // index[ 84] PINMUX_MIO_OUTSEL_REGWEN_13 + 4'b 0001, // index[ 85] PINMUX_MIO_OUTSEL_REGWEN_14 + 4'b 0001, // index[ 86] PINMUX_MIO_OUTSEL_REGWEN_15 + 4'b 0001, // index[ 87] PINMUX_MIO_OUTSEL_REGWEN_16 + 4'b 0001, // index[ 88] PINMUX_MIO_OUTSEL_REGWEN_17 + 4'b 0001, // index[ 89] PINMUX_MIO_OUTSEL_REGWEN_18 + 4'b 0001, // index[ 90] PINMUX_MIO_OUTSEL_REGWEN_19 + 4'b 0001, // index[ 91] PINMUX_MIO_OUTSEL_REGWEN_20 + 4'b 0001, // index[ 92] PINMUX_MIO_OUTSEL_REGWEN_21 + 4'b 0001, // index[ 93] PINMUX_MIO_OUTSEL_REGWEN_22 + 4'b 0001, // index[ 94] PINMUX_MIO_OUTSEL_REGWEN_23 + 4'b 0001, // index[ 95] PINMUX_MIO_OUTSEL_REGWEN_24 + 4'b 0001, // index[ 96] PINMUX_MIO_OUTSEL_REGWEN_25 + 4'b 0001, // index[ 97] PINMUX_MIO_OUTSEL_REGWEN_26 + 4'b 0001, // index[ 98] PINMUX_MIO_OUTSEL_REGWEN_27 + 4'b 0001, // index[ 99] PINMUX_MIO_OUTSEL_REGWEN_28 + 4'b 0001, // index[100] PINMUX_MIO_OUTSEL_REGWEN_29 + 4'b 0001, // index[101] PINMUX_MIO_OUTSEL_REGWEN_30 + 4'b 0001, // index[102] PINMUX_MIO_OUTSEL_REGWEN_31 + 4'b 0001, // index[103] PINMUX_MIO_OUTSEL_REGWEN_32 + 4'b 0001, // index[104] PINMUX_MIO_OUTSEL_REGWEN_33 + 4'b 0001, // index[105] PINMUX_MIO_OUTSEL_REGWEN_34 + 4'b 0001, // index[106] PINMUX_MIO_OUTSEL_REGWEN_35 + 4'b 0001, // index[107] PINMUX_MIO_OUTSEL_REGWEN_36 + 4'b 0001, // index[108] PINMUX_MIO_OUTSEL_REGWEN_37 + 4'b 0001, // index[109] PINMUX_MIO_OUTSEL_REGWEN_38 + 4'b 0001, // index[110] PINMUX_MIO_OUTSEL_REGWEN_39 + 4'b 0001, // index[111] PINMUX_MIO_OUTSEL_REGWEN_40 + 4'b 0001, // index[112] PINMUX_MIO_OUTSEL_REGWEN_41 + 4'b 0001, // index[113] PINMUX_MIO_OUTSEL_REGWEN_42 + 4'b 0001, // index[114] PINMUX_MIO_OUTSEL_REGWEN_43 + 4'b 0001, // index[115] PINMUX_MIO_OUTSEL_REGWEN_44 + 4'b 0001, // index[116] PINMUX_MIO_OUTSEL_REGWEN_45 + 4'b 0001, // index[117] PINMUX_MIO_OUTSEL_REGWEN_46 + 4'b 0001, // index[118] PINMUX_MIO_OUTSEL_0 + 4'b 0001, // index[119] PINMUX_MIO_OUTSEL_1 + 4'b 0001, // index[120] PINMUX_MIO_OUTSEL_2 + 4'b 0001, // index[121] PINMUX_MIO_OUTSEL_3 + 4'b 0001, // index[122] PINMUX_MIO_OUTSEL_4 + 4'b 0001, // index[123] PINMUX_MIO_OUTSEL_5 + 4'b 0001, // index[124] PINMUX_MIO_OUTSEL_6 + 4'b 0001, // index[125] PINMUX_MIO_OUTSEL_7 + 4'b 0001, // index[126] PINMUX_MIO_OUTSEL_8 + 4'b 0001, // index[127] PINMUX_MIO_OUTSEL_9 + 4'b 0001, // index[128] PINMUX_MIO_OUTSEL_10 + 4'b 0001, // index[129] PINMUX_MIO_OUTSEL_11 + 4'b 0001, // index[130] PINMUX_MIO_OUTSEL_12 + 4'b 0001, // index[131] PINMUX_MIO_OUTSEL_13 + 4'b 0001, // index[132] PINMUX_MIO_OUTSEL_14 + 4'b 0001, // index[133] PINMUX_MIO_OUTSEL_15 + 4'b 0001, // index[134] PINMUX_MIO_OUTSEL_16 + 4'b 0001, // index[135] PINMUX_MIO_OUTSEL_17 + 4'b 0001, // index[136] PINMUX_MIO_OUTSEL_18 + 4'b 0001, // index[137] PINMUX_MIO_OUTSEL_19 + 4'b 0001, // index[138] PINMUX_MIO_OUTSEL_20 + 4'b 0001, // index[139] PINMUX_MIO_OUTSEL_21 + 4'b 0001, // index[140] PINMUX_MIO_OUTSEL_22 + 4'b 0001, // index[141] PINMUX_MIO_OUTSEL_23 + 4'b 0001, // index[142] PINMUX_MIO_OUTSEL_24 + 4'b 0001, // index[143] PINMUX_MIO_OUTSEL_25 + 4'b 0001, // index[144] PINMUX_MIO_OUTSEL_26 + 4'b 0001, // index[145] PINMUX_MIO_OUTSEL_27 + 4'b 0001, // index[146] PINMUX_MIO_OUTSEL_28 + 4'b 0001, // index[147] PINMUX_MIO_OUTSEL_29 + 4'b 0001, // index[148] PINMUX_MIO_OUTSEL_30 + 4'b 0001, // index[149] PINMUX_MIO_OUTSEL_31 + 4'b 0001, // index[150] PINMUX_MIO_OUTSEL_32 + 4'b 0001, // index[151] PINMUX_MIO_OUTSEL_33 + 4'b 0001, // index[152] PINMUX_MIO_OUTSEL_34 + 4'b 0001, // index[153] PINMUX_MIO_OUTSEL_35 + 4'b 0001, // index[154] PINMUX_MIO_OUTSEL_36 + 4'b 0001, // index[155] PINMUX_MIO_OUTSEL_37 + 4'b 0001, // index[156] PINMUX_MIO_OUTSEL_38 + 4'b 0001, // index[157] PINMUX_MIO_OUTSEL_39 + 4'b 0001, // index[158] PINMUX_MIO_OUTSEL_40 + 4'b 0001, // index[159] PINMUX_MIO_OUTSEL_41 + 4'b 0001, // index[160] PINMUX_MIO_OUTSEL_42 + 4'b 0001, // index[161] PINMUX_MIO_OUTSEL_43 + 4'b 0001, // index[162] PINMUX_MIO_OUTSEL_44 + 4'b 0001, // index[163] PINMUX_MIO_OUTSEL_45 + 4'b 0001, // index[164] PINMUX_MIO_OUTSEL_46 + 4'b 0001, // index[165] PINMUX_MIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[166] PINMUX_MIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[167] PINMUX_MIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[168] PINMUX_MIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[169] PINMUX_MIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[170] PINMUX_MIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[171] PINMUX_MIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[172] PINMUX_MIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[173] PINMUX_MIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[174] PINMUX_MIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[175] PINMUX_MIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[176] PINMUX_MIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[177] PINMUX_MIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[178] PINMUX_MIO_PAD_ATTR_REGWEN_13 + 4'b 0001, // index[179] PINMUX_MIO_PAD_ATTR_REGWEN_14 + 4'b 0001, // index[180] PINMUX_MIO_PAD_ATTR_REGWEN_15 + 4'b 0001, // index[181] PINMUX_MIO_PAD_ATTR_REGWEN_16 + 4'b 0001, // index[182] PINMUX_MIO_PAD_ATTR_REGWEN_17 + 4'b 0001, // index[183] PINMUX_MIO_PAD_ATTR_REGWEN_18 + 4'b 0001, // index[184] PINMUX_MIO_PAD_ATTR_REGWEN_19 + 4'b 0001, // index[185] PINMUX_MIO_PAD_ATTR_REGWEN_20 + 4'b 0001, // index[186] PINMUX_MIO_PAD_ATTR_REGWEN_21 + 4'b 0001, // index[187] PINMUX_MIO_PAD_ATTR_REGWEN_22 + 4'b 0001, // index[188] PINMUX_MIO_PAD_ATTR_REGWEN_23 + 4'b 0001, // index[189] PINMUX_MIO_PAD_ATTR_REGWEN_24 + 4'b 0001, // index[190] PINMUX_MIO_PAD_ATTR_REGWEN_25 + 4'b 0001, // index[191] PINMUX_MIO_PAD_ATTR_REGWEN_26 + 4'b 0001, // index[192] PINMUX_MIO_PAD_ATTR_REGWEN_27 + 4'b 0001, // index[193] PINMUX_MIO_PAD_ATTR_REGWEN_28 + 4'b 0001, // index[194] PINMUX_MIO_PAD_ATTR_REGWEN_29 + 4'b 0001, // index[195] PINMUX_MIO_PAD_ATTR_REGWEN_30 + 4'b 0001, // index[196] PINMUX_MIO_PAD_ATTR_REGWEN_31 + 4'b 0001, // index[197] PINMUX_MIO_PAD_ATTR_REGWEN_32 + 4'b 0001, // index[198] PINMUX_MIO_PAD_ATTR_REGWEN_33 + 4'b 0001, // index[199] PINMUX_MIO_PAD_ATTR_REGWEN_34 + 4'b 0001, // index[200] PINMUX_MIO_PAD_ATTR_REGWEN_35 + 4'b 0001, // index[201] PINMUX_MIO_PAD_ATTR_REGWEN_36 + 4'b 0001, // index[202] PINMUX_MIO_PAD_ATTR_REGWEN_37 + 4'b 0001, // index[203] PINMUX_MIO_PAD_ATTR_REGWEN_38 + 4'b 0001, // index[204] PINMUX_MIO_PAD_ATTR_REGWEN_39 + 4'b 0001, // index[205] PINMUX_MIO_PAD_ATTR_REGWEN_40 + 4'b 0001, // index[206] PINMUX_MIO_PAD_ATTR_REGWEN_41 + 4'b 0001, // index[207] PINMUX_MIO_PAD_ATTR_REGWEN_42 + 4'b 0001, // index[208] PINMUX_MIO_PAD_ATTR_REGWEN_43 + 4'b 0001, // index[209] PINMUX_MIO_PAD_ATTR_REGWEN_44 + 4'b 0001, // index[210] PINMUX_MIO_PAD_ATTR_REGWEN_45 + 4'b 0001, // index[211] PINMUX_MIO_PAD_ATTR_REGWEN_46 + 4'b 0111, // index[212] PINMUX_MIO_PAD_ATTR_0 + 4'b 0111, // index[213] PINMUX_MIO_PAD_ATTR_1 + 4'b 0111, // index[214] PINMUX_MIO_PAD_ATTR_2 + 4'b 0111, // index[215] PINMUX_MIO_PAD_ATTR_3 + 4'b 0111, // index[216] PINMUX_MIO_PAD_ATTR_4 + 4'b 0111, // index[217] PINMUX_MIO_PAD_ATTR_5 + 4'b 0111, // index[218] PINMUX_MIO_PAD_ATTR_6 + 4'b 0111, // index[219] PINMUX_MIO_PAD_ATTR_7 + 4'b 0111, // index[220] PINMUX_MIO_PAD_ATTR_8 + 4'b 0111, // index[221] PINMUX_MIO_PAD_ATTR_9 + 4'b 0111, // index[222] PINMUX_MIO_PAD_ATTR_10 + 4'b 0111, // index[223] PINMUX_MIO_PAD_ATTR_11 + 4'b 0111, // index[224] PINMUX_MIO_PAD_ATTR_12 + 4'b 0111, // index[225] PINMUX_MIO_PAD_ATTR_13 + 4'b 0111, // index[226] PINMUX_MIO_PAD_ATTR_14 + 4'b 0111, // index[227] PINMUX_MIO_PAD_ATTR_15 + 4'b 0111, // index[228] PINMUX_MIO_PAD_ATTR_16 + 4'b 0111, // index[229] PINMUX_MIO_PAD_ATTR_17 + 4'b 0111, // index[230] PINMUX_MIO_PAD_ATTR_18 + 4'b 0111, // index[231] PINMUX_MIO_PAD_ATTR_19 + 4'b 0111, // index[232] PINMUX_MIO_PAD_ATTR_20 + 4'b 0111, // index[233] PINMUX_MIO_PAD_ATTR_21 + 4'b 0111, // index[234] PINMUX_MIO_PAD_ATTR_22 + 4'b 0111, // index[235] PINMUX_MIO_PAD_ATTR_23 + 4'b 0111, // index[236] PINMUX_MIO_PAD_ATTR_24 + 4'b 0111, // index[237] PINMUX_MIO_PAD_ATTR_25 + 4'b 0111, // index[238] PINMUX_MIO_PAD_ATTR_26 + 4'b 0111, // index[239] PINMUX_MIO_PAD_ATTR_27 + 4'b 0111, // index[240] PINMUX_MIO_PAD_ATTR_28 + 4'b 0111, // index[241] PINMUX_MIO_PAD_ATTR_29 + 4'b 0111, // index[242] PINMUX_MIO_PAD_ATTR_30 + 4'b 0111, // index[243] PINMUX_MIO_PAD_ATTR_31 + 4'b 0111, // index[244] PINMUX_MIO_PAD_ATTR_32 + 4'b 0111, // index[245] PINMUX_MIO_PAD_ATTR_33 + 4'b 0111, // index[246] PINMUX_MIO_PAD_ATTR_34 + 4'b 0111, // index[247] PINMUX_MIO_PAD_ATTR_35 + 4'b 0111, // index[248] PINMUX_MIO_PAD_ATTR_36 + 4'b 0111, // index[249] PINMUX_MIO_PAD_ATTR_37 + 4'b 0111, // index[250] PINMUX_MIO_PAD_ATTR_38 + 4'b 0111, // index[251] PINMUX_MIO_PAD_ATTR_39 + 4'b 0111, // index[252] PINMUX_MIO_PAD_ATTR_40 + 4'b 0111, // index[253] PINMUX_MIO_PAD_ATTR_41 + 4'b 0111, // index[254] PINMUX_MIO_PAD_ATTR_42 + 4'b 0111, // index[255] PINMUX_MIO_PAD_ATTR_43 + 4'b 0111, // index[256] PINMUX_MIO_PAD_ATTR_44 + 4'b 0111, // index[257] PINMUX_MIO_PAD_ATTR_45 + 4'b 0111, // index[258] PINMUX_MIO_PAD_ATTR_46 + 4'b 0001, // index[259] PINMUX_DIO_PAD_ATTR_REGWEN_0 + 4'b 0001, // index[260] PINMUX_DIO_PAD_ATTR_REGWEN_1 + 4'b 0001, // index[261] PINMUX_DIO_PAD_ATTR_REGWEN_2 + 4'b 0001, // index[262] PINMUX_DIO_PAD_ATTR_REGWEN_3 + 4'b 0001, // index[263] PINMUX_DIO_PAD_ATTR_REGWEN_4 + 4'b 0001, // index[264] PINMUX_DIO_PAD_ATTR_REGWEN_5 + 4'b 0001, // index[265] PINMUX_DIO_PAD_ATTR_REGWEN_6 + 4'b 0001, // index[266] PINMUX_DIO_PAD_ATTR_REGWEN_7 + 4'b 0001, // index[267] PINMUX_DIO_PAD_ATTR_REGWEN_8 + 4'b 0001, // index[268] PINMUX_DIO_PAD_ATTR_REGWEN_9 + 4'b 0001, // index[269] PINMUX_DIO_PAD_ATTR_REGWEN_10 + 4'b 0001, // index[270] PINMUX_DIO_PAD_ATTR_REGWEN_11 + 4'b 0001, // index[271] PINMUX_DIO_PAD_ATTR_REGWEN_12 + 4'b 0001, // index[272] PINMUX_DIO_PAD_ATTR_REGWEN_13 + 4'b 0111, // index[273] PINMUX_DIO_PAD_ATTR_0 + 4'b 0111, // index[274] PINMUX_DIO_PAD_ATTR_1 + 4'b 0111, // index[275] PINMUX_DIO_PAD_ATTR_2 + 4'b 0111, // index[276] PINMUX_DIO_PAD_ATTR_3 + 4'b 0111, // index[277] PINMUX_DIO_PAD_ATTR_4 + 4'b 0111, // index[278] PINMUX_DIO_PAD_ATTR_5 + 4'b 0111, // index[279] PINMUX_DIO_PAD_ATTR_6 + 4'b 0111, // index[280] PINMUX_DIO_PAD_ATTR_7 + 4'b 0111, // index[281] PINMUX_DIO_PAD_ATTR_8 + 4'b 0111, // index[282] PINMUX_DIO_PAD_ATTR_9 + 4'b 0111, // index[283] PINMUX_DIO_PAD_ATTR_10 + 4'b 0111, // index[284] PINMUX_DIO_PAD_ATTR_11 + 4'b 0111, // index[285] PINMUX_DIO_PAD_ATTR_12 + 4'b 0111, // index[286] PINMUX_DIO_PAD_ATTR_13 + 4'b 1111, // index[287] PINMUX_MIO_PAD_SLEEP_STATUS_0 + 4'b 0011, // index[288] PINMUX_MIO_PAD_SLEEP_STATUS_1 + 4'b 0001, // index[289] PINMUX_MIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[290] PINMUX_MIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[291] PINMUX_MIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[292] PINMUX_MIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[293] PINMUX_MIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[294] PINMUX_MIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[295] PINMUX_MIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[296] PINMUX_MIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[297] PINMUX_MIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[298] PINMUX_MIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[299] PINMUX_MIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[300] PINMUX_MIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[301] PINMUX_MIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[302] PINMUX_MIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[303] PINMUX_MIO_PAD_SLEEP_REGWEN_14 + 4'b 0001, // index[304] PINMUX_MIO_PAD_SLEEP_REGWEN_15 + 4'b 0001, // index[305] PINMUX_MIO_PAD_SLEEP_REGWEN_16 + 4'b 0001, // index[306] PINMUX_MIO_PAD_SLEEP_REGWEN_17 + 4'b 0001, // index[307] PINMUX_MIO_PAD_SLEEP_REGWEN_18 + 4'b 0001, // index[308] PINMUX_MIO_PAD_SLEEP_REGWEN_19 + 4'b 0001, // index[309] PINMUX_MIO_PAD_SLEEP_REGWEN_20 + 4'b 0001, // index[310] PINMUX_MIO_PAD_SLEEP_REGWEN_21 + 4'b 0001, // index[311] PINMUX_MIO_PAD_SLEEP_REGWEN_22 + 4'b 0001, // index[312] PINMUX_MIO_PAD_SLEEP_REGWEN_23 + 4'b 0001, // index[313] PINMUX_MIO_PAD_SLEEP_REGWEN_24 + 4'b 0001, // index[314] PINMUX_MIO_PAD_SLEEP_REGWEN_25 + 4'b 0001, // index[315] PINMUX_MIO_PAD_SLEEP_REGWEN_26 + 4'b 0001, // index[316] PINMUX_MIO_PAD_SLEEP_REGWEN_27 + 4'b 0001, // index[317] PINMUX_MIO_PAD_SLEEP_REGWEN_28 + 4'b 0001, // index[318] PINMUX_MIO_PAD_SLEEP_REGWEN_29 + 4'b 0001, // index[319] PINMUX_MIO_PAD_SLEEP_REGWEN_30 + 4'b 0001, // index[320] PINMUX_MIO_PAD_SLEEP_REGWEN_31 + 4'b 0001, // index[321] PINMUX_MIO_PAD_SLEEP_REGWEN_32 + 4'b 0001, // index[322] PINMUX_MIO_PAD_SLEEP_REGWEN_33 + 4'b 0001, // index[323] PINMUX_MIO_PAD_SLEEP_REGWEN_34 + 4'b 0001, // index[324] PINMUX_MIO_PAD_SLEEP_REGWEN_35 + 4'b 0001, // index[325] PINMUX_MIO_PAD_SLEEP_REGWEN_36 + 4'b 0001, // index[326] PINMUX_MIO_PAD_SLEEP_REGWEN_37 + 4'b 0001, // index[327] PINMUX_MIO_PAD_SLEEP_REGWEN_38 + 4'b 0001, // index[328] PINMUX_MIO_PAD_SLEEP_REGWEN_39 + 4'b 0001, // index[329] PINMUX_MIO_PAD_SLEEP_REGWEN_40 + 4'b 0001, // index[330] PINMUX_MIO_PAD_SLEEP_REGWEN_41 + 4'b 0001, // index[331] PINMUX_MIO_PAD_SLEEP_REGWEN_42 + 4'b 0001, // index[332] PINMUX_MIO_PAD_SLEEP_REGWEN_43 + 4'b 0001, // index[333] PINMUX_MIO_PAD_SLEEP_REGWEN_44 + 4'b 0001, // index[334] PINMUX_MIO_PAD_SLEEP_REGWEN_45 + 4'b 0001, // index[335] PINMUX_MIO_PAD_SLEEP_REGWEN_46 + 4'b 0001, // index[336] PINMUX_MIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[337] PINMUX_MIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[338] PINMUX_MIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[339] PINMUX_MIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[340] PINMUX_MIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[341] PINMUX_MIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[342] PINMUX_MIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[343] PINMUX_MIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[344] PINMUX_MIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[345] PINMUX_MIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[346] PINMUX_MIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[347] PINMUX_MIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[348] PINMUX_MIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[349] PINMUX_MIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[350] PINMUX_MIO_PAD_SLEEP_EN_14 + 4'b 0001, // index[351] PINMUX_MIO_PAD_SLEEP_EN_15 + 4'b 0001, // index[352] PINMUX_MIO_PAD_SLEEP_EN_16 + 4'b 0001, // index[353] PINMUX_MIO_PAD_SLEEP_EN_17 + 4'b 0001, // index[354] PINMUX_MIO_PAD_SLEEP_EN_18 + 4'b 0001, // index[355] PINMUX_MIO_PAD_SLEEP_EN_19 + 4'b 0001, // index[356] PINMUX_MIO_PAD_SLEEP_EN_20 + 4'b 0001, // index[357] PINMUX_MIO_PAD_SLEEP_EN_21 + 4'b 0001, // index[358] PINMUX_MIO_PAD_SLEEP_EN_22 + 4'b 0001, // index[359] PINMUX_MIO_PAD_SLEEP_EN_23 + 4'b 0001, // index[360] PINMUX_MIO_PAD_SLEEP_EN_24 + 4'b 0001, // index[361] PINMUX_MIO_PAD_SLEEP_EN_25 + 4'b 0001, // index[362] PINMUX_MIO_PAD_SLEEP_EN_26 + 4'b 0001, // index[363] PINMUX_MIO_PAD_SLEEP_EN_27 + 4'b 0001, // index[364] PINMUX_MIO_PAD_SLEEP_EN_28 + 4'b 0001, // index[365] PINMUX_MIO_PAD_SLEEP_EN_29 + 4'b 0001, // index[366] PINMUX_MIO_PAD_SLEEP_EN_30 + 4'b 0001, // index[367] PINMUX_MIO_PAD_SLEEP_EN_31 + 4'b 0001, // index[368] PINMUX_MIO_PAD_SLEEP_EN_32 + 4'b 0001, // index[369] PINMUX_MIO_PAD_SLEEP_EN_33 + 4'b 0001, // index[370] PINMUX_MIO_PAD_SLEEP_EN_34 + 4'b 0001, // index[371] PINMUX_MIO_PAD_SLEEP_EN_35 + 4'b 0001, // index[372] PINMUX_MIO_PAD_SLEEP_EN_36 + 4'b 0001, // index[373] PINMUX_MIO_PAD_SLEEP_EN_37 + 4'b 0001, // index[374] PINMUX_MIO_PAD_SLEEP_EN_38 + 4'b 0001, // index[375] PINMUX_MIO_PAD_SLEEP_EN_39 + 4'b 0001, // index[376] PINMUX_MIO_PAD_SLEEP_EN_40 + 4'b 0001, // index[377] PINMUX_MIO_PAD_SLEEP_EN_41 + 4'b 0001, // index[378] PINMUX_MIO_PAD_SLEEP_EN_42 + 4'b 0001, // index[379] PINMUX_MIO_PAD_SLEEP_EN_43 + 4'b 0001, // index[380] PINMUX_MIO_PAD_SLEEP_EN_44 + 4'b 0001, // index[381] PINMUX_MIO_PAD_SLEEP_EN_45 + 4'b 0001, // index[382] PINMUX_MIO_PAD_SLEEP_EN_46 + 4'b 0001, // index[383] PINMUX_MIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[384] PINMUX_MIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[385] PINMUX_MIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[386] PINMUX_MIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[387] PINMUX_MIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[388] PINMUX_MIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[389] PINMUX_MIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[390] PINMUX_MIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[391] PINMUX_MIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[392] PINMUX_MIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[393] PINMUX_MIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[394] PINMUX_MIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[395] PINMUX_MIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[396] PINMUX_MIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[397] PINMUX_MIO_PAD_SLEEP_MODE_14 + 4'b 0001, // index[398] PINMUX_MIO_PAD_SLEEP_MODE_15 + 4'b 0001, // index[399] PINMUX_MIO_PAD_SLEEP_MODE_16 + 4'b 0001, // index[400] PINMUX_MIO_PAD_SLEEP_MODE_17 + 4'b 0001, // index[401] PINMUX_MIO_PAD_SLEEP_MODE_18 + 4'b 0001, // index[402] PINMUX_MIO_PAD_SLEEP_MODE_19 + 4'b 0001, // index[403] PINMUX_MIO_PAD_SLEEP_MODE_20 + 4'b 0001, // index[404] PINMUX_MIO_PAD_SLEEP_MODE_21 + 4'b 0001, // index[405] PINMUX_MIO_PAD_SLEEP_MODE_22 + 4'b 0001, // index[406] PINMUX_MIO_PAD_SLEEP_MODE_23 + 4'b 0001, // index[407] PINMUX_MIO_PAD_SLEEP_MODE_24 + 4'b 0001, // index[408] PINMUX_MIO_PAD_SLEEP_MODE_25 + 4'b 0001, // index[409] PINMUX_MIO_PAD_SLEEP_MODE_26 + 4'b 0001, // index[410] PINMUX_MIO_PAD_SLEEP_MODE_27 + 4'b 0001, // index[411] PINMUX_MIO_PAD_SLEEP_MODE_28 + 4'b 0001, // index[412] PINMUX_MIO_PAD_SLEEP_MODE_29 + 4'b 0001, // index[413] PINMUX_MIO_PAD_SLEEP_MODE_30 + 4'b 0001, // index[414] PINMUX_MIO_PAD_SLEEP_MODE_31 + 4'b 0001, // index[415] PINMUX_MIO_PAD_SLEEP_MODE_32 + 4'b 0001, // index[416] PINMUX_MIO_PAD_SLEEP_MODE_33 + 4'b 0001, // index[417] PINMUX_MIO_PAD_SLEEP_MODE_34 + 4'b 0001, // index[418] PINMUX_MIO_PAD_SLEEP_MODE_35 + 4'b 0001, // index[419] PINMUX_MIO_PAD_SLEEP_MODE_36 + 4'b 0001, // index[420] PINMUX_MIO_PAD_SLEEP_MODE_37 + 4'b 0001, // index[421] PINMUX_MIO_PAD_SLEEP_MODE_38 + 4'b 0001, // index[422] PINMUX_MIO_PAD_SLEEP_MODE_39 + 4'b 0001, // index[423] PINMUX_MIO_PAD_SLEEP_MODE_40 + 4'b 0001, // index[424] PINMUX_MIO_PAD_SLEEP_MODE_41 + 4'b 0001, // index[425] PINMUX_MIO_PAD_SLEEP_MODE_42 + 4'b 0001, // index[426] PINMUX_MIO_PAD_SLEEP_MODE_43 + 4'b 0001, // index[427] PINMUX_MIO_PAD_SLEEP_MODE_44 + 4'b 0001, // index[428] PINMUX_MIO_PAD_SLEEP_MODE_45 + 4'b 0001, // index[429] PINMUX_MIO_PAD_SLEEP_MODE_46 + 4'b 0011, // index[430] PINMUX_DIO_PAD_SLEEP_STATUS + 4'b 0001, // index[431] PINMUX_DIO_PAD_SLEEP_REGWEN_0 + 4'b 0001, // index[432] PINMUX_DIO_PAD_SLEEP_REGWEN_1 + 4'b 0001, // index[433] PINMUX_DIO_PAD_SLEEP_REGWEN_2 + 4'b 0001, // index[434] PINMUX_DIO_PAD_SLEEP_REGWEN_3 + 4'b 0001, // index[435] PINMUX_DIO_PAD_SLEEP_REGWEN_4 + 4'b 0001, // index[436] PINMUX_DIO_PAD_SLEEP_REGWEN_5 + 4'b 0001, // index[437] PINMUX_DIO_PAD_SLEEP_REGWEN_6 + 4'b 0001, // index[438] PINMUX_DIO_PAD_SLEEP_REGWEN_7 + 4'b 0001, // index[439] PINMUX_DIO_PAD_SLEEP_REGWEN_8 + 4'b 0001, // index[440] PINMUX_DIO_PAD_SLEEP_REGWEN_9 + 4'b 0001, // index[441] PINMUX_DIO_PAD_SLEEP_REGWEN_10 + 4'b 0001, // index[442] PINMUX_DIO_PAD_SLEEP_REGWEN_11 + 4'b 0001, // index[443] PINMUX_DIO_PAD_SLEEP_REGWEN_12 + 4'b 0001, // index[444] PINMUX_DIO_PAD_SLEEP_REGWEN_13 + 4'b 0001, // index[445] PINMUX_DIO_PAD_SLEEP_EN_0 + 4'b 0001, // index[446] PINMUX_DIO_PAD_SLEEP_EN_1 + 4'b 0001, // index[447] PINMUX_DIO_PAD_SLEEP_EN_2 + 4'b 0001, // index[448] PINMUX_DIO_PAD_SLEEP_EN_3 + 4'b 0001, // index[449] PINMUX_DIO_PAD_SLEEP_EN_4 + 4'b 0001, // index[450] PINMUX_DIO_PAD_SLEEP_EN_5 + 4'b 0001, // index[451] PINMUX_DIO_PAD_SLEEP_EN_6 + 4'b 0001, // index[452] PINMUX_DIO_PAD_SLEEP_EN_7 + 4'b 0001, // index[453] PINMUX_DIO_PAD_SLEEP_EN_8 + 4'b 0001, // index[454] PINMUX_DIO_PAD_SLEEP_EN_9 + 4'b 0001, // index[455] PINMUX_DIO_PAD_SLEEP_EN_10 + 4'b 0001, // index[456] PINMUX_DIO_PAD_SLEEP_EN_11 + 4'b 0001, // index[457] PINMUX_DIO_PAD_SLEEP_EN_12 + 4'b 0001, // index[458] PINMUX_DIO_PAD_SLEEP_EN_13 + 4'b 0001, // index[459] PINMUX_DIO_PAD_SLEEP_MODE_0 + 4'b 0001, // index[460] PINMUX_DIO_PAD_SLEEP_MODE_1 + 4'b 0001, // index[461] PINMUX_DIO_PAD_SLEEP_MODE_2 + 4'b 0001, // index[462] PINMUX_DIO_PAD_SLEEP_MODE_3 + 4'b 0001, // index[463] PINMUX_DIO_PAD_SLEEP_MODE_4 + 4'b 0001, // index[464] PINMUX_DIO_PAD_SLEEP_MODE_5 + 4'b 0001, // index[465] PINMUX_DIO_PAD_SLEEP_MODE_6 + 4'b 0001, // index[466] PINMUX_DIO_PAD_SLEEP_MODE_7 + 4'b 0001, // index[467] PINMUX_DIO_PAD_SLEEP_MODE_8 + 4'b 0001, // index[468] PINMUX_DIO_PAD_SLEEP_MODE_9 + 4'b 0001, // index[469] PINMUX_DIO_PAD_SLEEP_MODE_10 + 4'b 0001, // index[470] PINMUX_DIO_PAD_SLEEP_MODE_11 + 4'b 0001, // index[471] PINMUX_DIO_PAD_SLEEP_MODE_12 + 4'b 0001, // index[472] PINMUX_DIO_PAD_SLEEP_MODE_13 + 4'b 0001, // index[473] PINMUX_WKUP_DETECTOR_REGWEN_0 + 4'b 0001, // index[474] PINMUX_WKUP_DETECTOR_REGWEN_1 + 4'b 0001, // index[475] PINMUX_WKUP_DETECTOR_REGWEN_2 + 4'b 0001, // index[476] PINMUX_WKUP_DETECTOR_REGWEN_3 + 4'b 0001, // index[477] PINMUX_WKUP_DETECTOR_REGWEN_4 + 4'b 0001, // index[478] PINMUX_WKUP_DETECTOR_REGWEN_5 + 4'b 0001, // index[479] PINMUX_WKUP_DETECTOR_REGWEN_6 + 4'b 0001, // index[480] PINMUX_WKUP_DETECTOR_REGWEN_7 + 4'b 0001, // index[481] PINMUX_WKUP_DETECTOR_EN_0 + 4'b 0001, // index[482] PINMUX_WKUP_DETECTOR_EN_1 + 4'b 0001, // index[483] PINMUX_WKUP_DETECTOR_EN_2 + 4'b 0001, // index[484] PINMUX_WKUP_DETECTOR_EN_3 + 4'b 0001, // index[485] PINMUX_WKUP_DETECTOR_EN_4 + 4'b 0001, // index[486] PINMUX_WKUP_DETECTOR_EN_5 + 4'b 0001, // index[487] PINMUX_WKUP_DETECTOR_EN_6 + 4'b 0001, // index[488] PINMUX_WKUP_DETECTOR_EN_7 + 4'b 0001, // index[489] PINMUX_WKUP_DETECTOR_0 + 4'b 0001, // index[490] PINMUX_WKUP_DETECTOR_1 + 4'b 0001, // index[491] PINMUX_WKUP_DETECTOR_2 + 4'b 0001, // index[492] PINMUX_WKUP_DETECTOR_3 + 4'b 0001, // index[493] PINMUX_WKUP_DETECTOR_4 + 4'b 0001, // index[494] PINMUX_WKUP_DETECTOR_5 + 4'b 0001, // index[495] PINMUX_WKUP_DETECTOR_6 + 4'b 0001, // index[496] PINMUX_WKUP_DETECTOR_7 + 4'b 0001, // index[497] PINMUX_WKUP_DETECTOR_CNT_TH_0 + 4'b 0001, // index[498] PINMUX_WKUP_DETECTOR_CNT_TH_1 + 4'b 0001, // index[499] PINMUX_WKUP_DETECTOR_CNT_TH_2 + 4'b 0001, // index[500] PINMUX_WKUP_DETECTOR_CNT_TH_3 + 4'b 0001, // index[501] PINMUX_WKUP_DETECTOR_CNT_TH_4 + 4'b 0001, // index[502] PINMUX_WKUP_DETECTOR_CNT_TH_5 + 4'b 0001, // index[503] PINMUX_WKUP_DETECTOR_CNT_TH_6 + 4'b 0001, // index[504] PINMUX_WKUP_DETECTOR_CNT_TH_7 + 4'b 0001, // index[505] PINMUX_WKUP_DETECTOR_PADSEL_0 + 4'b 0001, // index[506] PINMUX_WKUP_DETECTOR_PADSEL_1 + 4'b 0001, // index[507] PINMUX_WKUP_DETECTOR_PADSEL_2 + 4'b 0001, // index[508] PINMUX_WKUP_DETECTOR_PADSEL_3 + 4'b 0001, // index[509] PINMUX_WKUP_DETECTOR_PADSEL_4 + 4'b 0001, // index[510] PINMUX_WKUP_DETECTOR_PADSEL_5 + 4'b 0001, // index[511] PINMUX_WKUP_DETECTOR_PADSEL_6 + 4'b 0001, // index[512] PINMUX_WKUP_DETECTOR_PADSEL_7 + 4'b 0001 // index[513] PINMUX_WKUP_CAUSE }; endpackage diff --git a/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_top.sv b/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_top.sv index 8e690cac69a..c60487d251f 100644 --- a/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_top.sv +++ b/hw/top_englishbreakfast/ip_autogen/pinmux/rtl/pinmux_reg_top.sv @@ -54,9 +54,9 @@ module pinmux_reg_top ( // also check for spurious write enables logic reg_we_err; - logic [519:0] reg_we_check; + logic [513:0] reg_we_check; prim_reg_we_check #( - .OneHotWidth(520) + .OneHotWidth(514) ) u_prim_reg_we_check ( .clk_i(clk_i), .rst_ni(rst_ni), @@ -230,15 +230,6 @@ module pinmux_reg_top ( logic mio_periph_insel_regwen_34_we; logic mio_periph_insel_regwen_34_qs; logic mio_periph_insel_regwen_34_wd; - logic mio_periph_insel_regwen_35_we; - logic mio_periph_insel_regwen_35_qs; - logic mio_periph_insel_regwen_35_wd; - logic mio_periph_insel_regwen_36_we; - logic mio_periph_insel_regwen_36_qs; - logic mio_periph_insel_regwen_36_wd; - logic mio_periph_insel_regwen_37_we; - logic mio_periph_insel_regwen_37_qs; - logic mio_periph_insel_regwen_37_wd; logic mio_periph_insel_0_we; logic [5:0] mio_periph_insel_0_qs; logic [5:0] mio_periph_insel_0_wd; @@ -344,15 +335,6 @@ module pinmux_reg_top ( logic mio_periph_insel_34_we; logic [5:0] mio_periph_insel_34_qs; logic [5:0] mio_periph_insel_34_wd; - logic mio_periph_insel_35_we; - logic [5:0] mio_periph_insel_35_qs; - logic [5:0] mio_periph_insel_35_wd; - logic mio_periph_insel_36_we; - logic [5:0] mio_periph_insel_36_qs; - logic [5:0] mio_periph_insel_36_wd; - logic mio_periph_insel_37_we; - logic [5:0] mio_periph_insel_37_qs; - logic [5:0] mio_periph_insel_37_wd; logic mio_outsel_regwen_0_we; logic mio_outsel_regwen_0_qs; logic mio_outsel_regwen_0_wd; @@ -5035,93 +5017,6 @@ module pinmux_reg_top ( ); - // Subregister 35 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_35]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_35 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_35_we), - .wd (mio_periph_insel_regwen_35_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_35_qs) - ); - - - // Subregister 36 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_36]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_36 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_36_we), - .wd (mio_periph_insel_regwen_36_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_36_qs) - ); - - - // Subregister 37 of Multireg mio_periph_insel_regwen - // R[mio_periph_insel_regwen_37]: V(False) - prim_subreg #( - .DW (1), - .SwAccess(prim_subreg_pkg::SwAccessW0C), - .RESVAL (1'h1), - .Mubi (1'b0) - ) u_mio_periph_insel_regwen_37 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_regwen_37_we), - .wd (mio_periph_insel_regwen_37_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_regwen_37_qs) - ); - - // Subregister 0 of Multireg mio_periph_insel // R[mio_periph_insel_0]: V(False) // Create REGWEN-gated WE signal @@ -6242,102 +6137,6 @@ module pinmux_reg_top ( ); - // Subregister 35 of Multireg mio_periph_insel - // R[mio_periph_insel_35]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_35_gated_we; - assign mio_periph_insel_35_gated_we = mio_periph_insel_35_we & mio_periph_insel_regwen_35_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_35 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_35_gated_we), - .wd (mio_periph_insel_35_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[35].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_35_qs) - ); - - - // Subregister 36 of Multireg mio_periph_insel - // R[mio_periph_insel_36]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_36_gated_we; - assign mio_periph_insel_36_gated_we = mio_periph_insel_36_we & mio_periph_insel_regwen_36_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_36 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_36_gated_we), - .wd (mio_periph_insel_36_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[36].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_36_qs) - ); - - - // Subregister 37 of Multireg mio_periph_insel - // R[mio_periph_insel_37]: V(False) - // Create REGWEN-gated WE signal - logic mio_periph_insel_37_gated_we; - assign mio_periph_insel_37_gated_we = mio_periph_insel_37_we & mio_periph_insel_regwen_37_qs; - prim_subreg #( - .DW (6), - .SwAccess(prim_subreg_pkg::SwAccessRW), - .RESVAL (6'h0), - .Mubi (1'b0) - ) u_mio_periph_insel_37 ( - .clk_i (clk_i), - .rst_ni (rst_ni), - - // from register interface - .we (mio_periph_insel_37_gated_we), - .wd (mio_periph_insel_37_wd), - - // from internal hardware - .de (1'b0), - .d ('0), - - // to internal hardware - .qe (), - .q (reg2hw.mio_periph_insel[37].q), - .ds (), - - // to register interface (read) - .qs (mio_periph_insel_37_qs) - ); - - // Subregister 0 of Multireg mio_outsel_regwen // R[mio_outsel_regwen_0]: V(False) prim_subreg #( @@ -30546,7 +30345,7 @@ module pinmux_reg_top ( - logic [519:0] addr_hit; + logic [513:0] addr_hit; always_comb begin addr_hit[ 0] = (reg_addr == PINMUX_ALERT_TEST_OFFSET); addr_hit[ 1] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_0_OFFSET); @@ -30584,490 +30383,484 @@ module pinmux_reg_top ( addr_hit[ 33] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_32_OFFSET); addr_hit[ 34] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_33_OFFSET); addr_hit[ 35] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_34_OFFSET); - addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_35_OFFSET); - addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_36_OFFSET); - addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_REGWEN_37_OFFSET); - addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); - addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); - addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); - addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); - addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); - addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); - addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); - addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); - addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); - addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); - addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); - addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); - addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); - addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); - addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); - addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); - addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); - addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); - addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); - addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); - addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); - addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); - addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); - addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); - addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); - addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); - addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); - addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); - addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); - addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); - addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); - addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); - addr_hit[ 71] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); - addr_hit[ 72] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); - addr_hit[ 73] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); - addr_hit[ 74] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_35_OFFSET); - addr_hit[ 75] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_36_OFFSET); - addr_hit[ 76] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_37_OFFSET); - addr_hit[ 77] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); - addr_hit[ 78] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); - addr_hit[ 79] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); - addr_hit[ 80] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); - addr_hit[ 81] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); - addr_hit[ 82] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); - addr_hit[ 83] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); - addr_hit[ 84] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); - addr_hit[ 85] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); - addr_hit[ 86] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); - addr_hit[ 87] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); - addr_hit[ 88] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); - addr_hit[ 89] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); - addr_hit[ 90] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); - addr_hit[ 91] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); - addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); - addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); - addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); - addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); - addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); - addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); - addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); - addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); - addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); - addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); - addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); - addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); - addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); - addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); - addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); - addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); - addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); - addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); - addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); - addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); - addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); - addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); - addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); - addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); - addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); - addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); - addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); - addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); - addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); - addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); - addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); - addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); - addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); - addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); - addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); - addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); - addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); - addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); - addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); - addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); - addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); - addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); - addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); - addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); - addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); - addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); - addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); - addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); - addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); - addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); - addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); - addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); - addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); - addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); - addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); - addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); - addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); - addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); - addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); - addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); - addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); - addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); - addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); - addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); - addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); - addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); - addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); - addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); - addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); - addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); - addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); - addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); - addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); - addr_hit[165] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); - addr_hit[166] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); - addr_hit[167] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); - addr_hit[168] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); - addr_hit[169] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); - addr_hit[170] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); - addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); - addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); - addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); - addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); - addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); - addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); - addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); - addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); - addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); - addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); - addr_hit[195] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); - addr_hit[196] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); - addr_hit[197] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); - addr_hit[198] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); - addr_hit[199] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); - addr_hit[200] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); - addr_hit[201] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); - addr_hit[202] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); - addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); - addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); - addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); - addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); - addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); - addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); - addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); - addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); - addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); - addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); - addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); - addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); - addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); - addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); - addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); - addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); - addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); - addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); - addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); - addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); - addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); - addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); - addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); - addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); - addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); - addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); - addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); - addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); - addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); - addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); - addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); - addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); - addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); - addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); - addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); - addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); - addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); - addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); - addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); - addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); - addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); - addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); - addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); - addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); - addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); - addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); - addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); - addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); - addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); - addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); - addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); - addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); - addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); - addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); - addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); - addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); - addr_hit[259] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); - addr_hit[260] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); - addr_hit[261] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); - addr_hit[262] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); - addr_hit[263] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); - addr_hit[264] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); - addr_hit[265] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); - addr_hit[266] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); - addr_hit[267] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); - addr_hit[268] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); - addr_hit[269] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); - addr_hit[270] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); - addr_hit[271] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); - addr_hit[272] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); - addr_hit[273] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); - addr_hit[274] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); - addr_hit[275] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); - addr_hit[276] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); - addr_hit[277] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); - addr_hit[278] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); - addr_hit[279] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); - addr_hit[280] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); - addr_hit[281] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); - addr_hit[282] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); - addr_hit[283] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); - addr_hit[284] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); - addr_hit[285] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); - addr_hit[286] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); - addr_hit[287] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); - addr_hit[288] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); - addr_hit[289] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); - addr_hit[290] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); - addr_hit[291] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); - addr_hit[292] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); - addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); - addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); - addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); - addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); - addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); - addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); - addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); - addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); - addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); - addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); - addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); - addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); - addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); - addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); - addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); - addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); - addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); - addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); - addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); - addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); - addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); - addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); - addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); - addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); - addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); - addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); - addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); - addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); - addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); - addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); - addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); - addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); - addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); - addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); - addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); - addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); - addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); - addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); - addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); - addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); - addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); - addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); - addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); - addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); - addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); - addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); - addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); - addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); - addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); - addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); - addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); - addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); - addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); - addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); - addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); - addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); - addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); - addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); - addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); - addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); - addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); - addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); - addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); - addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); - addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); - addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); - addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); - addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); - addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); - addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); - addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); - addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); - addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); - addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); - addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); - addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); - addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); - addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); - addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); - addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); - addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); - addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); - addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); - addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); - addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); - addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); - addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); - addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); - addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); - addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); - addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); - addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); - addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); - addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); - addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); - addr_hit[430] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); - addr_hit[431] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); - addr_hit[432] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); - addr_hit[433] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); - addr_hit[434] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); - addr_hit[435] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); - addr_hit[436] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); - addr_hit[437] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); - addr_hit[438] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); - addr_hit[439] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); - addr_hit[440] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); - addr_hit[441] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); - addr_hit[442] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); - addr_hit[443] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); - addr_hit[444] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); - addr_hit[445] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); - addr_hit[446] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); - addr_hit[447] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); - addr_hit[448] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); - addr_hit[449] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); - addr_hit[450] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); - addr_hit[451] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); - addr_hit[452] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); - addr_hit[453] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); - addr_hit[454] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); - addr_hit[455] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); - addr_hit[456] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); - addr_hit[457] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); - addr_hit[458] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); - addr_hit[459] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); - addr_hit[460] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); - addr_hit[461] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); - addr_hit[462] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); - addr_hit[463] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); - addr_hit[464] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); - addr_hit[465] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); - addr_hit[466] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); - addr_hit[467] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); - addr_hit[468] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); - addr_hit[469] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); - addr_hit[470] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); - addr_hit[471] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); - addr_hit[472] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); - addr_hit[473] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); - addr_hit[474] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); - addr_hit[475] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); - addr_hit[476] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); - addr_hit[477] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); - addr_hit[478] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); - addr_hit[479] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); - addr_hit[480] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); - addr_hit[481] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); - addr_hit[482] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); - addr_hit[483] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); - addr_hit[484] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); - addr_hit[485] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); - addr_hit[486] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); - addr_hit[487] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); - addr_hit[488] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); - addr_hit[489] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); - addr_hit[490] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); - addr_hit[491] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); - addr_hit[492] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); - addr_hit[493] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); - addr_hit[494] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); - addr_hit[495] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); - addr_hit[496] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); - addr_hit[497] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); - addr_hit[498] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); - addr_hit[499] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); - addr_hit[500] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); - addr_hit[501] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); - addr_hit[502] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); - addr_hit[503] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); - addr_hit[504] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); - addr_hit[505] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); - addr_hit[506] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); - addr_hit[507] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); - addr_hit[508] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); - addr_hit[509] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); - addr_hit[510] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); - addr_hit[511] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); - addr_hit[512] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); - addr_hit[513] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); - addr_hit[514] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); - addr_hit[515] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); - addr_hit[516] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); - addr_hit[517] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); - addr_hit[518] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); - addr_hit[519] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); + addr_hit[ 36] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_0_OFFSET); + addr_hit[ 37] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_1_OFFSET); + addr_hit[ 38] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_2_OFFSET); + addr_hit[ 39] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_3_OFFSET); + addr_hit[ 40] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_4_OFFSET); + addr_hit[ 41] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_5_OFFSET); + addr_hit[ 42] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_6_OFFSET); + addr_hit[ 43] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_7_OFFSET); + addr_hit[ 44] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_8_OFFSET); + addr_hit[ 45] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_9_OFFSET); + addr_hit[ 46] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_10_OFFSET); + addr_hit[ 47] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_11_OFFSET); + addr_hit[ 48] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_12_OFFSET); + addr_hit[ 49] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_13_OFFSET); + addr_hit[ 50] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_14_OFFSET); + addr_hit[ 51] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_15_OFFSET); + addr_hit[ 52] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_16_OFFSET); + addr_hit[ 53] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_17_OFFSET); + addr_hit[ 54] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_18_OFFSET); + addr_hit[ 55] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_19_OFFSET); + addr_hit[ 56] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_20_OFFSET); + addr_hit[ 57] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_21_OFFSET); + addr_hit[ 58] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_22_OFFSET); + addr_hit[ 59] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_23_OFFSET); + addr_hit[ 60] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_24_OFFSET); + addr_hit[ 61] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_25_OFFSET); + addr_hit[ 62] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_26_OFFSET); + addr_hit[ 63] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_27_OFFSET); + addr_hit[ 64] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_28_OFFSET); + addr_hit[ 65] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_29_OFFSET); + addr_hit[ 66] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_30_OFFSET); + addr_hit[ 67] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_31_OFFSET); + addr_hit[ 68] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_32_OFFSET); + addr_hit[ 69] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_33_OFFSET); + addr_hit[ 70] = (reg_addr == PINMUX_MIO_PERIPH_INSEL_34_OFFSET); + addr_hit[ 71] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_0_OFFSET); + addr_hit[ 72] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_1_OFFSET); + addr_hit[ 73] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_2_OFFSET); + addr_hit[ 74] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_3_OFFSET); + addr_hit[ 75] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_4_OFFSET); + addr_hit[ 76] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_5_OFFSET); + addr_hit[ 77] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_6_OFFSET); + addr_hit[ 78] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_7_OFFSET); + addr_hit[ 79] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_8_OFFSET); + addr_hit[ 80] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_9_OFFSET); + addr_hit[ 81] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_10_OFFSET); + addr_hit[ 82] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_11_OFFSET); + addr_hit[ 83] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_12_OFFSET); + addr_hit[ 84] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_13_OFFSET); + addr_hit[ 85] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_14_OFFSET); + addr_hit[ 86] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_15_OFFSET); + addr_hit[ 87] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_16_OFFSET); + addr_hit[ 88] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_17_OFFSET); + addr_hit[ 89] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_18_OFFSET); + addr_hit[ 90] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_19_OFFSET); + addr_hit[ 91] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_20_OFFSET); + addr_hit[ 92] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_21_OFFSET); + addr_hit[ 93] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_22_OFFSET); + addr_hit[ 94] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_23_OFFSET); + addr_hit[ 95] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_24_OFFSET); + addr_hit[ 96] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_25_OFFSET); + addr_hit[ 97] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_26_OFFSET); + addr_hit[ 98] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_27_OFFSET); + addr_hit[ 99] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_28_OFFSET); + addr_hit[100] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_29_OFFSET); + addr_hit[101] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_30_OFFSET); + addr_hit[102] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_31_OFFSET); + addr_hit[103] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_32_OFFSET); + addr_hit[104] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_33_OFFSET); + addr_hit[105] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_34_OFFSET); + addr_hit[106] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_35_OFFSET); + addr_hit[107] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_36_OFFSET); + addr_hit[108] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_37_OFFSET); + addr_hit[109] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_38_OFFSET); + addr_hit[110] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_39_OFFSET); + addr_hit[111] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_40_OFFSET); + addr_hit[112] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_41_OFFSET); + addr_hit[113] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_42_OFFSET); + addr_hit[114] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_43_OFFSET); + addr_hit[115] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_44_OFFSET); + addr_hit[116] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_45_OFFSET); + addr_hit[117] = (reg_addr == PINMUX_MIO_OUTSEL_REGWEN_46_OFFSET); + addr_hit[118] = (reg_addr == PINMUX_MIO_OUTSEL_0_OFFSET); + addr_hit[119] = (reg_addr == PINMUX_MIO_OUTSEL_1_OFFSET); + addr_hit[120] = (reg_addr == PINMUX_MIO_OUTSEL_2_OFFSET); + addr_hit[121] = (reg_addr == PINMUX_MIO_OUTSEL_3_OFFSET); + addr_hit[122] = (reg_addr == PINMUX_MIO_OUTSEL_4_OFFSET); + addr_hit[123] = (reg_addr == PINMUX_MIO_OUTSEL_5_OFFSET); + addr_hit[124] = (reg_addr == PINMUX_MIO_OUTSEL_6_OFFSET); + addr_hit[125] = (reg_addr == PINMUX_MIO_OUTSEL_7_OFFSET); + addr_hit[126] = (reg_addr == PINMUX_MIO_OUTSEL_8_OFFSET); + addr_hit[127] = (reg_addr == PINMUX_MIO_OUTSEL_9_OFFSET); + addr_hit[128] = (reg_addr == PINMUX_MIO_OUTSEL_10_OFFSET); + addr_hit[129] = (reg_addr == PINMUX_MIO_OUTSEL_11_OFFSET); + addr_hit[130] = (reg_addr == PINMUX_MIO_OUTSEL_12_OFFSET); + addr_hit[131] = (reg_addr == PINMUX_MIO_OUTSEL_13_OFFSET); + addr_hit[132] = (reg_addr == PINMUX_MIO_OUTSEL_14_OFFSET); + addr_hit[133] = (reg_addr == PINMUX_MIO_OUTSEL_15_OFFSET); + addr_hit[134] = (reg_addr == PINMUX_MIO_OUTSEL_16_OFFSET); + addr_hit[135] = (reg_addr == PINMUX_MIO_OUTSEL_17_OFFSET); + addr_hit[136] = (reg_addr == PINMUX_MIO_OUTSEL_18_OFFSET); + addr_hit[137] = (reg_addr == PINMUX_MIO_OUTSEL_19_OFFSET); + addr_hit[138] = (reg_addr == PINMUX_MIO_OUTSEL_20_OFFSET); + addr_hit[139] = (reg_addr == PINMUX_MIO_OUTSEL_21_OFFSET); + addr_hit[140] = (reg_addr == PINMUX_MIO_OUTSEL_22_OFFSET); + addr_hit[141] = (reg_addr == PINMUX_MIO_OUTSEL_23_OFFSET); + addr_hit[142] = (reg_addr == PINMUX_MIO_OUTSEL_24_OFFSET); + addr_hit[143] = (reg_addr == PINMUX_MIO_OUTSEL_25_OFFSET); + addr_hit[144] = (reg_addr == PINMUX_MIO_OUTSEL_26_OFFSET); + addr_hit[145] = (reg_addr == PINMUX_MIO_OUTSEL_27_OFFSET); + addr_hit[146] = (reg_addr == PINMUX_MIO_OUTSEL_28_OFFSET); + addr_hit[147] = (reg_addr == PINMUX_MIO_OUTSEL_29_OFFSET); + addr_hit[148] = (reg_addr == PINMUX_MIO_OUTSEL_30_OFFSET); + addr_hit[149] = (reg_addr == PINMUX_MIO_OUTSEL_31_OFFSET); + addr_hit[150] = (reg_addr == PINMUX_MIO_OUTSEL_32_OFFSET); + addr_hit[151] = (reg_addr == PINMUX_MIO_OUTSEL_33_OFFSET); + addr_hit[152] = (reg_addr == PINMUX_MIO_OUTSEL_34_OFFSET); + addr_hit[153] = (reg_addr == PINMUX_MIO_OUTSEL_35_OFFSET); + addr_hit[154] = (reg_addr == PINMUX_MIO_OUTSEL_36_OFFSET); + addr_hit[155] = (reg_addr == PINMUX_MIO_OUTSEL_37_OFFSET); + addr_hit[156] = (reg_addr == PINMUX_MIO_OUTSEL_38_OFFSET); + addr_hit[157] = (reg_addr == PINMUX_MIO_OUTSEL_39_OFFSET); + addr_hit[158] = (reg_addr == PINMUX_MIO_OUTSEL_40_OFFSET); + addr_hit[159] = (reg_addr == PINMUX_MIO_OUTSEL_41_OFFSET); + addr_hit[160] = (reg_addr == PINMUX_MIO_OUTSEL_42_OFFSET); + addr_hit[161] = (reg_addr == PINMUX_MIO_OUTSEL_43_OFFSET); + addr_hit[162] = (reg_addr == PINMUX_MIO_OUTSEL_44_OFFSET); + addr_hit[163] = (reg_addr == PINMUX_MIO_OUTSEL_45_OFFSET); + addr_hit[164] = (reg_addr == PINMUX_MIO_OUTSEL_46_OFFSET); + addr_hit[165] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[166] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[167] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[168] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[169] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[170] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[171] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[172] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[173] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[174] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[175] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[176] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[177] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[178] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[179] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_14_OFFSET); + addr_hit[180] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_15_OFFSET); + addr_hit[181] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_16_OFFSET); + addr_hit[182] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_17_OFFSET); + addr_hit[183] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_18_OFFSET); + addr_hit[184] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_19_OFFSET); + addr_hit[185] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_20_OFFSET); + addr_hit[186] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_21_OFFSET); + addr_hit[187] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_22_OFFSET); + addr_hit[188] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_23_OFFSET); + addr_hit[189] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_24_OFFSET); + addr_hit[190] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_25_OFFSET); + addr_hit[191] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_26_OFFSET); + addr_hit[192] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_27_OFFSET); + addr_hit[193] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_28_OFFSET); + addr_hit[194] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_29_OFFSET); + addr_hit[195] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_30_OFFSET); + addr_hit[196] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_31_OFFSET); + addr_hit[197] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_32_OFFSET); + addr_hit[198] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_33_OFFSET); + addr_hit[199] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_34_OFFSET); + addr_hit[200] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_35_OFFSET); + addr_hit[201] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_36_OFFSET); + addr_hit[202] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_37_OFFSET); + addr_hit[203] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_38_OFFSET); + addr_hit[204] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_39_OFFSET); + addr_hit[205] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_40_OFFSET); + addr_hit[206] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_41_OFFSET); + addr_hit[207] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_42_OFFSET); + addr_hit[208] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_43_OFFSET); + addr_hit[209] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_44_OFFSET); + addr_hit[210] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_45_OFFSET); + addr_hit[211] = (reg_addr == PINMUX_MIO_PAD_ATTR_REGWEN_46_OFFSET); + addr_hit[212] = (reg_addr == PINMUX_MIO_PAD_ATTR_0_OFFSET); + addr_hit[213] = (reg_addr == PINMUX_MIO_PAD_ATTR_1_OFFSET); + addr_hit[214] = (reg_addr == PINMUX_MIO_PAD_ATTR_2_OFFSET); + addr_hit[215] = (reg_addr == PINMUX_MIO_PAD_ATTR_3_OFFSET); + addr_hit[216] = (reg_addr == PINMUX_MIO_PAD_ATTR_4_OFFSET); + addr_hit[217] = (reg_addr == PINMUX_MIO_PAD_ATTR_5_OFFSET); + addr_hit[218] = (reg_addr == PINMUX_MIO_PAD_ATTR_6_OFFSET); + addr_hit[219] = (reg_addr == PINMUX_MIO_PAD_ATTR_7_OFFSET); + addr_hit[220] = (reg_addr == PINMUX_MIO_PAD_ATTR_8_OFFSET); + addr_hit[221] = (reg_addr == PINMUX_MIO_PAD_ATTR_9_OFFSET); + addr_hit[222] = (reg_addr == PINMUX_MIO_PAD_ATTR_10_OFFSET); + addr_hit[223] = (reg_addr == PINMUX_MIO_PAD_ATTR_11_OFFSET); + addr_hit[224] = (reg_addr == PINMUX_MIO_PAD_ATTR_12_OFFSET); + addr_hit[225] = (reg_addr == PINMUX_MIO_PAD_ATTR_13_OFFSET); + addr_hit[226] = (reg_addr == PINMUX_MIO_PAD_ATTR_14_OFFSET); + addr_hit[227] = (reg_addr == PINMUX_MIO_PAD_ATTR_15_OFFSET); + addr_hit[228] = (reg_addr == PINMUX_MIO_PAD_ATTR_16_OFFSET); + addr_hit[229] = (reg_addr == PINMUX_MIO_PAD_ATTR_17_OFFSET); + addr_hit[230] = (reg_addr == PINMUX_MIO_PAD_ATTR_18_OFFSET); + addr_hit[231] = (reg_addr == PINMUX_MIO_PAD_ATTR_19_OFFSET); + addr_hit[232] = (reg_addr == PINMUX_MIO_PAD_ATTR_20_OFFSET); + addr_hit[233] = (reg_addr == PINMUX_MIO_PAD_ATTR_21_OFFSET); + addr_hit[234] = (reg_addr == PINMUX_MIO_PAD_ATTR_22_OFFSET); + addr_hit[235] = (reg_addr == PINMUX_MIO_PAD_ATTR_23_OFFSET); + addr_hit[236] = (reg_addr == PINMUX_MIO_PAD_ATTR_24_OFFSET); + addr_hit[237] = (reg_addr == PINMUX_MIO_PAD_ATTR_25_OFFSET); + addr_hit[238] = (reg_addr == PINMUX_MIO_PAD_ATTR_26_OFFSET); + addr_hit[239] = (reg_addr == PINMUX_MIO_PAD_ATTR_27_OFFSET); + addr_hit[240] = (reg_addr == PINMUX_MIO_PAD_ATTR_28_OFFSET); + addr_hit[241] = (reg_addr == PINMUX_MIO_PAD_ATTR_29_OFFSET); + addr_hit[242] = (reg_addr == PINMUX_MIO_PAD_ATTR_30_OFFSET); + addr_hit[243] = (reg_addr == PINMUX_MIO_PAD_ATTR_31_OFFSET); + addr_hit[244] = (reg_addr == PINMUX_MIO_PAD_ATTR_32_OFFSET); + addr_hit[245] = (reg_addr == PINMUX_MIO_PAD_ATTR_33_OFFSET); + addr_hit[246] = (reg_addr == PINMUX_MIO_PAD_ATTR_34_OFFSET); + addr_hit[247] = (reg_addr == PINMUX_MIO_PAD_ATTR_35_OFFSET); + addr_hit[248] = (reg_addr == PINMUX_MIO_PAD_ATTR_36_OFFSET); + addr_hit[249] = (reg_addr == PINMUX_MIO_PAD_ATTR_37_OFFSET); + addr_hit[250] = (reg_addr == PINMUX_MIO_PAD_ATTR_38_OFFSET); + addr_hit[251] = (reg_addr == PINMUX_MIO_PAD_ATTR_39_OFFSET); + addr_hit[252] = (reg_addr == PINMUX_MIO_PAD_ATTR_40_OFFSET); + addr_hit[253] = (reg_addr == PINMUX_MIO_PAD_ATTR_41_OFFSET); + addr_hit[254] = (reg_addr == PINMUX_MIO_PAD_ATTR_42_OFFSET); + addr_hit[255] = (reg_addr == PINMUX_MIO_PAD_ATTR_43_OFFSET); + addr_hit[256] = (reg_addr == PINMUX_MIO_PAD_ATTR_44_OFFSET); + addr_hit[257] = (reg_addr == PINMUX_MIO_PAD_ATTR_45_OFFSET); + addr_hit[258] = (reg_addr == PINMUX_MIO_PAD_ATTR_46_OFFSET); + addr_hit[259] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_0_OFFSET); + addr_hit[260] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_1_OFFSET); + addr_hit[261] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_2_OFFSET); + addr_hit[262] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_3_OFFSET); + addr_hit[263] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_4_OFFSET); + addr_hit[264] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_5_OFFSET); + addr_hit[265] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_6_OFFSET); + addr_hit[266] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_7_OFFSET); + addr_hit[267] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_8_OFFSET); + addr_hit[268] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_9_OFFSET); + addr_hit[269] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_10_OFFSET); + addr_hit[270] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_11_OFFSET); + addr_hit[271] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_12_OFFSET); + addr_hit[272] = (reg_addr == PINMUX_DIO_PAD_ATTR_REGWEN_13_OFFSET); + addr_hit[273] = (reg_addr == PINMUX_DIO_PAD_ATTR_0_OFFSET); + addr_hit[274] = (reg_addr == PINMUX_DIO_PAD_ATTR_1_OFFSET); + addr_hit[275] = (reg_addr == PINMUX_DIO_PAD_ATTR_2_OFFSET); + addr_hit[276] = (reg_addr == PINMUX_DIO_PAD_ATTR_3_OFFSET); + addr_hit[277] = (reg_addr == PINMUX_DIO_PAD_ATTR_4_OFFSET); + addr_hit[278] = (reg_addr == PINMUX_DIO_PAD_ATTR_5_OFFSET); + addr_hit[279] = (reg_addr == PINMUX_DIO_PAD_ATTR_6_OFFSET); + addr_hit[280] = (reg_addr == PINMUX_DIO_PAD_ATTR_7_OFFSET); + addr_hit[281] = (reg_addr == PINMUX_DIO_PAD_ATTR_8_OFFSET); + addr_hit[282] = (reg_addr == PINMUX_DIO_PAD_ATTR_9_OFFSET); + addr_hit[283] = (reg_addr == PINMUX_DIO_PAD_ATTR_10_OFFSET); + addr_hit[284] = (reg_addr == PINMUX_DIO_PAD_ATTR_11_OFFSET); + addr_hit[285] = (reg_addr == PINMUX_DIO_PAD_ATTR_12_OFFSET); + addr_hit[286] = (reg_addr == PINMUX_DIO_PAD_ATTR_13_OFFSET); + addr_hit[287] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_0_OFFSET); + addr_hit[288] = (reg_addr == PINMUX_MIO_PAD_SLEEP_STATUS_1_OFFSET); + addr_hit[289] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[290] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[291] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[292] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[293] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[294] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[295] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[296] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[297] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[298] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[299] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[300] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[301] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[302] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[303] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_14_OFFSET); + addr_hit[304] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_15_OFFSET); + addr_hit[305] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_16_OFFSET); + addr_hit[306] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_17_OFFSET); + addr_hit[307] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_18_OFFSET); + addr_hit[308] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_19_OFFSET); + addr_hit[309] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_20_OFFSET); + addr_hit[310] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_21_OFFSET); + addr_hit[311] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_22_OFFSET); + addr_hit[312] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_23_OFFSET); + addr_hit[313] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_24_OFFSET); + addr_hit[314] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_25_OFFSET); + addr_hit[315] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_26_OFFSET); + addr_hit[316] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_27_OFFSET); + addr_hit[317] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_28_OFFSET); + addr_hit[318] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_29_OFFSET); + addr_hit[319] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_30_OFFSET); + addr_hit[320] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_31_OFFSET); + addr_hit[321] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_32_OFFSET); + addr_hit[322] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_33_OFFSET); + addr_hit[323] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_34_OFFSET); + addr_hit[324] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_35_OFFSET); + addr_hit[325] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_36_OFFSET); + addr_hit[326] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_37_OFFSET); + addr_hit[327] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_38_OFFSET); + addr_hit[328] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_39_OFFSET); + addr_hit[329] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_40_OFFSET); + addr_hit[330] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_41_OFFSET); + addr_hit[331] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_42_OFFSET); + addr_hit[332] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_43_OFFSET); + addr_hit[333] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_44_OFFSET); + addr_hit[334] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_45_OFFSET); + addr_hit[335] = (reg_addr == PINMUX_MIO_PAD_SLEEP_REGWEN_46_OFFSET); + addr_hit[336] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[337] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[338] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[339] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[340] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[341] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[342] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[343] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[344] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[345] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[346] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[347] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[348] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[349] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[350] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_14_OFFSET); + addr_hit[351] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_15_OFFSET); + addr_hit[352] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_16_OFFSET); + addr_hit[353] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_17_OFFSET); + addr_hit[354] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_18_OFFSET); + addr_hit[355] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_19_OFFSET); + addr_hit[356] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_20_OFFSET); + addr_hit[357] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_21_OFFSET); + addr_hit[358] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_22_OFFSET); + addr_hit[359] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_23_OFFSET); + addr_hit[360] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_24_OFFSET); + addr_hit[361] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_25_OFFSET); + addr_hit[362] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_26_OFFSET); + addr_hit[363] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_27_OFFSET); + addr_hit[364] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_28_OFFSET); + addr_hit[365] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_29_OFFSET); + addr_hit[366] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_30_OFFSET); + addr_hit[367] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_31_OFFSET); + addr_hit[368] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_32_OFFSET); + addr_hit[369] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_33_OFFSET); + addr_hit[370] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_34_OFFSET); + addr_hit[371] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_35_OFFSET); + addr_hit[372] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_36_OFFSET); + addr_hit[373] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_37_OFFSET); + addr_hit[374] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_38_OFFSET); + addr_hit[375] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_39_OFFSET); + addr_hit[376] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_40_OFFSET); + addr_hit[377] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_41_OFFSET); + addr_hit[378] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_42_OFFSET); + addr_hit[379] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_43_OFFSET); + addr_hit[380] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_44_OFFSET); + addr_hit[381] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_45_OFFSET); + addr_hit[382] = (reg_addr == PINMUX_MIO_PAD_SLEEP_EN_46_OFFSET); + addr_hit[383] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[384] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[385] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[386] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[387] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[388] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[389] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[390] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[391] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[392] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[393] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[394] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[395] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[396] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[397] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_14_OFFSET); + addr_hit[398] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_15_OFFSET); + addr_hit[399] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_16_OFFSET); + addr_hit[400] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_17_OFFSET); + addr_hit[401] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_18_OFFSET); + addr_hit[402] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_19_OFFSET); + addr_hit[403] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_20_OFFSET); + addr_hit[404] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_21_OFFSET); + addr_hit[405] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_22_OFFSET); + addr_hit[406] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_23_OFFSET); + addr_hit[407] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_24_OFFSET); + addr_hit[408] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_25_OFFSET); + addr_hit[409] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_26_OFFSET); + addr_hit[410] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_27_OFFSET); + addr_hit[411] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_28_OFFSET); + addr_hit[412] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_29_OFFSET); + addr_hit[413] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_30_OFFSET); + addr_hit[414] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_31_OFFSET); + addr_hit[415] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_32_OFFSET); + addr_hit[416] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_33_OFFSET); + addr_hit[417] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_34_OFFSET); + addr_hit[418] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_35_OFFSET); + addr_hit[419] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_36_OFFSET); + addr_hit[420] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_37_OFFSET); + addr_hit[421] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_38_OFFSET); + addr_hit[422] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_39_OFFSET); + addr_hit[423] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_40_OFFSET); + addr_hit[424] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_41_OFFSET); + addr_hit[425] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_42_OFFSET); + addr_hit[426] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_43_OFFSET); + addr_hit[427] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_44_OFFSET); + addr_hit[428] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_45_OFFSET); + addr_hit[429] = (reg_addr == PINMUX_MIO_PAD_SLEEP_MODE_46_OFFSET); + addr_hit[430] = (reg_addr == PINMUX_DIO_PAD_SLEEP_STATUS_OFFSET); + addr_hit[431] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_0_OFFSET); + addr_hit[432] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_1_OFFSET); + addr_hit[433] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_2_OFFSET); + addr_hit[434] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_3_OFFSET); + addr_hit[435] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_4_OFFSET); + addr_hit[436] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_5_OFFSET); + addr_hit[437] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_6_OFFSET); + addr_hit[438] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_7_OFFSET); + addr_hit[439] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_8_OFFSET); + addr_hit[440] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_9_OFFSET); + addr_hit[441] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_10_OFFSET); + addr_hit[442] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_11_OFFSET); + addr_hit[443] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_12_OFFSET); + addr_hit[444] = (reg_addr == PINMUX_DIO_PAD_SLEEP_REGWEN_13_OFFSET); + addr_hit[445] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_0_OFFSET); + addr_hit[446] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_1_OFFSET); + addr_hit[447] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_2_OFFSET); + addr_hit[448] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_3_OFFSET); + addr_hit[449] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_4_OFFSET); + addr_hit[450] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_5_OFFSET); + addr_hit[451] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_6_OFFSET); + addr_hit[452] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_7_OFFSET); + addr_hit[453] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_8_OFFSET); + addr_hit[454] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_9_OFFSET); + addr_hit[455] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_10_OFFSET); + addr_hit[456] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_11_OFFSET); + addr_hit[457] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_12_OFFSET); + addr_hit[458] = (reg_addr == PINMUX_DIO_PAD_SLEEP_EN_13_OFFSET); + addr_hit[459] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_0_OFFSET); + addr_hit[460] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_1_OFFSET); + addr_hit[461] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_2_OFFSET); + addr_hit[462] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_3_OFFSET); + addr_hit[463] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_4_OFFSET); + addr_hit[464] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_5_OFFSET); + addr_hit[465] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_6_OFFSET); + addr_hit[466] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_7_OFFSET); + addr_hit[467] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_8_OFFSET); + addr_hit[468] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_9_OFFSET); + addr_hit[469] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_10_OFFSET); + addr_hit[470] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_11_OFFSET); + addr_hit[471] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_12_OFFSET); + addr_hit[472] = (reg_addr == PINMUX_DIO_PAD_SLEEP_MODE_13_OFFSET); + addr_hit[473] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_0_OFFSET); + addr_hit[474] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_1_OFFSET); + addr_hit[475] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_2_OFFSET); + addr_hit[476] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_3_OFFSET); + addr_hit[477] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_4_OFFSET); + addr_hit[478] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_5_OFFSET); + addr_hit[479] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_6_OFFSET); + addr_hit[480] = (reg_addr == PINMUX_WKUP_DETECTOR_REGWEN_7_OFFSET); + addr_hit[481] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_0_OFFSET); + addr_hit[482] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_1_OFFSET); + addr_hit[483] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_2_OFFSET); + addr_hit[484] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_3_OFFSET); + addr_hit[485] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_4_OFFSET); + addr_hit[486] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_5_OFFSET); + addr_hit[487] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_6_OFFSET); + addr_hit[488] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_7_OFFSET); + addr_hit[489] = (reg_addr == PINMUX_WKUP_DETECTOR_0_OFFSET); + addr_hit[490] = (reg_addr == PINMUX_WKUP_DETECTOR_1_OFFSET); + addr_hit[491] = (reg_addr == PINMUX_WKUP_DETECTOR_2_OFFSET); + addr_hit[492] = (reg_addr == PINMUX_WKUP_DETECTOR_3_OFFSET); + addr_hit[493] = (reg_addr == PINMUX_WKUP_DETECTOR_4_OFFSET); + addr_hit[494] = (reg_addr == PINMUX_WKUP_DETECTOR_5_OFFSET); + addr_hit[495] = (reg_addr == PINMUX_WKUP_DETECTOR_6_OFFSET); + addr_hit[496] = (reg_addr == PINMUX_WKUP_DETECTOR_7_OFFSET); + addr_hit[497] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_0_OFFSET); + addr_hit[498] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_1_OFFSET); + addr_hit[499] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_2_OFFSET); + addr_hit[500] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_3_OFFSET); + addr_hit[501] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_4_OFFSET); + addr_hit[502] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_5_OFFSET); + addr_hit[503] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_6_OFFSET); + addr_hit[504] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH_7_OFFSET); + addr_hit[505] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_0_OFFSET); + addr_hit[506] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_1_OFFSET); + addr_hit[507] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_2_OFFSET); + addr_hit[508] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_3_OFFSET); + addr_hit[509] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_4_OFFSET); + addr_hit[510] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_5_OFFSET); + addr_hit[511] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_6_OFFSET); + addr_hit[512] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL_7_OFFSET); + addr_hit[513] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET); end assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; @@ -31588,13 +31381,7 @@ module pinmux_reg_top ( (addr_hit[510] & (|(PINMUX_PERMIT[510] & ~reg_be))) | (addr_hit[511] & (|(PINMUX_PERMIT[511] & ~reg_be))) | (addr_hit[512] & (|(PINMUX_PERMIT[512] & ~reg_be))) | - (addr_hit[513] & (|(PINMUX_PERMIT[513] & ~reg_be))) | - (addr_hit[514] & (|(PINMUX_PERMIT[514] & ~reg_be))) | - (addr_hit[515] & (|(PINMUX_PERMIT[515] & ~reg_be))) | - (addr_hit[516] & (|(PINMUX_PERMIT[516] & ~reg_be))) | - (addr_hit[517] & (|(PINMUX_PERMIT[517] & ~reg_be))) | - (addr_hit[518] & (|(PINMUX_PERMIT[518] & ~reg_be))) | - (addr_hit[519] & (|(PINMUX_PERMIT[519] & ~reg_be))))); + (addr_hit[513] & (|(PINMUX_PERMIT[513] & ~reg_be))))); end // Generate write-enables @@ -31706,554 +31493,536 @@ module pinmux_reg_top ( assign mio_periph_insel_regwen_34_we = addr_hit[35] & reg_we & !reg_error; assign mio_periph_insel_regwen_34_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_35_we = addr_hit[36] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_35_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_36_we = addr_hit[37] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_36_wd = reg_wdata[0]; - assign mio_periph_insel_regwen_37_we = addr_hit[38] & reg_we & !reg_error; - - assign mio_periph_insel_regwen_37_wd = reg_wdata[0]; - assign mio_periph_insel_0_we = addr_hit[39] & reg_we & !reg_error; + assign mio_periph_insel_0_we = addr_hit[36] & reg_we & !reg_error; assign mio_periph_insel_0_wd = reg_wdata[5:0]; - assign mio_periph_insel_1_we = addr_hit[40] & reg_we & !reg_error; + assign mio_periph_insel_1_we = addr_hit[37] & reg_we & !reg_error; assign mio_periph_insel_1_wd = reg_wdata[5:0]; - assign mio_periph_insel_2_we = addr_hit[41] & reg_we & !reg_error; + assign mio_periph_insel_2_we = addr_hit[38] & reg_we & !reg_error; assign mio_periph_insel_2_wd = reg_wdata[5:0]; - assign mio_periph_insel_3_we = addr_hit[42] & reg_we & !reg_error; + assign mio_periph_insel_3_we = addr_hit[39] & reg_we & !reg_error; assign mio_periph_insel_3_wd = reg_wdata[5:0]; - assign mio_periph_insel_4_we = addr_hit[43] & reg_we & !reg_error; + assign mio_periph_insel_4_we = addr_hit[40] & reg_we & !reg_error; assign mio_periph_insel_4_wd = reg_wdata[5:0]; - assign mio_periph_insel_5_we = addr_hit[44] & reg_we & !reg_error; + assign mio_periph_insel_5_we = addr_hit[41] & reg_we & !reg_error; assign mio_periph_insel_5_wd = reg_wdata[5:0]; - assign mio_periph_insel_6_we = addr_hit[45] & reg_we & !reg_error; + assign mio_periph_insel_6_we = addr_hit[42] & reg_we & !reg_error; assign mio_periph_insel_6_wd = reg_wdata[5:0]; - assign mio_periph_insel_7_we = addr_hit[46] & reg_we & !reg_error; + assign mio_periph_insel_7_we = addr_hit[43] & reg_we & !reg_error; assign mio_periph_insel_7_wd = reg_wdata[5:0]; - assign mio_periph_insel_8_we = addr_hit[47] & reg_we & !reg_error; + assign mio_periph_insel_8_we = addr_hit[44] & reg_we & !reg_error; assign mio_periph_insel_8_wd = reg_wdata[5:0]; - assign mio_periph_insel_9_we = addr_hit[48] & reg_we & !reg_error; + assign mio_periph_insel_9_we = addr_hit[45] & reg_we & !reg_error; assign mio_periph_insel_9_wd = reg_wdata[5:0]; - assign mio_periph_insel_10_we = addr_hit[49] & reg_we & !reg_error; + assign mio_periph_insel_10_we = addr_hit[46] & reg_we & !reg_error; assign mio_periph_insel_10_wd = reg_wdata[5:0]; - assign mio_periph_insel_11_we = addr_hit[50] & reg_we & !reg_error; + assign mio_periph_insel_11_we = addr_hit[47] & reg_we & !reg_error; assign mio_periph_insel_11_wd = reg_wdata[5:0]; - assign mio_periph_insel_12_we = addr_hit[51] & reg_we & !reg_error; + assign mio_periph_insel_12_we = addr_hit[48] & reg_we & !reg_error; assign mio_periph_insel_12_wd = reg_wdata[5:0]; - assign mio_periph_insel_13_we = addr_hit[52] & reg_we & !reg_error; + assign mio_periph_insel_13_we = addr_hit[49] & reg_we & !reg_error; assign mio_periph_insel_13_wd = reg_wdata[5:0]; - assign mio_periph_insel_14_we = addr_hit[53] & reg_we & !reg_error; + assign mio_periph_insel_14_we = addr_hit[50] & reg_we & !reg_error; assign mio_periph_insel_14_wd = reg_wdata[5:0]; - assign mio_periph_insel_15_we = addr_hit[54] & reg_we & !reg_error; + assign mio_periph_insel_15_we = addr_hit[51] & reg_we & !reg_error; assign mio_periph_insel_15_wd = reg_wdata[5:0]; - assign mio_periph_insel_16_we = addr_hit[55] & reg_we & !reg_error; + assign mio_periph_insel_16_we = addr_hit[52] & reg_we & !reg_error; assign mio_periph_insel_16_wd = reg_wdata[5:0]; - assign mio_periph_insel_17_we = addr_hit[56] & reg_we & !reg_error; + assign mio_periph_insel_17_we = addr_hit[53] & reg_we & !reg_error; assign mio_periph_insel_17_wd = reg_wdata[5:0]; - assign mio_periph_insel_18_we = addr_hit[57] & reg_we & !reg_error; + assign mio_periph_insel_18_we = addr_hit[54] & reg_we & !reg_error; assign mio_periph_insel_18_wd = reg_wdata[5:0]; - assign mio_periph_insel_19_we = addr_hit[58] & reg_we & !reg_error; + assign mio_periph_insel_19_we = addr_hit[55] & reg_we & !reg_error; assign mio_periph_insel_19_wd = reg_wdata[5:0]; - assign mio_periph_insel_20_we = addr_hit[59] & reg_we & !reg_error; + assign mio_periph_insel_20_we = addr_hit[56] & reg_we & !reg_error; assign mio_periph_insel_20_wd = reg_wdata[5:0]; - assign mio_periph_insel_21_we = addr_hit[60] & reg_we & !reg_error; + assign mio_periph_insel_21_we = addr_hit[57] & reg_we & !reg_error; assign mio_periph_insel_21_wd = reg_wdata[5:0]; - assign mio_periph_insel_22_we = addr_hit[61] & reg_we & !reg_error; + assign mio_periph_insel_22_we = addr_hit[58] & reg_we & !reg_error; assign mio_periph_insel_22_wd = reg_wdata[5:0]; - assign mio_periph_insel_23_we = addr_hit[62] & reg_we & !reg_error; + assign mio_periph_insel_23_we = addr_hit[59] & reg_we & !reg_error; assign mio_periph_insel_23_wd = reg_wdata[5:0]; - assign mio_periph_insel_24_we = addr_hit[63] & reg_we & !reg_error; + assign mio_periph_insel_24_we = addr_hit[60] & reg_we & !reg_error; assign mio_periph_insel_24_wd = reg_wdata[5:0]; - assign mio_periph_insel_25_we = addr_hit[64] & reg_we & !reg_error; + assign mio_periph_insel_25_we = addr_hit[61] & reg_we & !reg_error; assign mio_periph_insel_25_wd = reg_wdata[5:0]; - assign mio_periph_insel_26_we = addr_hit[65] & reg_we & !reg_error; + assign mio_periph_insel_26_we = addr_hit[62] & reg_we & !reg_error; assign mio_periph_insel_26_wd = reg_wdata[5:0]; - assign mio_periph_insel_27_we = addr_hit[66] & reg_we & !reg_error; + assign mio_periph_insel_27_we = addr_hit[63] & reg_we & !reg_error; assign mio_periph_insel_27_wd = reg_wdata[5:0]; - assign mio_periph_insel_28_we = addr_hit[67] & reg_we & !reg_error; + assign mio_periph_insel_28_we = addr_hit[64] & reg_we & !reg_error; assign mio_periph_insel_28_wd = reg_wdata[5:0]; - assign mio_periph_insel_29_we = addr_hit[68] & reg_we & !reg_error; + assign mio_periph_insel_29_we = addr_hit[65] & reg_we & !reg_error; assign mio_periph_insel_29_wd = reg_wdata[5:0]; - assign mio_periph_insel_30_we = addr_hit[69] & reg_we & !reg_error; + assign mio_periph_insel_30_we = addr_hit[66] & reg_we & !reg_error; assign mio_periph_insel_30_wd = reg_wdata[5:0]; - assign mio_periph_insel_31_we = addr_hit[70] & reg_we & !reg_error; + assign mio_periph_insel_31_we = addr_hit[67] & reg_we & !reg_error; assign mio_periph_insel_31_wd = reg_wdata[5:0]; - assign mio_periph_insel_32_we = addr_hit[71] & reg_we & !reg_error; + assign mio_periph_insel_32_we = addr_hit[68] & reg_we & !reg_error; assign mio_periph_insel_32_wd = reg_wdata[5:0]; - assign mio_periph_insel_33_we = addr_hit[72] & reg_we & !reg_error; + assign mio_periph_insel_33_we = addr_hit[69] & reg_we & !reg_error; assign mio_periph_insel_33_wd = reg_wdata[5:0]; - assign mio_periph_insel_34_we = addr_hit[73] & reg_we & !reg_error; + assign mio_periph_insel_34_we = addr_hit[70] & reg_we & !reg_error; assign mio_periph_insel_34_wd = reg_wdata[5:0]; - assign mio_periph_insel_35_we = addr_hit[74] & reg_we & !reg_error; - - assign mio_periph_insel_35_wd = reg_wdata[5:0]; - assign mio_periph_insel_36_we = addr_hit[75] & reg_we & !reg_error; - - assign mio_periph_insel_36_wd = reg_wdata[5:0]; - assign mio_periph_insel_37_we = addr_hit[76] & reg_we & !reg_error; - - assign mio_periph_insel_37_wd = reg_wdata[5:0]; - assign mio_outsel_regwen_0_we = addr_hit[77] & reg_we & !reg_error; + assign mio_outsel_regwen_0_we = addr_hit[71] & reg_we & !reg_error; assign mio_outsel_regwen_0_wd = reg_wdata[0]; - assign mio_outsel_regwen_1_we = addr_hit[78] & reg_we & !reg_error; + assign mio_outsel_regwen_1_we = addr_hit[72] & reg_we & !reg_error; assign mio_outsel_regwen_1_wd = reg_wdata[0]; - assign mio_outsel_regwen_2_we = addr_hit[79] & reg_we & !reg_error; + assign mio_outsel_regwen_2_we = addr_hit[73] & reg_we & !reg_error; assign mio_outsel_regwen_2_wd = reg_wdata[0]; - assign mio_outsel_regwen_3_we = addr_hit[80] & reg_we & !reg_error; + assign mio_outsel_regwen_3_we = addr_hit[74] & reg_we & !reg_error; assign mio_outsel_regwen_3_wd = reg_wdata[0]; - assign mio_outsel_regwen_4_we = addr_hit[81] & reg_we & !reg_error; + assign mio_outsel_regwen_4_we = addr_hit[75] & reg_we & !reg_error; assign mio_outsel_regwen_4_wd = reg_wdata[0]; - assign mio_outsel_regwen_5_we = addr_hit[82] & reg_we & !reg_error; + assign mio_outsel_regwen_5_we = addr_hit[76] & reg_we & !reg_error; assign mio_outsel_regwen_5_wd = reg_wdata[0]; - assign mio_outsel_regwen_6_we = addr_hit[83] & reg_we & !reg_error; + assign mio_outsel_regwen_6_we = addr_hit[77] & reg_we & !reg_error; assign mio_outsel_regwen_6_wd = reg_wdata[0]; - assign mio_outsel_regwen_7_we = addr_hit[84] & reg_we & !reg_error; + assign mio_outsel_regwen_7_we = addr_hit[78] & reg_we & !reg_error; assign mio_outsel_regwen_7_wd = reg_wdata[0]; - assign mio_outsel_regwen_8_we = addr_hit[85] & reg_we & !reg_error; + assign mio_outsel_regwen_8_we = addr_hit[79] & reg_we & !reg_error; assign mio_outsel_regwen_8_wd = reg_wdata[0]; - assign mio_outsel_regwen_9_we = addr_hit[86] & reg_we & !reg_error; + assign mio_outsel_regwen_9_we = addr_hit[80] & reg_we & !reg_error; assign mio_outsel_regwen_9_wd = reg_wdata[0]; - assign mio_outsel_regwen_10_we = addr_hit[87] & reg_we & !reg_error; + assign mio_outsel_regwen_10_we = addr_hit[81] & reg_we & !reg_error; assign mio_outsel_regwen_10_wd = reg_wdata[0]; - assign mio_outsel_regwen_11_we = addr_hit[88] & reg_we & !reg_error; + assign mio_outsel_regwen_11_we = addr_hit[82] & reg_we & !reg_error; assign mio_outsel_regwen_11_wd = reg_wdata[0]; - assign mio_outsel_regwen_12_we = addr_hit[89] & reg_we & !reg_error; + assign mio_outsel_regwen_12_we = addr_hit[83] & reg_we & !reg_error; assign mio_outsel_regwen_12_wd = reg_wdata[0]; - assign mio_outsel_regwen_13_we = addr_hit[90] & reg_we & !reg_error; + assign mio_outsel_regwen_13_we = addr_hit[84] & reg_we & !reg_error; assign mio_outsel_regwen_13_wd = reg_wdata[0]; - assign mio_outsel_regwen_14_we = addr_hit[91] & reg_we & !reg_error; + assign mio_outsel_regwen_14_we = addr_hit[85] & reg_we & !reg_error; assign mio_outsel_regwen_14_wd = reg_wdata[0]; - assign mio_outsel_regwen_15_we = addr_hit[92] & reg_we & !reg_error; + assign mio_outsel_regwen_15_we = addr_hit[86] & reg_we & !reg_error; assign mio_outsel_regwen_15_wd = reg_wdata[0]; - assign mio_outsel_regwen_16_we = addr_hit[93] & reg_we & !reg_error; + assign mio_outsel_regwen_16_we = addr_hit[87] & reg_we & !reg_error; assign mio_outsel_regwen_16_wd = reg_wdata[0]; - assign mio_outsel_regwen_17_we = addr_hit[94] & reg_we & !reg_error; + assign mio_outsel_regwen_17_we = addr_hit[88] & reg_we & !reg_error; assign mio_outsel_regwen_17_wd = reg_wdata[0]; - assign mio_outsel_regwen_18_we = addr_hit[95] & reg_we & !reg_error; + assign mio_outsel_regwen_18_we = addr_hit[89] & reg_we & !reg_error; assign mio_outsel_regwen_18_wd = reg_wdata[0]; - assign mio_outsel_regwen_19_we = addr_hit[96] & reg_we & !reg_error; + assign mio_outsel_regwen_19_we = addr_hit[90] & reg_we & !reg_error; assign mio_outsel_regwen_19_wd = reg_wdata[0]; - assign mio_outsel_regwen_20_we = addr_hit[97] & reg_we & !reg_error; + assign mio_outsel_regwen_20_we = addr_hit[91] & reg_we & !reg_error; assign mio_outsel_regwen_20_wd = reg_wdata[0]; - assign mio_outsel_regwen_21_we = addr_hit[98] & reg_we & !reg_error; + assign mio_outsel_regwen_21_we = addr_hit[92] & reg_we & !reg_error; assign mio_outsel_regwen_21_wd = reg_wdata[0]; - assign mio_outsel_regwen_22_we = addr_hit[99] & reg_we & !reg_error; + assign mio_outsel_regwen_22_we = addr_hit[93] & reg_we & !reg_error; assign mio_outsel_regwen_22_wd = reg_wdata[0]; - assign mio_outsel_regwen_23_we = addr_hit[100] & reg_we & !reg_error; + assign mio_outsel_regwen_23_we = addr_hit[94] & reg_we & !reg_error; assign mio_outsel_regwen_23_wd = reg_wdata[0]; - assign mio_outsel_regwen_24_we = addr_hit[101] & reg_we & !reg_error; + assign mio_outsel_regwen_24_we = addr_hit[95] & reg_we & !reg_error; assign mio_outsel_regwen_24_wd = reg_wdata[0]; - assign mio_outsel_regwen_25_we = addr_hit[102] & reg_we & !reg_error; + assign mio_outsel_regwen_25_we = addr_hit[96] & reg_we & !reg_error; assign mio_outsel_regwen_25_wd = reg_wdata[0]; - assign mio_outsel_regwen_26_we = addr_hit[103] & reg_we & !reg_error; + assign mio_outsel_regwen_26_we = addr_hit[97] & reg_we & !reg_error; assign mio_outsel_regwen_26_wd = reg_wdata[0]; - assign mio_outsel_regwen_27_we = addr_hit[104] & reg_we & !reg_error; + assign mio_outsel_regwen_27_we = addr_hit[98] & reg_we & !reg_error; assign mio_outsel_regwen_27_wd = reg_wdata[0]; - assign mio_outsel_regwen_28_we = addr_hit[105] & reg_we & !reg_error; + assign mio_outsel_regwen_28_we = addr_hit[99] & reg_we & !reg_error; assign mio_outsel_regwen_28_wd = reg_wdata[0]; - assign mio_outsel_regwen_29_we = addr_hit[106] & reg_we & !reg_error; + assign mio_outsel_regwen_29_we = addr_hit[100] & reg_we & !reg_error; assign mio_outsel_regwen_29_wd = reg_wdata[0]; - assign mio_outsel_regwen_30_we = addr_hit[107] & reg_we & !reg_error; + assign mio_outsel_regwen_30_we = addr_hit[101] & reg_we & !reg_error; assign mio_outsel_regwen_30_wd = reg_wdata[0]; - assign mio_outsel_regwen_31_we = addr_hit[108] & reg_we & !reg_error; + assign mio_outsel_regwen_31_we = addr_hit[102] & reg_we & !reg_error; assign mio_outsel_regwen_31_wd = reg_wdata[0]; - assign mio_outsel_regwen_32_we = addr_hit[109] & reg_we & !reg_error; + assign mio_outsel_regwen_32_we = addr_hit[103] & reg_we & !reg_error; assign mio_outsel_regwen_32_wd = reg_wdata[0]; - assign mio_outsel_regwen_33_we = addr_hit[110] & reg_we & !reg_error; + assign mio_outsel_regwen_33_we = addr_hit[104] & reg_we & !reg_error; assign mio_outsel_regwen_33_wd = reg_wdata[0]; - assign mio_outsel_regwen_34_we = addr_hit[111] & reg_we & !reg_error; + assign mio_outsel_regwen_34_we = addr_hit[105] & reg_we & !reg_error; assign mio_outsel_regwen_34_wd = reg_wdata[0]; - assign mio_outsel_regwen_35_we = addr_hit[112] & reg_we & !reg_error; + assign mio_outsel_regwen_35_we = addr_hit[106] & reg_we & !reg_error; assign mio_outsel_regwen_35_wd = reg_wdata[0]; - assign mio_outsel_regwen_36_we = addr_hit[113] & reg_we & !reg_error; + assign mio_outsel_regwen_36_we = addr_hit[107] & reg_we & !reg_error; assign mio_outsel_regwen_36_wd = reg_wdata[0]; - assign mio_outsel_regwen_37_we = addr_hit[114] & reg_we & !reg_error; + assign mio_outsel_regwen_37_we = addr_hit[108] & reg_we & !reg_error; assign mio_outsel_regwen_37_wd = reg_wdata[0]; - assign mio_outsel_regwen_38_we = addr_hit[115] & reg_we & !reg_error; + assign mio_outsel_regwen_38_we = addr_hit[109] & reg_we & !reg_error; assign mio_outsel_regwen_38_wd = reg_wdata[0]; - assign mio_outsel_regwen_39_we = addr_hit[116] & reg_we & !reg_error; + assign mio_outsel_regwen_39_we = addr_hit[110] & reg_we & !reg_error; assign mio_outsel_regwen_39_wd = reg_wdata[0]; - assign mio_outsel_regwen_40_we = addr_hit[117] & reg_we & !reg_error; + assign mio_outsel_regwen_40_we = addr_hit[111] & reg_we & !reg_error; assign mio_outsel_regwen_40_wd = reg_wdata[0]; - assign mio_outsel_regwen_41_we = addr_hit[118] & reg_we & !reg_error; + assign mio_outsel_regwen_41_we = addr_hit[112] & reg_we & !reg_error; assign mio_outsel_regwen_41_wd = reg_wdata[0]; - assign mio_outsel_regwen_42_we = addr_hit[119] & reg_we & !reg_error; + assign mio_outsel_regwen_42_we = addr_hit[113] & reg_we & !reg_error; assign mio_outsel_regwen_42_wd = reg_wdata[0]; - assign mio_outsel_regwen_43_we = addr_hit[120] & reg_we & !reg_error; + assign mio_outsel_regwen_43_we = addr_hit[114] & reg_we & !reg_error; assign mio_outsel_regwen_43_wd = reg_wdata[0]; - assign mio_outsel_regwen_44_we = addr_hit[121] & reg_we & !reg_error; + assign mio_outsel_regwen_44_we = addr_hit[115] & reg_we & !reg_error; assign mio_outsel_regwen_44_wd = reg_wdata[0]; - assign mio_outsel_regwen_45_we = addr_hit[122] & reg_we & !reg_error; + assign mio_outsel_regwen_45_we = addr_hit[116] & reg_we & !reg_error; assign mio_outsel_regwen_45_wd = reg_wdata[0]; - assign mio_outsel_regwen_46_we = addr_hit[123] & reg_we & !reg_error; + assign mio_outsel_regwen_46_we = addr_hit[117] & reg_we & !reg_error; assign mio_outsel_regwen_46_wd = reg_wdata[0]; - assign mio_outsel_0_we = addr_hit[124] & reg_we & !reg_error; + assign mio_outsel_0_we = addr_hit[118] & reg_we & !reg_error; assign mio_outsel_0_wd = reg_wdata[5:0]; - assign mio_outsel_1_we = addr_hit[125] & reg_we & !reg_error; + assign mio_outsel_1_we = addr_hit[119] & reg_we & !reg_error; assign mio_outsel_1_wd = reg_wdata[5:0]; - assign mio_outsel_2_we = addr_hit[126] & reg_we & !reg_error; + assign mio_outsel_2_we = addr_hit[120] & reg_we & !reg_error; assign mio_outsel_2_wd = reg_wdata[5:0]; - assign mio_outsel_3_we = addr_hit[127] & reg_we & !reg_error; + assign mio_outsel_3_we = addr_hit[121] & reg_we & !reg_error; assign mio_outsel_3_wd = reg_wdata[5:0]; - assign mio_outsel_4_we = addr_hit[128] & reg_we & !reg_error; + assign mio_outsel_4_we = addr_hit[122] & reg_we & !reg_error; assign mio_outsel_4_wd = reg_wdata[5:0]; - assign mio_outsel_5_we = addr_hit[129] & reg_we & !reg_error; + assign mio_outsel_5_we = addr_hit[123] & reg_we & !reg_error; assign mio_outsel_5_wd = reg_wdata[5:0]; - assign mio_outsel_6_we = addr_hit[130] & reg_we & !reg_error; + assign mio_outsel_6_we = addr_hit[124] & reg_we & !reg_error; assign mio_outsel_6_wd = reg_wdata[5:0]; - assign mio_outsel_7_we = addr_hit[131] & reg_we & !reg_error; + assign mio_outsel_7_we = addr_hit[125] & reg_we & !reg_error; assign mio_outsel_7_wd = reg_wdata[5:0]; - assign mio_outsel_8_we = addr_hit[132] & reg_we & !reg_error; + assign mio_outsel_8_we = addr_hit[126] & reg_we & !reg_error; assign mio_outsel_8_wd = reg_wdata[5:0]; - assign mio_outsel_9_we = addr_hit[133] & reg_we & !reg_error; + assign mio_outsel_9_we = addr_hit[127] & reg_we & !reg_error; assign mio_outsel_9_wd = reg_wdata[5:0]; - assign mio_outsel_10_we = addr_hit[134] & reg_we & !reg_error; + assign mio_outsel_10_we = addr_hit[128] & reg_we & !reg_error; assign mio_outsel_10_wd = reg_wdata[5:0]; - assign mio_outsel_11_we = addr_hit[135] & reg_we & !reg_error; + assign mio_outsel_11_we = addr_hit[129] & reg_we & !reg_error; assign mio_outsel_11_wd = reg_wdata[5:0]; - assign mio_outsel_12_we = addr_hit[136] & reg_we & !reg_error; + assign mio_outsel_12_we = addr_hit[130] & reg_we & !reg_error; assign mio_outsel_12_wd = reg_wdata[5:0]; - assign mio_outsel_13_we = addr_hit[137] & reg_we & !reg_error; + assign mio_outsel_13_we = addr_hit[131] & reg_we & !reg_error; assign mio_outsel_13_wd = reg_wdata[5:0]; - assign mio_outsel_14_we = addr_hit[138] & reg_we & !reg_error; + assign mio_outsel_14_we = addr_hit[132] & reg_we & !reg_error; assign mio_outsel_14_wd = reg_wdata[5:0]; - assign mio_outsel_15_we = addr_hit[139] & reg_we & !reg_error; + assign mio_outsel_15_we = addr_hit[133] & reg_we & !reg_error; assign mio_outsel_15_wd = reg_wdata[5:0]; - assign mio_outsel_16_we = addr_hit[140] & reg_we & !reg_error; + assign mio_outsel_16_we = addr_hit[134] & reg_we & !reg_error; assign mio_outsel_16_wd = reg_wdata[5:0]; - assign mio_outsel_17_we = addr_hit[141] & reg_we & !reg_error; + assign mio_outsel_17_we = addr_hit[135] & reg_we & !reg_error; assign mio_outsel_17_wd = reg_wdata[5:0]; - assign mio_outsel_18_we = addr_hit[142] & reg_we & !reg_error; + assign mio_outsel_18_we = addr_hit[136] & reg_we & !reg_error; assign mio_outsel_18_wd = reg_wdata[5:0]; - assign mio_outsel_19_we = addr_hit[143] & reg_we & !reg_error; + assign mio_outsel_19_we = addr_hit[137] & reg_we & !reg_error; assign mio_outsel_19_wd = reg_wdata[5:0]; - assign mio_outsel_20_we = addr_hit[144] & reg_we & !reg_error; + assign mio_outsel_20_we = addr_hit[138] & reg_we & !reg_error; assign mio_outsel_20_wd = reg_wdata[5:0]; - assign mio_outsel_21_we = addr_hit[145] & reg_we & !reg_error; + assign mio_outsel_21_we = addr_hit[139] & reg_we & !reg_error; assign mio_outsel_21_wd = reg_wdata[5:0]; - assign mio_outsel_22_we = addr_hit[146] & reg_we & !reg_error; + assign mio_outsel_22_we = addr_hit[140] & reg_we & !reg_error; assign mio_outsel_22_wd = reg_wdata[5:0]; - assign mio_outsel_23_we = addr_hit[147] & reg_we & !reg_error; + assign mio_outsel_23_we = addr_hit[141] & reg_we & !reg_error; assign mio_outsel_23_wd = reg_wdata[5:0]; - assign mio_outsel_24_we = addr_hit[148] & reg_we & !reg_error; + assign mio_outsel_24_we = addr_hit[142] & reg_we & !reg_error; assign mio_outsel_24_wd = reg_wdata[5:0]; - assign mio_outsel_25_we = addr_hit[149] & reg_we & !reg_error; + assign mio_outsel_25_we = addr_hit[143] & reg_we & !reg_error; assign mio_outsel_25_wd = reg_wdata[5:0]; - assign mio_outsel_26_we = addr_hit[150] & reg_we & !reg_error; + assign mio_outsel_26_we = addr_hit[144] & reg_we & !reg_error; assign mio_outsel_26_wd = reg_wdata[5:0]; - assign mio_outsel_27_we = addr_hit[151] & reg_we & !reg_error; + assign mio_outsel_27_we = addr_hit[145] & reg_we & !reg_error; assign mio_outsel_27_wd = reg_wdata[5:0]; - assign mio_outsel_28_we = addr_hit[152] & reg_we & !reg_error; + assign mio_outsel_28_we = addr_hit[146] & reg_we & !reg_error; assign mio_outsel_28_wd = reg_wdata[5:0]; - assign mio_outsel_29_we = addr_hit[153] & reg_we & !reg_error; + assign mio_outsel_29_we = addr_hit[147] & reg_we & !reg_error; assign mio_outsel_29_wd = reg_wdata[5:0]; - assign mio_outsel_30_we = addr_hit[154] & reg_we & !reg_error; + assign mio_outsel_30_we = addr_hit[148] & reg_we & !reg_error; assign mio_outsel_30_wd = reg_wdata[5:0]; - assign mio_outsel_31_we = addr_hit[155] & reg_we & !reg_error; + assign mio_outsel_31_we = addr_hit[149] & reg_we & !reg_error; assign mio_outsel_31_wd = reg_wdata[5:0]; - assign mio_outsel_32_we = addr_hit[156] & reg_we & !reg_error; + assign mio_outsel_32_we = addr_hit[150] & reg_we & !reg_error; assign mio_outsel_32_wd = reg_wdata[5:0]; - assign mio_outsel_33_we = addr_hit[157] & reg_we & !reg_error; + assign mio_outsel_33_we = addr_hit[151] & reg_we & !reg_error; assign mio_outsel_33_wd = reg_wdata[5:0]; - assign mio_outsel_34_we = addr_hit[158] & reg_we & !reg_error; + assign mio_outsel_34_we = addr_hit[152] & reg_we & !reg_error; assign mio_outsel_34_wd = reg_wdata[5:0]; - assign mio_outsel_35_we = addr_hit[159] & reg_we & !reg_error; + assign mio_outsel_35_we = addr_hit[153] & reg_we & !reg_error; assign mio_outsel_35_wd = reg_wdata[5:0]; - assign mio_outsel_36_we = addr_hit[160] & reg_we & !reg_error; + assign mio_outsel_36_we = addr_hit[154] & reg_we & !reg_error; assign mio_outsel_36_wd = reg_wdata[5:0]; - assign mio_outsel_37_we = addr_hit[161] & reg_we & !reg_error; + assign mio_outsel_37_we = addr_hit[155] & reg_we & !reg_error; assign mio_outsel_37_wd = reg_wdata[5:0]; - assign mio_outsel_38_we = addr_hit[162] & reg_we & !reg_error; + assign mio_outsel_38_we = addr_hit[156] & reg_we & !reg_error; assign mio_outsel_38_wd = reg_wdata[5:0]; - assign mio_outsel_39_we = addr_hit[163] & reg_we & !reg_error; + assign mio_outsel_39_we = addr_hit[157] & reg_we & !reg_error; assign mio_outsel_39_wd = reg_wdata[5:0]; - assign mio_outsel_40_we = addr_hit[164] & reg_we & !reg_error; + assign mio_outsel_40_we = addr_hit[158] & reg_we & !reg_error; assign mio_outsel_40_wd = reg_wdata[5:0]; - assign mio_outsel_41_we = addr_hit[165] & reg_we & !reg_error; + assign mio_outsel_41_we = addr_hit[159] & reg_we & !reg_error; assign mio_outsel_41_wd = reg_wdata[5:0]; - assign mio_outsel_42_we = addr_hit[166] & reg_we & !reg_error; + assign mio_outsel_42_we = addr_hit[160] & reg_we & !reg_error; assign mio_outsel_42_wd = reg_wdata[5:0]; - assign mio_outsel_43_we = addr_hit[167] & reg_we & !reg_error; + assign mio_outsel_43_we = addr_hit[161] & reg_we & !reg_error; assign mio_outsel_43_wd = reg_wdata[5:0]; - assign mio_outsel_44_we = addr_hit[168] & reg_we & !reg_error; + assign mio_outsel_44_we = addr_hit[162] & reg_we & !reg_error; assign mio_outsel_44_wd = reg_wdata[5:0]; - assign mio_outsel_45_we = addr_hit[169] & reg_we & !reg_error; + assign mio_outsel_45_we = addr_hit[163] & reg_we & !reg_error; assign mio_outsel_45_wd = reg_wdata[5:0]; - assign mio_outsel_46_we = addr_hit[170] & reg_we & !reg_error; + assign mio_outsel_46_we = addr_hit[164] & reg_we & !reg_error; assign mio_outsel_46_wd = reg_wdata[5:0]; - assign mio_pad_attr_regwen_0_we = addr_hit[171] & reg_we & !reg_error; + assign mio_pad_attr_regwen_0_we = addr_hit[165] & reg_we & !reg_error; assign mio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_1_we = addr_hit[172] & reg_we & !reg_error; + assign mio_pad_attr_regwen_1_we = addr_hit[166] & reg_we & !reg_error; assign mio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_2_we = addr_hit[173] & reg_we & !reg_error; + assign mio_pad_attr_regwen_2_we = addr_hit[167] & reg_we & !reg_error; assign mio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_3_we = addr_hit[174] & reg_we & !reg_error; + assign mio_pad_attr_regwen_3_we = addr_hit[168] & reg_we & !reg_error; assign mio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_4_we = addr_hit[175] & reg_we & !reg_error; + assign mio_pad_attr_regwen_4_we = addr_hit[169] & reg_we & !reg_error; assign mio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_5_we = addr_hit[176] & reg_we & !reg_error; + assign mio_pad_attr_regwen_5_we = addr_hit[170] & reg_we & !reg_error; assign mio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_6_we = addr_hit[177] & reg_we & !reg_error; + assign mio_pad_attr_regwen_6_we = addr_hit[171] & reg_we & !reg_error; assign mio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_7_we = addr_hit[178] & reg_we & !reg_error; + assign mio_pad_attr_regwen_7_we = addr_hit[172] & reg_we & !reg_error; assign mio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_8_we = addr_hit[179] & reg_we & !reg_error; + assign mio_pad_attr_regwen_8_we = addr_hit[173] & reg_we & !reg_error; assign mio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_9_we = addr_hit[180] & reg_we & !reg_error; + assign mio_pad_attr_regwen_9_we = addr_hit[174] & reg_we & !reg_error; assign mio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_10_we = addr_hit[181] & reg_we & !reg_error; + assign mio_pad_attr_regwen_10_we = addr_hit[175] & reg_we & !reg_error; assign mio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_11_we = addr_hit[182] & reg_we & !reg_error; + assign mio_pad_attr_regwen_11_we = addr_hit[176] & reg_we & !reg_error; assign mio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_12_we = addr_hit[183] & reg_we & !reg_error; + assign mio_pad_attr_regwen_12_we = addr_hit[177] & reg_we & !reg_error; assign mio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_13_we = addr_hit[184] & reg_we & !reg_error; + assign mio_pad_attr_regwen_13_we = addr_hit[178] & reg_we & !reg_error; assign mio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_14_we = addr_hit[185] & reg_we & !reg_error; + assign mio_pad_attr_regwen_14_we = addr_hit[179] & reg_we & !reg_error; assign mio_pad_attr_regwen_14_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_15_we = addr_hit[186] & reg_we & !reg_error; + assign mio_pad_attr_regwen_15_we = addr_hit[180] & reg_we & !reg_error; assign mio_pad_attr_regwen_15_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_16_we = addr_hit[187] & reg_we & !reg_error; + assign mio_pad_attr_regwen_16_we = addr_hit[181] & reg_we & !reg_error; assign mio_pad_attr_regwen_16_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_17_we = addr_hit[188] & reg_we & !reg_error; + assign mio_pad_attr_regwen_17_we = addr_hit[182] & reg_we & !reg_error; assign mio_pad_attr_regwen_17_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_18_we = addr_hit[189] & reg_we & !reg_error; + assign mio_pad_attr_regwen_18_we = addr_hit[183] & reg_we & !reg_error; assign mio_pad_attr_regwen_18_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_19_we = addr_hit[190] & reg_we & !reg_error; + assign mio_pad_attr_regwen_19_we = addr_hit[184] & reg_we & !reg_error; assign mio_pad_attr_regwen_19_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_20_we = addr_hit[191] & reg_we & !reg_error; + assign mio_pad_attr_regwen_20_we = addr_hit[185] & reg_we & !reg_error; assign mio_pad_attr_regwen_20_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_21_we = addr_hit[192] & reg_we & !reg_error; + assign mio_pad_attr_regwen_21_we = addr_hit[186] & reg_we & !reg_error; assign mio_pad_attr_regwen_21_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_22_we = addr_hit[193] & reg_we & !reg_error; + assign mio_pad_attr_regwen_22_we = addr_hit[187] & reg_we & !reg_error; assign mio_pad_attr_regwen_22_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_23_we = addr_hit[194] & reg_we & !reg_error; + assign mio_pad_attr_regwen_23_we = addr_hit[188] & reg_we & !reg_error; assign mio_pad_attr_regwen_23_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_24_we = addr_hit[195] & reg_we & !reg_error; + assign mio_pad_attr_regwen_24_we = addr_hit[189] & reg_we & !reg_error; assign mio_pad_attr_regwen_24_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_25_we = addr_hit[196] & reg_we & !reg_error; + assign mio_pad_attr_regwen_25_we = addr_hit[190] & reg_we & !reg_error; assign mio_pad_attr_regwen_25_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_26_we = addr_hit[197] & reg_we & !reg_error; + assign mio_pad_attr_regwen_26_we = addr_hit[191] & reg_we & !reg_error; assign mio_pad_attr_regwen_26_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_27_we = addr_hit[198] & reg_we & !reg_error; + assign mio_pad_attr_regwen_27_we = addr_hit[192] & reg_we & !reg_error; assign mio_pad_attr_regwen_27_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_28_we = addr_hit[199] & reg_we & !reg_error; + assign mio_pad_attr_regwen_28_we = addr_hit[193] & reg_we & !reg_error; assign mio_pad_attr_regwen_28_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_29_we = addr_hit[200] & reg_we & !reg_error; + assign mio_pad_attr_regwen_29_we = addr_hit[194] & reg_we & !reg_error; assign mio_pad_attr_regwen_29_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_30_we = addr_hit[201] & reg_we & !reg_error; + assign mio_pad_attr_regwen_30_we = addr_hit[195] & reg_we & !reg_error; assign mio_pad_attr_regwen_30_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_31_we = addr_hit[202] & reg_we & !reg_error; + assign mio_pad_attr_regwen_31_we = addr_hit[196] & reg_we & !reg_error; assign mio_pad_attr_regwen_31_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_32_we = addr_hit[203] & reg_we & !reg_error; + assign mio_pad_attr_regwen_32_we = addr_hit[197] & reg_we & !reg_error; assign mio_pad_attr_regwen_32_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_33_we = addr_hit[204] & reg_we & !reg_error; + assign mio_pad_attr_regwen_33_we = addr_hit[198] & reg_we & !reg_error; assign mio_pad_attr_regwen_33_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_34_we = addr_hit[205] & reg_we & !reg_error; + assign mio_pad_attr_regwen_34_we = addr_hit[199] & reg_we & !reg_error; assign mio_pad_attr_regwen_34_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_35_we = addr_hit[206] & reg_we & !reg_error; + assign mio_pad_attr_regwen_35_we = addr_hit[200] & reg_we & !reg_error; assign mio_pad_attr_regwen_35_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_36_we = addr_hit[207] & reg_we & !reg_error; + assign mio_pad_attr_regwen_36_we = addr_hit[201] & reg_we & !reg_error; assign mio_pad_attr_regwen_36_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_37_we = addr_hit[208] & reg_we & !reg_error; + assign mio_pad_attr_regwen_37_we = addr_hit[202] & reg_we & !reg_error; assign mio_pad_attr_regwen_37_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_38_we = addr_hit[209] & reg_we & !reg_error; + assign mio_pad_attr_regwen_38_we = addr_hit[203] & reg_we & !reg_error; assign mio_pad_attr_regwen_38_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_39_we = addr_hit[210] & reg_we & !reg_error; + assign mio_pad_attr_regwen_39_we = addr_hit[204] & reg_we & !reg_error; assign mio_pad_attr_regwen_39_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_40_we = addr_hit[211] & reg_we & !reg_error; + assign mio_pad_attr_regwen_40_we = addr_hit[205] & reg_we & !reg_error; assign mio_pad_attr_regwen_40_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_41_we = addr_hit[212] & reg_we & !reg_error; + assign mio_pad_attr_regwen_41_we = addr_hit[206] & reg_we & !reg_error; assign mio_pad_attr_regwen_41_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_42_we = addr_hit[213] & reg_we & !reg_error; + assign mio_pad_attr_regwen_42_we = addr_hit[207] & reg_we & !reg_error; assign mio_pad_attr_regwen_42_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_43_we = addr_hit[214] & reg_we & !reg_error; + assign mio_pad_attr_regwen_43_we = addr_hit[208] & reg_we & !reg_error; assign mio_pad_attr_regwen_43_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_44_we = addr_hit[215] & reg_we & !reg_error; + assign mio_pad_attr_regwen_44_we = addr_hit[209] & reg_we & !reg_error; assign mio_pad_attr_regwen_44_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_45_we = addr_hit[216] & reg_we & !reg_error; + assign mio_pad_attr_regwen_45_we = addr_hit[210] & reg_we & !reg_error; assign mio_pad_attr_regwen_45_wd = reg_wdata[0]; - assign mio_pad_attr_regwen_46_we = addr_hit[217] & reg_we & !reg_error; + assign mio_pad_attr_regwen_46_we = addr_hit[211] & reg_we & !reg_error; assign mio_pad_attr_regwen_46_wd = reg_wdata[0]; - assign mio_pad_attr_0_re = addr_hit[218] & reg_re & !reg_error; - assign mio_pad_attr_0_we = addr_hit[218] & reg_we & !reg_error; + assign mio_pad_attr_0_re = addr_hit[212] & reg_re & !reg_error; + assign mio_pad_attr_0_we = addr_hit[212] & reg_we & !reg_error; assign mio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -32274,8 +32043,8 @@ module pinmux_reg_top ( assign mio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign mio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign mio_pad_attr_1_re = addr_hit[219] & reg_re & !reg_error; - assign mio_pad_attr_1_we = addr_hit[219] & reg_we & !reg_error; + assign mio_pad_attr_1_re = addr_hit[213] & reg_re & !reg_error; + assign mio_pad_attr_1_we = addr_hit[213] & reg_we & !reg_error; assign mio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -32296,8 +32065,8 @@ module pinmux_reg_top ( assign mio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign mio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign mio_pad_attr_2_re = addr_hit[220] & reg_re & !reg_error; - assign mio_pad_attr_2_we = addr_hit[220] & reg_we & !reg_error; + assign mio_pad_attr_2_re = addr_hit[214] & reg_re & !reg_error; + assign mio_pad_attr_2_we = addr_hit[214] & reg_we & !reg_error; assign mio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -32318,8 +32087,8 @@ module pinmux_reg_top ( assign mio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign mio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign mio_pad_attr_3_re = addr_hit[221] & reg_re & !reg_error; - assign mio_pad_attr_3_we = addr_hit[221] & reg_we & !reg_error; + assign mio_pad_attr_3_re = addr_hit[215] & reg_re & !reg_error; + assign mio_pad_attr_3_we = addr_hit[215] & reg_we & !reg_error; assign mio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -32340,8 +32109,8 @@ module pinmux_reg_top ( assign mio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign mio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign mio_pad_attr_4_re = addr_hit[222] & reg_re & !reg_error; - assign mio_pad_attr_4_we = addr_hit[222] & reg_we & !reg_error; + assign mio_pad_attr_4_re = addr_hit[216] & reg_re & !reg_error; + assign mio_pad_attr_4_we = addr_hit[216] & reg_we & !reg_error; assign mio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -32362,8 +32131,8 @@ module pinmux_reg_top ( assign mio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign mio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign mio_pad_attr_5_re = addr_hit[223] & reg_re & !reg_error; - assign mio_pad_attr_5_we = addr_hit[223] & reg_we & !reg_error; + assign mio_pad_attr_5_re = addr_hit[217] & reg_re & !reg_error; + assign mio_pad_attr_5_we = addr_hit[217] & reg_we & !reg_error; assign mio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -32384,8 +32153,8 @@ module pinmux_reg_top ( assign mio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign mio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign mio_pad_attr_6_re = addr_hit[224] & reg_re & !reg_error; - assign mio_pad_attr_6_we = addr_hit[224] & reg_we & !reg_error; + assign mio_pad_attr_6_re = addr_hit[218] & reg_re & !reg_error; + assign mio_pad_attr_6_we = addr_hit[218] & reg_we & !reg_error; assign mio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -32406,8 +32175,8 @@ module pinmux_reg_top ( assign mio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign mio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign mio_pad_attr_7_re = addr_hit[225] & reg_re & !reg_error; - assign mio_pad_attr_7_we = addr_hit[225] & reg_we & !reg_error; + assign mio_pad_attr_7_re = addr_hit[219] & reg_re & !reg_error; + assign mio_pad_attr_7_we = addr_hit[219] & reg_we & !reg_error; assign mio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -32428,8 +32197,8 @@ module pinmux_reg_top ( assign mio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign mio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign mio_pad_attr_8_re = addr_hit[226] & reg_re & !reg_error; - assign mio_pad_attr_8_we = addr_hit[226] & reg_we & !reg_error; + assign mio_pad_attr_8_re = addr_hit[220] & reg_re & !reg_error; + assign mio_pad_attr_8_we = addr_hit[220] & reg_we & !reg_error; assign mio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -32450,8 +32219,8 @@ module pinmux_reg_top ( assign mio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign mio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign mio_pad_attr_9_re = addr_hit[227] & reg_re & !reg_error; - assign mio_pad_attr_9_we = addr_hit[227] & reg_we & !reg_error; + assign mio_pad_attr_9_re = addr_hit[221] & reg_re & !reg_error; + assign mio_pad_attr_9_we = addr_hit[221] & reg_we & !reg_error; assign mio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -32472,8 +32241,8 @@ module pinmux_reg_top ( assign mio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign mio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign mio_pad_attr_10_re = addr_hit[228] & reg_re & !reg_error; - assign mio_pad_attr_10_we = addr_hit[228] & reg_we & !reg_error; + assign mio_pad_attr_10_re = addr_hit[222] & reg_re & !reg_error; + assign mio_pad_attr_10_we = addr_hit[222] & reg_we & !reg_error; assign mio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -32494,8 +32263,8 @@ module pinmux_reg_top ( assign mio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign mio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign mio_pad_attr_11_re = addr_hit[229] & reg_re & !reg_error; - assign mio_pad_attr_11_we = addr_hit[229] & reg_we & !reg_error; + assign mio_pad_attr_11_re = addr_hit[223] & reg_re & !reg_error; + assign mio_pad_attr_11_we = addr_hit[223] & reg_we & !reg_error; assign mio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -32516,8 +32285,8 @@ module pinmux_reg_top ( assign mio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign mio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign mio_pad_attr_12_re = addr_hit[230] & reg_re & !reg_error; - assign mio_pad_attr_12_we = addr_hit[230] & reg_we & !reg_error; + assign mio_pad_attr_12_re = addr_hit[224] & reg_re & !reg_error; + assign mio_pad_attr_12_we = addr_hit[224] & reg_we & !reg_error; assign mio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -32538,8 +32307,8 @@ module pinmux_reg_top ( assign mio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign mio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign mio_pad_attr_13_re = addr_hit[231] & reg_re & !reg_error; - assign mio_pad_attr_13_we = addr_hit[231] & reg_we & !reg_error; + assign mio_pad_attr_13_re = addr_hit[225] & reg_re & !reg_error; + assign mio_pad_attr_13_we = addr_hit[225] & reg_we & !reg_error; assign mio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -32560,8 +32329,8 @@ module pinmux_reg_top ( assign mio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign mio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_attr_14_re = addr_hit[232] & reg_re & !reg_error; - assign mio_pad_attr_14_we = addr_hit[232] & reg_we & !reg_error; + assign mio_pad_attr_14_re = addr_hit[226] & reg_re & !reg_error; + assign mio_pad_attr_14_we = addr_hit[226] & reg_we & !reg_error; assign mio_pad_attr_14_invert_14_wd = reg_wdata[0]; @@ -32582,8 +32351,8 @@ module pinmux_reg_top ( assign mio_pad_attr_14_slew_rate_14_wd = reg_wdata[17:16]; assign mio_pad_attr_14_drive_strength_14_wd = reg_wdata[23:20]; - assign mio_pad_attr_15_re = addr_hit[233] & reg_re & !reg_error; - assign mio_pad_attr_15_we = addr_hit[233] & reg_we & !reg_error; + assign mio_pad_attr_15_re = addr_hit[227] & reg_re & !reg_error; + assign mio_pad_attr_15_we = addr_hit[227] & reg_we & !reg_error; assign mio_pad_attr_15_invert_15_wd = reg_wdata[0]; @@ -32604,8 +32373,8 @@ module pinmux_reg_top ( assign mio_pad_attr_15_slew_rate_15_wd = reg_wdata[17:16]; assign mio_pad_attr_15_drive_strength_15_wd = reg_wdata[23:20]; - assign mio_pad_attr_16_re = addr_hit[234] & reg_re & !reg_error; - assign mio_pad_attr_16_we = addr_hit[234] & reg_we & !reg_error; + assign mio_pad_attr_16_re = addr_hit[228] & reg_re & !reg_error; + assign mio_pad_attr_16_we = addr_hit[228] & reg_we & !reg_error; assign mio_pad_attr_16_invert_16_wd = reg_wdata[0]; @@ -32626,8 +32395,8 @@ module pinmux_reg_top ( assign mio_pad_attr_16_slew_rate_16_wd = reg_wdata[17:16]; assign mio_pad_attr_16_drive_strength_16_wd = reg_wdata[23:20]; - assign mio_pad_attr_17_re = addr_hit[235] & reg_re & !reg_error; - assign mio_pad_attr_17_we = addr_hit[235] & reg_we & !reg_error; + assign mio_pad_attr_17_re = addr_hit[229] & reg_re & !reg_error; + assign mio_pad_attr_17_we = addr_hit[229] & reg_we & !reg_error; assign mio_pad_attr_17_invert_17_wd = reg_wdata[0]; @@ -32648,8 +32417,8 @@ module pinmux_reg_top ( assign mio_pad_attr_17_slew_rate_17_wd = reg_wdata[17:16]; assign mio_pad_attr_17_drive_strength_17_wd = reg_wdata[23:20]; - assign mio_pad_attr_18_re = addr_hit[236] & reg_re & !reg_error; - assign mio_pad_attr_18_we = addr_hit[236] & reg_we & !reg_error; + assign mio_pad_attr_18_re = addr_hit[230] & reg_re & !reg_error; + assign mio_pad_attr_18_we = addr_hit[230] & reg_we & !reg_error; assign mio_pad_attr_18_invert_18_wd = reg_wdata[0]; @@ -32670,8 +32439,8 @@ module pinmux_reg_top ( assign mio_pad_attr_18_slew_rate_18_wd = reg_wdata[17:16]; assign mio_pad_attr_18_drive_strength_18_wd = reg_wdata[23:20]; - assign mio_pad_attr_19_re = addr_hit[237] & reg_re & !reg_error; - assign mio_pad_attr_19_we = addr_hit[237] & reg_we & !reg_error; + assign mio_pad_attr_19_re = addr_hit[231] & reg_re & !reg_error; + assign mio_pad_attr_19_we = addr_hit[231] & reg_we & !reg_error; assign mio_pad_attr_19_invert_19_wd = reg_wdata[0]; @@ -32692,8 +32461,8 @@ module pinmux_reg_top ( assign mio_pad_attr_19_slew_rate_19_wd = reg_wdata[17:16]; assign mio_pad_attr_19_drive_strength_19_wd = reg_wdata[23:20]; - assign mio_pad_attr_20_re = addr_hit[238] & reg_re & !reg_error; - assign mio_pad_attr_20_we = addr_hit[238] & reg_we & !reg_error; + assign mio_pad_attr_20_re = addr_hit[232] & reg_re & !reg_error; + assign mio_pad_attr_20_we = addr_hit[232] & reg_we & !reg_error; assign mio_pad_attr_20_invert_20_wd = reg_wdata[0]; @@ -32714,8 +32483,8 @@ module pinmux_reg_top ( assign mio_pad_attr_20_slew_rate_20_wd = reg_wdata[17:16]; assign mio_pad_attr_20_drive_strength_20_wd = reg_wdata[23:20]; - assign mio_pad_attr_21_re = addr_hit[239] & reg_re & !reg_error; - assign mio_pad_attr_21_we = addr_hit[239] & reg_we & !reg_error; + assign mio_pad_attr_21_re = addr_hit[233] & reg_re & !reg_error; + assign mio_pad_attr_21_we = addr_hit[233] & reg_we & !reg_error; assign mio_pad_attr_21_invert_21_wd = reg_wdata[0]; @@ -32736,8 +32505,8 @@ module pinmux_reg_top ( assign mio_pad_attr_21_slew_rate_21_wd = reg_wdata[17:16]; assign mio_pad_attr_21_drive_strength_21_wd = reg_wdata[23:20]; - assign mio_pad_attr_22_re = addr_hit[240] & reg_re & !reg_error; - assign mio_pad_attr_22_we = addr_hit[240] & reg_we & !reg_error; + assign mio_pad_attr_22_re = addr_hit[234] & reg_re & !reg_error; + assign mio_pad_attr_22_we = addr_hit[234] & reg_we & !reg_error; assign mio_pad_attr_22_invert_22_wd = reg_wdata[0]; @@ -32758,8 +32527,8 @@ module pinmux_reg_top ( assign mio_pad_attr_22_slew_rate_22_wd = reg_wdata[17:16]; assign mio_pad_attr_22_drive_strength_22_wd = reg_wdata[23:20]; - assign mio_pad_attr_23_re = addr_hit[241] & reg_re & !reg_error; - assign mio_pad_attr_23_we = addr_hit[241] & reg_we & !reg_error; + assign mio_pad_attr_23_re = addr_hit[235] & reg_re & !reg_error; + assign mio_pad_attr_23_we = addr_hit[235] & reg_we & !reg_error; assign mio_pad_attr_23_invert_23_wd = reg_wdata[0]; @@ -32780,8 +32549,8 @@ module pinmux_reg_top ( assign mio_pad_attr_23_slew_rate_23_wd = reg_wdata[17:16]; assign mio_pad_attr_23_drive_strength_23_wd = reg_wdata[23:20]; - assign mio_pad_attr_24_re = addr_hit[242] & reg_re & !reg_error; - assign mio_pad_attr_24_we = addr_hit[242] & reg_we & !reg_error; + assign mio_pad_attr_24_re = addr_hit[236] & reg_re & !reg_error; + assign mio_pad_attr_24_we = addr_hit[236] & reg_we & !reg_error; assign mio_pad_attr_24_invert_24_wd = reg_wdata[0]; @@ -32802,8 +32571,8 @@ module pinmux_reg_top ( assign mio_pad_attr_24_slew_rate_24_wd = reg_wdata[17:16]; assign mio_pad_attr_24_drive_strength_24_wd = reg_wdata[23:20]; - assign mio_pad_attr_25_re = addr_hit[243] & reg_re & !reg_error; - assign mio_pad_attr_25_we = addr_hit[243] & reg_we & !reg_error; + assign mio_pad_attr_25_re = addr_hit[237] & reg_re & !reg_error; + assign mio_pad_attr_25_we = addr_hit[237] & reg_we & !reg_error; assign mio_pad_attr_25_invert_25_wd = reg_wdata[0]; @@ -32824,8 +32593,8 @@ module pinmux_reg_top ( assign mio_pad_attr_25_slew_rate_25_wd = reg_wdata[17:16]; assign mio_pad_attr_25_drive_strength_25_wd = reg_wdata[23:20]; - assign mio_pad_attr_26_re = addr_hit[244] & reg_re & !reg_error; - assign mio_pad_attr_26_we = addr_hit[244] & reg_we & !reg_error; + assign mio_pad_attr_26_re = addr_hit[238] & reg_re & !reg_error; + assign mio_pad_attr_26_we = addr_hit[238] & reg_we & !reg_error; assign mio_pad_attr_26_invert_26_wd = reg_wdata[0]; @@ -32846,8 +32615,8 @@ module pinmux_reg_top ( assign mio_pad_attr_26_slew_rate_26_wd = reg_wdata[17:16]; assign mio_pad_attr_26_drive_strength_26_wd = reg_wdata[23:20]; - assign mio_pad_attr_27_re = addr_hit[245] & reg_re & !reg_error; - assign mio_pad_attr_27_we = addr_hit[245] & reg_we & !reg_error; + assign mio_pad_attr_27_re = addr_hit[239] & reg_re & !reg_error; + assign mio_pad_attr_27_we = addr_hit[239] & reg_we & !reg_error; assign mio_pad_attr_27_invert_27_wd = reg_wdata[0]; @@ -32868,8 +32637,8 @@ module pinmux_reg_top ( assign mio_pad_attr_27_slew_rate_27_wd = reg_wdata[17:16]; assign mio_pad_attr_27_drive_strength_27_wd = reg_wdata[23:20]; - assign mio_pad_attr_28_re = addr_hit[246] & reg_re & !reg_error; - assign mio_pad_attr_28_we = addr_hit[246] & reg_we & !reg_error; + assign mio_pad_attr_28_re = addr_hit[240] & reg_re & !reg_error; + assign mio_pad_attr_28_we = addr_hit[240] & reg_we & !reg_error; assign mio_pad_attr_28_invert_28_wd = reg_wdata[0]; @@ -32890,8 +32659,8 @@ module pinmux_reg_top ( assign mio_pad_attr_28_slew_rate_28_wd = reg_wdata[17:16]; assign mio_pad_attr_28_drive_strength_28_wd = reg_wdata[23:20]; - assign mio_pad_attr_29_re = addr_hit[247] & reg_re & !reg_error; - assign mio_pad_attr_29_we = addr_hit[247] & reg_we & !reg_error; + assign mio_pad_attr_29_re = addr_hit[241] & reg_re & !reg_error; + assign mio_pad_attr_29_we = addr_hit[241] & reg_we & !reg_error; assign mio_pad_attr_29_invert_29_wd = reg_wdata[0]; @@ -32912,8 +32681,8 @@ module pinmux_reg_top ( assign mio_pad_attr_29_slew_rate_29_wd = reg_wdata[17:16]; assign mio_pad_attr_29_drive_strength_29_wd = reg_wdata[23:20]; - assign mio_pad_attr_30_re = addr_hit[248] & reg_re & !reg_error; - assign mio_pad_attr_30_we = addr_hit[248] & reg_we & !reg_error; + assign mio_pad_attr_30_re = addr_hit[242] & reg_re & !reg_error; + assign mio_pad_attr_30_we = addr_hit[242] & reg_we & !reg_error; assign mio_pad_attr_30_invert_30_wd = reg_wdata[0]; @@ -32934,8 +32703,8 @@ module pinmux_reg_top ( assign mio_pad_attr_30_slew_rate_30_wd = reg_wdata[17:16]; assign mio_pad_attr_30_drive_strength_30_wd = reg_wdata[23:20]; - assign mio_pad_attr_31_re = addr_hit[249] & reg_re & !reg_error; - assign mio_pad_attr_31_we = addr_hit[249] & reg_we & !reg_error; + assign mio_pad_attr_31_re = addr_hit[243] & reg_re & !reg_error; + assign mio_pad_attr_31_we = addr_hit[243] & reg_we & !reg_error; assign mio_pad_attr_31_invert_31_wd = reg_wdata[0]; @@ -32956,8 +32725,8 @@ module pinmux_reg_top ( assign mio_pad_attr_31_slew_rate_31_wd = reg_wdata[17:16]; assign mio_pad_attr_31_drive_strength_31_wd = reg_wdata[23:20]; - assign mio_pad_attr_32_re = addr_hit[250] & reg_re & !reg_error; - assign mio_pad_attr_32_we = addr_hit[250] & reg_we & !reg_error; + assign mio_pad_attr_32_re = addr_hit[244] & reg_re & !reg_error; + assign mio_pad_attr_32_we = addr_hit[244] & reg_we & !reg_error; assign mio_pad_attr_32_invert_32_wd = reg_wdata[0]; @@ -32978,8 +32747,8 @@ module pinmux_reg_top ( assign mio_pad_attr_32_slew_rate_32_wd = reg_wdata[17:16]; assign mio_pad_attr_32_drive_strength_32_wd = reg_wdata[23:20]; - assign mio_pad_attr_33_re = addr_hit[251] & reg_re & !reg_error; - assign mio_pad_attr_33_we = addr_hit[251] & reg_we & !reg_error; + assign mio_pad_attr_33_re = addr_hit[245] & reg_re & !reg_error; + assign mio_pad_attr_33_we = addr_hit[245] & reg_we & !reg_error; assign mio_pad_attr_33_invert_33_wd = reg_wdata[0]; @@ -33000,8 +32769,8 @@ module pinmux_reg_top ( assign mio_pad_attr_33_slew_rate_33_wd = reg_wdata[17:16]; assign mio_pad_attr_33_drive_strength_33_wd = reg_wdata[23:20]; - assign mio_pad_attr_34_re = addr_hit[252] & reg_re & !reg_error; - assign mio_pad_attr_34_we = addr_hit[252] & reg_we & !reg_error; + assign mio_pad_attr_34_re = addr_hit[246] & reg_re & !reg_error; + assign mio_pad_attr_34_we = addr_hit[246] & reg_we & !reg_error; assign mio_pad_attr_34_invert_34_wd = reg_wdata[0]; @@ -33022,8 +32791,8 @@ module pinmux_reg_top ( assign mio_pad_attr_34_slew_rate_34_wd = reg_wdata[17:16]; assign mio_pad_attr_34_drive_strength_34_wd = reg_wdata[23:20]; - assign mio_pad_attr_35_re = addr_hit[253] & reg_re & !reg_error; - assign mio_pad_attr_35_we = addr_hit[253] & reg_we & !reg_error; + assign mio_pad_attr_35_re = addr_hit[247] & reg_re & !reg_error; + assign mio_pad_attr_35_we = addr_hit[247] & reg_we & !reg_error; assign mio_pad_attr_35_invert_35_wd = reg_wdata[0]; @@ -33044,8 +32813,8 @@ module pinmux_reg_top ( assign mio_pad_attr_35_slew_rate_35_wd = reg_wdata[17:16]; assign mio_pad_attr_35_drive_strength_35_wd = reg_wdata[23:20]; - assign mio_pad_attr_36_re = addr_hit[254] & reg_re & !reg_error; - assign mio_pad_attr_36_we = addr_hit[254] & reg_we & !reg_error; + assign mio_pad_attr_36_re = addr_hit[248] & reg_re & !reg_error; + assign mio_pad_attr_36_we = addr_hit[248] & reg_we & !reg_error; assign mio_pad_attr_36_invert_36_wd = reg_wdata[0]; @@ -33066,8 +32835,8 @@ module pinmux_reg_top ( assign mio_pad_attr_36_slew_rate_36_wd = reg_wdata[17:16]; assign mio_pad_attr_36_drive_strength_36_wd = reg_wdata[23:20]; - assign mio_pad_attr_37_re = addr_hit[255] & reg_re & !reg_error; - assign mio_pad_attr_37_we = addr_hit[255] & reg_we & !reg_error; + assign mio_pad_attr_37_re = addr_hit[249] & reg_re & !reg_error; + assign mio_pad_attr_37_we = addr_hit[249] & reg_we & !reg_error; assign mio_pad_attr_37_invert_37_wd = reg_wdata[0]; @@ -33088,8 +32857,8 @@ module pinmux_reg_top ( assign mio_pad_attr_37_slew_rate_37_wd = reg_wdata[17:16]; assign mio_pad_attr_37_drive_strength_37_wd = reg_wdata[23:20]; - assign mio_pad_attr_38_re = addr_hit[256] & reg_re & !reg_error; - assign mio_pad_attr_38_we = addr_hit[256] & reg_we & !reg_error; + assign mio_pad_attr_38_re = addr_hit[250] & reg_re & !reg_error; + assign mio_pad_attr_38_we = addr_hit[250] & reg_we & !reg_error; assign mio_pad_attr_38_invert_38_wd = reg_wdata[0]; @@ -33110,8 +32879,8 @@ module pinmux_reg_top ( assign mio_pad_attr_38_slew_rate_38_wd = reg_wdata[17:16]; assign mio_pad_attr_38_drive_strength_38_wd = reg_wdata[23:20]; - assign mio_pad_attr_39_re = addr_hit[257] & reg_re & !reg_error; - assign mio_pad_attr_39_we = addr_hit[257] & reg_we & !reg_error; + assign mio_pad_attr_39_re = addr_hit[251] & reg_re & !reg_error; + assign mio_pad_attr_39_we = addr_hit[251] & reg_we & !reg_error; assign mio_pad_attr_39_invert_39_wd = reg_wdata[0]; @@ -33132,8 +32901,8 @@ module pinmux_reg_top ( assign mio_pad_attr_39_slew_rate_39_wd = reg_wdata[17:16]; assign mio_pad_attr_39_drive_strength_39_wd = reg_wdata[23:20]; - assign mio_pad_attr_40_re = addr_hit[258] & reg_re & !reg_error; - assign mio_pad_attr_40_we = addr_hit[258] & reg_we & !reg_error; + assign mio_pad_attr_40_re = addr_hit[252] & reg_re & !reg_error; + assign mio_pad_attr_40_we = addr_hit[252] & reg_we & !reg_error; assign mio_pad_attr_40_invert_40_wd = reg_wdata[0]; @@ -33154,8 +32923,8 @@ module pinmux_reg_top ( assign mio_pad_attr_40_slew_rate_40_wd = reg_wdata[17:16]; assign mio_pad_attr_40_drive_strength_40_wd = reg_wdata[23:20]; - assign mio_pad_attr_41_re = addr_hit[259] & reg_re & !reg_error; - assign mio_pad_attr_41_we = addr_hit[259] & reg_we & !reg_error; + assign mio_pad_attr_41_re = addr_hit[253] & reg_re & !reg_error; + assign mio_pad_attr_41_we = addr_hit[253] & reg_we & !reg_error; assign mio_pad_attr_41_invert_41_wd = reg_wdata[0]; @@ -33176,8 +32945,8 @@ module pinmux_reg_top ( assign mio_pad_attr_41_slew_rate_41_wd = reg_wdata[17:16]; assign mio_pad_attr_41_drive_strength_41_wd = reg_wdata[23:20]; - assign mio_pad_attr_42_re = addr_hit[260] & reg_re & !reg_error; - assign mio_pad_attr_42_we = addr_hit[260] & reg_we & !reg_error; + assign mio_pad_attr_42_re = addr_hit[254] & reg_re & !reg_error; + assign mio_pad_attr_42_we = addr_hit[254] & reg_we & !reg_error; assign mio_pad_attr_42_invert_42_wd = reg_wdata[0]; @@ -33198,8 +32967,8 @@ module pinmux_reg_top ( assign mio_pad_attr_42_slew_rate_42_wd = reg_wdata[17:16]; assign mio_pad_attr_42_drive_strength_42_wd = reg_wdata[23:20]; - assign mio_pad_attr_43_re = addr_hit[261] & reg_re & !reg_error; - assign mio_pad_attr_43_we = addr_hit[261] & reg_we & !reg_error; + assign mio_pad_attr_43_re = addr_hit[255] & reg_re & !reg_error; + assign mio_pad_attr_43_we = addr_hit[255] & reg_we & !reg_error; assign mio_pad_attr_43_invert_43_wd = reg_wdata[0]; @@ -33220,8 +32989,8 @@ module pinmux_reg_top ( assign mio_pad_attr_43_slew_rate_43_wd = reg_wdata[17:16]; assign mio_pad_attr_43_drive_strength_43_wd = reg_wdata[23:20]; - assign mio_pad_attr_44_re = addr_hit[262] & reg_re & !reg_error; - assign mio_pad_attr_44_we = addr_hit[262] & reg_we & !reg_error; + assign mio_pad_attr_44_re = addr_hit[256] & reg_re & !reg_error; + assign mio_pad_attr_44_we = addr_hit[256] & reg_we & !reg_error; assign mio_pad_attr_44_invert_44_wd = reg_wdata[0]; @@ -33242,8 +33011,8 @@ module pinmux_reg_top ( assign mio_pad_attr_44_slew_rate_44_wd = reg_wdata[17:16]; assign mio_pad_attr_44_drive_strength_44_wd = reg_wdata[23:20]; - assign mio_pad_attr_45_re = addr_hit[263] & reg_re & !reg_error; - assign mio_pad_attr_45_we = addr_hit[263] & reg_we & !reg_error; + assign mio_pad_attr_45_re = addr_hit[257] & reg_re & !reg_error; + assign mio_pad_attr_45_we = addr_hit[257] & reg_we & !reg_error; assign mio_pad_attr_45_invert_45_wd = reg_wdata[0]; @@ -33264,8 +33033,8 @@ module pinmux_reg_top ( assign mio_pad_attr_45_slew_rate_45_wd = reg_wdata[17:16]; assign mio_pad_attr_45_drive_strength_45_wd = reg_wdata[23:20]; - assign mio_pad_attr_46_re = addr_hit[264] & reg_re & !reg_error; - assign mio_pad_attr_46_we = addr_hit[264] & reg_we & !reg_error; + assign mio_pad_attr_46_re = addr_hit[258] & reg_re & !reg_error; + assign mio_pad_attr_46_we = addr_hit[258] & reg_we & !reg_error; assign mio_pad_attr_46_invert_46_wd = reg_wdata[0]; @@ -33286,50 +33055,50 @@ module pinmux_reg_top ( assign mio_pad_attr_46_slew_rate_46_wd = reg_wdata[17:16]; assign mio_pad_attr_46_drive_strength_46_wd = reg_wdata[23:20]; - assign dio_pad_attr_regwen_0_we = addr_hit[265] & reg_we & !reg_error; + assign dio_pad_attr_regwen_0_we = addr_hit[259] & reg_we & !reg_error; assign dio_pad_attr_regwen_0_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_1_we = addr_hit[266] & reg_we & !reg_error; + assign dio_pad_attr_regwen_1_we = addr_hit[260] & reg_we & !reg_error; assign dio_pad_attr_regwen_1_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_2_we = addr_hit[267] & reg_we & !reg_error; + assign dio_pad_attr_regwen_2_we = addr_hit[261] & reg_we & !reg_error; assign dio_pad_attr_regwen_2_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_3_we = addr_hit[268] & reg_we & !reg_error; + assign dio_pad_attr_regwen_3_we = addr_hit[262] & reg_we & !reg_error; assign dio_pad_attr_regwen_3_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_4_we = addr_hit[269] & reg_we & !reg_error; + assign dio_pad_attr_regwen_4_we = addr_hit[263] & reg_we & !reg_error; assign dio_pad_attr_regwen_4_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_5_we = addr_hit[270] & reg_we & !reg_error; + assign dio_pad_attr_regwen_5_we = addr_hit[264] & reg_we & !reg_error; assign dio_pad_attr_regwen_5_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_6_we = addr_hit[271] & reg_we & !reg_error; + assign dio_pad_attr_regwen_6_we = addr_hit[265] & reg_we & !reg_error; assign dio_pad_attr_regwen_6_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_7_we = addr_hit[272] & reg_we & !reg_error; + assign dio_pad_attr_regwen_7_we = addr_hit[266] & reg_we & !reg_error; assign dio_pad_attr_regwen_7_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_8_we = addr_hit[273] & reg_we & !reg_error; + assign dio_pad_attr_regwen_8_we = addr_hit[267] & reg_we & !reg_error; assign dio_pad_attr_regwen_8_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_9_we = addr_hit[274] & reg_we & !reg_error; + assign dio_pad_attr_regwen_9_we = addr_hit[268] & reg_we & !reg_error; assign dio_pad_attr_regwen_9_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_10_we = addr_hit[275] & reg_we & !reg_error; + assign dio_pad_attr_regwen_10_we = addr_hit[269] & reg_we & !reg_error; assign dio_pad_attr_regwen_10_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_11_we = addr_hit[276] & reg_we & !reg_error; + assign dio_pad_attr_regwen_11_we = addr_hit[270] & reg_we & !reg_error; assign dio_pad_attr_regwen_11_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_12_we = addr_hit[277] & reg_we & !reg_error; + assign dio_pad_attr_regwen_12_we = addr_hit[271] & reg_we & !reg_error; assign dio_pad_attr_regwen_12_wd = reg_wdata[0]; - assign dio_pad_attr_regwen_13_we = addr_hit[278] & reg_we & !reg_error; + assign dio_pad_attr_regwen_13_we = addr_hit[272] & reg_we & !reg_error; assign dio_pad_attr_regwen_13_wd = reg_wdata[0]; - assign dio_pad_attr_0_re = addr_hit[279] & reg_re & !reg_error; - assign dio_pad_attr_0_we = addr_hit[279] & reg_we & !reg_error; + assign dio_pad_attr_0_re = addr_hit[273] & reg_re & !reg_error; + assign dio_pad_attr_0_we = addr_hit[273] & reg_we & !reg_error; assign dio_pad_attr_0_invert_0_wd = reg_wdata[0]; @@ -33350,8 +33119,8 @@ module pinmux_reg_top ( assign dio_pad_attr_0_slew_rate_0_wd = reg_wdata[17:16]; assign dio_pad_attr_0_drive_strength_0_wd = reg_wdata[23:20]; - assign dio_pad_attr_1_re = addr_hit[280] & reg_re & !reg_error; - assign dio_pad_attr_1_we = addr_hit[280] & reg_we & !reg_error; + assign dio_pad_attr_1_re = addr_hit[274] & reg_re & !reg_error; + assign dio_pad_attr_1_we = addr_hit[274] & reg_we & !reg_error; assign dio_pad_attr_1_invert_1_wd = reg_wdata[0]; @@ -33372,8 +33141,8 @@ module pinmux_reg_top ( assign dio_pad_attr_1_slew_rate_1_wd = reg_wdata[17:16]; assign dio_pad_attr_1_drive_strength_1_wd = reg_wdata[23:20]; - assign dio_pad_attr_2_re = addr_hit[281] & reg_re & !reg_error; - assign dio_pad_attr_2_we = addr_hit[281] & reg_we & !reg_error; + assign dio_pad_attr_2_re = addr_hit[275] & reg_re & !reg_error; + assign dio_pad_attr_2_we = addr_hit[275] & reg_we & !reg_error; assign dio_pad_attr_2_invert_2_wd = reg_wdata[0]; @@ -33394,8 +33163,8 @@ module pinmux_reg_top ( assign dio_pad_attr_2_slew_rate_2_wd = reg_wdata[17:16]; assign dio_pad_attr_2_drive_strength_2_wd = reg_wdata[23:20]; - assign dio_pad_attr_3_re = addr_hit[282] & reg_re & !reg_error; - assign dio_pad_attr_3_we = addr_hit[282] & reg_we & !reg_error; + assign dio_pad_attr_3_re = addr_hit[276] & reg_re & !reg_error; + assign dio_pad_attr_3_we = addr_hit[276] & reg_we & !reg_error; assign dio_pad_attr_3_invert_3_wd = reg_wdata[0]; @@ -33416,8 +33185,8 @@ module pinmux_reg_top ( assign dio_pad_attr_3_slew_rate_3_wd = reg_wdata[17:16]; assign dio_pad_attr_3_drive_strength_3_wd = reg_wdata[23:20]; - assign dio_pad_attr_4_re = addr_hit[283] & reg_re & !reg_error; - assign dio_pad_attr_4_we = addr_hit[283] & reg_we & !reg_error; + assign dio_pad_attr_4_re = addr_hit[277] & reg_re & !reg_error; + assign dio_pad_attr_4_we = addr_hit[277] & reg_we & !reg_error; assign dio_pad_attr_4_invert_4_wd = reg_wdata[0]; @@ -33438,8 +33207,8 @@ module pinmux_reg_top ( assign dio_pad_attr_4_slew_rate_4_wd = reg_wdata[17:16]; assign dio_pad_attr_4_drive_strength_4_wd = reg_wdata[23:20]; - assign dio_pad_attr_5_re = addr_hit[284] & reg_re & !reg_error; - assign dio_pad_attr_5_we = addr_hit[284] & reg_we & !reg_error; + assign dio_pad_attr_5_re = addr_hit[278] & reg_re & !reg_error; + assign dio_pad_attr_5_we = addr_hit[278] & reg_we & !reg_error; assign dio_pad_attr_5_invert_5_wd = reg_wdata[0]; @@ -33460,8 +33229,8 @@ module pinmux_reg_top ( assign dio_pad_attr_5_slew_rate_5_wd = reg_wdata[17:16]; assign dio_pad_attr_5_drive_strength_5_wd = reg_wdata[23:20]; - assign dio_pad_attr_6_re = addr_hit[285] & reg_re & !reg_error; - assign dio_pad_attr_6_we = addr_hit[285] & reg_we & !reg_error; + assign dio_pad_attr_6_re = addr_hit[279] & reg_re & !reg_error; + assign dio_pad_attr_6_we = addr_hit[279] & reg_we & !reg_error; assign dio_pad_attr_6_invert_6_wd = reg_wdata[0]; @@ -33482,8 +33251,8 @@ module pinmux_reg_top ( assign dio_pad_attr_6_slew_rate_6_wd = reg_wdata[17:16]; assign dio_pad_attr_6_drive_strength_6_wd = reg_wdata[23:20]; - assign dio_pad_attr_7_re = addr_hit[286] & reg_re & !reg_error; - assign dio_pad_attr_7_we = addr_hit[286] & reg_we & !reg_error; + assign dio_pad_attr_7_re = addr_hit[280] & reg_re & !reg_error; + assign dio_pad_attr_7_we = addr_hit[280] & reg_we & !reg_error; assign dio_pad_attr_7_invert_7_wd = reg_wdata[0]; @@ -33504,8 +33273,8 @@ module pinmux_reg_top ( assign dio_pad_attr_7_slew_rate_7_wd = reg_wdata[17:16]; assign dio_pad_attr_7_drive_strength_7_wd = reg_wdata[23:20]; - assign dio_pad_attr_8_re = addr_hit[287] & reg_re & !reg_error; - assign dio_pad_attr_8_we = addr_hit[287] & reg_we & !reg_error; + assign dio_pad_attr_8_re = addr_hit[281] & reg_re & !reg_error; + assign dio_pad_attr_8_we = addr_hit[281] & reg_we & !reg_error; assign dio_pad_attr_8_invert_8_wd = reg_wdata[0]; @@ -33526,8 +33295,8 @@ module pinmux_reg_top ( assign dio_pad_attr_8_slew_rate_8_wd = reg_wdata[17:16]; assign dio_pad_attr_8_drive_strength_8_wd = reg_wdata[23:20]; - assign dio_pad_attr_9_re = addr_hit[288] & reg_re & !reg_error; - assign dio_pad_attr_9_we = addr_hit[288] & reg_we & !reg_error; + assign dio_pad_attr_9_re = addr_hit[282] & reg_re & !reg_error; + assign dio_pad_attr_9_we = addr_hit[282] & reg_we & !reg_error; assign dio_pad_attr_9_invert_9_wd = reg_wdata[0]; @@ -33548,8 +33317,8 @@ module pinmux_reg_top ( assign dio_pad_attr_9_slew_rate_9_wd = reg_wdata[17:16]; assign dio_pad_attr_9_drive_strength_9_wd = reg_wdata[23:20]; - assign dio_pad_attr_10_re = addr_hit[289] & reg_re & !reg_error; - assign dio_pad_attr_10_we = addr_hit[289] & reg_we & !reg_error; + assign dio_pad_attr_10_re = addr_hit[283] & reg_re & !reg_error; + assign dio_pad_attr_10_we = addr_hit[283] & reg_we & !reg_error; assign dio_pad_attr_10_invert_10_wd = reg_wdata[0]; @@ -33570,8 +33339,8 @@ module pinmux_reg_top ( assign dio_pad_attr_10_slew_rate_10_wd = reg_wdata[17:16]; assign dio_pad_attr_10_drive_strength_10_wd = reg_wdata[23:20]; - assign dio_pad_attr_11_re = addr_hit[290] & reg_re & !reg_error; - assign dio_pad_attr_11_we = addr_hit[290] & reg_we & !reg_error; + assign dio_pad_attr_11_re = addr_hit[284] & reg_re & !reg_error; + assign dio_pad_attr_11_we = addr_hit[284] & reg_we & !reg_error; assign dio_pad_attr_11_invert_11_wd = reg_wdata[0]; @@ -33592,8 +33361,8 @@ module pinmux_reg_top ( assign dio_pad_attr_11_slew_rate_11_wd = reg_wdata[17:16]; assign dio_pad_attr_11_drive_strength_11_wd = reg_wdata[23:20]; - assign dio_pad_attr_12_re = addr_hit[291] & reg_re & !reg_error; - assign dio_pad_attr_12_we = addr_hit[291] & reg_we & !reg_error; + assign dio_pad_attr_12_re = addr_hit[285] & reg_re & !reg_error; + assign dio_pad_attr_12_we = addr_hit[285] & reg_we & !reg_error; assign dio_pad_attr_12_invert_12_wd = reg_wdata[0]; @@ -33614,8 +33383,8 @@ module pinmux_reg_top ( assign dio_pad_attr_12_slew_rate_12_wd = reg_wdata[17:16]; assign dio_pad_attr_12_drive_strength_12_wd = reg_wdata[23:20]; - assign dio_pad_attr_13_re = addr_hit[292] & reg_re & !reg_error; - assign dio_pad_attr_13_we = addr_hit[292] & reg_we & !reg_error; + assign dio_pad_attr_13_re = addr_hit[286] & reg_re & !reg_error; + assign dio_pad_attr_13_we = addr_hit[286] & reg_we & !reg_error; assign dio_pad_attr_13_invert_13_wd = reg_wdata[0]; @@ -33636,7 +33405,7 @@ module pinmux_reg_top ( assign dio_pad_attr_13_slew_rate_13_wd = reg_wdata[17:16]; assign dio_pad_attr_13_drive_strength_13_wd = reg_wdata[23:20]; - assign mio_pad_sleep_status_0_we = addr_hit[293] & reg_we & !reg_error; + assign mio_pad_sleep_status_0_we = addr_hit[287] & reg_we & !reg_error; assign mio_pad_sleep_status_0_en_0_wd = reg_wdata[0]; @@ -33701,7 +33470,7 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_0_en_30_wd = reg_wdata[30]; assign mio_pad_sleep_status_0_en_31_wd = reg_wdata[31]; - assign mio_pad_sleep_status_1_we = addr_hit[294] & reg_we & !reg_error; + assign mio_pad_sleep_status_1_we = addr_hit[288] & reg_we & !reg_error; assign mio_pad_sleep_status_1_en_32_wd = reg_wdata[0]; @@ -33732,430 +33501,430 @@ module pinmux_reg_top ( assign mio_pad_sleep_status_1_en_45_wd = reg_wdata[13]; assign mio_pad_sleep_status_1_en_46_wd = reg_wdata[14]; - assign mio_pad_sleep_regwen_0_we = addr_hit[295] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_0_we = addr_hit[289] & reg_we & !reg_error; assign mio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_1_we = addr_hit[296] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_1_we = addr_hit[290] & reg_we & !reg_error; assign mio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_2_we = addr_hit[297] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_2_we = addr_hit[291] & reg_we & !reg_error; assign mio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_3_we = addr_hit[298] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_3_we = addr_hit[292] & reg_we & !reg_error; assign mio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_4_we = addr_hit[299] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_4_we = addr_hit[293] & reg_we & !reg_error; assign mio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_5_we = addr_hit[300] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_5_we = addr_hit[294] & reg_we & !reg_error; assign mio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_6_we = addr_hit[301] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_6_we = addr_hit[295] & reg_we & !reg_error; assign mio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_7_we = addr_hit[302] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_7_we = addr_hit[296] & reg_we & !reg_error; assign mio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_8_we = addr_hit[303] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_8_we = addr_hit[297] & reg_we & !reg_error; assign mio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_9_we = addr_hit[304] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_9_we = addr_hit[298] & reg_we & !reg_error; assign mio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_10_we = addr_hit[305] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_10_we = addr_hit[299] & reg_we & !reg_error; assign mio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_11_we = addr_hit[306] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_11_we = addr_hit[300] & reg_we & !reg_error; assign mio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_12_we = addr_hit[307] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_12_we = addr_hit[301] & reg_we & !reg_error; assign mio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_13_we = addr_hit[308] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_13_we = addr_hit[302] & reg_we & !reg_error; assign mio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_14_we = addr_hit[309] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_14_we = addr_hit[303] & reg_we & !reg_error; assign mio_pad_sleep_regwen_14_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_15_we = addr_hit[310] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_15_we = addr_hit[304] & reg_we & !reg_error; assign mio_pad_sleep_regwen_15_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_16_we = addr_hit[311] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_16_we = addr_hit[305] & reg_we & !reg_error; assign mio_pad_sleep_regwen_16_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_17_we = addr_hit[312] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_17_we = addr_hit[306] & reg_we & !reg_error; assign mio_pad_sleep_regwen_17_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_18_we = addr_hit[313] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_18_we = addr_hit[307] & reg_we & !reg_error; assign mio_pad_sleep_regwen_18_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_19_we = addr_hit[314] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_19_we = addr_hit[308] & reg_we & !reg_error; assign mio_pad_sleep_regwen_19_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_20_we = addr_hit[315] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_20_we = addr_hit[309] & reg_we & !reg_error; assign mio_pad_sleep_regwen_20_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_21_we = addr_hit[316] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_21_we = addr_hit[310] & reg_we & !reg_error; assign mio_pad_sleep_regwen_21_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_22_we = addr_hit[317] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_22_we = addr_hit[311] & reg_we & !reg_error; assign mio_pad_sleep_regwen_22_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_23_we = addr_hit[318] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_23_we = addr_hit[312] & reg_we & !reg_error; assign mio_pad_sleep_regwen_23_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_24_we = addr_hit[319] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_24_we = addr_hit[313] & reg_we & !reg_error; assign mio_pad_sleep_regwen_24_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_25_we = addr_hit[320] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_25_we = addr_hit[314] & reg_we & !reg_error; assign mio_pad_sleep_regwen_25_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_26_we = addr_hit[321] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_26_we = addr_hit[315] & reg_we & !reg_error; assign mio_pad_sleep_regwen_26_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_27_we = addr_hit[322] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_27_we = addr_hit[316] & reg_we & !reg_error; assign mio_pad_sleep_regwen_27_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_28_we = addr_hit[323] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_28_we = addr_hit[317] & reg_we & !reg_error; assign mio_pad_sleep_regwen_28_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_29_we = addr_hit[324] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_29_we = addr_hit[318] & reg_we & !reg_error; assign mio_pad_sleep_regwen_29_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_30_we = addr_hit[325] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_30_we = addr_hit[319] & reg_we & !reg_error; assign mio_pad_sleep_regwen_30_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_31_we = addr_hit[326] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_31_we = addr_hit[320] & reg_we & !reg_error; assign mio_pad_sleep_regwen_31_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_32_we = addr_hit[327] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_32_we = addr_hit[321] & reg_we & !reg_error; assign mio_pad_sleep_regwen_32_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_33_we = addr_hit[328] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_33_we = addr_hit[322] & reg_we & !reg_error; assign mio_pad_sleep_regwen_33_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_34_we = addr_hit[329] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_34_we = addr_hit[323] & reg_we & !reg_error; assign mio_pad_sleep_regwen_34_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_35_we = addr_hit[330] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_35_we = addr_hit[324] & reg_we & !reg_error; assign mio_pad_sleep_regwen_35_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_36_we = addr_hit[331] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_36_we = addr_hit[325] & reg_we & !reg_error; assign mio_pad_sleep_regwen_36_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_37_we = addr_hit[332] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_37_we = addr_hit[326] & reg_we & !reg_error; assign mio_pad_sleep_regwen_37_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_38_we = addr_hit[333] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_38_we = addr_hit[327] & reg_we & !reg_error; assign mio_pad_sleep_regwen_38_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_39_we = addr_hit[334] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_39_we = addr_hit[328] & reg_we & !reg_error; assign mio_pad_sleep_regwen_39_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_40_we = addr_hit[335] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_40_we = addr_hit[329] & reg_we & !reg_error; assign mio_pad_sleep_regwen_40_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_41_we = addr_hit[336] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_41_we = addr_hit[330] & reg_we & !reg_error; assign mio_pad_sleep_regwen_41_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_42_we = addr_hit[337] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_42_we = addr_hit[331] & reg_we & !reg_error; assign mio_pad_sleep_regwen_42_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_43_we = addr_hit[338] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_43_we = addr_hit[332] & reg_we & !reg_error; assign mio_pad_sleep_regwen_43_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_44_we = addr_hit[339] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_44_we = addr_hit[333] & reg_we & !reg_error; assign mio_pad_sleep_regwen_44_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_45_we = addr_hit[340] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_45_we = addr_hit[334] & reg_we & !reg_error; assign mio_pad_sleep_regwen_45_wd = reg_wdata[0]; - assign mio_pad_sleep_regwen_46_we = addr_hit[341] & reg_we & !reg_error; + assign mio_pad_sleep_regwen_46_we = addr_hit[335] & reg_we & !reg_error; assign mio_pad_sleep_regwen_46_wd = reg_wdata[0]; - assign mio_pad_sleep_en_0_we = addr_hit[342] & reg_we & !reg_error; + assign mio_pad_sleep_en_0_we = addr_hit[336] & reg_we & !reg_error; assign mio_pad_sleep_en_0_wd = reg_wdata[0]; - assign mio_pad_sleep_en_1_we = addr_hit[343] & reg_we & !reg_error; + assign mio_pad_sleep_en_1_we = addr_hit[337] & reg_we & !reg_error; assign mio_pad_sleep_en_1_wd = reg_wdata[0]; - assign mio_pad_sleep_en_2_we = addr_hit[344] & reg_we & !reg_error; + assign mio_pad_sleep_en_2_we = addr_hit[338] & reg_we & !reg_error; assign mio_pad_sleep_en_2_wd = reg_wdata[0]; - assign mio_pad_sleep_en_3_we = addr_hit[345] & reg_we & !reg_error; + assign mio_pad_sleep_en_3_we = addr_hit[339] & reg_we & !reg_error; assign mio_pad_sleep_en_3_wd = reg_wdata[0]; - assign mio_pad_sleep_en_4_we = addr_hit[346] & reg_we & !reg_error; + assign mio_pad_sleep_en_4_we = addr_hit[340] & reg_we & !reg_error; assign mio_pad_sleep_en_4_wd = reg_wdata[0]; - assign mio_pad_sleep_en_5_we = addr_hit[347] & reg_we & !reg_error; + assign mio_pad_sleep_en_5_we = addr_hit[341] & reg_we & !reg_error; assign mio_pad_sleep_en_5_wd = reg_wdata[0]; - assign mio_pad_sleep_en_6_we = addr_hit[348] & reg_we & !reg_error; + assign mio_pad_sleep_en_6_we = addr_hit[342] & reg_we & !reg_error; assign mio_pad_sleep_en_6_wd = reg_wdata[0]; - assign mio_pad_sleep_en_7_we = addr_hit[349] & reg_we & !reg_error; + assign mio_pad_sleep_en_7_we = addr_hit[343] & reg_we & !reg_error; assign mio_pad_sleep_en_7_wd = reg_wdata[0]; - assign mio_pad_sleep_en_8_we = addr_hit[350] & reg_we & !reg_error; + assign mio_pad_sleep_en_8_we = addr_hit[344] & reg_we & !reg_error; assign mio_pad_sleep_en_8_wd = reg_wdata[0]; - assign mio_pad_sleep_en_9_we = addr_hit[351] & reg_we & !reg_error; + assign mio_pad_sleep_en_9_we = addr_hit[345] & reg_we & !reg_error; assign mio_pad_sleep_en_9_wd = reg_wdata[0]; - assign mio_pad_sleep_en_10_we = addr_hit[352] & reg_we & !reg_error; + assign mio_pad_sleep_en_10_we = addr_hit[346] & reg_we & !reg_error; assign mio_pad_sleep_en_10_wd = reg_wdata[0]; - assign mio_pad_sleep_en_11_we = addr_hit[353] & reg_we & !reg_error; + assign mio_pad_sleep_en_11_we = addr_hit[347] & reg_we & !reg_error; assign mio_pad_sleep_en_11_wd = reg_wdata[0]; - assign mio_pad_sleep_en_12_we = addr_hit[354] & reg_we & !reg_error; + assign mio_pad_sleep_en_12_we = addr_hit[348] & reg_we & !reg_error; assign mio_pad_sleep_en_12_wd = reg_wdata[0]; - assign mio_pad_sleep_en_13_we = addr_hit[355] & reg_we & !reg_error; + assign mio_pad_sleep_en_13_we = addr_hit[349] & reg_we & !reg_error; assign mio_pad_sleep_en_13_wd = reg_wdata[0]; - assign mio_pad_sleep_en_14_we = addr_hit[356] & reg_we & !reg_error; + assign mio_pad_sleep_en_14_we = addr_hit[350] & reg_we & !reg_error; assign mio_pad_sleep_en_14_wd = reg_wdata[0]; - assign mio_pad_sleep_en_15_we = addr_hit[357] & reg_we & !reg_error; + assign mio_pad_sleep_en_15_we = addr_hit[351] & reg_we & !reg_error; assign mio_pad_sleep_en_15_wd = reg_wdata[0]; - assign mio_pad_sleep_en_16_we = addr_hit[358] & reg_we & !reg_error; + assign mio_pad_sleep_en_16_we = addr_hit[352] & reg_we & !reg_error; assign mio_pad_sleep_en_16_wd = reg_wdata[0]; - assign mio_pad_sleep_en_17_we = addr_hit[359] & reg_we & !reg_error; + assign mio_pad_sleep_en_17_we = addr_hit[353] & reg_we & !reg_error; assign mio_pad_sleep_en_17_wd = reg_wdata[0]; - assign mio_pad_sleep_en_18_we = addr_hit[360] & reg_we & !reg_error; + assign mio_pad_sleep_en_18_we = addr_hit[354] & reg_we & !reg_error; assign mio_pad_sleep_en_18_wd = reg_wdata[0]; - assign mio_pad_sleep_en_19_we = addr_hit[361] & reg_we & !reg_error; + assign mio_pad_sleep_en_19_we = addr_hit[355] & reg_we & !reg_error; assign mio_pad_sleep_en_19_wd = reg_wdata[0]; - assign mio_pad_sleep_en_20_we = addr_hit[362] & reg_we & !reg_error; + assign mio_pad_sleep_en_20_we = addr_hit[356] & reg_we & !reg_error; assign mio_pad_sleep_en_20_wd = reg_wdata[0]; - assign mio_pad_sleep_en_21_we = addr_hit[363] & reg_we & !reg_error; + assign mio_pad_sleep_en_21_we = addr_hit[357] & reg_we & !reg_error; assign mio_pad_sleep_en_21_wd = reg_wdata[0]; - assign mio_pad_sleep_en_22_we = addr_hit[364] & reg_we & !reg_error; + assign mio_pad_sleep_en_22_we = addr_hit[358] & reg_we & !reg_error; assign mio_pad_sleep_en_22_wd = reg_wdata[0]; - assign mio_pad_sleep_en_23_we = addr_hit[365] & reg_we & !reg_error; + assign mio_pad_sleep_en_23_we = addr_hit[359] & reg_we & !reg_error; assign mio_pad_sleep_en_23_wd = reg_wdata[0]; - assign mio_pad_sleep_en_24_we = addr_hit[366] & reg_we & !reg_error; + assign mio_pad_sleep_en_24_we = addr_hit[360] & reg_we & !reg_error; assign mio_pad_sleep_en_24_wd = reg_wdata[0]; - assign mio_pad_sleep_en_25_we = addr_hit[367] & reg_we & !reg_error; + assign mio_pad_sleep_en_25_we = addr_hit[361] & reg_we & !reg_error; assign mio_pad_sleep_en_25_wd = reg_wdata[0]; - assign mio_pad_sleep_en_26_we = addr_hit[368] & reg_we & !reg_error; + assign mio_pad_sleep_en_26_we = addr_hit[362] & reg_we & !reg_error; assign mio_pad_sleep_en_26_wd = reg_wdata[0]; - assign mio_pad_sleep_en_27_we = addr_hit[369] & reg_we & !reg_error; + assign mio_pad_sleep_en_27_we = addr_hit[363] & reg_we & !reg_error; assign mio_pad_sleep_en_27_wd = reg_wdata[0]; - assign mio_pad_sleep_en_28_we = addr_hit[370] & reg_we & !reg_error; + assign mio_pad_sleep_en_28_we = addr_hit[364] & reg_we & !reg_error; assign mio_pad_sleep_en_28_wd = reg_wdata[0]; - assign mio_pad_sleep_en_29_we = addr_hit[371] & reg_we & !reg_error; + assign mio_pad_sleep_en_29_we = addr_hit[365] & reg_we & !reg_error; assign mio_pad_sleep_en_29_wd = reg_wdata[0]; - assign mio_pad_sleep_en_30_we = addr_hit[372] & reg_we & !reg_error; + assign mio_pad_sleep_en_30_we = addr_hit[366] & reg_we & !reg_error; assign mio_pad_sleep_en_30_wd = reg_wdata[0]; - assign mio_pad_sleep_en_31_we = addr_hit[373] & reg_we & !reg_error; + assign mio_pad_sleep_en_31_we = addr_hit[367] & reg_we & !reg_error; assign mio_pad_sleep_en_31_wd = reg_wdata[0]; - assign mio_pad_sleep_en_32_we = addr_hit[374] & reg_we & !reg_error; + assign mio_pad_sleep_en_32_we = addr_hit[368] & reg_we & !reg_error; assign mio_pad_sleep_en_32_wd = reg_wdata[0]; - assign mio_pad_sleep_en_33_we = addr_hit[375] & reg_we & !reg_error; + assign mio_pad_sleep_en_33_we = addr_hit[369] & reg_we & !reg_error; assign mio_pad_sleep_en_33_wd = reg_wdata[0]; - assign mio_pad_sleep_en_34_we = addr_hit[376] & reg_we & !reg_error; + assign mio_pad_sleep_en_34_we = addr_hit[370] & reg_we & !reg_error; assign mio_pad_sleep_en_34_wd = reg_wdata[0]; - assign mio_pad_sleep_en_35_we = addr_hit[377] & reg_we & !reg_error; + assign mio_pad_sleep_en_35_we = addr_hit[371] & reg_we & !reg_error; assign mio_pad_sleep_en_35_wd = reg_wdata[0]; - assign mio_pad_sleep_en_36_we = addr_hit[378] & reg_we & !reg_error; + assign mio_pad_sleep_en_36_we = addr_hit[372] & reg_we & !reg_error; assign mio_pad_sleep_en_36_wd = reg_wdata[0]; - assign mio_pad_sleep_en_37_we = addr_hit[379] & reg_we & !reg_error; + assign mio_pad_sleep_en_37_we = addr_hit[373] & reg_we & !reg_error; assign mio_pad_sleep_en_37_wd = reg_wdata[0]; - assign mio_pad_sleep_en_38_we = addr_hit[380] & reg_we & !reg_error; + assign mio_pad_sleep_en_38_we = addr_hit[374] & reg_we & !reg_error; assign mio_pad_sleep_en_38_wd = reg_wdata[0]; - assign mio_pad_sleep_en_39_we = addr_hit[381] & reg_we & !reg_error; + assign mio_pad_sleep_en_39_we = addr_hit[375] & reg_we & !reg_error; assign mio_pad_sleep_en_39_wd = reg_wdata[0]; - assign mio_pad_sleep_en_40_we = addr_hit[382] & reg_we & !reg_error; + assign mio_pad_sleep_en_40_we = addr_hit[376] & reg_we & !reg_error; assign mio_pad_sleep_en_40_wd = reg_wdata[0]; - assign mio_pad_sleep_en_41_we = addr_hit[383] & reg_we & !reg_error; + assign mio_pad_sleep_en_41_we = addr_hit[377] & reg_we & !reg_error; assign mio_pad_sleep_en_41_wd = reg_wdata[0]; - assign mio_pad_sleep_en_42_we = addr_hit[384] & reg_we & !reg_error; + assign mio_pad_sleep_en_42_we = addr_hit[378] & reg_we & !reg_error; assign mio_pad_sleep_en_42_wd = reg_wdata[0]; - assign mio_pad_sleep_en_43_we = addr_hit[385] & reg_we & !reg_error; + assign mio_pad_sleep_en_43_we = addr_hit[379] & reg_we & !reg_error; assign mio_pad_sleep_en_43_wd = reg_wdata[0]; - assign mio_pad_sleep_en_44_we = addr_hit[386] & reg_we & !reg_error; + assign mio_pad_sleep_en_44_we = addr_hit[380] & reg_we & !reg_error; assign mio_pad_sleep_en_44_wd = reg_wdata[0]; - assign mio_pad_sleep_en_45_we = addr_hit[387] & reg_we & !reg_error; + assign mio_pad_sleep_en_45_we = addr_hit[381] & reg_we & !reg_error; assign mio_pad_sleep_en_45_wd = reg_wdata[0]; - assign mio_pad_sleep_en_46_we = addr_hit[388] & reg_we & !reg_error; + assign mio_pad_sleep_en_46_we = addr_hit[382] & reg_we & !reg_error; assign mio_pad_sleep_en_46_wd = reg_wdata[0]; - assign mio_pad_sleep_mode_0_we = addr_hit[389] & reg_we & !reg_error; + assign mio_pad_sleep_mode_0_we = addr_hit[383] & reg_we & !reg_error; assign mio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_1_we = addr_hit[390] & reg_we & !reg_error; + assign mio_pad_sleep_mode_1_we = addr_hit[384] & reg_we & !reg_error; assign mio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_2_we = addr_hit[391] & reg_we & !reg_error; + assign mio_pad_sleep_mode_2_we = addr_hit[385] & reg_we & !reg_error; assign mio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_3_we = addr_hit[392] & reg_we & !reg_error; + assign mio_pad_sleep_mode_3_we = addr_hit[386] & reg_we & !reg_error; assign mio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_4_we = addr_hit[393] & reg_we & !reg_error; + assign mio_pad_sleep_mode_4_we = addr_hit[387] & reg_we & !reg_error; assign mio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_5_we = addr_hit[394] & reg_we & !reg_error; + assign mio_pad_sleep_mode_5_we = addr_hit[388] & reg_we & !reg_error; assign mio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_6_we = addr_hit[395] & reg_we & !reg_error; + assign mio_pad_sleep_mode_6_we = addr_hit[389] & reg_we & !reg_error; assign mio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_7_we = addr_hit[396] & reg_we & !reg_error; + assign mio_pad_sleep_mode_7_we = addr_hit[390] & reg_we & !reg_error; assign mio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_8_we = addr_hit[397] & reg_we & !reg_error; + assign mio_pad_sleep_mode_8_we = addr_hit[391] & reg_we & !reg_error; assign mio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_9_we = addr_hit[398] & reg_we & !reg_error; + assign mio_pad_sleep_mode_9_we = addr_hit[392] & reg_we & !reg_error; assign mio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_10_we = addr_hit[399] & reg_we & !reg_error; + assign mio_pad_sleep_mode_10_we = addr_hit[393] & reg_we & !reg_error; assign mio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_11_we = addr_hit[400] & reg_we & !reg_error; + assign mio_pad_sleep_mode_11_we = addr_hit[394] & reg_we & !reg_error; assign mio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_12_we = addr_hit[401] & reg_we & !reg_error; + assign mio_pad_sleep_mode_12_we = addr_hit[395] & reg_we & !reg_error; assign mio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_13_we = addr_hit[402] & reg_we & !reg_error; + assign mio_pad_sleep_mode_13_we = addr_hit[396] & reg_we & !reg_error; assign mio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_14_we = addr_hit[403] & reg_we & !reg_error; + assign mio_pad_sleep_mode_14_we = addr_hit[397] & reg_we & !reg_error; assign mio_pad_sleep_mode_14_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_15_we = addr_hit[404] & reg_we & !reg_error; + assign mio_pad_sleep_mode_15_we = addr_hit[398] & reg_we & !reg_error; assign mio_pad_sleep_mode_15_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_16_we = addr_hit[405] & reg_we & !reg_error; + assign mio_pad_sleep_mode_16_we = addr_hit[399] & reg_we & !reg_error; assign mio_pad_sleep_mode_16_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_17_we = addr_hit[406] & reg_we & !reg_error; + assign mio_pad_sleep_mode_17_we = addr_hit[400] & reg_we & !reg_error; assign mio_pad_sleep_mode_17_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_18_we = addr_hit[407] & reg_we & !reg_error; + assign mio_pad_sleep_mode_18_we = addr_hit[401] & reg_we & !reg_error; assign mio_pad_sleep_mode_18_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_19_we = addr_hit[408] & reg_we & !reg_error; + assign mio_pad_sleep_mode_19_we = addr_hit[402] & reg_we & !reg_error; assign mio_pad_sleep_mode_19_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_20_we = addr_hit[409] & reg_we & !reg_error; + assign mio_pad_sleep_mode_20_we = addr_hit[403] & reg_we & !reg_error; assign mio_pad_sleep_mode_20_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_21_we = addr_hit[410] & reg_we & !reg_error; + assign mio_pad_sleep_mode_21_we = addr_hit[404] & reg_we & !reg_error; assign mio_pad_sleep_mode_21_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_22_we = addr_hit[411] & reg_we & !reg_error; + assign mio_pad_sleep_mode_22_we = addr_hit[405] & reg_we & !reg_error; assign mio_pad_sleep_mode_22_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_23_we = addr_hit[412] & reg_we & !reg_error; + assign mio_pad_sleep_mode_23_we = addr_hit[406] & reg_we & !reg_error; assign mio_pad_sleep_mode_23_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_24_we = addr_hit[413] & reg_we & !reg_error; + assign mio_pad_sleep_mode_24_we = addr_hit[407] & reg_we & !reg_error; assign mio_pad_sleep_mode_24_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_25_we = addr_hit[414] & reg_we & !reg_error; + assign mio_pad_sleep_mode_25_we = addr_hit[408] & reg_we & !reg_error; assign mio_pad_sleep_mode_25_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_26_we = addr_hit[415] & reg_we & !reg_error; + assign mio_pad_sleep_mode_26_we = addr_hit[409] & reg_we & !reg_error; assign mio_pad_sleep_mode_26_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_27_we = addr_hit[416] & reg_we & !reg_error; + assign mio_pad_sleep_mode_27_we = addr_hit[410] & reg_we & !reg_error; assign mio_pad_sleep_mode_27_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_28_we = addr_hit[417] & reg_we & !reg_error; + assign mio_pad_sleep_mode_28_we = addr_hit[411] & reg_we & !reg_error; assign mio_pad_sleep_mode_28_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_29_we = addr_hit[418] & reg_we & !reg_error; + assign mio_pad_sleep_mode_29_we = addr_hit[412] & reg_we & !reg_error; assign mio_pad_sleep_mode_29_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_30_we = addr_hit[419] & reg_we & !reg_error; + assign mio_pad_sleep_mode_30_we = addr_hit[413] & reg_we & !reg_error; assign mio_pad_sleep_mode_30_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_31_we = addr_hit[420] & reg_we & !reg_error; + assign mio_pad_sleep_mode_31_we = addr_hit[414] & reg_we & !reg_error; assign mio_pad_sleep_mode_31_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_32_we = addr_hit[421] & reg_we & !reg_error; + assign mio_pad_sleep_mode_32_we = addr_hit[415] & reg_we & !reg_error; assign mio_pad_sleep_mode_32_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_33_we = addr_hit[422] & reg_we & !reg_error; + assign mio_pad_sleep_mode_33_we = addr_hit[416] & reg_we & !reg_error; assign mio_pad_sleep_mode_33_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_34_we = addr_hit[423] & reg_we & !reg_error; + assign mio_pad_sleep_mode_34_we = addr_hit[417] & reg_we & !reg_error; assign mio_pad_sleep_mode_34_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_35_we = addr_hit[424] & reg_we & !reg_error; + assign mio_pad_sleep_mode_35_we = addr_hit[418] & reg_we & !reg_error; assign mio_pad_sleep_mode_35_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_36_we = addr_hit[425] & reg_we & !reg_error; + assign mio_pad_sleep_mode_36_we = addr_hit[419] & reg_we & !reg_error; assign mio_pad_sleep_mode_36_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_37_we = addr_hit[426] & reg_we & !reg_error; + assign mio_pad_sleep_mode_37_we = addr_hit[420] & reg_we & !reg_error; assign mio_pad_sleep_mode_37_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_38_we = addr_hit[427] & reg_we & !reg_error; + assign mio_pad_sleep_mode_38_we = addr_hit[421] & reg_we & !reg_error; assign mio_pad_sleep_mode_38_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_39_we = addr_hit[428] & reg_we & !reg_error; + assign mio_pad_sleep_mode_39_we = addr_hit[422] & reg_we & !reg_error; assign mio_pad_sleep_mode_39_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_40_we = addr_hit[429] & reg_we & !reg_error; + assign mio_pad_sleep_mode_40_we = addr_hit[423] & reg_we & !reg_error; assign mio_pad_sleep_mode_40_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_41_we = addr_hit[430] & reg_we & !reg_error; + assign mio_pad_sleep_mode_41_we = addr_hit[424] & reg_we & !reg_error; assign mio_pad_sleep_mode_41_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_42_we = addr_hit[431] & reg_we & !reg_error; + assign mio_pad_sleep_mode_42_we = addr_hit[425] & reg_we & !reg_error; assign mio_pad_sleep_mode_42_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_43_we = addr_hit[432] & reg_we & !reg_error; + assign mio_pad_sleep_mode_43_we = addr_hit[426] & reg_we & !reg_error; assign mio_pad_sleep_mode_43_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_44_we = addr_hit[433] & reg_we & !reg_error; + assign mio_pad_sleep_mode_44_we = addr_hit[427] & reg_we & !reg_error; assign mio_pad_sleep_mode_44_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_45_we = addr_hit[434] & reg_we & !reg_error; + assign mio_pad_sleep_mode_45_we = addr_hit[428] & reg_we & !reg_error; assign mio_pad_sleep_mode_45_wd = reg_wdata[1:0]; - assign mio_pad_sleep_mode_46_we = addr_hit[435] & reg_we & !reg_error; + assign mio_pad_sleep_mode_46_we = addr_hit[429] & reg_we & !reg_error; assign mio_pad_sleep_mode_46_wd = reg_wdata[1:0]; - assign dio_pad_sleep_status_we = addr_hit[436] & reg_we & !reg_error; + assign dio_pad_sleep_status_we = addr_hit[430] & reg_we & !reg_error; assign dio_pad_sleep_status_en_0_wd = reg_wdata[0]; @@ -34184,245 +33953,245 @@ module pinmux_reg_top ( assign dio_pad_sleep_status_en_12_wd = reg_wdata[12]; assign dio_pad_sleep_status_en_13_wd = reg_wdata[13]; - assign dio_pad_sleep_regwen_0_we = addr_hit[437] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_0_we = addr_hit[431] & reg_we & !reg_error; assign dio_pad_sleep_regwen_0_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_1_we = addr_hit[438] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_1_we = addr_hit[432] & reg_we & !reg_error; assign dio_pad_sleep_regwen_1_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_2_we = addr_hit[439] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_2_we = addr_hit[433] & reg_we & !reg_error; assign dio_pad_sleep_regwen_2_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_3_we = addr_hit[440] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_3_we = addr_hit[434] & reg_we & !reg_error; assign dio_pad_sleep_regwen_3_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_4_we = addr_hit[441] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_4_we = addr_hit[435] & reg_we & !reg_error; assign dio_pad_sleep_regwen_4_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_5_we = addr_hit[442] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_5_we = addr_hit[436] & reg_we & !reg_error; assign dio_pad_sleep_regwen_5_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_6_we = addr_hit[443] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_6_we = addr_hit[437] & reg_we & !reg_error; assign dio_pad_sleep_regwen_6_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_7_we = addr_hit[444] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_7_we = addr_hit[438] & reg_we & !reg_error; assign dio_pad_sleep_regwen_7_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_8_we = addr_hit[445] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_8_we = addr_hit[439] & reg_we & !reg_error; assign dio_pad_sleep_regwen_8_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_9_we = addr_hit[446] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_9_we = addr_hit[440] & reg_we & !reg_error; assign dio_pad_sleep_regwen_9_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_10_we = addr_hit[447] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_10_we = addr_hit[441] & reg_we & !reg_error; assign dio_pad_sleep_regwen_10_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_11_we = addr_hit[448] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_11_we = addr_hit[442] & reg_we & !reg_error; assign dio_pad_sleep_regwen_11_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_12_we = addr_hit[449] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_12_we = addr_hit[443] & reg_we & !reg_error; assign dio_pad_sleep_regwen_12_wd = reg_wdata[0]; - assign dio_pad_sleep_regwen_13_we = addr_hit[450] & reg_we & !reg_error; + assign dio_pad_sleep_regwen_13_we = addr_hit[444] & reg_we & !reg_error; assign dio_pad_sleep_regwen_13_wd = reg_wdata[0]; - assign dio_pad_sleep_en_0_we = addr_hit[451] & reg_we & !reg_error; + assign dio_pad_sleep_en_0_we = addr_hit[445] & reg_we & !reg_error; assign dio_pad_sleep_en_0_wd = reg_wdata[0]; - assign dio_pad_sleep_en_1_we = addr_hit[452] & reg_we & !reg_error; + assign dio_pad_sleep_en_1_we = addr_hit[446] & reg_we & !reg_error; assign dio_pad_sleep_en_1_wd = reg_wdata[0]; - assign dio_pad_sleep_en_2_we = addr_hit[453] & reg_we & !reg_error; + assign dio_pad_sleep_en_2_we = addr_hit[447] & reg_we & !reg_error; assign dio_pad_sleep_en_2_wd = reg_wdata[0]; - assign dio_pad_sleep_en_3_we = addr_hit[454] & reg_we & !reg_error; + assign dio_pad_sleep_en_3_we = addr_hit[448] & reg_we & !reg_error; assign dio_pad_sleep_en_3_wd = reg_wdata[0]; - assign dio_pad_sleep_en_4_we = addr_hit[455] & reg_we & !reg_error; + assign dio_pad_sleep_en_4_we = addr_hit[449] & reg_we & !reg_error; assign dio_pad_sleep_en_4_wd = reg_wdata[0]; - assign dio_pad_sleep_en_5_we = addr_hit[456] & reg_we & !reg_error; + assign dio_pad_sleep_en_5_we = addr_hit[450] & reg_we & !reg_error; assign dio_pad_sleep_en_5_wd = reg_wdata[0]; - assign dio_pad_sleep_en_6_we = addr_hit[457] & reg_we & !reg_error; + assign dio_pad_sleep_en_6_we = addr_hit[451] & reg_we & !reg_error; assign dio_pad_sleep_en_6_wd = reg_wdata[0]; - assign dio_pad_sleep_en_7_we = addr_hit[458] & reg_we & !reg_error; + assign dio_pad_sleep_en_7_we = addr_hit[452] & reg_we & !reg_error; assign dio_pad_sleep_en_7_wd = reg_wdata[0]; - assign dio_pad_sleep_en_8_we = addr_hit[459] & reg_we & !reg_error; + assign dio_pad_sleep_en_8_we = addr_hit[453] & reg_we & !reg_error; assign dio_pad_sleep_en_8_wd = reg_wdata[0]; - assign dio_pad_sleep_en_9_we = addr_hit[460] & reg_we & !reg_error; + assign dio_pad_sleep_en_9_we = addr_hit[454] & reg_we & !reg_error; assign dio_pad_sleep_en_9_wd = reg_wdata[0]; - assign dio_pad_sleep_en_10_we = addr_hit[461] & reg_we & !reg_error; + assign dio_pad_sleep_en_10_we = addr_hit[455] & reg_we & !reg_error; assign dio_pad_sleep_en_10_wd = reg_wdata[0]; - assign dio_pad_sleep_en_11_we = addr_hit[462] & reg_we & !reg_error; + assign dio_pad_sleep_en_11_we = addr_hit[456] & reg_we & !reg_error; assign dio_pad_sleep_en_11_wd = reg_wdata[0]; - assign dio_pad_sleep_en_12_we = addr_hit[463] & reg_we & !reg_error; + assign dio_pad_sleep_en_12_we = addr_hit[457] & reg_we & !reg_error; assign dio_pad_sleep_en_12_wd = reg_wdata[0]; - assign dio_pad_sleep_en_13_we = addr_hit[464] & reg_we & !reg_error; + assign dio_pad_sleep_en_13_we = addr_hit[458] & reg_we & !reg_error; assign dio_pad_sleep_en_13_wd = reg_wdata[0]; - assign dio_pad_sleep_mode_0_we = addr_hit[465] & reg_we & !reg_error; + assign dio_pad_sleep_mode_0_we = addr_hit[459] & reg_we & !reg_error; assign dio_pad_sleep_mode_0_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_1_we = addr_hit[466] & reg_we & !reg_error; + assign dio_pad_sleep_mode_1_we = addr_hit[460] & reg_we & !reg_error; assign dio_pad_sleep_mode_1_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_2_we = addr_hit[467] & reg_we & !reg_error; + assign dio_pad_sleep_mode_2_we = addr_hit[461] & reg_we & !reg_error; assign dio_pad_sleep_mode_2_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_3_we = addr_hit[468] & reg_we & !reg_error; + assign dio_pad_sleep_mode_3_we = addr_hit[462] & reg_we & !reg_error; assign dio_pad_sleep_mode_3_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_4_we = addr_hit[469] & reg_we & !reg_error; + assign dio_pad_sleep_mode_4_we = addr_hit[463] & reg_we & !reg_error; assign dio_pad_sleep_mode_4_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_5_we = addr_hit[470] & reg_we & !reg_error; + assign dio_pad_sleep_mode_5_we = addr_hit[464] & reg_we & !reg_error; assign dio_pad_sleep_mode_5_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_6_we = addr_hit[471] & reg_we & !reg_error; + assign dio_pad_sleep_mode_6_we = addr_hit[465] & reg_we & !reg_error; assign dio_pad_sleep_mode_6_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_7_we = addr_hit[472] & reg_we & !reg_error; + assign dio_pad_sleep_mode_7_we = addr_hit[466] & reg_we & !reg_error; assign dio_pad_sleep_mode_7_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_8_we = addr_hit[473] & reg_we & !reg_error; + assign dio_pad_sleep_mode_8_we = addr_hit[467] & reg_we & !reg_error; assign dio_pad_sleep_mode_8_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_9_we = addr_hit[474] & reg_we & !reg_error; + assign dio_pad_sleep_mode_9_we = addr_hit[468] & reg_we & !reg_error; assign dio_pad_sleep_mode_9_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_10_we = addr_hit[475] & reg_we & !reg_error; + assign dio_pad_sleep_mode_10_we = addr_hit[469] & reg_we & !reg_error; assign dio_pad_sleep_mode_10_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_11_we = addr_hit[476] & reg_we & !reg_error; + assign dio_pad_sleep_mode_11_we = addr_hit[470] & reg_we & !reg_error; assign dio_pad_sleep_mode_11_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_12_we = addr_hit[477] & reg_we & !reg_error; + assign dio_pad_sleep_mode_12_we = addr_hit[471] & reg_we & !reg_error; assign dio_pad_sleep_mode_12_wd = reg_wdata[1:0]; - assign dio_pad_sleep_mode_13_we = addr_hit[478] & reg_we & !reg_error; + assign dio_pad_sleep_mode_13_we = addr_hit[472] & reg_we & !reg_error; assign dio_pad_sleep_mode_13_wd = reg_wdata[1:0]; - assign wkup_detector_regwen_0_we = addr_hit[479] & reg_we & !reg_error; + assign wkup_detector_regwen_0_we = addr_hit[473] & reg_we & !reg_error; assign wkup_detector_regwen_0_wd = reg_wdata[0]; - assign wkup_detector_regwen_1_we = addr_hit[480] & reg_we & !reg_error; + assign wkup_detector_regwen_1_we = addr_hit[474] & reg_we & !reg_error; assign wkup_detector_regwen_1_wd = reg_wdata[0]; - assign wkup_detector_regwen_2_we = addr_hit[481] & reg_we & !reg_error; + assign wkup_detector_regwen_2_we = addr_hit[475] & reg_we & !reg_error; assign wkup_detector_regwen_2_wd = reg_wdata[0]; - assign wkup_detector_regwen_3_we = addr_hit[482] & reg_we & !reg_error; + assign wkup_detector_regwen_3_we = addr_hit[476] & reg_we & !reg_error; assign wkup_detector_regwen_3_wd = reg_wdata[0]; - assign wkup_detector_regwen_4_we = addr_hit[483] & reg_we & !reg_error; + assign wkup_detector_regwen_4_we = addr_hit[477] & reg_we & !reg_error; assign wkup_detector_regwen_4_wd = reg_wdata[0]; - assign wkup_detector_regwen_5_we = addr_hit[484] & reg_we & !reg_error; + assign wkup_detector_regwen_5_we = addr_hit[478] & reg_we & !reg_error; assign wkup_detector_regwen_5_wd = reg_wdata[0]; - assign wkup_detector_regwen_6_we = addr_hit[485] & reg_we & !reg_error; + assign wkup_detector_regwen_6_we = addr_hit[479] & reg_we & !reg_error; assign wkup_detector_regwen_6_wd = reg_wdata[0]; - assign wkup_detector_regwen_7_we = addr_hit[486] & reg_we & !reg_error; + assign wkup_detector_regwen_7_we = addr_hit[480] & reg_we & !reg_error; assign wkup_detector_regwen_7_wd = reg_wdata[0]; - assign wkup_detector_en_0_we = addr_hit[487] & reg_we & !reg_error; + assign wkup_detector_en_0_we = addr_hit[481] & reg_we & !reg_error; - assign wkup_detector_en_1_we = addr_hit[488] & reg_we & !reg_error; + assign wkup_detector_en_1_we = addr_hit[482] & reg_we & !reg_error; - assign wkup_detector_en_2_we = addr_hit[489] & reg_we & !reg_error; + assign wkup_detector_en_2_we = addr_hit[483] & reg_we & !reg_error; - assign wkup_detector_en_3_we = addr_hit[490] & reg_we & !reg_error; + assign wkup_detector_en_3_we = addr_hit[484] & reg_we & !reg_error; - assign wkup_detector_en_4_we = addr_hit[491] & reg_we & !reg_error; + assign wkup_detector_en_4_we = addr_hit[485] & reg_we & !reg_error; - assign wkup_detector_en_5_we = addr_hit[492] & reg_we & !reg_error; + assign wkup_detector_en_5_we = addr_hit[486] & reg_we & !reg_error; - assign wkup_detector_en_6_we = addr_hit[493] & reg_we & !reg_error; + assign wkup_detector_en_6_we = addr_hit[487] & reg_we & !reg_error; - assign wkup_detector_en_7_we = addr_hit[494] & reg_we & !reg_error; + assign wkup_detector_en_7_we = addr_hit[488] & reg_we & !reg_error; - assign wkup_detector_0_we = addr_hit[495] & reg_we & !reg_error; + assign wkup_detector_0_we = addr_hit[489] & reg_we & !reg_error; - assign wkup_detector_1_we = addr_hit[496] & reg_we & !reg_error; + assign wkup_detector_1_we = addr_hit[490] & reg_we & !reg_error; - assign wkup_detector_2_we = addr_hit[497] & reg_we & !reg_error; + assign wkup_detector_2_we = addr_hit[491] & reg_we & !reg_error; - assign wkup_detector_3_we = addr_hit[498] & reg_we & !reg_error; + assign wkup_detector_3_we = addr_hit[492] & reg_we & !reg_error; - assign wkup_detector_4_we = addr_hit[499] & reg_we & !reg_error; + assign wkup_detector_4_we = addr_hit[493] & reg_we & !reg_error; - assign wkup_detector_5_we = addr_hit[500] & reg_we & !reg_error; + assign wkup_detector_5_we = addr_hit[494] & reg_we & !reg_error; - assign wkup_detector_6_we = addr_hit[501] & reg_we & !reg_error; + assign wkup_detector_6_we = addr_hit[495] & reg_we & !reg_error; - assign wkup_detector_7_we = addr_hit[502] & reg_we & !reg_error; + assign wkup_detector_7_we = addr_hit[496] & reg_we & !reg_error; - assign wkup_detector_cnt_th_0_we = addr_hit[503] & reg_we & !reg_error; + assign wkup_detector_cnt_th_0_we = addr_hit[497] & reg_we & !reg_error; - assign wkup_detector_cnt_th_1_we = addr_hit[504] & reg_we & !reg_error; + assign wkup_detector_cnt_th_1_we = addr_hit[498] & reg_we & !reg_error; - assign wkup_detector_cnt_th_2_we = addr_hit[505] & reg_we & !reg_error; + assign wkup_detector_cnt_th_2_we = addr_hit[499] & reg_we & !reg_error; - assign wkup_detector_cnt_th_3_we = addr_hit[506] & reg_we & !reg_error; + assign wkup_detector_cnt_th_3_we = addr_hit[500] & reg_we & !reg_error; - assign wkup_detector_cnt_th_4_we = addr_hit[507] & reg_we & !reg_error; + assign wkup_detector_cnt_th_4_we = addr_hit[501] & reg_we & !reg_error; - assign wkup_detector_cnt_th_5_we = addr_hit[508] & reg_we & !reg_error; + assign wkup_detector_cnt_th_5_we = addr_hit[502] & reg_we & !reg_error; - assign wkup_detector_cnt_th_6_we = addr_hit[509] & reg_we & !reg_error; + assign wkup_detector_cnt_th_6_we = addr_hit[503] & reg_we & !reg_error; - assign wkup_detector_cnt_th_7_we = addr_hit[510] & reg_we & !reg_error; + assign wkup_detector_cnt_th_7_we = addr_hit[504] & reg_we & !reg_error; - assign wkup_detector_padsel_0_we = addr_hit[511] & reg_we & !reg_error; + assign wkup_detector_padsel_0_we = addr_hit[505] & reg_we & !reg_error; assign wkup_detector_padsel_0_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_1_we = addr_hit[512] & reg_we & !reg_error; + assign wkup_detector_padsel_1_we = addr_hit[506] & reg_we & !reg_error; assign wkup_detector_padsel_1_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_2_we = addr_hit[513] & reg_we & !reg_error; + assign wkup_detector_padsel_2_we = addr_hit[507] & reg_we & !reg_error; assign wkup_detector_padsel_2_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_3_we = addr_hit[514] & reg_we & !reg_error; + assign wkup_detector_padsel_3_we = addr_hit[508] & reg_we & !reg_error; assign wkup_detector_padsel_3_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_4_we = addr_hit[515] & reg_we & !reg_error; + assign wkup_detector_padsel_4_we = addr_hit[509] & reg_we & !reg_error; assign wkup_detector_padsel_4_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_5_we = addr_hit[516] & reg_we & !reg_error; + assign wkup_detector_padsel_5_we = addr_hit[510] & reg_we & !reg_error; assign wkup_detector_padsel_5_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_6_we = addr_hit[517] & reg_we & !reg_error; + assign wkup_detector_padsel_6_we = addr_hit[511] & reg_we & !reg_error; assign wkup_detector_padsel_6_wd = reg_wdata[5:0]; - assign wkup_detector_padsel_7_we = addr_hit[518] & reg_we & !reg_error; + assign wkup_detector_padsel_7_we = addr_hit[512] & reg_we & !reg_error; assign wkup_detector_padsel_7_wd = reg_wdata[5:0]; - assign wkup_cause_we = addr_hit[519] & reg_we & !reg_error; + assign wkup_cause_we = addr_hit[513] & reg_we & !reg_error; @@ -34470,490 +34239,484 @@ module pinmux_reg_top ( reg_we_check[33] = mio_periph_insel_regwen_32_we; reg_we_check[34] = mio_periph_insel_regwen_33_we; reg_we_check[35] = mio_periph_insel_regwen_34_we; - reg_we_check[36] = mio_periph_insel_regwen_35_we; - reg_we_check[37] = mio_periph_insel_regwen_36_we; - reg_we_check[38] = mio_periph_insel_regwen_37_we; - reg_we_check[39] = mio_periph_insel_0_gated_we; - reg_we_check[40] = mio_periph_insel_1_gated_we; - reg_we_check[41] = mio_periph_insel_2_gated_we; - reg_we_check[42] = mio_periph_insel_3_gated_we; - reg_we_check[43] = mio_periph_insel_4_gated_we; - reg_we_check[44] = mio_periph_insel_5_gated_we; - reg_we_check[45] = mio_periph_insel_6_gated_we; - reg_we_check[46] = mio_periph_insel_7_gated_we; - reg_we_check[47] = mio_periph_insel_8_gated_we; - reg_we_check[48] = mio_periph_insel_9_gated_we; - reg_we_check[49] = mio_periph_insel_10_gated_we; - reg_we_check[50] = mio_periph_insel_11_gated_we; - reg_we_check[51] = mio_periph_insel_12_gated_we; - reg_we_check[52] = mio_periph_insel_13_gated_we; - reg_we_check[53] = mio_periph_insel_14_gated_we; - reg_we_check[54] = mio_periph_insel_15_gated_we; - reg_we_check[55] = mio_periph_insel_16_gated_we; - reg_we_check[56] = mio_periph_insel_17_gated_we; - reg_we_check[57] = mio_periph_insel_18_gated_we; - reg_we_check[58] = mio_periph_insel_19_gated_we; - reg_we_check[59] = mio_periph_insel_20_gated_we; - reg_we_check[60] = mio_periph_insel_21_gated_we; - reg_we_check[61] = mio_periph_insel_22_gated_we; - reg_we_check[62] = mio_periph_insel_23_gated_we; - reg_we_check[63] = mio_periph_insel_24_gated_we; - reg_we_check[64] = mio_periph_insel_25_gated_we; - reg_we_check[65] = mio_periph_insel_26_gated_we; - reg_we_check[66] = mio_periph_insel_27_gated_we; - reg_we_check[67] = mio_periph_insel_28_gated_we; - reg_we_check[68] = mio_periph_insel_29_gated_we; - reg_we_check[69] = mio_periph_insel_30_gated_we; - reg_we_check[70] = mio_periph_insel_31_gated_we; - reg_we_check[71] = mio_periph_insel_32_gated_we; - reg_we_check[72] = mio_periph_insel_33_gated_we; - reg_we_check[73] = mio_periph_insel_34_gated_we; - reg_we_check[74] = mio_periph_insel_35_gated_we; - reg_we_check[75] = mio_periph_insel_36_gated_we; - reg_we_check[76] = mio_periph_insel_37_gated_we; - reg_we_check[77] = mio_outsel_regwen_0_we; - reg_we_check[78] = mio_outsel_regwen_1_we; - reg_we_check[79] = mio_outsel_regwen_2_we; - reg_we_check[80] = mio_outsel_regwen_3_we; - reg_we_check[81] = mio_outsel_regwen_4_we; - reg_we_check[82] = mio_outsel_regwen_5_we; - reg_we_check[83] = mio_outsel_regwen_6_we; - reg_we_check[84] = mio_outsel_regwen_7_we; - reg_we_check[85] = mio_outsel_regwen_8_we; - reg_we_check[86] = mio_outsel_regwen_9_we; - reg_we_check[87] = mio_outsel_regwen_10_we; - reg_we_check[88] = mio_outsel_regwen_11_we; - reg_we_check[89] = mio_outsel_regwen_12_we; - reg_we_check[90] = mio_outsel_regwen_13_we; - reg_we_check[91] = mio_outsel_regwen_14_we; - reg_we_check[92] = mio_outsel_regwen_15_we; - reg_we_check[93] = mio_outsel_regwen_16_we; - reg_we_check[94] = mio_outsel_regwen_17_we; - reg_we_check[95] = mio_outsel_regwen_18_we; - reg_we_check[96] = mio_outsel_regwen_19_we; - reg_we_check[97] = mio_outsel_regwen_20_we; - reg_we_check[98] = mio_outsel_regwen_21_we; - reg_we_check[99] = mio_outsel_regwen_22_we; - reg_we_check[100] = mio_outsel_regwen_23_we; - reg_we_check[101] = mio_outsel_regwen_24_we; - reg_we_check[102] = mio_outsel_regwen_25_we; - reg_we_check[103] = mio_outsel_regwen_26_we; - reg_we_check[104] = mio_outsel_regwen_27_we; - reg_we_check[105] = mio_outsel_regwen_28_we; - reg_we_check[106] = mio_outsel_regwen_29_we; - reg_we_check[107] = mio_outsel_regwen_30_we; - reg_we_check[108] = mio_outsel_regwen_31_we; - reg_we_check[109] = mio_outsel_regwen_32_we; - reg_we_check[110] = mio_outsel_regwen_33_we; - reg_we_check[111] = mio_outsel_regwen_34_we; - reg_we_check[112] = mio_outsel_regwen_35_we; - reg_we_check[113] = mio_outsel_regwen_36_we; - reg_we_check[114] = mio_outsel_regwen_37_we; - reg_we_check[115] = mio_outsel_regwen_38_we; - reg_we_check[116] = mio_outsel_regwen_39_we; - reg_we_check[117] = mio_outsel_regwen_40_we; - reg_we_check[118] = mio_outsel_regwen_41_we; - reg_we_check[119] = mio_outsel_regwen_42_we; - reg_we_check[120] = mio_outsel_regwen_43_we; - reg_we_check[121] = mio_outsel_regwen_44_we; - reg_we_check[122] = mio_outsel_regwen_45_we; - reg_we_check[123] = mio_outsel_regwen_46_we; - reg_we_check[124] = mio_outsel_0_gated_we; - reg_we_check[125] = mio_outsel_1_gated_we; - reg_we_check[126] = mio_outsel_2_gated_we; - reg_we_check[127] = mio_outsel_3_gated_we; - reg_we_check[128] = mio_outsel_4_gated_we; - reg_we_check[129] = mio_outsel_5_gated_we; - reg_we_check[130] = mio_outsel_6_gated_we; - reg_we_check[131] = mio_outsel_7_gated_we; - reg_we_check[132] = mio_outsel_8_gated_we; - reg_we_check[133] = mio_outsel_9_gated_we; - reg_we_check[134] = mio_outsel_10_gated_we; - reg_we_check[135] = mio_outsel_11_gated_we; - reg_we_check[136] = mio_outsel_12_gated_we; - reg_we_check[137] = mio_outsel_13_gated_we; - reg_we_check[138] = mio_outsel_14_gated_we; - reg_we_check[139] = mio_outsel_15_gated_we; - reg_we_check[140] = mio_outsel_16_gated_we; - reg_we_check[141] = mio_outsel_17_gated_we; - reg_we_check[142] = mio_outsel_18_gated_we; - reg_we_check[143] = mio_outsel_19_gated_we; - reg_we_check[144] = mio_outsel_20_gated_we; - reg_we_check[145] = mio_outsel_21_gated_we; - reg_we_check[146] = mio_outsel_22_gated_we; - reg_we_check[147] = mio_outsel_23_gated_we; - reg_we_check[148] = mio_outsel_24_gated_we; - reg_we_check[149] = mio_outsel_25_gated_we; - reg_we_check[150] = mio_outsel_26_gated_we; - reg_we_check[151] = mio_outsel_27_gated_we; - reg_we_check[152] = mio_outsel_28_gated_we; - reg_we_check[153] = mio_outsel_29_gated_we; - reg_we_check[154] = mio_outsel_30_gated_we; - reg_we_check[155] = mio_outsel_31_gated_we; - reg_we_check[156] = mio_outsel_32_gated_we; - reg_we_check[157] = mio_outsel_33_gated_we; - reg_we_check[158] = mio_outsel_34_gated_we; - reg_we_check[159] = mio_outsel_35_gated_we; - reg_we_check[160] = mio_outsel_36_gated_we; - reg_we_check[161] = mio_outsel_37_gated_we; - reg_we_check[162] = mio_outsel_38_gated_we; - reg_we_check[163] = mio_outsel_39_gated_we; - reg_we_check[164] = mio_outsel_40_gated_we; - reg_we_check[165] = mio_outsel_41_gated_we; - reg_we_check[166] = mio_outsel_42_gated_we; - reg_we_check[167] = mio_outsel_43_gated_we; - reg_we_check[168] = mio_outsel_44_gated_we; - reg_we_check[169] = mio_outsel_45_gated_we; - reg_we_check[170] = mio_outsel_46_gated_we; - reg_we_check[171] = mio_pad_attr_regwen_0_we; - reg_we_check[172] = mio_pad_attr_regwen_1_we; - reg_we_check[173] = mio_pad_attr_regwen_2_we; - reg_we_check[174] = mio_pad_attr_regwen_3_we; - reg_we_check[175] = mio_pad_attr_regwen_4_we; - reg_we_check[176] = mio_pad_attr_regwen_5_we; - reg_we_check[177] = mio_pad_attr_regwen_6_we; - reg_we_check[178] = mio_pad_attr_regwen_7_we; - reg_we_check[179] = mio_pad_attr_regwen_8_we; - reg_we_check[180] = mio_pad_attr_regwen_9_we; - reg_we_check[181] = mio_pad_attr_regwen_10_we; - reg_we_check[182] = mio_pad_attr_regwen_11_we; - reg_we_check[183] = mio_pad_attr_regwen_12_we; - reg_we_check[184] = mio_pad_attr_regwen_13_we; - reg_we_check[185] = mio_pad_attr_regwen_14_we; - reg_we_check[186] = mio_pad_attr_regwen_15_we; - reg_we_check[187] = mio_pad_attr_regwen_16_we; - reg_we_check[188] = mio_pad_attr_regwen_17_we; - reg_we_check[189] = mio_pad_attr_regwen_18_we; - reg_we_check[190] = mio_pad_attr_regwen_19_we; - reg_we_check[191] = mio_pad_attr_regwen_20_we; - reg_we_check[192] = mio_pad_attr_regwen_21_we; - reg_we_check[193] = mio_pad_attr_regwen_22_we; - reg_we_check[194] = mio_pad_attr_regwen_23_we; - reg_we_check[195] = mio_pad_attr_regwen_24_we; - reg_we_check[196] = mio_pad_attr_regwen_25_we; - reg_we_check[197] = mio_pad_attr_regwen_26_we; - reg_we_check[198] = mio_pad_attr_regwen_27_we; - reg_we_check[199] = mio_pad_attr_regwen_28_we; - reg_we_check[200] = mio_pad_attr_regwen_29_we; - reg_we_check[201] = mio_pad_attr_regwen_30_we; - reg_we_check[202] = mio_pad_attr_regwen_31_we; - reg_we_check[203] = mio_pad_attr_regwen_32_we; - reg_we_check[204] = mio_pad_attr_regwen_33_we; - reg_we_check[205] = mio_pad_attr_regwen_34_we; - reg_we_check[206] = mio_pad_attr_regwen_35_we; - reg_we_check[207] = mio_pad_attr_regwen_36_we; - reg_we_check[208] = mio_pad_attr_regwen_37_we; - reg_we_check[209] = mio_pad_attr_regwen_38_we; - reg_we_check[210] = mio_pad_attr_regwen_39_we; - reg_we_check[211] = mio_pad_attr_regwen_40_we; - reg_we_check[212] = mio_pad_attr_regwen_41_we; - reg_we_check[213] = mio_pad_attr_regwen_42_we; - reg_we_check[214] = mio_pad_attr_regwen_43_we; - reg_we_check[215] = mio_pad_attr_regwen_44_we; - reg_we_check[216] = mio_pad_attr_regwen_45_we; - reg_we_check[217] = mio_pad_attr_regwen_46_we; - reg_we_check[218] = mio_pad_attr_0_gated_we; - reg_we_check[219] = mio_pad_attr_1_gated_we; - reg_we_check[220] = mio_pad_attr_2_gated_we; - reg_we_check[221] = mio_pad_attr_3_gated_we; - reg_we_check[222] = mio_pad_attr_4_gated_we; - reg_we_check[223] = mio_pad_attr_5_gated_we; - reg_we_check[224] = mio_pad_attr_6_gated_we; - reg_we_check[225] = mio_pad_attr_7_gated_we; - reg_we_check[226] = mio_pad_attr_8_gated_we; - reg_we_check[227] = mio_pad_attr_9_gated_we; - reg_we_check[228] = mio_pad_attr_10_gated_we; - reg_we_check[229] = mio_pad_attr_11_gated_we; - reg_we_check[230] = mio_pad_attr_12_gated_we; - reg_we_check[231] = mio_pad_attr_13_gated_we; - reg_we_check[232] = mio_pad_attr_14_gated_we; - reg_we_check[233] = mio_pad_attr_15_gated_we; - reg_we_check[234] = mio_pad_attr_16_gated_we; - reg_we_check[235] = mio_pad_attr_17_gated_we; - reg_we_check[236] = mio_pad_attr_18_gated_we; - reg_we_check[237] = mio_pad_attr_19_gated_we; - reg_we_check[238] = mio_pad_attr_20_gated_we; - reg_we_check[239] = mio_pad_attr_21_gated_we; - reg_we_check[240] = mio_pad_attr_22_gated_we; - reg_we_check[241] = mio_pad_attr_23_gated_we; - reg_we_check[242] = mio_pad_attr_24_gated_we; - reg_we_check[243] = mio_pad_attr_25_gated_we; - reg_we_check[244] = mio_pad_attr_26_gated_we; - reg_we_check[245] = mio_pad_attr_27_gated_we; - reg_we_check[246] = mio_pad_attr_28_gated_we; - reg_we_check[247] = mio_pad_attr_29_gated_we; - reg_we_check[248] = mio_pad_attr_30_gated_we; - reg_we_check[249] = mio_pad_attr_31_gated_we; - reg_we_check[250] = mio_pad_attr_32_gated_we; - reg_we_check[251] = mio_pad_attr_33_gated_we; - reg_we_check[252] = mio_pad_attr_34_gated_we; - reg_we_check[253] = mio_pad_attr_35_gated_we; - reg_we_check[254] = mio_pad_attr_36_gated_we; - reg_we_check[255] = mio_pad_attr_37_gated_we; - reg_we_check[256] = mio_pad_attr_38_gated_we; - reg_we_check[257] = mio_pad_attr_39_gated_we; - reg_we_check[258] = mio_pad_attr_40_gated_we; - reg_we_check[259] = mio_pad_attr_41_gated_we; - reg_we_check[260] = mio_pad_attr_42_gated_we; - reg_we_check[261] = mio_pad_attr_43_gated_we; - reg_we_check[262] = mio_pad_attr_44_gated_we; - reg_we_check[263] = mio_pad_attr_45_gated_we; - reg_we_check[264] = mio_pad_attr_46_gated_we; - reg_we_check[265] = dio_pad_attr_regwen_0_we; - reg_we_check[266] = dio_pad_attr_regwen_1_we; - reg_we_check[267] = dio_pad_attr_regwen_2_we; - reg_we_check[268] = dio_pad_attr_regwen_3_we; - reg_we_check[269] = dio_pad_attr_regwen_4_we; - reg_we_check[270] = dio_pad_attr_regwen_5_we; - reg_we_check[271] = dio_pad_attr_regwen_6_we; - reg_we_check[272] = dio_pad_attr_regwen_7_we; - reg_we_check[273] = dio_pad_attr_regwen_8_we; - reg_we_check[274] = dio_pad_attr_regwen_9_we; - reg_we_check[275] = dio_pad_attr_regwen_10_we; - reg_we_check[276] = dio_pad_attr_regwen_11_we; - reg_we_check[277] = dio_pad_attr_regwen_12_we; - reg_we_check[278] = dio_pad_attr_regwen_13_we; - reg_we_check[279] = dio_pad_attr_0_gated_we; - reg_we_check[280] = dio_pad_attr_1_gated_we; - reg_we_check[281] = dio_pad_attr_2_gated_we; - reg_we_check[282] = dio_pad_attr_3_gated_we; - reg_we_check[283] = dio_pad_attr_4_gated_we; - reg_we_check[284] = dio_pad_attr_5_gated_we; - reg_we_check[285] = dio_pad_attr_6_gated_we; - reg_we_check[286] = dio_pad_attr_7_gated_we; - reg_we_check[287] = dio_pad_attr_8_gated_we; - reg_we_check[288] = dio_pad_attr_9_gated_we; - reg_we_check[289] = dio_pad_attr_10_gated_we; - reg_we_check[290] = dio_pad_attr_11_gated_we; - reg_we_check[291] = dio_pad_attr_12_gated_we; - reg_we_check[292] = dio_pad_attr_13_gated_we; - reg_we_check[293] = mio_pad_sleep_status_0_we; - reg_we_check[294] = mio_pad_sleep_status_1_we; - reg_we_check[295] = mio_pad_sleep_regwen_0_we; - reg_we_check[296] = mio_pad_sleep_regwen_1_we; - reg_we_check[297] = mio_pad_sleep_regwen_2_we; - reg_we_check[298] = mio_pad_sleep_regwen_3_we; - reg_we_check[299] = mio_pad_sleep_regwen_4_we; - reg_we_check[300] = mio_pad_sleep_regwen_5_we; - reg_we_check[301] = mio_pad_sleep_regwen_6_we; - reg_we_check[302] = mio_pad_sleep_regwen_7_we; - reg_we_check[303] = mio_pad_sleep_regwen_8_we; - reg_we_check[304] = mio_pad_sleep_regwen_9_we; - reg_we_check[305] = mio_pad_sleep_regwen_10_we; - reg_we_check[306] = mio_pad_sleep_regwen_11_we; - reg_we_check[307] = mio_pad_sleep_regwen_12_we; - reg_we_check[308] = mio_pad_sleep_regwen_13_we; - reg_we_check[309] = mio_pad_sleep_regwen_14_we; - reg_we_check[310] = mio_pad_sleep_regwen_15_we; - reg_we_check[311] = mio_pad_sleep_regwen_16_we; - reg_we_check[312] = mio_pad_sleep_regwen_17_we; - reg_we_check[313] = mio_pad_sleep_regwen_18_we; - reg_we_check[314] = mio_pad_sleep_regwen_19_we; - reg_we_check[315] = mio_pad_sleep_regwen_20_we; - reg_we_check[316] = mio_pad_sleep_regwen_21_we; - reg_we_check[317] = mio_pad_sleep_regwen_22_we; - reg_we_check[318] = mio_pad_sleep_regwen_23_we; - reg_we_check[319] = mio_pad_sleep_regwen_24_we; - reg_we_check[320] = mio_pad_sleep_regwen_25_we; - reg_we_check[321] = mio_pad_sleep_regwen_26_we; - reg_we_check[322] = mio_pad_sleep_regwen_27_we; - reg_we_check[323] = mio_pad_sleep_regwen_28_we; - reg_we_check[324] = mio_pad_sleep_regwen_29_we; - reg_we_check[325] = mio_pad_sleep_regwen_30_we; - reg_we_check[326] = mio_pad_sleep_regwen_31_we; - reg_we_check[327] = mio_pad_sleep_regwen_32_we; - reg_we_check[328] = mio_pad_sleep_regwen_33_we; - reg_we_check[329] = mio_pad_sleep_regwen_34_we; - reg_we_check[330] = mio_pad_sleep_regwen_35_we; - reg_we_check[331] = mio_pad_sleep_regwen_36_we; - reg_we_check[332] = mio_pad_sleep_regwen_37_we; - reg_we_check[333] = mio_pad_sleep_regwen_38_we; - reg_we_check[334] = mio_pad_sleep_regwen_39_we; - reg_we_check[335] = mio_pad_sleep_regwen_40_we; - reg_we_check[336] = mio_pad_sleep_regwen_41_we; - reg_we_check[337] = mio_pad_sleep_regwen_42_we; - reg_we_check[338] = mio_pad_sleep_regwen_43_we; - reg_we_check[339] = mio_pad_sleep_regwen_44_we; - reg_we_check[340] = mio_pad_sleep_regwen_45_we; - reg_we_check[341] = mio_pad_sleep_regwen_46_we; - reg_we_check[342] = mio_pad_sleep_en_0_gated_we; - reg_we_check[343] = mio_pad_sleep_en_1_gated_we; - reg_we_check[344] = mio_pad_sleep_en_2_gated_we; - reg_we_check[345] = mio_pad_sleep_en_3_gated_we; - reg_we_check[346] = mio_pad_sleep_en_4_gated_we; - reg_we_check[347] = mio_pad_sleep_en_5_gated_we; - reg_we_check[348] = mio_pad_sleep_en_6_gated_we; - reg_we_check[349] = mio_pad_sleep_en_7_gated_we; - reg_we_check[350] = mio_pad_sleep_en_8_gated_we; - reg_we_check[351] = mio_pad_sleep_en_9_gated_we; - reg_we_check[352] = mio_pad_sleep_en_10_gated_we; - reg_we_check[353] = mio_pad_sleep_en_11_gated_we; - reg_we_check[354] = mio_pad_sleep_en_12_gated_we; - reg_we_check[355] = mio_pad_sleep_en_13_gated_we; - reg_we_check[356] = mio_pad_sleep_en_14_gated_we; - reg_we_check[357] = mio_pad_sleep_en_15_gated_we; - reg_we_check[358] = mio_pad_sleep_en_16_gated_we; - reg_we_check[359] = mio_pad_sleep_en_17_gated_we; - reg_we_check[360] = mio_pad_sleep_en_18_gated_we; - reg_we_check[361] = mio_pad_sleep_en_19_gated_we; - reg_we_check[362] = mio_pad_sleep_en_20_gated_we; - reg_we_check[363] = mio_pad_sleep_en_21_gated_we; - reg_we_check[364] = mio_pad_sleep_en_22_gated_we; - reg_we_check[365] = mio_pad_sleep_en_23_gated_we; - reg_we_check[366] = mio_pad_sleep_en_24_gated_we; - reg_we_check[367] = mio_pad_sleep_en_25_gated_we; - reg_we_check[368] = mio_pad_sleep_en_26_gated_we; - reg_we_check[369] = mio_pad_sleep_en_27_gated_we; - reg_we_check[370] = mio_pad_sleep_en_28_gated_we; - reg_we_check[371] = mio_pad_sleep_en_29_gated_we; - reg_we_check[372] = mio_pad_sleep_en_30_gated_we; - reg_we_check[373] = mio_pad_sleep_en_31_gated_we; - reg_we_check[374] = mio_pad_sleep_en_32_gated_we; - reg_we_check[375] = mio_pad_sleep_en_33_gated_we; - reg_we_check[376] = mio_pad_sleep_en_34_gated_we; - reg_we_check[377] = mio_pad_sleep_en_35_gated_we; - reg_we_check[378] = mio_pad_sleep_en_36_gated_we; - reg_we_check[379] = mio_pad_sleep_en_37_gated_we; - reg_we_check[380] = mio_pad_sleep_en_38_gated_we; - reg_we_check[381] = mio_pad_sleep_en_39_gated_we; - reg_we_check[382] = mio_pad_sleep_en_40_gated_we; - reg_we_check[383] = mio_pad_sleep_en_41_gated_we; - reg_we_check[384] = mio_pad_sleep_en_42_gated_we; - reg_we_check[385] = mio_pad_sleep_en_43_gated_we; - reg_we_check[386] = mio_pad_sleep_en_44_gated_we; - reg_we_check[387] = mio_pad_sleep_en_45_gated_we; - reg_we_check[388] = mio_pad_sleep_en_46_gated_we; - reg_we_check[389] = mio_pad_sleep_mode_0_gated_we; - reg_we_check[390] = mio_pad_sleep_mode_1_gated_we; - reg_we_check[391] = mio_pad_sleep_mode_2_gated_we; - reg_we_check[392] = mio_pad_sleep_mode_3_gated_we; - reg_we_check[393] = mio_pad_sleep_mode_4_gated_we; - reg_we_check[394] = mio_pad_sleep_mode_5_gated_we; - reg_we_check[395] = mio_pad_sleep_mode_6_gated_we; - reg_we_check[396] = mio_pad_sleep_mode_7_gated_we; - reg_we_check[397] = mio_pad_sleep_mode_8_gated_we; - reg_we_check[398] = mio_pad_sleep_mode_9_gated_we; - reg_we_check[399] = mio_pad_sleep_mode_10_gated_we; - reg_we_check[400] = mio_pad_sleep_mode_11_gated_we; - reg_we_check[401] = mio_pad_sleep_mode_12_gated_we; - reg_we_check[402] = mio_pad_sleep_mode_13_gated_we; - reg_we_check[403] = mio_pad_sleep_mode_14_gated_we; - reg_we_check[404] = mio_pad_sleep_mode_15_gated_we; - reg_we_check[405] = mio_pad_sleep_mode_16_gated_we; - reg_we_check[406] = mio_pad_sleep_mode_17_gated_we; - reg_we_check[407] = mio_pad_sleep_mode_18_gated_we; - reg_we_check[408] = mio_pad_sleep_mode_19_gated_we; - reg_we_check[409] = mio_pad_sleep_mode_20_gated_we; - reg_we_check[410] = mio_pad_sleep_mode_21_gated_we; - reg_we_check[411] = mio_pad_sleep_mode_22_gated_we; - reg_we_check[412] = mio_pad_sleep_mode_23_gated_we; - reg_we_check[413] = mio_pad_sleep_mode_24_gated_we; - reg_we_check[414] = mio_pad_sleep_mode_25_gated_we; - reg_we_check[415] = mio_pad_sleep_mode_26_gated_we; - reg_we_check[416] = mio_pad_sleep_mode_27_gated_we; - reg_we_check[417] = mio_pad_sleep_mode_28_gated_we; - reg_we_check[418] = mio_pad_sleep_mode_29_gated_we; - reg_we_check[419] = mio_pad_sleep_mode_30_gated_we; - reg_we_check[420] = mio_pad_sleep_mode_31_gated_we; - reg_we_check[421] = mio_pad_sleep_mode_32_gated_we; - reg_we_check[422] = mio_pad_sleep_mode_33_gated_we; - reg_we_check[423] = mio_pad_sleep_mode_34_gated_we; - reg_we_check[424] = mio_pad_sleep_mode_35_gated_we; - reg_we_check[425] = mio_pad_sleep_mode_36_gated_we; - reg_we_check[426] = mio_pad_sleep_mode_37_gated_we; - reg_we_check[427] = mio_pad_sleep_mode_38_gated_we; - reg_we_check[428] = mio_pad_sleep_mode_39_gated_we; - reg_we_check[429] = mio_pad_sleep_mode_40_gated_we; - reg_we_check[430] = mio_pad_sleep_mode_41_gated_we; - reg_we_check[431] = mio_pad_sleep_mode_42_gated_we; - reg_we_check[432] = mio_pad_sleep_mode_43_gated_we; - reg_we_check[433] = mio_pad_sleep_mode_44_gated_we; - reg_we_check[434] = mio_pad_sleep_mode_45_gated_we; - reg_we_check[435] = mio_pad_sleep_mode_46_gated_we; - reg_we_check[436] = dio_pad_sleep_status_we; - reg_we_check[437] = dio_pad_sleep_regwen_0_we; - reg_we_check[438] = dio_pad_sleep_regwen_1_we; - reg_we_check[439] = dio_pad_sleep_regwen_2_we; - reg_we_check[440] = dio_pad_sleep_regwen_3_we; - reg_we_check[441] = dio_pad_sleep_regwen_4_we; - reg_we_check[442] = dio_pad_sleep_regwen_5_we; - reg_we_check[443] = dio_pad_sleep_regwen_6_we; - reg_we_check[444] = dio_pad_sleep_regwen_7_we; - reg_we_check[445] = dio_pad_sleep_regwen_8_we; - reg_we_check[446] = dio_pad_sleep_regwen_9_we; - reg_we_check[447] = dio_pad_sleep_regwen_10_we; - reg_we_check[448] = dio_pad_sleep_regwen_11_we; - reg_we_check[449] = dio_pad_sleep_regwen_12_we; - reg_we_check[450] = dio_pad_sleep_regwen_13_we; - reg_we_check[451] = dio_pad_sleep_en_0_gated_we; - reg_we_check[452] = dio_pad_sleep_en_1_gated_we; - reg_we_check[453] = dio_pad_sleep_en_2_gated_we; - reg_we_check[454] = dio_pad_sleep_en_3_gated_we; - reg_we_check[455] = dio_pad_sleep_en_4_gated_we; - reg_we_check[456] = dio_pad_sleep_en_5_gated_we; - reg_we_check[457] = dio_pad_sleep_en_6_gated_we; - reg_we_check[458] = dio_pad_sleep_en_7_gated_we; - reg_we_check[459] = dio_pad_sleep_en_8_gated_we; - reg_we_check[460] = dio_pad_sleep_en_9_gated_we; - reg_we_check[461] = dio_pad_sleep_en_10_gated_we; - reg_we_check[462] = dio_pad_sleep_en_11_gated_we; - reg_we_check[463] = dio_pad_sleep_en_12_gated_we; - reg_we_check[464] = dio_pad_sleep_en_13_gated_we; - reg_we_check[465] = dio_pad_sleep_mode_0_gated_we; - reg_we_check[466] = dio_pad_sleep_mode_1_gated_we; - reg_we_check[467] = dio_pad_sleep_mode_2_gated_we; - reg_we_check[468] = dio_pad_sleep_mode_3_gated_we; - reg_we_check[469] = dio_pad_sleep_mode_4_gated_we; - reg_we_check[470] = dio_pad_sleep_mode_5_gated_we; - reg_we_check[471] = dio_pad_sleep_mode_6_gated_we; - reg_we_check[472] = dio_pad_sleep_mode_7_gated_we; - reg_we_check[473] = dio_pad_sleep_mode_8_gated_we; - reg_we_check[474] = dio_pad_sleep_mode_9_gated_we; - reg_we_check[475] = dio_pad_sleep_mode_10_gated_we; - reg_we_check[476] = dio_pad_sleep_mode_11_gated_we; - reg_we_check[477] = dio_pad_sleep_mode_12_gated_we; - reg_we_check[478] = dio_pad_sleep_mode_13_gated_we; - reg_we_check[479] = wkup_detector_regwen_0_we; - reg_we_check[480] = wkup_detector_regwen_1_we; - reg_we_check[481] = wkup_detector_regwen_2_we; - reg_we_check[482] = wkup_detector_regwen_3_we; - reg_we_check[483] = wkup_detector_regwen_4_we; - reg_we_check[484] = wkup_detector_regwen_5_we; - reg_we_check[485] = wkup_detector_regwen_6_we; - reg_we_check[486] = wkup_detector_regwen_7_we; - reg_we_check[487] = wkup_detector_en_0_we; - reg_we_check[488] = wkup_detector_en_1_we; - reg_we_check[489] = wkup_detector_en_2_we; - reg_we_check[490] = wkup_detector_en_3_we; - reg_we_check[491] = wkup_detector_en_4_we; - reg_we_check[492] = wkup_detector_en_5_we; - reg_we_check[493] = wkup_detector_en_6_we; - reg_we_check[494] = wkup_detector_en_7_we; - reg_we_check[495] = wkup_detector_0_we; - reg_we_check[496] = wkup_detector_1_we; - reg_we_check[497] = wkup_detector_2_we; - reg_we_check[498] = wkup_detector_3_we; - reg_we_check[499] = wkup_detector_4_we; - reg_we_check[500] = wkup_detector_5_we; - reg_we_check[501] = wkup_detector_6_we; - reg_we_check[502] = wkup_detector_7_we; - reg_we_check[503] = wkup_detector_cnt_th_0_we; - reg_we_check[504] = wkup_detector_cnt_th_1_we; - reg_we_check[505] = wkup_detector_cnt_th_2_we; - reg_we_check[506] = wkup_detector_cnt_th_3_we; - reg_we_check[507] = wkup_detector_cnt_th_4_we; - reg_we_check[508] = wkup_detector_cnt_th_5_we; - reg_we_check[509] = wkup_detector_cnt_th_6_we; - reg_we_check[510] = wkup_detector_cnt_th_7_we; - reg_we_check[511] = wkup_detector_padsel_0_gated_we; - reg_we_check[512] = wkup_detector_padsel_1_gated_we; - reg_we_check[513] = wkup_detector_padsel_2_gated_we; - reg_we_check[514] = wkup_detector_padsel_3_gated_we; - reg_we_check[515] = wkup_detector_padsel_4_gated_we; - reg_we_check[516] = wkup_detector_padsel_5_gated_we; - reg_we_check[517] = wkup_detector_padsel_6_gated_we; - reg_we_check[518] = wkup_detector_padsel_7_gated_we; - reg_we_check[519] = wkup_cause_we; + reg_we_check[36] = mio_periph_insel_0_gated_we; + reg_we_check[37] = mio_periph_insel_1_gated_we; + reg_we_check[38] = mio_periph_insel_2_gated_we; + reg_we_check[39] = mio_periph_insel_3_gated_we; + reg_we_check[40] = mio_periph_insel_4_gated_we; + reg_we_check[41] = mio_periph_insel_5_gated_we; + reg_we_check[42] = mio_periph_insel_6_gated_we; + reg_we_check[43] = mio_periph_insel_7_gated_we; + reg_we_check[44] = mio_periph_insel_8_gated_we; + reg_we_check[45] = mio_periph_insel_9_gated_we; + reg_we_check[46] = mio_periph_insel_10_gated_we; + reg_we_check[47] = mio_periph_insel_11_gated_we; + reg_we_check[48] = mio_periph_insel_12_gated_we; + reg_we_check[49] = mio_periph_insel_13_gated_we; + reg_we_check[50] = mio_periph_insel_14_gated_we; + reg_we_check[51] = mio_periph_insel_15_gated_we; + reg_we_check[52] = mio_periph_insel_16_gated_we; + reg_we_check[53] = mio_periph_insel_17_gated_we; + reg_we_check[54] = mio_periph_insel_18_gated_we; + reg_we_check[55] = mio_periph_insel_19_gated_we; + reg_we_check[56] = mio_periph_insel_20_gated_we; + reg_we_check[57] = mio_periph_insel_21_gated_we; + reg_we_check[58] = mio_periph_insel_22_gated_we; + reg_we_check[59] = mio_periph_insel_23_gated_we; + reg_we_check[60] = mio_periph_insel_24_gated_we; + reg_we_check[61] = mio_periph_insel_25_gated_we; + reg_we_check[62] = mio_periph_insel_26_gated_we; + reg_we_check[63] = mio_periph_insel_27_gated_we; + reg_we_check[64] = mio_periph_insel_28_gated_we; + reg_we_check[65] = mio_periph_insel_29_gated_we; + reg_we_check[66] = mio_periph_insel_30_gated_we; + reg_we_check[67] = mio_periph_insel_31_gated_we; + reg_we_check[68] = mio_periph_insel_32_gated_we; + reg_we_check[69] = mio_periph_insel_33_gated_we; + reg_we_check[70] = mio_periph_insel_34_gated_we; + reg_we_check[71] = mio_outsel_regwen_0_we; + reg_we_check[72] = mio_outsel_regwen_1_we; + reg_we_check[73] = mio_outsel_regwen_2_we; + reg_we_check[74] = mio_outsel_regwen_3_we; + reg_we_check[75] = mio_outsel_regwen_4_we; + reg_we_check[76] = mio_outsel_regwen_5_we; + reg_we_check[77] = mio_outsel_regwen_6_we; + reg_we_check[78] = mio_outsel_regwen_7_we; + reg_we_check[79] = mio_outsel_regwen_8_we; + reg_we_check[80] = mio_outsel_regwen_9_we; + reg_we_check[81] = mio_outsel_regwen_10_we; + reg_we_check[82] = mio_outsel_regwen_11_we; + reg_we_check[83] = mio_outsel_regwen_12_we; + reg_we_check[84] = mio_outsel_regwen_13_we; + reg_we_check[85] = mio_outsel_regwen_14_we; + reg_we_check[86] = mio_outsel_regwen_15_we; + reg_we_check[87] = mio_outsel_regwen_16_we; + reg_we_check[88] = mio_outsel_regwen_17_we; + reg_we_check[89] = mio_outsel_regwen_18_we; + reg_we_check[90] = mio_outsel_regwen_19_we; + reg_we_check[91] = mio_outsel_regwen_20_we; + reg_we_check[92] = mio_outsel_regwen_21_we; + reg_we_check[93] = mio_outsel_regwen_22_we; + reg_we_check[94] = mio_outsel_regwen_23_we; + reg_we_check[95] = mio_outsel_regwen_24_we; + reg_we_check[96] = mio_outsel_regwen_25_we; + reg_we_check[97] = mio_outsel_regwen_26_we; + reg_we_check[98] = mio_outsel_regwen_27_we; + reg_we_check[99] = mio_outsel_regwen_28_we; + reg_we_check[100] = mio_outsel_regwen_29_we; + reg_we_check[101] = mio_outsel_regwen_30_we; + reg_we_check[102] = mio_outsel_regwen_31_we; + reg_we_check[103] = mio_outsel_regwen_32_we; + reg_we_check[104] = mio_outsel_regwen_33_we; + reg_we_check[105] = mio_outsel_regwen_34_we; + reg_we_check[106] = mio_outsel_regwen_35_we; + reg_we_check[107] = mio_outsel_regwen_36_we; + reg_we_check[108] = mio_outsel_regwen_37_we; + reg_we_check[109] = mio_outsel_regwen_38_we; + reg_we_check[110] = mio_outsel_regwen_39_we; + reg_we_check[111] = mio_outsel_regwen_40_we; + reg_we_check[112] = mio_outsel_regwen_41_we; + reg_we_check[113] = mio_outsel_regwen_42_we; + reg_we_check[114] = mio_outsel_regwen_43_we; + reg_we_check[115] = mio_outsel_regwen_44_we; + reg_we_check[116] = mio_outsel_regwen_45_we; + reg_we_check[117] = mio_outsel_regwen_46_we; + reg_we_check[118] = mio_outsel_0_gated_we; + reg_we_check[119] = mio_outsel_1_gated_we; + reg_we_check[120] = mio_outsel_2_gated_we; + reg_we_check[121] = mio_outsel_3_gated_we; + reg_we_check[122] = mio_outsel_4_gated_we; + reg_we_check[123] = mio_outsel_5_gated_we; + reg_we_check[124] = mio_outsel_6_gated_we; + reg_we_check[125] = mio_outsel_7_gated_we; + reg_we_check[126] = mio_outsel_8_gated_we; + reg_we_check[127] = mio_outsel_9_gated_we; + reg_we_check[128] = mio_outsel_10_gated_we; + reg_we_check[129] = mio_outsel_11_gated_we; + reg_we_check[130] = mio_outsel_12_gated_we; + reg_we_check[131] = mio_outsel_13_gated_we; + reg_we_check[132] = mio_outsel_14_gated_we; + reg_we_check[133] = mio_outsel_15_gated_we; + reg_we_check[134] = mio_outsel_16_gated_we; + reg_we_check[135] = mio_outsel_17_gated_we; + reg_we_check[136] = mio_outsel_18_gated_we; + reg_we_check[137] = mio_outsel_19_gated_we; + reg_we_check[138] = mio_outsel_20_gated_we; + reg_we_check[139] = mio_outsel_21_gated_we; + reg_we_check[140] = mio_outsel_22_gated_we; + reg_we_check[141] = mio_outsel_23_gated_we; + reg_we_check[142] = mio_outsel_24_gated_we; + reg_we_check[143] = mio_outsel_25_gated_we; + reg_we_check[144] = mio_outsel_26_gated_we; + reg_we_check[145] = mio_outsel_27_gated_we; + reg_we_check[146] = mio_outsel_28_gated_we; + reg_we_check[147] = mio_outsel_29_gated_we; + reg_we_check[148] = mio_outsel_30_gated_we; + reg_we_check[149] = mio_outsel_31_gated_we; + reg_we_check[150] = mio_outsel_32_gated_we; + reg_we_check[151] = mio_outsel_33_gated_we; + reg_we_check[152] = mio_outsel_34_gated_we; + reg_we_check[153] = mio_outsel_35_gated_we; + reg_we_check[154] = mio_outsel_36_gated_we; + reg_we_check[155] = mio_outsel_37_gated_we; + reg_we_check[156] = mio_outsel_38_gated_we; + reg_we_check[157] = mio_outsel_39_gated_we; + reg_we_check[158] = mio_outsel_40_gated_we; + reg_we_check[159] = mio_outsel_41_gated_we; + reg_we_check[160] = mio_outsel_42_gated_we; + reg_we_check[161] = mio_outsel_43_gated_we; + reg_we_check[162] = mio_outsel_44_gated_we; + reg_we_check[163] = mio_outsel_45_gated_we; + reg_we_check[164] = mio_outsel_46_gated_we; + reg_we_check[165] = mio_pad_attr_regwen_0_we; + reg_we_check[166] = mio_pad_attr_regwen_1_we; + reg_we_check[167] = mio_pad_attr_regwen_2_we; + reg_we_check[168] = mio_pad_attr_regwen_3_we; + reg_we_check[169] = mio_pad_attr_regwen_4_we; + reg_we_check[170] = mio_pad_attr_regwen_5_we; + reg_we_check[171] = mio_pad_attr_regwen_6_we; + reg_we_check[172] = mio_pad_attr_regwen_7_we; + reg_we_check[173] = mio_pad_attr_regwen_8_we; + reg_we_check[174] = mio_pad_attr_regwen_9_we; + reg_we_check[175] = mio_pad_attr_regwen_10_we; + reg_we_check[176] = mio_pad_attr_regwen_11_we; + reg_we_check[177] = mio_pad_attr_regwen_12_we; + reg_we_check[178] = mio_pad_attr_regwen_13_we; + reg_we_check[179] = mio_pad_attr_regwen_14_we; + reg_we_check[180] = mio_pad_attr_regwen_15_we; + reg_we_check[181] = mio_pad_attr_regwen_16_we; + reg_we_check[182] = mio_pad_attr_regwen_17_we; + reg_we_check[183] = mio_pad_attr_regwen_18_we; + reg_we_check[184] = mio_pad_attr_regwen_19_we; + reg_we_check[185] = mio_pad_attr_regwen_20_we; + reg_we_check[186] = mio_pad_attr_regwen_21_we; + reg_we_check[187] = mio_pad_attr_regwen_22_we; + reg_we_check[188] = mio_pad_attr_regwen_23_we; + reg_we_check[189] = mio_pad_attr_regwen_24_we; + reg_we_check[190] = mio_pad_attr_regwen_25_we; + reg_we_check[191] = mio_pad_attr_regwen_26_we; + reg_we_check[192] = mio_pad_attr_regwen_27_we; + reg_we_check[193] = mio_pad_attr_regwen_28_we; + reg_we_check[194] = mio_pad_attr_regwen_29_we; + reg_we_check[195] = mio_pad_attr_regwen_30_we; + reg_we_check[196] = mio_pad_attr_regwen_31_we; + reg_we_check[197] = mio_pad_attr_regwen_32_we; + reg_we_check[198] = mio_pad_attr_regwen_33_we; + reg_we_check[199] = mio_pad_attr_regwen_34_we; + reg_we_check[200] = mio_pad_attr_regwen_35_we; + reg_we_check[201] = mio_pad_attr_regwen_36_we; + reg_we_check[202] = mio_pad_attr_regwen_37_we; + reg_we_check[203] = mio_pad_attr_regwen_38_we; + reg_we_check[204] = mio_pad_attr_regwen_39_we; + reg_we_check[205] = mio_pad_attr_regwen_40_we; + reg_we_check[206] = mio_pad_attr_regwen_41_we; + reg_we_check[207] = mio_pad_attr_regwen_42_we; + reg_we_check[208] = mio_pad_attr_regwen_43_we; + reg_we_check[209] = mio_pad_attr_regwen_44_we; + reg_we_check[210] = mio_pad_attr_regwen_45_we; + reg_we_check[211] = mio_pad_attr_regwen_46_we; + reg_we_check[212] = mio_pad_attr_0_gated_we; + reg_we_check[213] = mio_pad_attr_1_gated_we; + reg_we_check[214] = mio_pad_attr_2_gated_we; + reg_we_check[215] = mio_pad_attr_3_gated_we; + reg_we_check[216] = mio_pad_attr_4_gated_we; + reg_we_check[217] = mio_pad_attr_5_gated_we; + reg_we_check[218] = mio_pad_attr_6_gated_we; + reg_we_check[219] = mio_pad_attr_7_gated_we; + reg_we_check[220] = mio_pad_attr_8_gated_we; + reg_we_check[221] = mio_pad_attr_9_gated_we; + reg_we_check[222] = mio_pad_attr_10_gated_we; + reg_we_check[223] = mio_pad_attr_11_gated_we; + reg_we_check[224] = mio_pad_attr_12_gated_we; + reg_we_check[225] = mio_pad_attr_13_gated_we; + reg_we_check[226] = mio_pad_attr_14_gated_we; + reg_we_check[227] = mio_pad_attr_15_gated_we; + reg_we_check[228] = mio_pad_attr_16_gated_we; + reg_we_check[229] = mio_pad_attr_17_gated_we; + reg_we_check[230] = mio_pad_attr_18_gated_we; + reg_we_check[231] = mio_pad_attr_19_gated_we; + reg_we_check[232] = mio_pad_attr_20_gated_we; + reg_we_check[233] = mio_pad_attr_21_gated_we; + reg_we_check[234] = mio_pad_attr_22_gated_we; + reg_we_check[235] = mio_pad_attr_23_gated_we; + reg_we_check[236] = mio_pad_attr_24_gated_we; + reg_we_check[237] = mio_pad_attr_25_gated_we; + reg_we_check[238] = mio_pad_attr_26_gated_we; + reg_we_check[239] = mio_pad_attr_27_gated_we; + reg_we_check[240] = mio_pad_attr_28_gated_we; + reg_we_check[241] = mio_pad_attr_29_gated_we; + reg_we_check[242] = mio_pad_attr_30_gated_we; + reg_we_check[243] = mio_pad_attr_31_gated_we; + reg_we_check[244] = mio_pad_attr_32_gated_we; + reg_we_check[245] = mio_pad_attr_33_gated_we; + reg_we_check[246] = mio_pad_attr_34_gated_we; + reg_we_check[247] = mio_pad_attr_35_gated_we; + reg_we_check[248] = mio_pad_attr_36_gated_we; + reg_we_check[249] = mio_pad_attr_37_gated_we; + reg_we_check[250] = mio_pad_attr_38_gated_we; + reg_we_check[251] = mio_pad_attr_39_gated_we; + reg_we_check[252] = mio_pad_attr_40_gated_we; + reg_we_check[253] = mio_pad_attr_41_gated_we; + reg_we_check[254] = mio_pad_attr_42_gated_we; + reg_we_check[255] = mio_pad_attr_43_gated_we; + reg_we_check[256] = mio_pad_attr_44_gated_we; + reg_we_check[257] = mio_pad_attr_45_gated_we; + reg_we_check[258] = mio_pad_attr_46_gated_we; + reg_we_check[259] = dio_pad_attr_regwen_0_we; + reg_we_check[260] = dio_pad_attr_regwen_1_we; + reg_we_check[261] = dio_pad_attr_regwen_2_we; + reg_we_check[262] = dio_pad_attr_regwen_3_we; + reg_we_check[263] = dio_pad_attr_regwen_4_we; + reg_we_check[264] = dio_pad_attr_regwen_5_we; + reg_we_check[265] = dio_pad_attr_regwen_6_we; + reg_we_check[266] = dio_pad_attr_regwen_7_we; + reg_we_check[267] = dio_pad_attr_regwen_8_we; + reg_we_check[268] = dio_pad_attr_regwen_9_we; + reg_we_check[269] = dio_pad_attr_regwen_10_we; + reg_we_check[270] = dio_pad_attr_regwen_11_we; + reg_we_check[271] = dio_pad_attr_regwen_12_we; + reg_we_check[272] = dio_pad_attr_regwen_13_we; + reg_we_check[273] = dio_pad_attr_0_gated_we; + reg_we_check[274] = dio_pad_attr_1_gated_we; + reg_we_check[275] = dio_pad_attr_2_gated_we; + reg_we_check[276] = dio_pad_attr_3_gated_we; + reg_we_check[277] = dio_pad_attr_4_gated_we; + reg_we_check[278] = dio_pad_attr_5_gated_we; + reg_we_check[279] = dio_pad_attr_6_gated_we; + reg_we_check[280] = dio_pad_attr_7_gated_we; + reg_we_check[281] = dio_pad_attr_8_gated_we; + reg_we_check[282] = dio_pad_attr_9_gated_we; + reg_we_check[283] = dio_pad_attr_10_gated_we; + reg_we_check[284] = dio_pad_attr_11_gated_we; + reg_we_check[285] = dio_pad_attr_12_gated_we; + reg_we_check[286] = dio_pad_attr_13_gated_we; + reg_we_check[287] = mio_pad_sleep_status_0_we; + reg_we_check[288] = mio_pad_sleep_status_1_we; + reg_we_check[289] = mio_pad_sleep_regwen_0_we; + reg_we_check[290] = mio_pad_sleep_regwen_1_we; + reg_we_check[291] = mio_pad_sleep_regwen_2_we; + reg_we_check[292] = mio_pad_sleep_regwen_3_we; + reg_we_check[293] = mio_pad_sleep_regwen_4_we; + reg_we_check[294] = mio_pad_sleep_regwen_5_we; + reg_we_check[295] = mio_pad_sleep_regwen_6_we; + reg_we_check[296] = mio_pad_sleep_regwen_7_we; + reg_we_check[297] = mio_pad_sleep_regwen_8_we; + reg_we_check[298] = mio_pad_sleep_regwen_9_we; + reg_we_check[299] = mio_pad_sleep_regwen_10_we; + reg_we_check[300] = mio_pad_sleep_regwen_11_we; + reg_we_check[301] = mio_pad_sleep_regwen_12_we; + reg_we_check[302] = mio_pad_sleep_regwen_13_we; + reg_we_check[303] = mio_pad_sleep_regwen_14_we; + reg_we_check[304] = mio_pad_sleep_regwen_15_we; + reg_we_check[305] = mio_pad_sleep_regwen_16_we; + reg_we_check[306] = mio_pad_sleep_regwen_17_we; + reg_we_check[307] = mio_pad_sleep_regwen_18_we; + reg_we_check[308] = mio_pad_sleep_regwen_19_we; + reg_we_check[309] = mio_pad_sleep_regwen_20_we; + reg_we_check[310] = mio_pad_sleep_regwen_21_we; + reg_we_check[311] = mio_pad_sleep_regwen_22_we; + reg_we_check[312] = mio_pad_sleep_regwen_23_we; + reg_we_check[313] = mio_pad_sleep_regwen_24_we; + reg_we_check[314] = mio_pad_sleep_regwen_25_we; + reg_we_check[315] = mio_pad_sleep_regwen_26_we; + reg_we_check[316] = mio_pad_sleep_regwen_27_we; + reg_we_check[317] = mio_pad_sleep_regwen_28_we; + reg_we_check[318] = mio_pad_sleep_regwen_29_we; + reg_we_check[319] = mio_pad_sleep_regwen_30_we; + reg_we_check[320] = mio_pad_sleep_regwen_31_we; + reg_we_check[321] = mio_pad_sleep_regwen_32_we; + reg_we_check[322] = mio_pad_sleep_regwen_33_we; + reg_we_check[323] = mio_pad_sleep_regwen_34_we; + reg_we_check[324] = mio_pad_sleep_regwen_35_we; + reg_we_check[325] = mio_pad_sleep_regwen_36_we; + reg_we_check[326] = mio_pad_sleep_regwen_37_we; + reg_we_check[327] = mio_pad_sleep_regwen_38_we; + reg_we_check[328] = mio_pad_sleep_regwen_39_we; + reg_we_check[329] = mio_pad_sleep_regwen_40_we; + reg_we_check[330] = mio_pad_sleep_regwen_41_we; + reg_we_check[331] = mio_pad_sleep_regwen_42_we; + reg_we_check[332] = mio_pad_sleep_regwen_43_we; + reg_we_check[333] = mio_pad_sleep_regwen_44_we; + reg_we_check[334] = mio_pad_sleep_regwen_45_we; + reg_we_check[335] = mio_pad_sleep_regwen_46_we; + reg_we_check[336] = mio_pad_sleep_en_0_gated_we; + reg_we_check[337] = mio_pad_sleep_en_1_gated_we; + reg_we_check[338] = mio_pad_sleep_en_2_gated_we; + reg_we_check[339] = mio_pad_sleep_en_3_gated_we; + reg_we_check[340] = mio_pad_sleep_en_4_gated_we; + reg_we_check[341] = mio_pad_sleep_en_5_gated_we; + reg_we_check[342] = mio_pad_sleep_en_6_gated_we; + reg_we_check[343] = mio_pad_sleep_en_7_gated_we; + reg_we_check[344] = mio_pad_sleep_en_8_gated_we; + reg_we_check[345] = mio_pad_sleep_en_9_gated_we; + reg_we_check[346] = mio_pad_sleep_en_10_gated_we; + reg_we_check[347] = mio_pad_sleep_en_11_gated_we; + reg_we_check[348] = mio_pad_sleep_en_12_gated_we; + reg_we_check[349] = mio_pad_sleep_en_13_gated_we; + reg_we_check[350] = mio_pad_sleep_en_14_gated_we; + reg_we_check[351] = mio_pad_sleep_en_15_gated_we; + reg_we_check[352] = mio_pad_sleep_en_16_gated_we; + reg_we_check[353] = mio_pad_sleep_en_17_gated_we; + reg_we_check[354] = mio_pad_sleep_en_18_gated_we; + reg_we_check[355] = mio_pad_sleep_en_19_gated_we; + reg_we_check[356] = mio_pad_sleep_en_20_gated_we; + reg_we_check[357] = mio_pad_sleep_en_21_gated_we; + reg_we_check[358] = mio_pad_sleep_en_22_gated_we; + reg_we_check[359] = mio_pad_sleep_en_23_gated_we; + reg_we_check[360] = mio_pad_sleep_en_24_gated_we; + reg_we_check[361] = mio_pad_sleep_en_25_gated_we; + reg_we_check[362] = mio_pad_sleep_en_26_gated_we; + reg_we_check[363] = mio_pad_sleep_en_27_gated_we; + reg_we_check[364] = mio_pad_sleep_en_28_gated_we; + reg_we_check[365] = mio_pad_sleep_en_29_gated_we; + reg_we_check[366] = mio_pad_sleep_en_30_gated_we; + reg_we_check[367] = mio_pad_sleep_en_31_gated_we; + reg_we_check[368] = mio_pad_sleep_en_32_gated_we; + reg_we_check[369] = mio_pad_sleep_en_33_gated_we; + reg_we_check[370] = mio_pad_sleep_en_34_gated_we; + reg_we_check[371] = mio_pad_sleep_en_35_gated_we; + reg_we_check[372] = mio_pad_sleep_en_36_gated_we; + reg_we_check[373] = mio_pad_sleep_en_37_gated_we; + reg_we_check[374] = mio_pad_sleep_en_38_gated_we; + reg_we_check[375] = mio_pad_sleep_en_39_gated_we; + reg_we_check[376] = mio_pad_sleep_en_40_gated_we; + reg_we_check[377] = mio_pad_sleep_en_41_gated_we; + reg_we_check[378] = mio_pad_sleep_en_42_gated_we; + reg_we_check[379] = mio_pad_sleep_en_43_gated_we; + reg_we_check[380] = mio_pad_sleep_en_44_gated_we; + reg_we_check[381] = mio_pad_sleep_en_45_gated_we; + reg_we_check[382] = mio_pad_sleep_en_46_gated_we; + reg_we_check[383] = mio_pad_sleep_mode_0_gated_we; + reg_we_check[384] = mio_pad_sleep_mode_1_gated_we; + reg_we_check[385] = mio_pad_sleep_mode_2_gated_we; + reg_we_check[386] = mio_pad_sleep_mode_3_gated_we; + reg_we_check[387] = mio_pad_sleep_mode_4_gated_we; + reg_we_check[388] = mio_pad_sleep_mode_5_gated_we; + reg_we_check[389] = mio_pad_sleep_mode_6_gated_we; + reg_we_check[390] = mio_pad_sleep_mode_7_gated_we; + reg_we_check[391] = mio_pad_sleep_mode_8_gated_we; + reg_we_check[392] = mio_pad_sleep_mode_9_gated_we; + reg_we_check[393] = mio_pad_sleep_mode_10_gated_we; + reg_we_check[394] = mio_pad_sleep_mode_11_gated_we; + reg_we_check[395] = mio_pad_sleep_mode_12_gated_we; + reg_we_check[396] = mio_pad_sleep_mode_13_gated_we; + reg_we_check[397] = mio_pad_sleep_mode_14_gated_we; + reg_we_check[398] = mio_pad_sleep_mode_15_gated_we; + reg_we_check[399] = mio_pad_sleep_mode_16_gated_we; + reg_we_check[400] = mio_pad_sleep_mode_17_gated_we; + reg_we_check[401] = mio_pad_sleep_mode_18_gated_we; + reg_we_check[402] = mio_pad_sleep_mode_19_gated_we; + reg_we_check[403] = mio_pad_sleep_mode_20_gated_we; + reg_we_check[404] = mio_pad_sleep_mode_21_gated_we; + reg_we_check[405] = mio_pad_sleep_mode_22_gated_we; + reg_we_check[406] = mio_pad_sleep_mode_23_gated_we; + reg_we_check[407] = mio_pad_sleep_mode_24_gated_we; + reg_we_check[408] = mio_pad_sleep_mode_25_gated_we; + reg_we_check[409] = mio_pad_sleep_mode_26_gated_we; + reg_we_check[410] = mio_pad_sleep_mode_27_gated_we; + reg_we_check[411] = mio_pad_sleep_mode_28_gated_we; + reg_we_check[412] = mio_pad_sleep_mode_29_gated_we; + reg_we_check[413] = mio_pad_sleep_mode_30_gated_we; + reg_we_check[414] = mio_pad_sleep_mode_31_gated_we; + reg_we_check[415] = mio_pad_sleep_mode_32_gated_we; + reg_we_check[416] = mio_pad_sleep_mode_33_gated_we; + reg_we_check[417] = mio_pad_sleep_mode_34_gated_we; + reg_we_check[418] = mio_pad_sleep_mode_35_gated_we; + reg_we_check[419] = mio_pad_sleep_mode_36_gated_we; + reg_we_check[420] = mio_pad_sleep_mode_37_gated_we; + reg_we_check[421] = mio_pad_sleep_mode_38_gated_we; + reg_we_check[422] = mio_pad_sleep_mode_39_gated_we; + reg_we_check[423] = mio_pad_sleep_mode_40_gated_we; + reg_we_check[424] = mio_pad_sleep_mode_41_gated_we; + reg_we_check[425] = mio_pad_sleep_mode_42_gated_we; + reg_we_check[426] = mio_pad_sleep_mode_43_gated_we; + reg_we_check[427] = mio_pad_sleep_mode_44_gated_we; + reg_we_check[428] = mio_pad_sleep_mode_45_gated_we; + reg_we_check[429] = mio_pad_sleep_mode_46_gated_we; + reg_we_check[430] = dio_pad_sleep_status_we; + reg_we_check[431] = dio_pad_sleep_regwen_0_we; + reg_we_check[432] = dio_pad_sleep_regwen_1_we; + reg_we_check[433] = dio_pad_sleep_regwen_2_we; + reg_we_check[434] = dio_pad_sleep_regwen_3_we; + reg_we_check[435] = dio_pad_sleep_regwen_4_we; + reg_we_check[436] = dio_pad_sleep_regwen_5_we; + reg_we_check[437] = dio_pad_sleep_regwen_6_we; + reg_we_check[438] = dio_pad_sleep_regwen_7_we; + reg_we_check[439] = dio_pad_sleep_regwen_8_we; + reg_we_check[440] = dio_pad_sleep_regwen_9_we; + reg_we_check[441] = dio_pad_sleep_regwen_10_we; + reg_we_check[442] = dio_pad_sleep_regwen_11_we; + reg_we_check[443] = dio_pad_sleep_regwen_12_we; + reg_we_check[444] = dio_pad_sleep_regwen_13_we; + reg_we_check[445] = dio_pad_sleep_en_0_gated_we; + reg_we_check[446] = dio_pad_sleep_en_1_gated_we; + reg_we_check[447] = dio_pad_sleep_en_2_gated_we; + reg_we_check[448] = dio_pad_sleep_en_3_gated_we; + reg_we_check[449] = dio_pad_sleep_en_4_gated_we; + reg_we_check[450] = dio_pad_sleep_en_5_gated_we; + reg_we_check[451] = dio_pad_sleep_en_6_gated_we; + reg_we_check[452] = dio_pad_sleep_en_7_gated_we; + reg_we_check[453] = dio_pad_sleep_en_8_gated_we; + reg_we_check[454] = dio_pad_sleep_en_9_gated_we; + reg_we_check[455] = dio_pad_sleep_en_10_gated_we; + reg_we_check[456] = dio_pad_sleep_en_11_gated_we; + reg_we_check[457] = dio_pad_sleep_en_12_gated_we; + reg_we_check[458] = dio_pad_sleep_en_13_gated_we; + reg_we_check[459] = dio_pad_sleep_mode_0_gated_we; + reg_we_check[460] = dio_pad_sleep_mode_1_gated_we; + reg_we_check[461] = dio_pad_sleep_mode_2_gated_we; + reg_we_check[462] = dio_pad_sleep_mode_3_gated_we; + reg_we_check[463] = dio_pad_sleep_mode_4_gated_we; + reg_we_check[464] = dio_pad_sleep_mode_5_gated_we; + reg_we_check[465] = dio_pad_sleep_mode_6_gated_we; + reg_we_check[466] = dio_pad_sleep_mode_7_gated_we; + reg_we_check[467] = dio_pad_sleep_mode_8_gated_we; + reg_we_check[468] = dio_pad_sleep_mode_9_gated_we; + reg_we_check[469] = dio_pad_sleep_mode_10_gated_we; + reg_we_check[470] = dio_pad_sleep_mode_11_gated_we; + reg_we_check[471] = dio_pad_sleep_mode_12_gated_we; + reg_we_check[472] = dio_pad_sleep_mode_13_gated_we; + reg_we_check[473] = wkup_detector_regwen_0_we; + reg_we_check[474] = wkup_detector_regwen_1_we; + reg_we_check[475] = wkup_detector_regwen_2_we; + reg_we_check[476] = wkup_detector_regwen_3_we; + reg_we_check[477] = wkup_detector_regwen_4_we; + reg_we_check[478] = wkup_detector_regwen_5_we; + reg_we_check[479] = wkup_detector_regwen_6_we; + reg_we_check[480] = wkup_detector_regwen_7_we; + reg_we_check[481] = wkup_detector_en_0_we; + reg_we_check[482] = wkup_detector_en_1_we; + reg_we_check[483] = wkup_detector_en_2_we; + reg_we_check[484] = wkup_detector_en_3_we; + reg_we_check[485] = wkup_detector_en_4_we; + reg_we_check[486] = wkup_detector_en_5_we; + reg_we_check[487] = wkup_detector_en_6_we; + reg_we_check[488] = wkup_detector_en_7_we; + reg_we_check[489] = wkup_detector_0_we; + reg_we_check[490] = wkup_detector_1_we; + reg_we_check[491] = wkup_detector_2_we; + reg_we_check[492] = wkup_detector_3_we; + reg_we_check[493] = wkup_detector_4_we; + reg_we_check[494] = wkup_detector_5_we; + reg_we_check[495] = wkup_detector_6_we; + reg_we_check[496] = wkup_detector_7_we; + reg_we_check[497] = wkup_detector_cnt_th_0_we; + reg_we_check[498] = wkup_detector_cnt_th_1_we; + reg_we_check[499] = wkup_detector_cnt_th_2_we; + reg_we_check[500] = wkup_detector_cnt_th_3_we; + reg_we_check[501] = wkup_detector_cnt_th_4_we; + reg_we_check[502] = wkup_detector_cnt_th_5_we; + reg_we_check[503] = wkup_detector_cnt_th_6_we; + reg_we_check[504] = wkup_detector_cnt_th_7_we; + reg_we_check[505] = wkup_detector_padsel_0_gated_we; + reg_we_check[506] = wkup_detector_padsel_1_gated_we; + reg_we_check[507] = wkup_detector_padsel_2_gated_we; + reg_we_check[508] = wkup_detector_padsel_3_gated_we; + reg_we_check[509] = wkup_detector_padsel_4_gated_we; + reg_we_check[510] = wkup_detector_padsel_5_gated_we; + reg_we_check[511] = wkup_detector_padsel_6_gated_we; + reg_we_check[512] = wkup_detector_padsel_7_gated_we; + reg_we_check[513] = wkup_cause_we; end // Read data return @@ -35105,734 +34868,710 @@ module pinmux_reg_top ( end addr_hit[36]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_35_qs; - end - - addr_hit[37]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_36_qs; - end - - addr_hit[38]: begin - reg_rdata_next[0] = mio_periph_insel_regwen_37_qs; - end - - addr_hit[39]: begin reg_rdata_next[5:0] = mio_periph_insel_0_qs; end - addr_hit[40]: begin + addr_hit[37]: begin reg_rdata_next[5:0] = mio_periph_insel_1_qs; end - addr_hit[41]: begin + addr_hit[38]: begin reg_rdata_next[5:0] = mio_periph_insel_2_qs; end - addr_hit[42]: begin + addr_hit[39]: begin reg_rdata_next[5:0] = mio_periph_insel_3_qs; end - addr_hit[43]: begin + addr_hit[40]: begin reg_rdata_next[5:0] = mio_periph_insel_4_qs; end - addr_hit[44]: begin + addr_hit[41]: begin reg_rdata_next[5:0] = mio_periph_insel_5_qs; end - addr_hit[45]: begin + addr_hit[42]: begin reg_rdata_next[5:0] = mio_periph_insel_6_qs; end - addr_hit[46]: begin + addr_hit[43]: begin reg_rdata_next[5:0] = mio_periph_insel_7_qs; end - addr_hit[47]: begin + addr_hit[44]: begin reg_rdata_next[5:0] = mio_periph_insel_8_qs; end - addr_hit[48]: begin + addr_hit[45]: begin reg_rdata_next[5:0] = mio_periph_insel_9_qs; end - addr_hit[49]: begin + addr_hit[46]: begin reg_rdata_next[5:0] = mio_periph_insel_10_qs; end - addr_hit[50]: begin + addr_hit[47]: begin reg_rdata_next[5:0] = mio_periph_insel_11_qs; end - addr_hit[51]: begin + addr_hit[48]: begin reg_rdata_next[5:0] = mio_periph_insel_12_qs; end - addr_hit[52]: begin + addr_hit[49]: begin reg_rdata_next[5:0] = mio_periph_insel_13_qs; end - addr_hit[53]: begin + addr_hit[50]: begin reg_rdata_next[5:0] = mio_periph_insel_14_qs; end - addr_hit[54]: begin + addr_hit[51]: begin reg_rdata_next[5:0] = mio_periph_insel_15_qs; end - addr_hit[55]: begin + addr_hit[52]: begin reg_rdata_next[5:0] = mio_periph_insel_16_qs; end - addr_hit[56]: begin + addr_hit[53]: begin reg_rdata_next[5:0] = mio_periph_insel_17_qs; end - addr_hit[57]: begin + addr_hit[54]: begin reg_rdata_next[5:0] = mio_periph_insel_18_qs; end - addr_hit[58]: begin + addr_hit[55]: begin reg_rdata_next[5:0] = mio_periph_insel_19_qs; end - addr_hit[59]: begin + addr_hit[56]: begin reg_rdata_next[5:0] = mio_periph_insel_20_qs; end - addr_hit[60]: begin + addr_hit[57]: begin reg_rdata_next[5:0] = mio_periph_insel_21_qs; end - addr_hit[61]: begin + addr_hit[58]: begin reg_rdata_next[5:0] = mio_periph_insel_22_qs; end - addr_hit[62]: begin + addr_hit[59]: begin reg_rdata_next[5:0] = mio_periph_insel_23_qs; end - addr_hit[63]: begin + addr_hit[60]: begin reg_rdata_next[5:0] = mio_periph_insel_24_qs; end - addr_hit[64]: begin + addr_hit[61]: begin reg_rdata_next[5:0] = mio_periph_insel_25_qs; end - addr_hit[65]: begin + addr_hit[62]: begin reg_rdata_next[5:0] = mio_periph_insel_26_qs; end - addr_hit[66]: begin + addr_hit[63]: begin reg_rdata_next[5:0] = mio_periph_insel_27_qs; end - addr_hit[67]: begin + addr_hit[64]: begin reg_rdata_next[5:0] = mio_periph_insel_28_qs; end - addr_hit[68]: begin + addr_hit[65]: begin reg_rdata_next[5:0] = mio_periph_insel_29_qs; end - addr_hit[69]: begin + addr_hit[66]: begin reg_rdata_next[5:0] = mio_periph_insel_30_qs; end - addr_hit[70]: begin + addr_hit[67]: begin reg_rdata_next[5:0] = mio_periph_insel_31_qs; end - addr_hit[71]: begin + addr_hit[68]: begin reg_rdata_next[5:0] = mio_periph_insel_32_qs; end - addr_hit[72]: begin + addr_hit[69]: begin reg_rdata_next[5:0] = mio_periph_insel_33_qs; end - addr_hit[73]: begin + addr_hit[70]: begin reg_rdata_next[5:0] = mio_periph_insel_34_qs; end - addr_hit[74]: begin - reg_rdata_next[5:0] = mio_periph_insel_35_qs; - end - - addr_hit[75]: begin - reg_rdata_next[5:0] = mio_periph_insel_36_qs; - end - - addr_hit[76]: begin - reg_rdata_next[5:0] = mio_periph_insel_37_qs; - end - - addr_hit[77]: begin + addr_hit[71]: begin reg_rdata_next[0] = mio_outsel_regwen_0_qs; end - addr_hit[78]: begin + addr_hit[72]: begin reg_rdata_next[0] = mio_outsel_regwen_1_qs; end - addr_hit[79]: begin + addr_hit[73]: begin reg_rdata_next[0] = mio_outsel_regwen_2_qs; end - addr_hit[80]: begin + addr_hit[74]: begin reg_rdata_next[0] = mio_outsel_regwen_3_qs; end - addr_hit[81]: begin + addr_hit[75]: begin reg_rdata_next[0] = mio_outsel_regwen_4_qs; end - addr_hit[82]: begin + addr_hit[76]: begin reg_rdata_next[0] = mio_outsel_regwen_5_qs; end - addr_hit[83]: begin + addr_hit[77]: begin reg_rdata_next[0] = mio_outsel_regwen_6_qs; end - addr_hit[84]: begin + addr_hit[78]: begin reg_rdata_next[0] = mio_outsel_regwen_7_qs; end - addr_hit[85]: begin + addr_hit[79]: begin reg_rdata_next[0] = mio_outsel_regwen_8_qs; end - addr_hit[86]: begin + addr_hit[80]: begin reg_rdata_next[0] = mio_outsel_regwen_9_qs; end - addr_hit[87]: begin + addr_hit[81]: begin reg_rdata_next[0] = mio_outsel_regwen_10_qs; end - addr_hit[88]: begin + addr_hit[82]: begin reg_rdata_next[0] = mio_outsel_regwen_11_qs; end - addr_hit[89]: begin + addr_hit[83]: begin reg_rdata_next[0] = mio_outsel_regwen_12_qs; end - addr_hit[90]: begin + addr_hit[84]: begin reg_rdata_next[0] = mio_outsel_regwen_13_qs; end - addr_hit[91]: begin + addr_hit[85]: begin reg_rdata_next[0] = mio_outsel_regwen_14_qs; end - addr_hit[92]: begin + addr_hit[86]: begin reg_rdata_next[0] = mio_outsel_regwen_15_qs; end - addr_hit[93]: begin + addr_hit[87]: begin reg_rdata_next[0] = mio_outsel_regwen_16_qs; end - addr_hit[94]: begin + addr_hit[88]: begin reg_rdata_next[0] = mio_outsel_regwen_17_qs; end - addr_hit[95]: begin + addr_hit[89]: begin reg_rdata_next[0] = mio_outsel_regwen_18_qs; end - addr_hit[96]: begin + addr_hit[90]: begin reg_rdata_next[0] = mio_outsel_regwen_19_qs; end - addr_hit[97]: begin + addr_hit[91]: begin reg_rdata_next[0] = mio_outsel_regwen_20_qs; end - addr_hit[98]: begin + addr_hit[92]: begin reg_rdata_next[0] = mio_outsel_regwen_21_qs; end - addr_hit[99]: begin + addr_hit[93]: begin reg_rdata_next[0] = mio_outsel_regwen_22_qs; end - addr_hit[100]: begin + addr_hit[94]: begin reg_rdata_next[0] = mio_outsel_regwen_23_qs; end - addr_hit[101]: begin + addr_hit[95]: begin reg_rdata_next[0] = mio_outsel_regwen_24_qs; end - addr_hit[102]: begin + addr_hit[96]: begin reg_rdata_next[0] = mio_outsel_regwen_25_qs; end - addr_hit[103]: begin + addr_hit[97]: begin reg_rdata_next[0] = mio_outsel_regwen_26_qs; end - addr_hit[104]: begin + addr_hit[98]: begin reg_rdata_next[0] = mio_outsel_regwen_27_qs; end - addr_hit[105]: begin + addr_hit[99]: begin reg_rdata_next[0] = mio_outsel_regwen_28_qs; end - addr_hit[106]: begin + addr_hit[100]: begin reg_rdata_next[0] = mio_outsel_regwen_29_qs; end - addr_hit[107]: begin + addr_hit[101]: begin reg_rdata_next[0] = mio_outsel_regwen_30_qs; end - addr_hit[108]: begin + addr_hit[102]: begin reg_rdata_next[0] = mio_outsel_regwen_31_qs; end - addr_hit[109]: begin + addr_hit[103]: begin reg_rdata_next[0] = mio_outsel_regwen_32_qs; end - addr_hit[110]: begin + addr_hit[104]: begin reg_rdata_next[0] = mio_outsel_regwen_33_qs; end - addr_hit[111]: begin + addr_hit[105]: begin reg_rdata_next[0] = mio_outsel_regwen_34_qs; end - addr_hit[112]: begin + addr_hit[106]: begin reg_rdata_next[0] = mio_outsel_regwen_35_qs; end - addr_hit[113]: begin + addr_hit[107]: begin reg_rdata_next[0] = mio_outsel_regwen_36_qs; end - addr_hit[114]: begin + addr_hit[108]: begin reg_rdata_next[0] = mio_outsel_regwen_37_qs; end - addr_hit[115]: begin + addr_hit[109]: begin reg_rdata_next[0] = mio_outsel_regwen_38_qs; end - addr_hit[116]: begin + addr_hit[110]: begin reg_rdata_next[0] = mio_outsel_regwen_39_qs; end - addr_hit[117]: begin + addr_hit[111]: begin reg_rdata_next[0] = mio_outsel_regwen_40_qs; end - addr_hit[118]: begin + addr_hit[112]: begin reg_rdata_next[0] = mio_outsel_regwen_41_qs; end - addr_hit[119]: begin + addr_hit[113]: begin reg_rdata_next[0] = mio_outsel_regwen_42_qs; end - addr_hit[120]: begin + addr_hit[114]: begin reg_rdata_next[0] = mio_outsel_regwen_43_qs; end - addr_hit[121]: begin + addr_hit[115]: begin reg_rdata_next[0] = mio_outsel_regwen_44_qs; end - addr_hit[122]: begin + addr_hit[116]: begin reg_rdata_next[0] = mio_outsel_regwen_45_qs; end - addr_hit[123]: begin + addr_hit[117]: begin reg_rdata_next[0] = mio_outsel_regwen_46_qs; end - addr_hit[124]: begin + addr_hit[118]: begin reg_rdata_next[5:0] = mio_outsel_0_qs; end - addr_hit[125]: begin + addr_hit[119]: begin reg_rdata_next[5:0] = mio_outsel_1_qs; end - addr_hit[126]: begin + addr_hit[120]: begin reg_rdata_next[5:0] = mio_outsel_2_qs; end - addr_hit[127]: begin + addr_hit[121]: begin reg_rdata_next[5:0] = mio_outsel_3_qs; end - addr_hit[128]: begin + addr_hit[122]: begin reg_rdata_next[5:0] = mio_outsel_4_qs; end - addr_hit[129]: begin + addr_hit[123]: begin reg_rdata_next[5:0] = mio_outsel_5_qs; end - addr_hit[130]: begin + addr_hit[124]: begin reg_rdata_next[5:0] = mio_outsel_6_qs; end - addr_hit[131]: begin + addr_hit[125]: begin reg_rdata_next[5:0] = mio_outsel_7_qs; end - addr_hit[132]: begin + addr_hit[126]: begin reg_rdata_next[5:0] = mio_outsel_8_qs; end - addr_hit[133]: begin + addr_hit[127]: begin reg_rdata_next[5:0] = mio_outsel_9_qs; end - addr_hit[134]: begin + addr_hit[128]: begin reg_rdata_next[5:0] = mio_outsel_10_qs; end - addr_hit[135]: begin + addr_hit[129]: begin reg_rdata_next[5:0] = mio_outsel_11_qs; end - addr_hit[136]: begin + addr_hit[130]: begin reg_rdata_next[5:0] = mio_outsel_12_qs; end - addr_hit[137]: begin + addr_hit[131]: begin reg_rdata_next[5:0] = mio_outsel_13_qs; end - addr_hit[138]: begin + addr_hit[132]: begin reg_rdata_next[5:0] = mio_outsel_14_qs; end - addr_hit[139]: begin + addr_hit[133]: begin reg_rdata_next[5:0] = mio_outsel_15_qs; end - addr_hit[140]: begin + addr_hit[134]: begin reg_rdata_next[5:0] = mio_outsel_16_qs; end - addr_hit[141]: begin + addr_hit[135]: begin reg_rdata_next[5:0] = mio_outsel_17_qs; end - addr_hit[142]: begin + addr_hit[136]: begin reg_rdata_next[5:0] = mio_outsel_18_qs; end - addr_hit[143]: begin + addr_hit[137]: begin reg_rdata_next[5:0] = mio_outsel_19_qs; end - addr_hit[144]: begin + addr_hit[138]: begin reg_rdata_next[5:0] = mio_outsel_20_qs; end - addr_hit[145]: begin + addr_hit[139]: begin reg_rdata_next[5:0] = mio_outsel_21_qs; end - addr_hit[146]: begin + addr_hit[140]: begin reg_rdata_next[5:0] = mio_outsel_22_qs; end - addr_hit[147]: begin + addr_hit[141]: begin reg_rdata_next[5:0] = mio_outsel_23_qs; end - addr_hit[148]: begin + addr_hit[142]: begin reg_rdata_next[5:0] = mio_outsel_24_qs; end - addr_hit[149]: begin + addr_hit[143]: begin reg_rdata_next[5:0] = mio_outsel_25_qs; end - addr_hit[150]: begin + addr_hit[144]: begin reg_rdata_next[5:0] = mio_outsel_26_qs; end - addr_hit[151]: begin + addr_hit[145]: begin reg_rdata_next[5:0] = mio_outsel_27_qs; end - addr_hit[152]: begin + addr_hit[146]: begin reg_rdata_next[5:0] = mio_outsel_28_qs; end - addr_hit[153]: begin + addr_hit[147]: begin reg_rdata_next[5:0] = mio_outsel_29_qs; end - addr_hit[154]: begin + addr_hit[148]: begin reg_rdata_next[5:0] = mio_outsel_30_qs; end - addr_hit[155]: begin + addr_hit[149]: begin reg_rdata_next[5:0] = mio_outsel_31_qs; end - addr_hit[156]: begin + addr_hit[150]: begin reg_rdata_next[5:0] = mio_outsel_32_qs; end - addr_hit[157]: begin + addr_hit[151]: begin reg_rdata_next[5:0] = mio_outsel_33_qs; end - addr_hit[158]: begin + addr_hit[152]: begin reg_rdata_next[5:0] = mio_outsel_34_qs; end - addr_hit[159]: begin + addr_hit[153]: begin reg_rdata_next[5:0] = mio_outsel_35_qs; end - addr_hit[160]: begin + addr_hit[154]: begin reg_rdata_next[5:0] = mio_outsel_36_qs; end - addr_hit[161]: begin + addr_hit[155]: begin reg_rdata_next[5:0] = mio_outsel_37_qs; end - addr_hit[162]: begin + addr_hit[156]: begin reg_rdata_next[5:0] = mio_outsel_38_qs; end - addr_hit[163]: begin + addr_hit[157]: begin reg_rdata_next[5:0] = mio_outsel_39_qs; end - addr_hit[164]: begin + addr_hit[158]: begin reg_rdata_next[5:0] = mio_outsel_40_qs; end - addr_hit[165]: begin + addr_hit[159]: begin reg_rdata_next[5:0] = mio_outsel_41_qs; end - addr_hit[166]: begin + addr_hit[160]: begin reg_rdata_next[5:0] = mio_outsel_42_qs; end - addr_hit[167]: begin + addr_hit[161]: begin reg_rdata_next[5:0] = mio_outsel_43_qs; end - addr_hit[168]: begin + addr_hit[162]: begin reg_rdata_next[5:0] = mio_outsel_44_qs; end - addr_hit[169]: begin + addr_hit[163]: begin reg_rdata_next[5:0] = mio_outsel_45_qs; end - addr_hit[170]: begin + addr_hit[164]: begin reg_rdata_next[5:0] = mio_outsel_46_qs; end - addr_hit[171]: begin + addr_hit[165]: begin reg_rdata_next[0] = mio_pad_attr_regwen_0_qs; end - addr_hit[172]: begin + addr_hit[166]: begin reg_rdata_next[0] = mio_pad_attr_regwen_1_qs; end - addr_hit[173]: begin + addr_hit[167]: begin reg_rdata_next[0] = mio_pad_attr_regwen_2_qs; end - addr_hit[174]: begin + addr_hit[168]: begin reg_rdata_next[0] = mio_pad_attr_regwen_3_qs; end - addr_hit[175]: begin + addr_hit[169]: begin reg_rdata_next[0] = mio_pad_attr_regwen_4_qs; end - addr_hit[176]: begin + addr_hit[170]: begin reg_rdata_next[0] = mio_pad_attr_regwen_5_qs; end - addr_hit[177]: begin + addr_hit[171]: begin reg_rdata_next[0] = mio_pad_attr_regwen_6_qs; end - addr_hit[178]: begin + addr_hit[172]: begin reg_rdata_next[0] = mio_pad_attr_regwen_7_qs; end - addr_hit[179]: begin + addr_hit[173]: begin reg_rdata_next[0] = mio_pad_attr_regwen_8_qs; end - addr_hit[180]: begin + addr_hit[174]: begin reg_rdata_next[0] = mio_pad_attr_regwen_9_qs; end - addr_hit[181]: begin + addr_hit[175]: begin reg_rdata_next[0] = mio_pad_attr_regwen_10_qs; end - addr_hit[182]: begin + addr_hit[176]: begin reg_rdata_next[0] = mio_pad_attr_regwen_11_qs; end - addr_hit[183]: begin + addr_hit[177]: begin reg_rdata_next[0] = mio_pad_attr_regwen_12_qs; end - addr_hit[184]: begin + addr_hit[178]: begin reg_rdata_next[0] = mio_pad_attr_regwen_13_qs; end - addr_hit[185]: begin + addr_hit[179]: begin reg_rdata_next[0] = mio_pad_attr_regwen_14_qs; end - addr_hit[186]: begin + addr_hit[180]: begin reg_rdata_next[0] = mio_pad_attr_regwen_15_qs; end - addr_hit[187]: begin + addr_hit[181]: begin reg_rdata_next[0] = mio_pad_attr_regwen_16_qs; end - addr_hit[188]: begin + addr_hit[182]: begin reg_rdata_next[0] = mio_pad_attr_regwen_17_qs; end - addr_hit[189]: begin + addr_hit[183]: begin reg_rdata_next[0] = mio_pad_attr_regwen_18_qs; end - addr_hit[190]: begin + addr_hit[184]: begin reg_rdata_next[0] = mio_pad_attr_regwen_19_qs; end - addr_hit[191]: begin + addr_hit[185]: begin reg_rdata_next[0] = mio_pad_attr_regwen_20_qs; end - addr_hit[192]: begin + addr_hit[186]: begin reg_rdata_next[0] = mio_pad_attr_regwen_21_qs; end - addr_hit[193]: begin + addr_hit[187]: begin reg_rdata_next[0] = mio_pad_attr_regwen_22_qs; end - addr_hit[194]: begin + addr_hit[188]: begin reg_rdata_next[0] = mio_pad_attr_regwen_23_qs; end - addr_hit[195]: begin + addr_hit[189]: begin reg_rdata_next[0] = mio_pad_attr_regwen_24_qs; end - addr_hit[196]: begin + addr_hit[190]: begin reg_rdata_next[0] = mio_pad_attr_regwen_25_qs; end - addr_hit[197]: begin + addr_hit[191]: begin reg_rdata_next[0] = mio_pad_attr_regwen_26_qs; end - addr_hit[198]: begin + addr_hit[192]: begin reg_rdata_next[0] = mio_pad_attr_regwen_27_qs; end - addr_hit[199]: begin + addr_hit[193]: begin reg_rdata_next[0] = mio_pad_attr_regwen_28_qs; end - addr_hit[200]: begin + addr_hit[194]: begin reg_rdata_next[0] = mio_pad_attr_regwen_29_qs; end - addr_hit[201]: begin + addr_hit[195]: begin reg_rdata_next[0] = mio_pad_attr_regwen_30_qs; end - addr_hit[202]: begin + addr_hit[196]: begin reg_rdata_next[0] = mio_pad_attr_regwen_31_qs; end - addr_hit[203]: begin + addr_hit[197]: begin reg_rdata_next[0] = mio_pad_attr_regwen_32_qs; end - addr_hit[204]: begin + addr_hit[198]: begin reg_rdata_next[0] = mio_pad_attr_regwen_33_qs; end - addr_hit[205]: begin + addr_hit[199]: begin reg_rdata_next[0] = mio_pad_attr_regwen_34_qs; end - addr_hit[206]: begin + addr_hit[200]: begin reg_rdata_next[0] = mio_pad_attr_regwen_35_qs; end - addr_hit[207]: begin + addr_hit[201]: begin reg_rdata_next[0] = mio_pad_attr_regwen_36_qs; end - addr_hit[208]: begin + addr_hit[202]: begin reg_rdata_next[0] = mio_pad_attr_regwen_37_qs; end - addr_hit[209]: begin + addr_hit[203]: begin reg_rdata_next[0] = mio_pad_attr_regwen_38_qs; end - addr_hit[210]: begin + addr_hit[204]: begin reg_rdata_next[0] = mio_pad_attr_regwen_39_qs; end - addr_hit[211]: begin + addr_hit[205]: begin reg_rdata_next[0] = mio_pad_attr_regwen_40_qs; end - addr_hit[212]: begin + addr_hit[206]: begin reg_rdata_next[0] = mio_pad_attr_regwen_41_qs; end - addr_hit[213]: begin + addr_hit[207]: begin reg_rdata_next[0] = mio_pad_attr_regwen_42_qs; end - addr_hit[214]: begin + addr_hit[208]: begin reg_rdata_next[0] = mio_pad_attr_regwen_43_qs; end - addr_hit[215]: begin + addr_hit[209]: begin reg_rdata_next[0] = mio_pad_attr_regwen_44_qs; end - addr_hit[216]: begin + addr_hit[210]: begin reg_rdata_next[0] = mio_pad_attr_regwen_45_qs; end - addr_hit[217]: begin + addr_hit[211]: begin reg_rdata_next[0] = mio_pad_attr_regwen_46_qs; end - addr_hit[218]: begin + addr_hit[212]: begin reg_rdata_next[0] = mio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = mio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = mio_pad_attr_0_pull_en_0_qs; @@ -35845,7 +35584,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_0_drive_strength_0_qs; end - addr_hit[219]: begin + addr_hit[213]: begin reg_rdata_next[0] = mio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = mio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = mio_pad_attr_1_pull_en_1_qs; @@ -35858,7 +35597,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_1_drive_strength_1_qs; end - addr_hit[220]: begin + addr_hit[214]: begin reg_rdata_next[0] = mio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = mio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = mio_pad_attr_2_pull_en_2_qs; @@ -35871,7 +35610,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_2_drive_strength_2_qs; end - addr_hit[221]: begin + addr_hit[215]: begin reg_rdata_next[0] = mio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = mio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = mio_pad_attr_3_pull_en_3_qs; @@ -35884,7 +35623,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_3_drive_strength_3_qs; end - addr_hit[222]: begin + addr_hit[216]: begin reg_rdata_next[0] = mio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = mio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = mio_pad_attr_4_pull_en_4_qs; @@ -35897,7 +35636,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_4_drive_strength_4_qs; end - addr_hit[223]: begin + addr_hit[217]: begin reg_rdata_next[0] = mio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = mio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = mio_pad_attr_5_pull_en_5_qs; @@ -35910,7 +35649,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_5_drive_strength_5_qs; end - addr_hit[224]: begin + addr_hit[218]: begin reg_rdata_next[0] = mio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = mio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = mio_pad_attr_6_pull_en_6_qs; @@ -35923,7 +35662,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_6_drive_strength_6_qs; end - addr_hit[225]: begin + addr_hit[219]: begin reg_rdata_next[0] = mio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = mio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = mio_pad_attr_7_pull_en_7_qs; @@ -35936,7 +35675,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_7_drive_strength_7_qs; end - addr_hit[226]: begin + addr_hit[220]: begin reg_rdata_next[0] = mio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = mio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = mio_pad_attr_8_pull_en_8_qs; @@ -35949,7 +35688,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_8_drive_strength_8_qs; end - addr_hit[227]: begin + addr_hit[221]: begin reg_rdata_next[0] = mio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = mio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = mio_pad_attr_9_pull_en_9_qs; @@ -35962,7 +35701,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_9_drive_strength_9_qs; end - addr_hit[228]: begin + addr_hit[222]: begin reg_rdata_next[0] = mio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = mio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = mio_pad_attr_10_pull_en_10_qs; @@ -35975,7 +35714,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_10_drive_strength_10_qs; end - addr_hit[229]: begin + addr_hit[223]: begin reg_rdata_next[0] = mio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = mio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = mio_pad_attr_11_pull_en_11_qs; @@ -35988,7 +35727,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_11_drive_strength_11_qs; end - addr_hit[230]: begin + addr_hit[224]: begin reg_rdata_next[0] = mio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = mio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = mio_pad_attr_12_pull_en_12_qs; @@ -36001,7 +35740,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_12_drive_strength_12_qs; end - addr_hit[231]: begin + addr_hit[225]: begin reg_rdata_next[0] = mio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = mio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = mio_pad_attr_13_pull_en_13_qs; @@ -36014,7 +35753,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_13_drive_strength_13_qs; end - addr_hit[232]: begin + addr_hit[226]: begin reg_rdata_next[0] = mio_pad_attr_14_invert_14_qs; reg_rdata_next[1] = mio_pad_attr_14_virtual_od_en_14_qs; reg_rdata_next[2] = mio_pad_attr_14_pull_en_14_qs; @@ -36027,7 +35766,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_14_drive_strength_14_qs; end - addr_hit[233]: begin + addr_hit[227]: begin reg_rdata_next[0] = mio_pad_attr_15_invert_15_qs; reg_rdata_next[1] = mio_pad_attr_15_virtual_od_en_15_qs; reg_rdata_next[2] = mio_pad_attr_15_pull_en_15_qs; @@ -36040,7 +35779,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_15_drive_strength_15_qs; end - addr_hit[234]: begin + addr_hit[228]: begin reg_rdata_next[0] = mio_pad_attr_16_invert_16_qs; reg_rdata_next[1] = mio_pad_attr_16_virtual_od_en_16_qs; reg_rdata_next[2] = mio_pad_attr_16_pull_en_16_qs; @@ -36053,7 +35792,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_16_drive_strength_16_qs; end - addr_hit[235]: begin + addr_hit[229]: begin reg_rdata_next[0] = mio_pad_attr_17_invert_17_qs; reg_rdata_next[1] = mio_pad_attr_17_virtual_od_en_17_qs; reg_rdata_next[2] = mio_pad_attr_17_pull_en_17_qs; @@ -36066,7 +35805,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_17_drive_strength_17_qs; end - addr_hit[236]: begin + addr_hit[230]: begin reg_rdata_next[0] = mio_pad_attr_18_invert_18_qs; reg_rdata_next[1] = mio_pad_attr_18_virtual_od_en_18_qs; reg_rdata_next[2] = mio_pad_attr_18_pull_en_18_qs; @@ -36079,7 +35818,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_18_drive_strength_18_qs; end - addr_hit[237]: begin + addr_hit[231]: begin reg_rdata_next[0] = mio_pad_attr_19_invert_19_qs; reg_rdata_next[1] = mio_pad_attr_19_virtual_od_en_19_qs; reg_rdata_next[2] = mio_pad_attr_19_pull_en_19_qs; @@ -36092,7 +35831,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_19_drive_strength_19_qs; end - addr_hit[238]: begin + addr_hit[232]: begin reg_rdata_next[0] = mio_pad_attr_20_invert_20_qs; reg_rdata_next[1] = mio_pad_attr_20_virtual_od_en_20_qs; reg_rdata_next[2] = mio_pad_attr_20_pull_en_20_qs; @@ -36105,7 +35844,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_20_drive_strength_20_qs; end - addr_hit[239]: begin + addr_hit[233]: begin reg_rdata_next[0] = mio_pad_attr_21_invert_21_qs; reg_rdata_next[1] = mio_pad_attr_21_virtual_od_en_21_qs; reg_rdata_next[2] = mio_pad_attr_21_pull_en_21_qs; @@ -36118,7 +35857,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_21_drive_strength_21_qs; end - addr_hit[240]: begin + addr_hit[234]: begin reg_rdata_next[0] = mio_pad_attr_22_invert_22_qs; reg_rdata_next[1] = mio_pad_attr_22_virtual_od_en_22_qs; reg_rdata_next[2] = mio_pad_attr_22_pull_en_22_qs; @@ -36131,7 +35870,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_22_drive_strength_22_qs; end - addr_hit[241]: begin + addr_hit[235]: begin reg_rdata_next[0] = mio_pad_attr_23_invert_23_qs; reg_rdata_next[1] = mio_pad_attr_23_virtual_od_en_23_qs; reg_rdata_next[2] = mio_pad_attr_23_pull_en_23_qs; @@ -36144,7 +35883,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_23_drive_strength_23_qs; end - addr_hit[242]: begin + addr_hit[236]: begin reg_rdata_next[0] = mio_pad_attr_24_invert_24_qs; reg_rdata_next[1] = mio_pad_attr_24_virtual_od_en_24_qs; reg_rdata_next[2] = mio_pad_attr_24_pull_en_24_qs; @@ -36157,7 +35896,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_24_drive_strength_24_qs; end - addr_hit[243]: begin + addr_hit[237]: begin reg_rdata_next[0] = mio_pad_attr_25_invert_25_qs; reg_rdata_next[1] = mio_pad_attr_25_virtual_od_en_25_qs; reg_rdata_next[2] = mio_pad_attr_25_pull_en_25_qs; @@ -36170,7 +35909,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_25_drive_strength_25_qs; end - addr_hit[244]: begin + addr_hit[238]: begin reg_rdata_next[0] = mio_pad_attr_26_invert_26_qs; reg_rdata_next[1] = mio_pad_attr_26_virtual_od_en_26_qs; reg_rdata_next[2] = mio_pad_attr_26_pull_en_26_qs; @@ -36183,7 +35922,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_26_drive_strength_26_qs; end - addr_hit[245]: begin + addr_hit[239]: begin reg_rdata_next[0] = mio_pad_attr_27_invert_27_qs; reg_rdata_next[1] = mio_pad_attr_27_virtual_od_en_27_qs; reg_rdata_next[2] = mio_pad_attr_27_pull_en_27_qs; @@ -36196,7 +35935,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_27_drive_strength_27_qs; end - addr_hit[246]: begin + addr_hit[240]: begin reg_rdata_next[0] = mio_pad_attr_28_invert_28_qs; reg_rdata_next[1] = mio_pad_attr_28_virtual_od_en_28_qs; reg_rdata_next[2] = mio_pad_attr_28_pull_en_28_qs; @@ -36209,7 +35948,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_28_drive_strength_28_qs; end - addr_hit[247]: begin + addr_hit[241]: begin reg_rdata_next[0] = mio_pad_attr_29_invert_29_qs; reg_rdata_next[1] = mio_pad_attr_29_virtual_od_en_29_qs; reg_rdata_next[2] = mio_pad_attr_29_pull_en_29_qs; @@ -36222,7 +35961,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_29_drive_strength_29_qs; end - addr_hit[248]: begin + addr_hit[242]: begin reg_rdata_next[0] = mio_pad_attr_30_invert_30_qs; reg_rdata_next[1] = mio_pad_attr_30_virtual_od_en_30_qs; reg_rdata_next[2] = mio_pad_attr_30_pull_en_30_qs; @@ -36235,7 +35974,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_30_drive_strength_30_qs; end - addr_hit[249]: begin + addr_hit[243]: begin reg_rdata_next[0] = mio_pad_attr_31_invert_31_qs; reg_rdata_next[1] = mio_pad_attr_31_virtual_od_en_31_qs; reg_rdata_next[2] = mio_pad_attr_31_pull_en_31_qs; @@ -36248,7 +35987,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_31_drive_strength_31_qs; end - addr_hit[250]: begin + addr_hit[244]: begin reg_rdata_next[0] = mio_pad_attr_32_invert_32_qs; reg_rdata_next[1] = mio_pad_attr_32_virtual_od_en_32_qs; reg_rdata_next[2] = mio_pad_attr_32_pull_en_32_qs; @@ -36261,7 +36000,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_32_drive_strength_32_qs; end - addr_hit[251]: begin + addr_hit[245]: begin reg_rdata_next[0] = mio_pad_attr_33_invert_33_qs; reg_rdata_next[1] = mio_pad_attr_33_virtual_od_en_33_qs; reg_rdata_next[2] = mio_pad_attr_33_pull_en_33_qs; @@ -36274,7 +36013,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_33_drive_strength_33_qs; end - addr_hit[252]: begin + addr_hit[246]: begin reg_rdata_next[0] = mio_pad_attr_34_invert_34_qs; reg_rdata_next[1] = mio_pad_attr_34_virtual_od_en_34_qs; reg_rdata_next[2] = mio_pad_attr_34_pull_en_34_qs; @@ -36287,7 +36026,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_34_drive_strength_34_qs; end - addr_hit[253]: begin + addr_hit[247]: begin reg_rdata_next[0] = mio_pad_attr_35_invert_35_qs; reg_rdata_next[1] = mio_pad_attr_35_virtual_od_en_35_qs; reg_rdata_next[2] = mio_pad_attr_35_pull_en_35_qs; @@ -36300,7 +36039,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_35_drive_strength_35_qs; end - addr_hit[254]: begin + addr_hit[248]: begin reg_rdata_next[0] = mio_pad_attr_36_invert_36_qs; reg_rdata_next[1] = mio_pad_attr_36_virtual_od_en_36_qs; reg_rdata_next[2] = mio_pad_attr_36_pull_en_36_qs; @@ -36313,7 +36052,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_36_drive_strength_36_qs; end - addr_hit[255]: begin + addr_hit[249]: begin reg_rdata_next[0] = mio_pad_attr_37_invert_37_qs; reg_rdata_next[1] = mio_pad_attr_37_virtual_od_en_37_qs; reg_rdata_next[2] = mio_pad_attr_37_pull_en_37_qs; @@ -36326,7 +36065,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_37_drive_strength_37_qs; end - addr_hit[256]: begin + addr_hit[250]: begin reg_rdata_next[0] = mio_pad_attr_38_invert_38_qs; reg_rdata_next[1] = mio_pad_attr_38_virtual_od_en_38_qs; reg_rdata_next[2] = mio_pad_attr_38_pull_en_38_qs; @@ -36339,7 +36078,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_38_drive_strength_38_qs; end - addr_hit[257]: begin + addr_hit[251]: begin reg_rdata_next[0] = mio_pad_attr_39_invert_39_qs; reg_rdata_next[1] = mio_pad_attr_39_virtual_od_en_39_qs; reg_rdata_next[2] = mio_pad_attr_39_pull_en_39_qs; @@ -36352,7 +36091,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_39_drive_strength_39_qs; end - addr_hit[258]: begin + addr_hit[252]: begin reg_rdata_next[0] = mio_pad_attr_40_invert_40_qs; reg_rdata_next[1] = mio_pad_attr_40_virtual_od_en_40_qs; reg_rdata_next[2] = mio_pad_attr_40_pull_en_40_qs; @@ -36365,7 +36104,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_40_drive_strength_40_qs; end - addr_hit[259]: begin + addr_hit[253]: begin reg_rdata_next[0] = mio_pad_attr_41_invert_41_qs; reg_rdata_next[1] = mio_pad_attr_41_virtual_od_en_41_qs; reg_rdata_next[2] = mio_pad_attr_41_pull_en_41_qs; @@ -36378,7 +36117,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_41_drive_strength_41_qs; end - addr_hit[260]: begin + addr_hit[254]: begin reg_rdata_next[0] = mio_pad_attr_42_invert_42_qs; reg_rdata_next[1] = mio_pad_attr_42_virtual_od_en_42_qs; reg_rdata_next[2] = mio_pad_attr_42_pull_en_42_qs; @@ -36391,7 +36130,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_42_drive_strength_42_qs; end - addr_hit[261]: begin + addr_hit[255]: begin reg_rdata_next[0] = mio_pad_attr_43_invert_43_qs; reg_rdata_next[1] = mio_pad_attr_43_virtual_od_en_43_qs; reg_rdata_next[2] = mio_pad_attr_43_pull_en_43_qs; @@ -36404,7 +36143,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_43_drive_strength_43_qs; end - addr_hit[262]: begin + addr_hit[256]: begin reg_rdata_next[0] = mio_pad_attr_44_invert_44_qs; reg_rdata_next[1] = mio_pad_attr_44_virtual_od_en_44_qs; reg_rdata_next[2] = mio_pad_attr_44_pull_en_44_qs; @@ -36417,7 +36156,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_44_drive_strength_44_qs; end - addr_hit[263]: begin + addr_hit[257]: begin reg_rdata_next[0] = mio_pad_attr_45_invert_45_qs; reg_rdata_next[1] = mio_pad_attr_45_virtual_od_en_45_qs; reg_rdata_next[2] = mio_pad_attr_45_pull_en_45_qs; @@ -36430,7 +36169,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_45_drive_strength_45_qs; end - addr_hit[264]: begin + addr_hit[258]: begin reg_rdata_next[0] = mio_pad_attr_46_invert_46_qs; reg_rdata_next[1] = mio_pad_attr_46_virtual_od_en_46_qs; reg_rdata_next[2] = mio_pad_attr_46_pull_en_46_qs; @@ -36443,63 +36182,63 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = mio_pad_attr_46_drive_strength_46_qs; end - addr_hit[265]: begin + addr_hit[259]: begin reg_rdata_next[0] = dio_pad_attr_regwen_0_qs; end - addr_hit[266]: begin + addr_hit[260]: begin reg_rdata_next[0] = dio_pad_attr_regwen_1_qs; end - addr_hit[267]: begin + addr_hit[261]: begin reg_rdata_next[0] = dio_pad_attr_regwen_2_qs; end - addr_hit[268]: begin + addr_hit[262]: begin reg_rdata_next[0] = dio_pad_attr_regwen_3_qs; end - addr_hit[269]: begin + addr_hit[263]: begin reg_rdata_next[0] = dio_pad_attr_regwen_4_qs; end - addr_hit[270]: begin + addr_hit[264]: begin reg_rdata_next[0] = dio_pad_attr_regwen_5_qs; end - addr_hit[271]: begin + addr_hit[265]: begin reg_rdata_next[0] = dio_pad_attr_regwen_6_qs; end - addr_hit[272]: begin + addr_hit[266]: begin reg_rdata_next[0] = dio_pad_attr_regwen_7_qs; end - addr_hit[273]: begin + addr_hit[267]: begin reg_rdata_next[0] = dio_pad_attr_regwen_8_qs; end - addr_hit[274]: begin + addr_hit[268]: begin reg_rdata_next[0] = dio_pad_attr_regwen_9_qs; end - addr_hit[275]: begin + addr_hit[269]: begin reg_rdata_next[0] = dio_pad_attr_regwen_10_qs; end - addr_hit[276]: begin + addr_hit[270]: begin reg_rdata_next[0] = dio_pad_attr_regwen_11_qs; end - addr_hit[277]: begin + addr_hit[271]: begin reg_rdata_next[0] = dio_pad_attr_regwen_12_qs; end - addr_hit[278]: begin + addr_hit[272]: begin reg_rdata_next[0] = dio_pad_attr_regwen_13_qs; end - addr_hit[279]: begin + addr_hit[273]: begin reg_rdata_next[0] = dio_pad_attr_0_invert_0_qs; reg_rdata_next[1] = dio_pad_attr_0_virtual_od_en_0_qs; reg_rdata_next[2] = dio_pad_attr_0_pull_en_0_qs; @@ -36512,7 +36251,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_0_drive_strength_0_qs; end - addr_hit[280]: begin + addr_hit[274]: begin reg_rdata_next[0] = dio_pad_attr_1_invert_1_qs; reg_rdata_next[1] = dio_pad_attr_1_virtual_od_en_1_qs; reg_rdata_next[2] = dio_pad_attr_1_pull_en_1_qs; @@ -36525,7 +36264,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_1_drive_strength_1_qs; end - addr_hit[281]: begin + addr_hit[275]: begin reg_rdata_next[0] = dio_pad_attr_2_invert_2_qs; reg_rdata_next[1] = dio_pad_attr_2_virtual_od_en_2_qs; reg_rdata_next[2] = dio_pad_attr_2_pull_en_2_qs; @@ -36538,7 +36277,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_2_drive_strength_2_qs; end - addr_hit[282]: begin + addr_hit[276]: begin reg_rdata_next[0] = dio_pad_attr_3_invert_3_qs; reg_rdata_next[1] = dio_pad_attr_3_virtual_od_en_3_qs; reg_rdata_next[2] = dio_pad_attr_3_pull_en_3_qs; @@ -36551,7 +36290,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_3_drive_strength_3_qs; end - addr_hit[283]: begin + addr_hit[277]: begin reg_rdata_next[0] = dio_pad_attr_4_invert_4_qs; reg_rdata_next[1] = dio_pad_attr_4_virtual_od_en_4_qs; reg_rdata_next[2] = dio_pad_attr_4_pull_en_4_qs; @@ -36564,7 +36303,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_4_drive_strength_4_qs; end - addr_hit[284]: begin + addr_hit[278]: begin reg_rdata_next[0] = dio_pad_attr_5_invert_5_qs; reg_rdata_next[1] = dio_pad_attr_5_virtual_od_en_5_qs; reg_rdata_next[2] = dio_pad_attr_5_pull_en_5_qs; @@ -36577,7 +36316,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_5_drive_strength_5_qs; end - addr_hit[285]: begin + addr_hit[279]: begin reg_rdata_next[0] = dio_pad_attr_6_invert_6_qs; reg_rdata_next[1] = dio_pad_attr_6_virtual_od_en_6_qs; reg_rdata_next[2] = dio_pad_attr_6_pull_en_6_qs; @@ -36590,7 +36329,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_6_drive_strength_6_qs; end - addr_hit[286]: begin + addr_hit[280]: begin reg_rdata_next[0] = dio_pad_attr_7_invert_7_qs; reg_rdata_next[1] = dio_pad_attr_7_virtual_od_en_7_qs; reg_rdata_next[2] = dio_pad_attr_7_pull_en_7_qs; @@ -36603,7 +36342,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_7_drive_strength_7_qs; end - addr_hit[287]: begin + addr_hit[281]: begin reg_rdata_next[0] = dio_pad_attr_8_invert_8_qs; reg_rdata_next[1] = dio_pad_attr_8_virtual_od_en_8_qs; reg_rdata_next[2] = dio_pad_attr_8_pull_en_8_qs; @@ -36616,7 +36355,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_8_drive_strength_8_qs; end - addr_hit[288]: begin + addr_hit[282]: begin reg_rdata_next[0] = dio_pad_attr_9_invert_9_qs; reg_rdata_next[1] = dio_pad_attr_9_virtual_od_en_9_qs; reg_rdata_next[2] = dio_pad_attr_9_pull_en_9_qs; @@ -36629,7 +36368,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_9_drive_strength_9_qs; end - addr_hit[289]: begin + addr_hit[283]: begin reg_rdata_next[0] = dio_pad_attr_10_invert_10_qs; reg_rdata_next[1] = dio_pad_attr_10_virtual_od_en_10_qs; reg_rdata_next[2] = dio_pad_attr_10_pull_en_10_qs; @@ -36642,7 +36381,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_10_drive_strength_10_qs; end - addr_hit[290]: begin + addr_hit[284]: begin reg_rdata_next[0] = dio_pad_attr_11_invert_11_qs; reg_rdata_next[1] = dio_pad_attr_11_virtual_od_en_11_qs; reg_rdata_next[2] = dio_pad_attr_11_pull_en_11_qs; @@ -36655,7 +36394,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_11_drive_strength_11_qs; end - addr_hit[291]: begin + addr_hit[285]: begin reg_rdata_next[0] = dio_pad_attr_12_invert_12_qs; reg_rdata_next[1] = dio_pad_attr_12_virtual_od_en_12_qs; reg_rdata_next[2] = dio_pad_attr_12_pull_en_12_qs; @@ -36668,7 +36407,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_12_drive_strength_12_qs; end - addr_hit[292]: begin + addr_hit[286]: begin reg_rdata_next[0] = dio_pad_attr_13_invert_13_qs; reg_rdata_next[1] = dio_pad_attr_13_virtual_od_en_13_qs; reg_rdata_next[2] = dio_pad_attr_13_pull_en_13_qs; @@ -36681,7 +36420,7 @@ module pinmux_reg_top ( reg_rdata_next[23:20] = dio_pad_attr_13_drive_strength_13_qs; end - addr_hit[293]: begin + addr_hit[287]: begin reg_rdata_next[0] = mio_pad_sleep_status_0_en_0_qs; reg_rdata_next[1] = mio_pad_sleep_status_0_en_1_qs; reg_rdata_next[2] = mio_pad_sleep_status_0_en_2_qs; @@ -36716,7 +36455,7 @@ module pinmux_reg_top ( reg_rdata_next[31] = mio_pad_sleep_status_0_en_31_qs; end - addr_hit[294]: begin + addr_hit[288]: begin reg_rdata_next[0] = mio_pad_sleep_status_1_en_32_qs; reg_rdata_next[1] = mio_pad_sleep_status_1_en_33_qs; reg_rdata_next[2] = mio_pad_sleep_status_1_en_34_qs; @@ -36734,571 +36473,571 @@ module pinmux_reg_top ( reg_rdata_next[14] = mio_pad_sleep_status_1_en_46_qs; end - addr_hit[295]: begin + addr_hit[289]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_0_qs; end - addr_hit[296]: begin + addr_hit[290]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_1_qs; end - addr_hit[297]: begin + addr_hit[291]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_2_qs; end - addr_hit[298]: begin + addr_hit[292]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_3_qs; end - addr_hit[299]: begin + addr_hit[293]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_4_qs; end - addr_hit[300]: begin + addr_hit[294]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_5_qs; end - addr_hit[301]: begin + addr_hit[295]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_6_qs; end - addr_hit[302]: begin + addr_hit[296]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_7_qs; end - addr_hit[303]: begin + addr_hit[297]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_8_qs; end - addr_hit[304]: begin + addr_hit[298]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_9_qs; end - addr_hit[305]: begin + addr_hit[299]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_10_qs; end - addr_hit[306]: begin + addr_hit[300]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_11_qs; end - addr_hit[307]: begin + addr_hit[301]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_12_qs; end - addr_hit[308]: begin + addr_hit[302]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_13_qs; end - addr_hit[309]: begin + addr_hit[303]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_14_qs; end - addr_hit[310]: begin + addr_hit[304]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_15_qs; end - addr_hit[311]: begin + addr_hit[305]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_16_qs; end - addr_hit[312]: begin + addr_hit[306]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_17_qs; end - addr_hit[313]: begin + addr_hit[307]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_18_qs; end - addr_hit[314]: begin + addr_hit[308]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_19_qs; end - addr_hit[315]: begin + addr_hit[309]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_20_qs; end - addr_hit[316]: begin + addr_hit[310]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_21_qs; end - addr_hit[317]: begin + addr_hit[311]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_22_qs; end - addr_hit[318]: begin + addr_hit[312]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_23_qs; end - addr_hit[319]: begin + addr_hit[313]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_24_qs; end - addr_hit[320]: begin + addr_hit[314]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_25_qs; end - addr_hit[321]: begin + addr_hit[315]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_26_qs; end - addr_hit[322]: begin + addr_hit[316]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_27_qs; end - addr_hit[323]: begin + addr_hit[317]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_28_qs; end - addr_hit[324]: begin + addr_hit[318]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_29_qs; end - addr_hit[325]: begin + addr_hit[319]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_30_qs; end - addr_hit[326]: begin + addr_hit[320]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_31_qs; end - addr_hit[327]: begin + addr_hit[321]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_32_qs; end - addr_hit[328]: begin + addr_hit[322]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_33_qs; end - addr_hit[329]: begin + addr_hit[323]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_34_qs; end - addr_hit[330]: begin + addr_hit[324]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_35_qs; end - addr_hit[331]: begin + addr_hit[325]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_36_qs; end - addr_hit[332]: begin + addr_hit[326]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_37_qs; end - addr_hit[333]: begin + addr_hit[327]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_38_qs; end - addr_hit[334]: begin + addr_hit[328]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_39_qs; end - addr_hit[335]: begin + addr_hit[329]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_40_qs; end - addr_hit[336]: begin + addr_hit[330]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_41_qs; end - addr_hit[337]: begin + addr_hit[331]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_42_qs; end - addr_hit[338]: begin + addr_hit[332]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_43_qs; end - addr_hit[339]: begin + addr_hit[333]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_44_qs; end - addr_hit[340]: begin + addr_hit[334]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_45_qs; end - addr_hit[341]: begin + addr_hit[335]: begin reg_rdata_next[0] = mio_pad_sleep_regwen_46_qs; end - addr_hit[342]: begin + addr_hit[336]: begin reg_rdata_next[0] = mio_pad_sleep_en_0_qs; end - addr_hit[343]: begin + addr_hit[337]: begin reg_rdata_next[0] = mio_pad_sleep_en_1_qs; end - addr_hit[344]: begin + addr_hit[338]: begin reg_rdata_next[0] = mio_pad_sleep_en_2_qs; end - addr_hit[345]: begin + addr_hit[339]: begin reg_rdata_next[0] = mio_pad_sleep_en_3_qs; end - addr_hit[346]: begin + addr_hit[340]: begin reg_rdata_next[0] = mio_pad_sleep_en_4_qs; end - addr_hit[347]: begin + addr_hit[341]: begin reg_rdata_next[0] = mio_pad_sleep_en_5_qs; end - addr_hit[348]: begin + addr_hit[342]: begin reg_rdata_next[0] = mio_pad_sleep_en_6_qs; end - addr_hit[349]: begin + addr_hit[343]: begin reg_rdata_next[0] = mio_pad_sleep_en_7_qs; end - addr_hit[350]: begin + addr_hit[344]: begin reg_rdata_next[0] = mio_pad_sleep_en_8_qs; end - addr_hit[351]: begin + addr_hit[345]: begin reg_rdata_next[0] = mio_pad_sleep_en_9_qs; end - addr_hit[352]: begin + addr_hit[346]: begin reg_rdata_next[0] = mio_pad_sleep_en_10_qs; end - addr_hit[353]: begin + addr_hit[347]: begin reg_rdata_next[0] = mio_pad_sleep_en_11_qs; end - addr_hit[354]: begin + addr_hit[348]: begin reg_rdata_next[0] = mio_pad_sleep_en_12_qs; end - addr_hit[355]: begin + addr_hit[349]: begin reg_rdata_next[0] = mio_pad_sleep_en_13_qs; end - addr_hit[356]: begin + addr_hit[350]: begin reg_rdata_next[0] = mio_pad_sleep_en_14_qs; end - addr_hit[357]: begin + addr_hit[351]: begin reg_rdata_next[0] = mio_pad_sleep_en_15_qs; end - addr_hit[358]: begin + addr_hit[352]: begin reg_rdata_next[0] = mio_pad_sleep_en_16_qs; end - addr_hit[359]: begin + addr_hit[353]: begin reg_rdata_next[0] = mio_pad_sleep_en_17_qs; end - addr_hit[360]: begin + addr_hit[354]: begin reg_rdata_next[0] = mio_pad_sleep_en_18_qs; end - addr_hit[361]: begin + addr_hit[355]: begin reg_rdata_next[0] = mio_pad_sleep_en_19_qs; end - addr_hit[362]: begin + addr_hit[356]: begin reg_rdata_next[0] = mio_pad_sleep_en_20_qs; end - addr_hit[363]: begin + addr_hit[357]: begin reg_rdata_next[0] = mio_pad_sleep_en_21_qs; end - addr_hit[364]: begin + addr_hit[358]: begin reg_rdata_next[0] = mio_pad_sleep_en_22_qs; end - addr_hit[365]: begin + addr_hit[359]: begin reg_rdata_next[0] = mio_pad_sleep_en_23_qs; end - addr_hit[366]: begin + addr_hit[360]: begin reg_rdata_next[0] = mio_pad_sleep_en_24_qs; end - addr_hit[367]: begin + addr_hit[361]: begin reg_rdata_next[0] = mio_pad_sleep_en_25_qs; end - addr_hit[368]: begin + addr_hit[362]: begin reg_rdata_next[0] = mio_pad_sleep_en_26_qs; end - addr_hit[369]: begin + addr_hit[363]: begin reg_rdata_next[0] = mio_pad_sleep_en_27_qs; end - addr_hit[370]: begin + addr_hit[364]: begin reg_rdata_next[0] = mio_pad_sleep_en_28_qs; end - addr_hit[371]: begin + addr_hit[365]: begin reg_rdata_next[0] = mio_pad_sleep_en_29_qs; end - addr_hit[372]: begin + addr_hit[366]: begin reg_rdata_next[0] = mio_pad_sleep_en_30_qs; end - addr_hit[373]: begin + addr_hit[367]: begin reg_rdata_next[0] = mio_pad_sleep_en_31_qs; end - addr_hit[374]: begin + addr_hit[368]: begin reg_rdata_next[0] = mio_pad_sleep_en_32_qs; end - addr_hit[375]: begin + addr_hit[369]: begin reg_rdata_next[0] = mio_pad_sleep_en_33_qs; end - addr_hit[376]: begin + addr_hit[370]: begin reg_rdata_next[0] = mio_pad_sleep_en_34_qs; end - addr_hit[377]: begin + addr_hit[371]: begin reg_rdata_next[0] = mio_pad_sleep_en_35_qs; end - addr_hit[378]: begin + addr_hit[372]: begin reg_rdata_next[0] = mio_pad_sleep_en_36_qs; end - addr_hit[379]: begin + addr_hit[373]: begin reg_rdata_next[0] = mio_pad_sleep_en_37_qs; end - addr_hit[380]: begin + addr_hit[374]: begin reg_rdata_next[0] = mio_pad_sleep_en_38_qs; end - addr_hit[381]: begin + addr_hit[375]: begin reg_rdata_next[0] = mio_pad_sleep_en_39_qs; end - addr_hit[382]: begin + addr_hit[376]: begin reg_rdata_next[0] = mio_pad_sleep_en_40_qs; end - addr_hit[383]: begin + addr_hit[377]: begin reg_rdata_next[0] = mio_pad_sleep_en_41_qs; end - addr_hit[384]: begin + addr_hit[378]: begin reg_rdata_next[0] = mio_pad_sleep_en_42_qs; end - addr_hit[385]: begin + addr_hit[379]: begin reg_rdata_next[0] = mio_pad_sleep_en_43_qs; end - addr_hit[386]: begin + addr_hit[380]: begin reg_rdata_next[0] = mio_pad_sleep_en_44_qs; end - addr_hit[387]: begin + addr_hit[381]: begin reg_rdata_next[0] = mio_pad_sleep_en_45_qs; end - addr_hit[388]: begin + addr_hit[382]: begin reg_rdata_next[0] = mio_pad_sleep_en_46_qs; end - addr_hit[389]: begin + addr_hit[383]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_0_qs; end - addr_hit[390]: begin + addr_hit[384]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_1_qs; end - addr_hit[391]: begin + addr_hit[385]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_2_qs; end - addr_hit[392]: begin + addr_hit[386]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_3_qs; end - addr_hit[393]: begin + addr_hit[387]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_4_qs; end - addr_hit[394]: begin + addr_hit[388]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_5_qs; end - addr_hit[395]: begin + addr_hit[389]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_6_qs; end - addr_hit[396]: begin + addr_hit[390]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_7_qs; end - addr_hit[397]: begin + addr_hit[391]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_8_qs; end - addr_hit[398]: begin + addr_hit[392]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_9_qs; end - addr_hit[399]: begin + addr_hit[393]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_10_qs; end - addr_hit[400]: begin + addr_hit[394]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_11_qs; end - addr_hit[401]: begin + addr_hit[395]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_12_qs; end - addr_hit[402]: begin + addr_hit[396]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_13_qs; end - addr_hit[403]: begin + addr_hit[397]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_14_qs; end - addr_hit[404]: begin + addr_hit[398]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_15_qs; end - addr_hit[405]: begin + addr_hit[399]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_16_qs; end - addr_hit[406]: begin + addr_hit[400]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_17_qs; end - addr_hit[407]: begin + addr_hit[401]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_18_qs; end - addr_hit[408]: begin + addr_hit[402]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_19_qs; end - addr_hit[409]: begin + addr_hit[403]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_20_qs; end - addr_hit[410]: begin + addr_hit[404]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_21_qs; end - addr_hit[411]: begin + addr_hit[405]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_22_qs; end - addr_hit[412]: begin + addr_hit[406]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_23_qs; end - addr_hit[413]: begin + addr_hit[407]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_24_qs; end - addr_hit[414]: begin + addr_hit[408]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_25_qs; end - addr_hit[415]: begin + addr_hit[409]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_26_qs; end - addr_hit[416]: begin + addr_hit[410]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_27_qs; end - addr_hit[417]: begin + addr_hit[411]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_28_qs; end - addr_hit[418]: begin + addr_hit[412]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_29_qs; end - addr_hit[419]: begin + addr_hit[413]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_30_qs; end - addr_hit[420]: begin + addr_hit[414]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_31_qs; end - addr_hit[421]: begin + addr_hit[415]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_32_qs; end - addr_hit[422]: begin + addr_hit[416]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_33_qs; end - addr_hit[423]: begin + addr_hit[417]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_34_qs; end - addr_hit[424]: begin + addr_hit[418]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_35_qs; end - addr_hit[425]: begin + addr_hit[419]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_36_qs; end - addr_hit[426]: begin + addr_hit[420]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_37_qs; end - addr_hit[427]: begin + addr_hit[421]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_38_qs; end - addr_hit[428]: begin + addr_hit[422]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_39_qs; end - addr_hit[429]: begin + addr_hit[423]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_40_qs; end - addr_hit[430]: begin + addr_hit[424]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_41_qs; end - addr_hit[431]: begin + addr_hit[425]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_42_qs; end - addr_hit[432]: begin + addr_hit[426]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_43_qs; end - addr_hit[433]: begin + addr_hit[427]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_44_qs; end - addr_hit[434]: begin + addr_hit[428]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_45_qs; end - addr_hit[435]: begin + addr_hit[429]: begin reg_rdata_next[1:0] = mio_pad_sleep_mode_46_qs; end - addr_hit[436]: begin + addr_hit[430]: begin reg_rdata_next[0] = dio_pad_sleep_status_en_0_qs; reg_rdata_next[1] = dio_pad_sleep_status_en_1_qs; reg_rdata_next[2] = dio_pad_sleep_status_en_2_qs; @@ -37315,311 +37054,311 @@ module pinmux_reg_top ( reg_rdata_next[13] = dio_pad_sleep_status_en_13_qs; end - addr_hit[437]: begin + addr_hit[431]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_0_qs; end - addr_hit[438]: begin + addr_hit[432]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_1_qs; end - addr_hit[439]: begin + addr_hit[433]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_2_qs; end - addr_hit[440]: begin + addr_hit[434]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_3_qs; end - addr_hit[441]: begin + addr_hit[435]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_4_qs; end - addr_hit[442]: begin + addr_hit[436]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_5_qs; end - addr_hit[443]: begin + addr_hit[437]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_6_qs; end - addr_hit[444]: begin + addr_hit[438]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_7_qs; end - addr_hit[445]: begin + addr_hit[439]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_8_qs; end - addr_hit[446]: begin + addr_hit[440]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_9_qs; end - addr_hit[447]: begin + addr_hit[441]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_10_qs; end - addr_hit[448]: begin + addr_hit[442]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_11_qs; end - addr_hit[449]: begin + addr_hit[443]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_12_qs; end - addr_hit[450]: begin + addr_hit[444]: begin reg_rdata_next[0] = dio_pad_sleep_regwen_13_qs; end - addr_hit[451]: begin + addr_hit[445]: begin reg_rdata_next[0] = dio_pad_sleep_en_0_qs; end - addr_hit[452]: begin + addr_hit[446]: begin reg_rdata_next[0] = dio_pad_sleep_en_1_qs; end - addr_hit[453]: begin + addr_hit[447]: begin reg_rdata_next[0] = dio_pad_sleep_en_2_qs; end - addr_hit[454]: begin + addr_hit[448]: begin reg_rdata_next[0] = dio_pad_sleep_en_3_qs; end - addr_hit[455]: begin + addr_hit[449]: begin reg_rdata_next[0] = dio_pad_sleep_en_4_qs; end - addr_hit[456]: begin + addr_hit[450]: begin reg_rdata_next[0] = dio_pad_sleep_en_5_qs; end - addr_hit[457]: begin + addr_hit[451]: begin reg_rdata_next[0] = dio_pad_sleep_en_6_qs; end - addr_hit[458]: begin + addr_hit[452]: begin reg_rdata_next[0] = dio_pad_sleep_en_7_qs; end - addr_hit[459]: begin + addr_hit[453]: begin reg_rdata_next[0] = dio_pad_sleep_en_8_qs; end - addr_hit[460]: begin + addr_hit[454]: begin reg_rdata_next[0] = dio_pad_sleep_en_9_qs; end - addr_hit[461]: begin + addr_hit[455]: begin reg_rdata_next[0] = dio_pad_sleep_en_10_qs; end - addr_hit[462]: begin + addr_hit[456]: begin reg_rdata_next[0] = dio_pad_sleep_en_11_qs; end - addr_hit[463]: begin + addr_hit[457]: begin reg_rdata_next[0] = dio_pad_sleep_en_12_qs; end - addr_hit[464]: begin + addr_hit[458]: begin reg_rdata_next[0] = dio_pad_sleep_en_13_qs; end - addr_hit[465]: begin + addr_hit[459]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_0_qs; end - addr_hit[466]: begin + addr_hit[460]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_1_qs; end - addr_hit[467]: begin + addr_hit[461]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_2_qs; end - addr_hit[468]: begin + addr_hit[462]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_3_qs; end - addr_hit[469]: begin + addr_hit[463]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_4_qs; end - addr_hit[470]: begin + addr_hit[464]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_5_qs; end - addr_hit[471]: begin + addr_hit[465]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_6_qs; end - addr_hit[472]: begin + addr_hit[466]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_7_qs; end - addr_hit[473]: begin + addr_hit[467]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_8_qs; end - addr_hit[474]: begin + addr_hit[468]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_9_qs; end - addr_hit[475]: begin + addr_hit[469]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_10_qs; end - addr_hit[476]: begin + addr_hit[470]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_11_qs; end - addr_hit[477]: begin + addr_hit[471]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_12_qs; end - addr_hit[478]: begin + addr_hit[472]: begin reg_rdata_next[1:0] = dio_pad_sleep_mode_13_qs; end - addr_hit[479]: begin + addr_hit[473]: begin reg_rdata_next[0] = wkup_detector_regwen_0_qs; end - addr_hit[480]: begin + addr_hit[474]: begin reg_rdata_next[0] = wkup_detector_regwen_1_qs; end - addr_hit[481]: begin + addr_hit[475]: begin reg_rdata_next[0] = wkup_detector_regwen_2_qs; end - addr_hit[482]: begin + addr_hit[476]: begin reg_rdata_next[0] = wkup_detector_regwen_3_qs; end - addr_hit[483]: begin + addr_hit[477]: begin reg_rdata_next[0] = wkup_detector_regwen_4_qs; end - addr_hit[484]: begin + addr_hit[478]: begin reg_rdata_next[0] = wkup_detector_regwen_5_qs; end - addr_hit[485]: begin + addr_hit[479]: begin reg_rdata_next[0] = wkup_detector_regwen_6_qs; end - addr_hit[486]: begin + addr_hit[480]: begin reg_rdata_next[0] = wkup_detector_regwen_7_qs; end - addr_hit[487]: begin + addr_hit[481]: begin reg_rdata_next = DW'(wkup_detector_en_0_qs); end - addr_hit[488]: begin + addr_hit[482]: begin reg_rdata_next = DW'(wkup_detector_en_1_qs); end - addr_hit[489]: begin + addr_hit[483]: begin reg_rdata_next = DW'(wkup_detector_en_2_qs); end - addr_hit[490]: begin + addr_hit[484]: begin reg_rdata_next = DW'(wkup_detector_en_3_qs); end - addr_hit[491]: begin + addr_hit[485]: begin reg_rdata_next = DW'(wkup_detector_en_4_qs); end - addr_hit[492]: begin + addr_hit[486]: begin reg_rdata_next = DW'(wkup_detector_en_5_qs); end - addr_hit[493]: begin + addr_hit[487]: begin reg_rdata_next = DW'(wkup_detector_en_6_qs); end - addr_hit[494]: begin + addr_hit[488]: begin reg_rdata_next = DW'(wkup_detector_en_7_qs); end - addr_hit[495]: begin + addr_hit[489]: begin reg_rdata_next = DW'(wkup_detector_0_qs); end - addr_hit[496]: begin + addr_hit[490]: begin reg_rdata_next = DW'(wkup_detector_1_qs); end - addr_hit[497]: begin + addr_hit[491]: begin reg_rdata_next = DW'(wkup_detector_2_qs); end - addr_hit[498]: begin + addr_hit[492]: begin reg_rdata_next = DW'(wkup_detector_3_qs); end - addr_hit[499]: begin + addr_hit[493]: begin reg_rdata_next = DW'(wkup_detector_4_qs); end - addr_hit[500]: begin + addr_hit[494]: begin reg_rdata_next = DW'(wkup_detector_5_qs); end - addr_hit[501]: begin + addr_hit[495]: begin reg_rdata_next = DW'(wkup_detector_6_qs); end - addr_hit[502]: begin + addr_hit[496]: begin reg_rdata_next = DW'(wkup_detector_7_qs); end - addr_hit[503]: begin + addr_hit[497]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_0_qs); end - addr_hit[504]: begin + addr_hit[498]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_1_qs); end - addr_hit[505]: begin + addr_hit[499]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_2_qs); end - addr_hit[506]: begin + addr_hit[500]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_3_qs); end - addr_hit[507]: begin + addr_hit[501]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_4_qs); end - addr_hit[508]: begin + addr_hit[502]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_5_qs); end - addr_hit[509]: begin + addr_hit[503]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_6_qs); end - addr_hit[510]: begin + addr_hit[504]: begin reg_rdata_next = DW'(wkup_detector_cnt_th_7_qs); end - addr_hit[511]: begin + addr_hit[505]: begin reg_rdata_next[5:0] = wkup_detector_padsel_0_qs; end - addr_hit[512]: begin + addr_hit[506]: begin reg_rdata_next[5:0] = wkup_detector_padsel_1_qs; end - addr_hit[513]: begin + addr_hit[507]: begin reg_rdata_next[5:0] = wkup_detector_padsel_2_qs; end - addr_hit[514]: begin + addr_hit[508]: begin reg_rdata_next[5:0] = wkup_detector_padsel_3_qs; end - addr_hit[515]: begin + addr_hit[509]: begin reg_rdata_next[5:0] = wkup_detector_padsel_4_qs; end - addr_hit[516]: begin + addr_hit[510]: begin reg_rdata_next[5:0] = wkup_detector_padsel_5_qs; end - addr_hit[517]: begin + addr_hit[511]: begin reg_rdata_next[5:0] = wkup_detector_padsel_6_qs; end - addr_hit[518]: begin + addr_hit[512]: begin reg_rdata_next[5:0] = wkup_detector_padsel_7_qs; end - addr_hit[519]: begin + addr_hit[513]: begin reg_rdata_next = DW'(wkup_cause_qs); end default: begin @@ -37638,79 +37377,79 @@ module pinmux_reg_top ( always_comb begin reg_busy_sel = '0; unique case (1'b1) - addr_hit[487]: begin + addr_hit[481]: begin reg_busy_sel = wkup_detector_en_0_busy; end - addr_hit[488]: begin + addr_hit[482]: begin reg_busy_sel = wkup_detector_en_1_busy; end - addr_hit[489]: begin + addr_hit[483]: begin reg_busy_sel = wkup_detector_en_2_busy; end - addr_hit[490]: begin + addr_hit[484]: begin reg_busy_sel = wkup_detector_en_3_busy; end - addr_hit[491]: begin + addr_hit[485]: begin reg_busy_sel = wkup_detector_en_4_busy; end - addr_hit[492]: begin + addr_hit[486]: begin reg_busy_sel = wkup_detector_en_5_busy; end - addr_hit[493]: begin + addr_hit[487]: begin reg_busy_sel = wkup_detector_en_6_busy; end - addr_hit[494]: begin + addr_hit[488]: begin reg_busy_sel = wkup_detector_en_7_busy; end - addr_hit[495]: begin + addr_hit[489]: begin reg_busy_sel = wkup_detector_0_busy; end - addr_hit[496]: begin + addr_hit[490]: begin reg_busy_sel = wkup_detector_1_busy; end - addr_hit[497]: begin + addr_hit[491]: begin reg_busy_sel = wkup_detector_2_busy; end - addr_hit[498]: begin + addr_hit[492]: begin reg_busy_sel = wkup_detector_3_busy; end - addr_hit[499]: begin + addr_hit[493]: begin reg_busy_sel = wkup_detector_4_busy; end - addr_hit[500]: begin + addr_hit[494]: begin reg_busy_sel = wkup_detector_5_busy; end - addr_hit[501]: begin + addr_hit[495]: begin reg_busy_sel = wkup_detector_6_busy; end - addr_hit[502]: begin + addr_hit[496]: begin reg_busy_sel = wkup_detector_7_busy; end - addr_hit[503]: begin + addr_hit[497]: begin reg_busy_sel = wkup_detector_cnt_th_0_busy; end - addr_hit[504]: begin + addr_hit[498]: begin reg_busy_sel = wkup_detector_cnt_th_1_busy; end - addr_hit[505]: begin + addr_hit[499]: begin reg_busy_sel = wkup_detector_cnt_th_2_busy; end - addr_hit[506]: begin + addr_hit[500]: begin reg_busy_sel = wkup_detector_cnt_th_3_busy; end - addr_hit[507]: begin + addr_hit[501]: begin reg_busy_sel = wkup_detector_cnt_th_4_busy; end - addr_hit[508]: begin + addr_hit[502]: begin reg_busy_sel = wkup_detector_cnt_th_5_busy; end - addr_hit[509]: begin + addr_hit[503]: begin reg_busy_sel = wkup_detector_cnt_th_6_busy; end - addr_hit[510]: begin + addr_hit[504]: begin reg_busy_sel = wkup_detector_cnt_th_7_busy; end - addr_hit[519]: begin + addr_hit[513]: begin reg_busy_sel = wkup_cause_busy; end default: begin diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv index fbbd927825b..3582cc43173 100644 --- a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv +++ b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv @@ -37,6 +37,7 @@ module top_englishbreakfast #( parameter bit SecFlashCtrlScrambleEn = 0, parameter int FlashCtrlProgFifoDepth = 16, parameter int FlashCtrlRdFifoDepth = 16, + // parameters for flash_macro_wrapper // parameters for rv_plic // parameters for aes parameter bit SecAesMasking = 1, @@ -178,9 +179,9 @@ module top_englishbreakfast #( localparam bit RvCoreIbexInstructionPipeline = 1'b0; // Signals - logic [37:0] mio_p2d; - logic [34:0] mio_d2p; - logic [34:0] mio_en_d2p; + logic [34:0] mio_p2d; + logic [33:0] mio_d2p; + logic [33:0] mio_en_d2p; logic [13:0] dio_p2d; logic [13:0] dio_d2p; logic [13:0] dio_en_d2p; @@ -226,11 +227,12 @@ module top_englishbreakfast #( // pinmux_aon // aon_timer_aon // flash_ctrl - logic cio_flash_ctrl_tck_p2d; - logic cio_flash_ctrl_tms_p2d; - logic cio_flash_ctrl_tdi_p2d; - logic cio_flash_ctrl_tdo_d2p; - logic cio_flash_ctrl_tdo_en_d2p; + // flash_macro_wrapper + logic cio_flash_macro_wrapper_tck_p2d; + logic cio_flash_macro_wrapper_tms_p2d; + logic cio_flash_macro_wrapper_tdi_p2d; + logic cio_flash_macro_wrapper_tdo_d2p; + logic cio_flash_macro_wrapper_tdo_en_d2p; // rv_plic // aes // sram_ctrl_main @@ -318,6 +320,9 @@ module top_englishbreakfast #( logic usbdev_usb_aon_sense_lost; logic pinmux_aon_usbdev_wake_detect_active; prim_mubi_pkg::mubi4_t clkmgr_aon_idle; + flash_phy_macro_pkg::flash_phy_macro_req_t flash_ctrl_flash_macro_req; + flash_phy_macro_pkg::flash_phy_macro_rsp_t flash_ctrl_flash_macro_rsp; + flash_phy_macro_pkg::flash_macro_status_t flash_ctrl_flash_macro_status; logic rv_plic_msip; logic rv_plic_irq; rv_core_ibex_pkg::cpu_crash_dump_t rv_core_ibex_crash_dump; @@ -339,8 +344,8 @@ module top_englishbreakfast #( tlul_pkg::tl_d2h_t main_tl_peri_rsp; tlul_pkg::tl_h2d_t flash_ctrl_core_tl_req; tlul_pkg::tl_d2h_t flash_ctrl_core_tl_rsp; - tlul_pkg::tl_h2d_t flash_ctrl_prim_tl_req; - tlul_pkg::tl_d2h_t flash_ctrl_prim_tl_rsp; + tlul_pkg::tl_h2d_t flash_macro_wrapper_tl_req; + tlul_pkg::tl_d2h_t flash_macro_wrapper_tl_rsp; tlul_pkg::tl_h2d_t flash_ctrl_mem_tl_req; tlul_pkg::tl_d2h_t flash_ctrl_mem_tl_rsp; tlul_pkg::tl_h2d_t aes_tl_req; @@ -429,6 +434,9 @@ module top_englishbreakfast #( // secure_lc_io_div4_0 assign lpg_cg_en[0] = clkmgr_aon_cg_en.io_div4_secure; assign lpg_rst_en[0] = rstmgr_aon_rst_en.lc_io_div4[rstmgr_pkg::Domain0Sel]; + // infra_lc_0 + assign lpg_cg_en[1] = clkmgr_aon_cg_en.main_infra; + assign lpg_rst_en[1] = rstmgr_aon_rst_en.lc[rstmgr_pkg::Domain0Sel]; // Outgoing LPGs for alert group englishbreakfast // peri_lc_io_div4_0 @@ -1086,15 +1094,6 @@ module top_englishbreakfast #( .RdFifoDepth(FlashCtrlRdFifoDepth) ) u_flash_ctrl ( - // Input - .cio_tck_i (cio_flash_ctrl_tck_p2d), - .cio_tms_i (cio_flash_ctrl_tms_p2d), - .cio_tdi_i (cio_flash_ctrl_tdi_p2d), - - // Output - .cio_tdo_o (cio_flash_ctrl_tdo_d2p), - .cio_tdo_en_o (cio_flash_ctrl_tdo_en_d2p), - // Interrupt .intr_prog_empty_o (intr_flash_ctrl_prog_empty), .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl), @@ -1113,12 +1112,6 @@ module top_englishbreakfast #( // Inter-module signals .otp_o(), .otp_i(otp_ctrl_pkg::FLASH_OTP_KEY_RSP_DEFAULT), - .lc_nvm_debug_en_i(lc_ctrl_pkg::LC_TX_DEFAULT), - .flash_bist_enable_i(flash_bist_enable_i), - .flash_power_down_h_i(flash_power_down_h_i), - .flash_power_ready_h_i(flash_power_ready_h_i), - .flash_test_mode_a_io(), - .flash_test_voltage_h_io(), .lc_creator_seed_sw_rw_en_i(lc_ctrl_pkg::LC_TX_DEFAULT), .lc_owner_seed_sw_rw_en_i(lc_ctrl_pkg::LC_TX_DEFAULT), .lc_iso_part_sw_rd_en_i(lc_ctrl_pkg::LC_TX_DEFAULT), @@ -1130,17 +1123,13 @@ module top_englishbreakfast #( .rma_seed_i(lc_ctrl_pkg::LC_FLASH_RMA_SEED_DEFAULT), .pwrmgr_o(pwrmgr_aon_pwr_flash), .keymgr_o(), - .obs_ctrl_i(obs_ctrl_i), - .fla_obs_o(flash_obs_o), + .flash_macro_o(flash_ctrl_flash_macro_req), + .flash_macro_i(flash_ctrl_flash_macro_rsp), + .flash_macro_status_i(flash_ctrl_flash_macro_status), .core_tl_i(flash_ctrl_core_tl_req), .core_tl_o(flash_ctrl_core_tl_rsp), - .prim_tl_i(flash_ctrl_prim_tl_req), - .prim_tl_o(flash_ctrl_prim_tl_rsp), .mem_tl_i(flash_ctrl_mem_tl_req), .mem_tl_o(flash_ctrl_mem_tl_rsp), - .scanmode_i, - .scan_rst_ni, - .scan_en_i, // Clock and reset connections .clk_i (clkmgr_aon_clocks.clk_main_infra), @@ -1149,6 +1138,48 @@ module top_englishbreakfast #( .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]), .rst_otp_ni (rstmgr_aon_resets.rst_lc_io_div4_n[rstmgr_pkg::Domain0Sel]) ); + flash_macro_wrapper #( + .NumBanks(2), + .InfosPerBank(10), + .InfoTypes(3), + .InfoTypesWidth(2), + .PagesPerBank(16), + .WordsPerPage(256), + .DataWidth(72), + .TestModeWidth(2) + ) u_flash_macro_wrapper ( + + // Input + .cio_tck_i (cio_flash_macro_wrapper_tck_p2d), + .cio_tms_i (cio_flash_macro_wrapper_tms_p2d), + .cio_tdi_i (cio_flash_macro_wrapper_tdi_p2d), + + // Output + .cio_tdo_o (cio_flash_macro_wrapper_tdo_d2p), + .cio_tdo_en_o (cio_flash_macro_wrapper_tdo_en_d2p), + + // Inter-module signals + .flash_i(flash_ctrl_flash_macro_req), + .flash_o(flash_ctrl_flash_macro_rsp), + .status_o(flash_ctrl_flash_macro_status), + .lc_nvm_debug_en_i(lc_ctrl_pkg::LC_TX_DEFAULT), + .bist_enable_i(flash_bist_enable_i), + .power_down_h_i(flash_power_down_h_i), + .power_ready_h_i(flash_power_ready_h_i), + .test_mode_a_io(), + .test_voltage_h_io(), + .obs_ctrl_i(obs_ctrl_i), + .fla_obs_o(flash_obs_o), + .tl_i(flash_macro_wrapper_tl_req), + .tl_o(flash_macro_wrapper_tl_rsp), + .scanmode_i, + .scan_rst_ni, + .scan_en_i, + + // Clock and reset connections + .clk_i (clkmgr_aon_clocks.clk_main_infra), + .rst_ni (rstmgr_aon_resets.rst_lc_n[rstmgr_pkg::Domain0Sel]) + ); rv_plic #( .AlertAsyncOn(AsyncOnOutgoingAlertEnglishbreakfast[19:19]), .AlertSkewCycles(top_pkg::AlertSkewCycles) @@ -1461,9 +1492,9 @@ module top_englishbreakfast #( .tl_flash_ctrl__core_o(flash_ctrl_core_tl_req), .tl_flash_ctrl__core_i(flash_ctrl_core_tl_rsp), - // port: tl_flash_ctrl__prim - .tl_flash_ctrl__prim_o(flash_ctrl_prim_tl_req), - .tl_flash_ctrl__prim_i(flash_ctrl_prim_tl_rsp), + // port: tl_flash_macro_wrapper + .tl_flash_macro_wrapper_o(flash_macro_wrapper_tl_req), + .tl_flash_macro_wrapper_i(flash_macro_wrapper_tl_rsp), // port: tl_flash_ctrl__mem .tl_flash_ctrl__mem_o(flash_ctrl_mem_tl_req), @@ -1592,9 +1623,6 @@ module top_englishbreakfast #( assign cio_gpio_gpio_p2d[31] = mio_p2d[MioInGpioGpio31]; assign cio_uart0_rx_p2d = mio_p2d[MioInUart0Rx]; assign cio_uart1_rx_p2d = mio_p2d[MioInUart1Rx]; - assign cio_flash_ctrl_tck_p2d = mio_p2d[MioInFlashCtrlTck]; - assign cio_flash_ctrl_tms_p2d = mio_p2d[MioInFlashCtrlTms]; - assign cio_flash_ctrl_tdi_p2d = mio_p2d[MioInFlashCtrlTdi]; assign cio_usbdev_sense_p2d = mio_p2d[MioInUsbdevSense]; // All muxed outputs @@ -1632,7 +1660,6 @@ module top_englishbreakfast #( assign mio_d2p[MioOutGpioGpio31] = cio_gpio_gpio_d2p[31]; assign mio_d2p[MioOutUart0Tx] = cio_uart0_tx_d2p; assign mio_d2p[MioOutUart1Tx] = cio_uart1_tx_d2p; - assign mio_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_d2p; // All muxed output enables assign mio_en_d2p[MioOutGpioGpio0] = cio_gpio_gpio_en_d2p[0]; @@ -1669,7 +1696,6 @@ module top_englishbreakfast #( assign mio_en_d2p[MioOutGpioGpio31] = cio_gpio_gpio_en_d2p[31]; assign mio_en_d2p[MioOutUart0Tx] = cio_uart0_tx_en_d2p; assign mio_en_d2p[MioOutUart1Tx] = cio_uart1_tx_en_d2p; - assign mio_en_d2p[MioOutFlashCtrlTdo] = cio_flash_ctrl_tdo_en_d2p; // All dedicated inputs logic [13:0] unused_dio_p2d; diff --git a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv index 78abb489918..d152ce978d8 100644 --- a/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv +++ b/hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast_pkg.sv @@ -150,14 +150,14 @@ package top_englishbreakfast_pkg; parameter int unsigned TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES = 32'h200; /** - * Peripheral base address for prim device on flash_ctrl in top englishbreakfast. + * Peripheral base address for flash_macro_wrapper in top englishbreakfast. */ - parameter int unsigned TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR = 32'h41008000; + parameter int unsigned TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR = 32'h41008000; /** - * Peripheral size in bytes for prim device on flash_ctrl in top englishbreakfast. + * Peripheral size in bytes for flash_macro_wrapper in top englishbreakfast. */ - parameter int unsigned TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES = 32'h80; + parameter int unsigned TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_SIZE_BYTES = 32'h80; /** * Peripheral base address for rv_plic in top englishbreakfast. @@ -474,11 +474,8 @@ package top_englishbreakfast_pkg; MioInGpioGpio31 = 31, MioInUart0Rx = 32, MioInUart1Rx = 33, - MioInFlashCtrlTck = 34, - MioInFlashCtrlTms = 35, - MioInFlashCtrlTdi = 36, - MioInUsbdevSense = 37, - MioInCount = 38 + MioInUsbdevSense = 34, + MioInCount = 35 } mio_in_e; typedef enum { @@ -516,8 +513,7 @@ package top_englishbreakfast_pkg; MioOutGpioGpio31 = 31, MioOutUart0Tx = 32, MioOutUart1Tx = 33, - MioOutFlashCtrlTdo = 34, - MioOutCount = 35 + MioOutCount = 34 } mio_out_e; // Enumeration for DIO signals, used on both the top and chip-levels. @@ -630,6 +626,7 @@ package top_englishbreakfast_pkg; PeripheralAst, PeripheralClkmgrAon, PeripheralFlashCtrl, + PeripheralFlashMacroWrapper, PeripheralGpio, PeripheralPinmuxAon, PeripheralPwrmgrAon, diff --git a/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs b/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs index e7d0d8b05c5..9befb7445e2 100644 --- a/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs +++ b/hw/top_englishbreakfast/sw/autogen/chip/top_englishbreakfast.rs @@ -217,19 +217,19 @@ pub const FLASH_CTRL_CORE_BASE_ADDR: usize = 0x41000000; /// `FLASH_CTRL_CORE_BASE_ADDR + FLASH_CTRL_CORE_SIZE_BYTES`. pub const FLASH_CTRL_CORE_SIZE_BYTES: usize = 0x200; -/// Peripheral base address for prim device on flash_ctrl in top englishbreakfast. +/// Peripheral base address for flash_macro_wrapper in top englishbreakfast. /// /// This should be used with #mmio_region_from_addr to access the memory-mapped /// registers associated with the peripheral (usually via a DIF). -pub const FLASH_CTRL_PRIM_BASE_ADDR: usize = 0x41008000; +pub const FLASH_MACRO_WRAPPER_BASE_ADDR: usize = 0x41008000; -/// Peripheral size for prim device on flash_ctrl in top englishbreakfast. +/// Peripheral size for flash_macro_wrapper in top englishbreakfast. /// /// This is the size (in bytes) of the peripheral's reserved memory area. All /// memory-mapped registers associated with this peripheral should have an -/// address between #FLASH_CTRL_PRIM_BASE_ADDR and -/// `FLASH_CTRL_PRIM_BASE_ADDR + FLASH_CTRL_PRIM_SIZE_BYTES`. -pub const FLASH_CTRL_PRIM_SIZE_BYTES: usize = 0x80; +/// address between #FLASH_MACRO_WRAPPER_BASE_ADDR and +/// `FLASH_MACRO_WRAPPER_BASE_ADDR + FLASH_MACRO_WRAPPER_SIZE_BYTES`. +pub const FLASH_MACRO_WRAPPER_SIZE_BYTES: usize = 0x80; /// Peripheral base address for rv_plic in top englishbreakfast. /// @@ -924,13 +924,7 @@ pub enum PinmuxPeripheralIn { /// Peripheral Input 33 Uart1Rx = 33, /// Peripheral Input 34 - FlashCtrlTck = 34, - /// Peripheral Input 35 - FlashCtrlTms = 35, - /// Peripheral Input 36 - FlashCtrlTdi = 36, - /// Peripheral Input 37 - UsbdevSense = 37, + UsbdevSense = 34, } impl TryFrom for PinmuxPeripheralIn { @@ -971,10 +965,7 @@ impl TryFrom for PinmuxPeripheralIn { 31 => Ok(Self::GpioGpio31), 32 => Ok(Self::Uart0Rx), 33 => Ok(Self::Uart1Rx), - 34 => Ok(Self::FlashCtrlTck), - 35 => Ok(Self::FlashCtrlTms), - 36 => Ok(Self::FlashCtrlTdi), - 37 => Ok(Self::UsbdevSense), + 34 => Ok(Self::UsbdevSense), _ => Err(val), } } @@ -1376,8 +1367,6 @@ pub enum PinmuxOutsel { Uart0Tx = 35, /// Peripheral Output 33 Uart1Tx = 36, - /// Peripheral Output 34 - FlashCtrlTdo = 37, } impl TryFrom for PinmuxOutsel { @@ -1421,7 +1410,6 @@ impl TryFrom for PinmuxOutsel { 34 => Ok(Self::GpioGpio31), 35 => Ok(Self::Uart0Tx), 36 => Ok(Self::Uart1Tx), - 37 => Ok(Self::FlashCtrlTdo), _ => Err(val), } } diff --git a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h index a07eeac22dd..9e67786654a 100644 --- a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h +++ b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast.h @@ -282,22 +282,22 @@ extern "C" { #define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200u /** - * Peripheral base address for prim device on flash_ctrl in top englishbreakfast. + * Peripheral base address for flash_macro_wrapper in top englishbreakfast. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000u +#define TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000u /** - * Peripheral size for prim device on flash_ctrl in top englishbreakfast. + * Peripheral size for flash_macro_wrapper in top englishbreakfast. * * This is the size (in bytes) of the peripheral's reserved memory area. All * memory-mapped registers associated with this peripheral should have an - * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES`. + * address between #TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR and + * `TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_SIZE_BYTES`. */ -#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80u +#define TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80u /** * Peripheral base address for rv_plic in top englishbreakfast. @@ -607,11 +607,8 @@ typedef enum top_englishbreakfast_pinmux_peripheral_in { kTopEnglishbreakfastPinmuxPeripheralInGpioGpio31 = 31, /**< Peripheral Input 31 */ kTopEnglishbreakfastPinmuxPeripheralInUart0Rx = 32, /**< Peripheral Input 32 */ kTopEnglishbreakfastPinmuxPeripheralInUart1Rx = 33, /**< Peripheral Input 33 */ - kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTck = 34, /**< Peripheral Input 34 */ - kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTms = 35, /**< Peripheral Input 35 */ - kTopEnglishbreakfastPinmuxPeripheralInFlashCtrlTdi = 36, /**< Peripheral Input 36 */ - kTopEnglishbreakfastPinmuxPeripheralInUsbdevSense = 37, /**< Peripheral Input 37 */ - kTopEnglishbreakfastPinmuxPeripheralInLast = 37, /**< \internal Last valid peripheral input */ + kTopEnglishbreakfastPinmuxPeripheralInUsbdevSense = 34, /**< Peripheral Input 34 */ + kTopEnglishbreakfastPinmuxPeripheralInLast = 34, /**< \internal Last valid peripheral input */ } top_englishbreakfast_pinmux_peripheral_in_t; /** @@ -765,8 +762,7 @@ typedef enum top_englishbreakfast_pinmux_outsel { kTopEnglishbreakfastPinmuxOutselGpioGpio31 = 34, /**< Peripheral Output 31 */ kTopEnglishbreakfastPinmuxOutselUart0Tx = 35, /**< Peripheral Output 32 */ kTopEnglishbreakfastPinmuxOutselUart1Tx = 36, /**< Peripheral Output 33 */ - kTopEnglishbreakfastPinmuxOutselFlashCtrlTdo = 37, /**< Peripheral Output 34 */ - kTopEnglishbreakfastPinmuxOutselLast = 37, /**< \internal Last valid outsel value */ + kTopEnglishbreakfastPinmuxOutselLast = 36, /**< \internal Last valid outsel value */ } top_englishbreakfast_pinmux_outsel_t; /** diff --git a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h index eb17534bacc..6f790532124 100644 --- a/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h +++ b/hw/top_englishbreakfast/sw/autogen/top_englishbreakfast_memory.h @@ -295,22 +295,22 @@ */ #define TOP_ENGLISHBREAKFAST_FLASH_CTRL_CORE_SIZE_BYTES 0x200 /** - * Peripheral base address for prim device on flash_ctrl in top englishbreakfast. + * Peripheral base address for flash_macro_wrapper in top englishbreakfast. * * This should be used with #mmio_region_from_addr to access the memory-mapped * registers associated with the peripheral (usually via a DIF). */ -#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR 0x41008000 +#define TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR 0x41008000 /** - * Peripheral size for prim device on flash_ctrl in top englishbreakfast. + * Peripheral size for flash_macro_wrapper in top englishbreakfast. * * This is the size (in bytes) of the peripheral's reserved memory area. All * memory-mapped registers associated with this peripheral should have an - * address between #TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR and - * `TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES`. + * address between #TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR and + * `TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_BASE_ADDR + TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_SIZE_BYTES`. */ -#define TOP_ENGLISHBREAKFAST_FLASH_CTRL_PRIM_SIZE_BYTES 0x80 +#define TOP_ENGLISHBREAKFAST_FLASH_MACRO_WRAPPER_SIZE_BYTES 0x80 /** * Peripheral base address for rv_plic in top englishbreakfast. * diff --git a/hw/top_englishbreakfast/top_englishbreakfast.core b/hw/top_englishbreakfast/top_englishbreakfast.core index 9f510aa97d3..6f483b8b518 100644 --- a/hw/top_englishbreakfast/top_englishbreakfast.core +++ b/hw/top_englishbreakfast/top_englishbreakfast.core @@ -1,5 +1,6 @@ CAPI=2: # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 name: "lowrisc:systems:top_englishbreakfast:0.1" @@ -17,7 +18,6 @@ filesets: - lowrisc:prim:all - lowrisc:prim:ram_1p_adv - lowrisc:prim:ram_1p_scr - - lowrisc:prim:flash - lowrisc:ip:sram_ctrl # Instantiated by topgen - lowrisc:ip:uart:0.1 @@ -26,6 +26,7 @@ filesets: - lowrisc:ip:spi_host - lowrisc:ip:aes - lowrisc:ip:entropy_src + - lowrisc:ip:flash_macro_wrapper - lowrisc:ip:hmac - lowrisc:ip:kmac - lowrisc:ip:keymgr diff --git a/hw/top_englishbreakfast/util/vivado_hook_write_bitstream_pre.tcl b/hw/top_englishbreakfast/util/vivado_hook_write_bitstream_pre.tcl index f4bb033fce4..f1e88d012e6 100644 --- a/hw/top_englishbreakfast/util/vivado_hook_write_bitstream_pre.tcl +++ b/hw/top_englishbreakfast/util/vivado_hook_write_bitstream_pre.tcl @@ -1,4 +1,5 @@ # Copyright lowRISC contributors (OpenTitan project). +# Copyright zeroRISC Inc. # Licensed under the Apache License, Version 2.0, see LICENSE for details. # SPDX-License-Identifier: Apache-2.0 @@ -217,9 +218,9 @@ dict set memInfo rom [apply $gen_mem_info $rom_brams $mem_type_regex 0 1 "Memory ## The flash banks have 76-bit wide words. 64 bits are data, and 12 bits are metadata / integrity. #for {set bank 0} {$bank < 2} {incr bank} { # for {set partition 0} {$partition < 3} {incr partition} { -# set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[0].*"] " "] +# set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_macro_wrapper*gen_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[0].*"] " "] # dict set memInfo "flash${bank}_info${partition}_data" [apply $gen_mem_info $flash_info_brams $mem_type_regex 0 1 "MemoryArray"] -# set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_ctrl*gen_prim_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[64].*"] " "] +# set flash_info_brams [split [get_cells -hierarchical -filter " PRIMITIVE_TYPE =~ ${bram_regex} && NAME =~ *u_flash_macro_wrapper*gen_flash_banks[${bank}]*gen_info_types[${partition}].u_info_mem*gen_xpm.gen_split[64].*"] " "] # dict set memInfo "flash${bank}_info${partition}_intg" [apply $gen_mem_info $flash_info_brams $mem_type_regex 0 1 "MemoryArray"] # } #} diff --git a/sw/device/lib/testing/json/pinmux.h b/sw/device/lib/testing/json/pinmux.h index 60aea099d9b..797d2bc2e17 100644 --- a/sw/device/lib/testing/json/pinmux.h +++ b/sw/device/lib/testing/json/pinmux.h @@ -1,4 +1,5 @@ // Copyright lowRISC contributors (OpenTitan project). +// Copyright zeroRISC Inc. // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 @@ -67,9 +68,9 @@ extern "C" { value(_, Uart2Rx, kTopEarlgreyPinmuxPeripheralInUart2Rx) \ value(_, Uart3Rx, kTopEarlgreyPinmuxPeripheralInUart3Rx) \ value(_, SpiDeviceTpmCsb, kTopEarlgreyPinmuxPeripheralInSpiDeviceTpmCsb) \ - value(_, FlashCtrlTck, kTopEarlgreyPinmuxPeripheralInFlashCtrlTck) \ - value(_, FlashCtrlTms, kTopEarlgreyPinmuxPeripheralInFlashCtrlTms) \ - value(_, FlashCtrlTdi, kTopEarlgreyPinmuxPeripheralInFlashCtrlTdi) \ + value(_, FlashCtrlTck, kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTck) \ + value(_, FlashCtrlTms, kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTms) \ + value(_, FlashCtrlTdi, kTopEarlgreyPinmuxPeripheralInFlashMacroWrapperTdi) \ value(_, SysrstCtrlAonAcPresent, kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonAcPresent) \ value(_, SysrstCtrlAonKey0In, kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey0In) \ value(_, SysrstCtrlAonKey1In, kTopEarlgreyPinmuxPeripheralInSysrstCtrlAonKey1In) \ @@ -240,7 +241,7 @@ C_ONLY(UJSON_SERDE_ENUM(PinmuxMioOut, pinmux_mio_out_t, TOP_EARLGREY_PINMUX_MIO_ value(_, PattgenPcl1Tx, kTopEarlgreyPinmuxOutselPattgenPcl1Tx) \ value(_, SpiHost1Sck, kTopEarlgreyPinmuxOutselSpiHost1Sck) \ value(_, SpiHost1Csb, kTopEarlgreyPinmuxOutselSpiHost1Csb) \ - value(_, FlashCtrlTdo, kTopEarlgreyPinmuxOutselFlashCtrlTdo) \ + value(_, FlashMacroWrapperTdo, kTopEarlgreyPinmuxOutselFlashMacroWrapperTdo) \ value(_, SensorCtrlAstDebugOut0, kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut0) \ value(_, SensorCtrlAstDebugOut1, kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut1) \ value(_, SensorCtrlAstDebugOut2, kTopEarlgreyPinmuxOutselSensorCtrlAonAstDebugOut2) \ diff --git a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs index d66d1d75361..e954b974c94 100644 --- a/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs +++ b/sw/host/opentitanlib/src/chip/autogen/earlgrey.rs @@ -60,9 +60,9 @@ with_unknown! { Uart2Rx = 44, Uart3Rx = 45, SpiDeviceTpmCsb = 46, - FlashCtrlTck = 47, - FlashCtrlTms = 48, - FlashCtrlTdi = 49, + FlashMacroWrapperTck = 47, + FlashMacroWrapperTms = 48, + FlashMacroWrapperTdi = 49, SysrstCtrlAonAcPresent = 50, SysrstCtrlAonKey0In = 51, SysrstCtrlAonKey1In = 52, @@ -233,7 +233,7 @@ with_unknown! { PattgenPcl1Tx = 52, SpiHost1Sck = 53, SpiHost1Csb = 54, - FlashCtrlTdo = 55, + FlashMacroWrapperTdo = 55, SensorCtrlAonAstDebugOut0 = 56, SensorCtrlAonAstDebugOut1 = 57, SensorCtrlAonAstDebugOut2 = 58, diff --git a/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs b/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs index f7a7c2ea637..e0b6d9d0332 100644 --- a/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs +++ b/sw/host/opentitanlib/src/chip/autogen/englishbreakfast.rs @@ -47,11 +47,8 @@ with_unknown! { GpioGpio31 = 31, Uart0Rx = 32, Uart1Rx = 33, - FlashCtrlTck = 34, - FlashCtrlTms = 35, - FlashCtrlTdi = 36, - UsbdevSense = 37, - End = 38, + UsbdevSense = 34, + End = 35, } pub enum PinmuxInsel: u32 [default = Self::End] { @@ -196,8 +193,7 @@ with_unknown! { GpioGpio31 = 34, Uart0Tx = 35, Uart1Tx = 36, - FlashCtrlTdo = 37, - End = 38, + End = 37, } pub enum DirectPads: u32 [default = Self::End] {