From 75b6b568d382d41b81a4bf9db30865aca18f5cb1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Wed, 20 Aug 2025 15:45:53 +0200 Subject: [PATCH] compiler: move self-hosted backends from src/arch to src/codegen --- src/codegen.zig | 16 ++++++++-------- src/codegen/llvm.zig | 4 ++-- src/{arch => codegen}/riscv64/CodeGen.zig | 0 src/{arch => codegen}/riscv64/Emit.zig | 0 src/{arch => codegen}/riscv64/Lower.zig | 0 src/{arch => codegen}/riscv64/Mir.zig | 0 src/{arch => codegen}/riscv64/abi.zig | 0 src/{arch => codegen}/riscv64/bits.zig | 0 src/{arch => codegen}/riscv64/encoding.zig | 0 src/{arch => codegen}/riscv64/mnem.zig | 0 src/{arch => codegen}/sparc64/CodeGen.zig | 0 src/{arch => codegen}/sparc64/Emit.zig | 0 src/{arch => codegen}/sparc64/Mir.zig | 0 src/{arch => codegen}/sparc64/abi.zig | 0 src/{arch => codegen}/sparc64/bits.zig | 0 src/{arch => codegen}/wasm/CodeGen.zig | 0 src/{arch => codegen}/wasm/Emit.zig | 0 src/{arch => codegen}/wasm/Mir.zig | 0 src/{arch => codegen}/x86_64/CodeGen.zig | 0 src/{arch => codegen}/x86_64/Disassembler.zig | 0 src/{arch => codegen}/x86_64/Emit.zig | 0 src/{arch => codegen}/x86_64/Encoding.zig | 0 src/{arch => codegen}/x86_64/Lower.zig | 0 src/{arch => codegen}/x86_64/Mir.zig | 0 src/{arch => codegen}/x86_64/abi.zig | 0 src/{arch => codegen}/x86_64/bits.zig | 0 src/{arch => codegen}/x86_64/encoder.zig | 0 src/{arch => codegen}/x86_64/encodings.zon | 0 src/link/Dwarf.zig | 6 +++--- src/link/Elf/Atom.zig | 6 +++--- src/link/MachO/Atom.zig | 6 +++--- src/link/Wasm.zig | 4 ++-- src/link/Wasm/Flush.zig | 2 +- src/link/riscv.zig | 2 +- 34 files changed, 23 insertions(+), 23 deletions(-) rename src/{arch => codegen}/riscv64/CodeGen.zig (100%) rename src/{arch => codegen}/riscv64/Emit.zig (100%) rename src/{arch => codegen}/riscv64/Lower.zig (100%) rename src/{arch => codegen}/riscv64/Mir.zig (100%) rename src/{arch => codegen}/riscv64/abi.zig (100%) rename src/{arch => codegen}/riscv64/bits.zig (100%) rename src/{arch => codegen}/riscv64/encoding.zig (100%) rename src/{arch => codegen}/riscv64/mnem.zig (100%) rename src/{arch => codegen}/sparc64/CodeGen.zig (100%) rename src/{arch => codegen}/sparc64/Emit.zig (100%) rename src/{arch => codegen}/sparc64/Mir.zig (100%) rename src/{arch => codegen}/sparc64/abi.zig (100%) rename src/{arch => codegen}/sparc64/bits.zig (100%) rename src/{arch => codegen}/wasm/CodeGen.zig (100%) rename src/{arch => codegen}/wasm/Emit.zig (100%) rename src/{arch => codegen}/wasm/Mir.zig (100%) rename src/{arch => codegen}/x86_64/CodeGen.zig (100%) rename src/{arch => codegen}/x86_64/Disassembler.zig (100%) rename src/{arch => codegen}/x86_64/Emit.zig (100%) rename src/{arch => codegen}/x86_64/Encoding.zig (100%) rename src/{arch => codegen}/x86_64/Lower.zig (100%) rename src/{arch => codegen}/x86_64/Mir.zig (100%) rename src/{arch => codegen}/x86_64/abi.zig (100%) rename src/{arch => codegen}/x86_64/bits.zig (100%) rename src/{arch => codegen}/x86_64/encoder.zig (100%) rename src/{arch => codegen}/x86_64/encodings.zon (100%) diff --git a/src/codegen.zig b/src/codegen.zig index 56e6e7c99fb3..f0bd230538eb 100644 --- a/src/codegen.zig +++ b/src/codegen.zig @@ -56,11 +56,11 @@ fn importBackend(comptime backend: std.builtin.CompilerBackend) type { .stage2_c => @import("codegen/c.zig"), .stage2_llvm => @import("codegen/llvm.zig"), .stage2_powerpc => unreachable, - .stage2_riscv64 => @import("arch/riscv64/CodeGen.zig"), - .stage2_sparc64 => @import("arch/sparc64/CodeGen.zig"), + .stage2_riscv64 => @import("codegen/riscv64/CodeGen.zig"), + .stage2_sparc64 => @import("codegen/sparc64/CodeGen.zig"), .stage2_spirv => @import("codegen/spirv/CodeGen.zig"), - .stage2_wasm => @import("arch/wasm/CodeGen.zig"), - .stage2_x86, .stage2_x86_64 => @import("arch/x86_64/CodeGen.zig"), + .stage2_wasm => @import("codegen/wasm/CodeGen.zig"), + .stage2_x86, .stage2_x86_64 => @import("codegen/x86_64/CodeGen.zig"), _ => unreachable, }; } @@ -100,10 +100,10 @@ pub fn wantsLiveness(pt: Zcu.PerThread, nav_index: InternPool.Nav.Index) bool { /// union of all MIR types. The active tag is known from the backend in use; see `AnyMir.tag`. pub const AnyMir = union { aarch64: if (dev.env.supports(.aarch64_backend)) @import("codegen/aarch64/Mir.zig") else noreturn, - riscv64: if (dev.env.supports(.riscv64_backend)) @import("arch/riscv64/Mir.zig") else noreturn, - sparc64: if (dev.env.supports(.sparc64_backend)) @import("arch/sparc64/Mir.zig") else noreturn, - x86_64: if (dev.env.supports(.x86_64_backend)) @import("arch/x86_64/Mir.zig") else noreturn, - wasm: if (dev.env.supports(.wasm_backend)) @import("arch/wasm/Mir.zig") else noreturn, + riscv64: if (dev.env.supports(.riscv64_backend)) @import("codegen/riscv64/Mir.zig") else noreturn, + sparc64: if (dev.env.supports(.sparc64_backend)) @import("codegen/sparc64/Mir.zig") else noreturn, + x86_64: if (dev.env.supports(.x86_64_backend)) @import("codegen/x86_64/Mir.zig") else noreturn, + wasm: if (dev.env.supports(.wasm_backend)) @import("codegen/wasm/Mir.zig") else noreturn, c: if (dev.env.supports(.c_backend)) @import("codegen/c.zig").Mir else noreturn, pub inline fn tag(comptime backend: std.builtin.CompilerBackend) []const u8 { diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index e4abfcca436b..9c2008d3f7a9 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -21,11 +21,11 @@ const Air = @import("../Air.zig"); const Value = @import("../Value.zig"); const Type = @import("../Type.zig"); const codegen = @import("../codegen.zig"); -const x86_64_abi = @import("../arch/x86_64/abi.zig"); +const x86_64_abi = @import("x86_64/abi.zig"); const wasm_c_abi = @import("wasm/abi.zig"); const aarch64_c_abi = @import("aarch64/abi.zig"); const arm_c_abi = @import("arm/abi.zig"); -const riscv_c_abi = @import("../arch/riscv64/abi.zig"); +const riscv_c_abi = @import("riscv64/abi.zig"); const mips_c_abi = @import("mips/abi.zig"); const dev = @import("../dev.zig"); diff --git a/src/arch/riscv64/CodeGen.zig b/src/codegen/riscv64/CodeGen.zig similarity index 100% rename from src/arch/riscv64/CodeGen.zig rename to src/codegen/riscv64/CodeGen.zig diff --git a/src/arch/riscv64/Emit.zig b/src/codegen/riscv64/Emit.zig similarity index 100% rename from src/arch/riscv64/Emit.zig rename to src/codegen/riscv64/Emit.zig diff --git a/src/arch/riscv64/Lower.zig b/src/codegen/riscv64/Lower.zig similarity index 100% rename from src/arch/riscv64/Lower.zig rename to src/codegen/riscv64/Lower.zig diff --git a/src/arch/riscv64/Mir.zig b/src/codegen/riscv64/Mir.zig similarity index 100% rename from src/arch/riscv64/Mir.zig rename to src/codegen/riscv64/Mir.zig diff --git a/src/arch/riscv64/abi.zig b/src/codegen/riscv64/abi.zig similarity index 100% rename from src/arch/riscv64/abi.zig rename to src/codegen/riscv64/abi.zig diff --git a/src/arch/riscv64/bits.zig b/src/codegen/riscv64/bits.zig similarity index 100% rename from src/arch/riscv64/bits.zig rename to src/codegen/riscv64/bits.zig diff --git a/src/arch/riscv64/encoding.zig b/src/codegen/riscv64/encoding.zig similarity index 100% rename from src/arch/riscv64/encoding.zig rename to src/codegen/riscv64/encoding.zig diff --git a/src/arch/riscv64/mnem.zig b/src/codegen/riscv64/mnem.zig similarity index 100% rename from src/arch/riscv64/mnem.zig rename to src/codegen/riscv64/mnem.zig diff --git a/src/arch/sparc64/CodeGen.zig b/src/codegen/sparc64/CodeGen.zig similarity index 100% rename from src/arch/sparc64/CodeGen.zig rename to src/codegen/sparc64/CodeGen.zig diff --git a/src/arch/sparc64/Emit.zig b/src/codegen/sparc64/Emit.zig similarity index 100% rename from src/arch/sparc64/Emit.zig rename to src/codegen/sparc64/Emit.zig diff --git a/src/arch/sparc64/Mir.zig b/src/codegen/sparc64/Mir.zig similarity index 100% rename from src/arch/sparc64/Mir.zig rename to src/codegen/sparc64/Mir.zig diff --git a/src/arch/sparc64/abi.zig b/src/codegen/sparc64/abi.zig similarity index 100% rename from src/arch/sparc64/abi.zig rename to src/codegen/sparc64/abi.zig diff --git a/src/arch/sparc64/bits.zig b/src/codegen/sparc64/bits.zig similarity index 100% rename from src/arch/sparc64/bits.zig rename to src/codegen/sparc64/bits.zig diff --git a/src/arch/wasm/CodeGen.zig b/src/codegen/wasm/CodeGen.zig similarity index 100% rename from src/arch/wasm/CodeGen.zig rename to src/codegen/wasm/CodeGen.zig diff --git a/src/arch/wasm/Emit.zig b/src/codegen/wasm/Emit.zig similarity index 100% rename from src/arch/wasm/Emit.zig rename to src/codegen/wasm/Emit.zig diff --git a/src/arch/wasm/Mir.zig b/src/codegen/wasm/Mir.zig similarity index 100% rename from src/arch/wasm/Mir.zig rename to src/codegen/wasm/Mir.zig diff --git a/src/arch/x86_64/CodeGen.zig b/src/codegen/x86_64/CodeGen.zig similarity index 100% rename from src/arch/x86_64/CodeGen.zig rename to src/codegen/x86_64/CodeGen.zig diff --git a/src/arch/x86_64/Disassembler.zig b/src/codegen/x86_64/Disassembler.zig similarity index 100% rename from src/arch/x86_64/Disassembler.zig rename to src/codegen/x86_64/Disassembler.zig diff --git a/src/arch/x86_64/Emit.zig b/src/codegen/x86_64/Emit.zig similarity index 100% rename from src/arch/x86_64/Emit.zig rename to src/codegen/x86_64/Emit.zig diff --git a/src/arch/x86_64/Encoding.zig b/src/codegen/x86_64/Encoding.zig similarity index 100% rename from src/arch/x86_64/Encoding.zig rename to src/codegen/x86_64/Encoding.zig diff --git a/src/arch/x86_64/Lower.zig b/src/codegen/x86_64/Lower.zig similarity index 100% rename from src/arch/x86_64/Lower.zig rename to src/codegen/x86_64/Lower.zig diff --git a/src/arch/x86_64/Mir.zig b/src/codegen/x86_64/Mir.zig similarity index 100% rename from src/arch/x86_64/Mir.zig rename to src/codegen/x86_64/Mir.zig diff --git a/src/arch/x86_64/abi.zig b/src/codegen/x86_64/abi.zig similarity index 100% rename from src/arch/x86_64/abi.zig rename to src/codegen/x86_64/abi.zig diff --git a/src/arch/x86_64/bits.zig b/src/codegen/x86_64/bits.zig similarity index 100% rename from src/arch/x86_64/bits.zig rename to src/codegen/x86_64/bits.zig diff --git a/src/arch/x86_64/encoder.zig b/src/codegen/x86_64/encoder.zig similarity index 100% rename from src/arch/x86_64/encoder.zig rename to src/codegen/x86_64/encoder.zig diff --git a/src/arch/x86_64/encodings.zon b/src/codegen/x86_64/encodings.zon similarity index 100% rename from src/arch/x86_64/encodings.zon rename to src/codegen/x86_64/encodings.zon diff --git a/src/link/Dwarf.zig b/src/link/Dwarf.zig index f4af5f4148ad..f58e496c7fd2 100644 --- a/src/link/Dwarf.zig +++ b/src/link/Dwarf.zig @@ -102,7 +102,7 @@ const DebugFrame = struct { } + switch (target.cpu.arch) { .x86_64 => len: { dev.check(.x86_64_backend); - const Register = @import("../arch/x86_64/bits.zig").Register; + const Register = @import("../codegen/x86_64/bits.zig").Register; break :len uleb128Bytes(1) + sleb128Bytes(-8) + uleb128Bytes(Register.rip.dwarfNum()) + 1 + uleb128Bytes(Register.rsp.dwarfNum()) + sleb128Bytes(-1) + 1 + uleb128Bytes(1); @@ -2346,7 +2346,7 @@ pub fn init(lf: *link.File, format: DW.Format) Dwarf { .debug_aranges = .{ .section = Section.init }, .debug_frame = .{ .header = if (target.cpu.arch == .x86_64 and target.ofmt == .elf) header: { - const Register = @import("../arch/x86_64/bits.zig").Register; + const Register = @import("../codegen/x86_64/bits.zig").Register; break :header comptime .{ .format = .eh_frame, .code_alignment_factor = 1, @@ -4830,7 +4830,7 @@ fn flushWriterError(dwarf: *Dwarf, pt: Zcu.PerThread) (FlushError || Writer.Erro .eh_frame => switch (target.cpu.arch) { .x86_64 => { dev.check(.x86_64_backend); - const Register = @import("../arch/x86_64/bits.zig").Register; + const Register = @import("../codegen/x86_64/bits.zig").Register; for (dwarf.debug_frame.section.units.items) |*unit| { header_aw.clearRetainingCapacity(); try header_aw.ensureTotalCapacity(unit.header_len); diff --git a/src/link/Elf/Atom.zig b/src/link/Elf/Atom.zig index 6bfaddea97ba..f7323fcdd4d3 100644 --- a/src/link/Elf/Atom.zig +++ b/src/link/Elf/Atom.zig @@ -1473,9 +1473,9 @@ const x86_64 = struct { for (insts) |inst| try inst.encode(&writer, .{}); } - const bits = @import("../../arch/x86_64/bits.zig"); - const encoder = @import("../../arch/x86_64/encoder.zig"); - const Disassembler = @import("../../arch/x86_64/Disassembler.zig"); + const bits = @import("../../codegen/x86_64/bits.zig"); + const encoder = @import("../../codegen/x86_64/encoder.zig"); + const Disassembler = @import("../../codegen/x86_64/Disassembler.zig"); const Immediate = Instruction.Immediate; const Instruction = encoder.Instruction; }; diff --git a/src/link/MachO/Atom.zig b/src/link/MachO/Atom.zig index c5d29c7ff583..1658cb7ca968 100644 --- a/src/link/MachO/Atom.zig +++ b/src/link/MachO/Atom.zig @@ -901,9 +901,9 @@ const x86_64 = struct { for (insts) |inst| try inst.encode(&stream, .{}); } - const bits = @import("../../arch/x86_64/bits.zig"); - const encoder = @import("../../arch/x86_64/encoder.zig"); - const Disassembler = @import("../../arch/x86_64/Disassembler.zig"); + const bits = @import("../../codegen/x86_64/bits.zig"); + const encoder = @import("../../codegen/x86_64/encoder.zig"); + const Disassembler = @import("../../codegen/x86_64/Disassembler.zig"); const Immediate = bits.Immediate; const Instruction = encoder.Instruction; }; diff --git a/src/link/Wasm.zig b/src/link/Wasm.zig index 74c30c0c186d..382e0e1a826a 100644 --- a/src/link/Wasm.zig +++ b/src/link/Wasm.zig @@ -29,8 +29,8 @@ const leb = std.leb; const log = std.log.scoped(.link); const mem = std.mem; -const Mir = @import("../arch/wasm/Mir.zig"); -const CodeGen = @import("../arch/wasm/CodeGen.zig"); +const Mir = @import("../codegen/wasm/Mir.zig"); +const CodeGen = @import("../codegen/wasm/CodeGen.zig"); const abi = @import("../codegen/wasm/abi.zig"); const Compilation = @import("../Compilation.zig"); const Dwarf = @import("Dwarf.zig"); diff --git a/src/link/Wasm/Flush.zig b/src/link/Wasm/Flush.zig index f728a8578669..b5d93259e2f7 100644 --- a/src/link/Wasm/Flush.zig +++ b/src/link/Wasm/Flush.zig @@ -9,7 +9,7 @@ const Alignment = Wasm.Alignment; const String = Wasm.String; const Relocation = Wasm.Relocation; const InternPool = @import("../../InternPool.zig"); -const Mir = @import("../../arch/wasm/Mir.zig"); +const Mir = @import("../../codegen/wasm/Mir.zig"); const build_options = @import("build_options"); diff --git a/src/link/riscv.zig b/src/link/riscv.zig index 85cc491603b0..cfc42ac33969 100644 --- a/src/link/riscv.zig +++ b/src/link/riscv.zig @@ -113,5 +113,5 @@ pub const Eflags = packed struct(u32) { const mem = std.mem; const std = @import("std"); -const encoding = @import("../arch/riscv64/encoding.zig"); +const encoding = @import("../codegen/riscv64/encoding.zig"); const Instruction = encoding.Instruction;