Popular repositories Loading
-
FIR-Stereo-FPGA
FIR-Stereo-FPGA Public🎶 Implement a stereo FIR filter in Verilog with AXI-Stream for real-time audio processing, featuring configurable taps and deterministic latency.
SystemVerilog
-
ace24-desktop.github.io
ace24-desktop.github.io Public🔊 Implement a stereo FIR filter on FPGA with AXI-Stream for real-time audio processing, featuring a clean architecture and customizable parameters.
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.