Serpent Says (FPGA VGA Demo)

This repository contains a Verilog/Vivado project for a VGA-rendered "Serpent Says" scene on FPGA hardware.

At a high level, the design:

• Divides a 100 MHz board clock to a 25 MHz pixel clock.
• Generates 640x480 VGA timing (HSYNC/VSYNC + active video region).
• Renders a static snake-style playfield with an info bar, snake head/body, food, and obstacles.

Repository Layout

• serpent_says/rtl/: Main RTL modules (top_serpent_says, vga_controller, clk_divider).
• serpent_says/tb/: Basic simulation testbenches.
• serpent_says/xdc/: FPGA pin/timing constraints.
• serpent_says/serpent_says.xpr: Vivado project file.
• serpent_says/Evidence/: Optional waveform/schematic evidence artifacts.

Notes

• The canonical source RTL lives in serpent_says/rtl/.
• Most serpent_says.* build/simulation folders are tool-generated by Vivado/XSim.