Implemented to be as accurate as possible. Tested on A7 Minima. Each module is designed just like on the series.
- Active high logic
- Control signals ROM is implemented using LUT
- Data mask is used instead of 4-bit connection to the bus (PC, RAM address, instruction)
- Halt is implemented by forcing clock high
- Program is loaded using
.coefile and cannot be modified after synthesis
As featured on the series.
