Using stm32f334 implement the bi-directional buck boost control fully in register level programming
The STM32F334's High-Resolution Timer (HRTIM) peripheral serves as the core PWM generation unit, operating at 72MHz system clock with 13.89ns resolution. The switching frequency is configured to 150kHz to balance efficiency and control precision.
Dead Time Management: Critical protection against shoot-through conditions is implemented with 174ns dead time between complementary switches. This value exceeds the YJG60G10A MOSFET's total turn-off time of 89.7ns, providing adequate safety margin.
Four-Switch Control Strategy: The master timer coordinates all four switches through compare registers MCMP1R through MCMP4R. Timer A controls the buck half-bridge with high-side and low-side MOSFETs, while Timer B manages the boost half-bridge. Each timer generates complementary PWM signals with precise dead-time injection.
Center-Aligned PWM Simulation: To optimize ADC sampling timing, the system simulates center-aligned PWM behavior. Sampling points are positioned at the symmetry point of PWM waveforms, maximizing distance from switching transitions and reducing noise impact on measurements.
Duty Cycle Allocation Algorithm: The system automatically transitions between buck and boost operation modes based on voltage requirements. In buck mode, when total comparison value remains below 95% of the period, the buck half-bridge operates with variable duty cycle while the boost half-bridge maintains minimum 5% duty cycle. When output voltage requirements exceed input capabilities, the system enters boost mode with buck half-bridge fixed at 95% duty cycle and boost half-bridge handling the overflow comparison value.
Closed-Loop Implementation: Dual-loop control architecture employs incremental PID algorithms for both voltage and current regulation. The current loop operates continuously during charging and discharging phases, sampling high-side current through INA240 sensors. The voltage loop activates only during charging mode, comparing measured output voltage against target levels. The system selects the smaller output between voltage and current loop calculations to prevent over-regulation.
Multi-Stage Charging Protocol: Energy storage devices undergo three-phase charging process. Initial constant current phase maintains maximum charging current until voltage reaches first threshold. Intermediate constant power phase reduces current as voltage increases, maintaining power limit. Final constant voltage phase applies minimal maintenance current to sustain target voltage without overcharging.
Bidirectional Power Flow: The symmetric nature of the buck-boost topology enables energy feedback from storage devices to input side. During discharge cycles, stored energy supplements load power demands, preventing upstream power supply stress during high-power transients.
Soft-Start Protection: Critical protection mechanism prevents MOSFET damage during system initialization. Upon power-up, the system measures existing energy storage device voltage and calculates appropriate initial duty cycle to match output voltage. This eliminates voltage differentials that could cause destructive inrush currents. The calculated open-loop duty cycle serves as starting point for subsequent closed-loop operation.
Fault Detection and Shutdown: Continuous monitoring of input voltage, output current, and load conditions triggers protective shutdown when parameters exceed safe operating limits. Overvoltage, overcurrent, or undervoltage conditions immediately disable all PWM outputs and activate fault indicators. The system maintains fault status until manual reset after fault condition removal.
Signal Processing and Filtering: ADC measurements undergo sliding average filtering to reduce noise impact on control algorithms. Least-squares fitting techniques calibrate measured values against actual physical parameters, compensating for component tolerances and parasitic effects. This calibration process uses multimeter measurements as reference standards to ensure accuracy.
Bootstrap Capacitor Management: High-side MOSFET driving requires bootstrap capacitor refresh cycles. The system maintains minimum and maximum duty cycle limits of 5% and 95% respectively to ensure adequate bootstrap charging time. This prevents high-side drive voltage degradation during extended operation periods.
Microcontroller Selection: STM32F334 provides essential HRTIM peripheral previously exclusive to expensive DSP platforms. The 72MHz ARM Cortex-M4 core delivers sufficient computational power for real-time control algorithms while the integrated HRTIM enables high-resolution PWM generation with register-level configuration flexibility.
Power Stage Components: YJG60G10A MOSFETs offer optimal balance of switching characteristics with 36nC gate charge enabling low driving losses and fast switching transitions. The high voltage tolerance and low on-resistance support high-efficiency power conversion across wide operating ranges.
Gate Driver Architecture: UCC27211 drivers provide 4A peak drive current capability with bootstrap capacitor compatibility. The wide switching frequency range and reduced drive losses enhance overall system efficiency while simplifying external circuitry requirements.
Magnetic Components: Würth Elektronik 74435581000 flat-wire inductor in 2212 package delivers superior thermal performance and saturation current handling compared to standard molded inductors. The 10μH inductance value balances energy storage capacity with physical size constraints for high-power applications.
Sensing and Measurement: Triple INA240 current sensors enable comprehensive current monitoring at input, output, and load connection points. Bidirectional measurement capability with simple external pin configuration supports both charging and discharging current detection. RS8551 rail-to-rail operational amplifiers provide voltage measurement with 1:20 attenuation ratio, protecting ADC inputs while maintaining measurement accuracy.
Power Management: Dual XL7005A buck converters supply system power requirements, with primary converter delivering 5V for control circuits and secondary converter providing 11V for gate driver operation. SPX1117 LDO regulator steps 5V down to 3.3V for microcontroller and sensor operation. NCP51460SN33T1G reference voltage generator ensures stable ADC performance.