fix(flip-flops): resolve inconsistent latch vs flip-flop concepts

[LalitNarayanYadav]

Fixes #753

Changes done:

• Fixed typo: "his circuit" → "This circuit" in SR flip-flop introduction
• Clarified SR flip-flop introduction: replaced vague similarity
  with explicit edge-triggered vs level-sensitive distinction
• Clarified D flip-flop introduction: explicitly stated D flip-flop
  is edge-triggered unlike D latch which is level-sensitive
• Fixed SR characteristic table heading: "SR Latch" → "SR Flip Flop"
• Added Verilog mapping section under D flip-flop showing:
  - Edge-triggered FF: always @(posedge clk) with non-blocking <=
  - Level-sensitive latch: always @(D or en) for contrast
  - Note on non-blocking vs blocking assignment best practice
• Added Race Around Condition explanation in master-slave section
• Changed Race Around Condition to ### heading (subsection level)
• Removed stray triple backtick that broke page rendering

Screenshots

No UI changes — documentation and content fix only.

Preview Link(s):

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• Reviewed the contributing guidelines
• Sample preview link added (add the link(s) for all the pages
  changed/updated from the checks tab after checks complete)
• Tried Squashing the commits into one

Summary by CodeRabbit

• Documentation
  • Clarified flip-flop triggering behavior for SR and D flip-flops (edge-triggered)
  • Added mapping to hardware description (Verilog) for D flip-flops with explanatory examples
  • Corrected label in T flip-flop state table
  • Added explanation of race-around conditions and timing separation for JK flip-flops

[coderabbitai]

Walkthrough

The changes update documentation on flip-flops and latches in sequential logic. Instructional text was revised to characterize SR and D flip-flops as edge-triggered devices responding to positive clock transitions rather than level- or enable-sensitive elements. A new section maps D flip-flop behavior to Verilog with an always @(posedge clk) example using non-blocking assignment and contrasts it with a level-sensitive D-latch. The T flip-flop table header was corrected from D to T. A "Race-Around Condition" subsection was added under Master–slave JK flip-flops explaining JK toggling during a high clock pulse and master–slave timing separation.

Suggested labels

potential-ai-slop

🚥 Pre-merge checks | ✅ 5

✅ Passed checks (5 passed)

Check name	Status	Explanation
Description Check	✅ Passed	Check skipped - CodeRabbit’s high-level summary is enabled.
Title check	✅ Passed	The title clearly and accurately describes the main change: resolving inconsistent terminology between latches and flip-flops in the documentation, which is the primary focus of all modifications.
Linked Issues check	✅ Passed	The PR successfully addresses all coding/documentation requirements from issue #753: clarifying latch vs flip-flop distinctions, adding Verilog mapping section, correcting terminology in tables, fixing typos, explaining race-around conditions, and removing rendering errors.
Out of Scope Changes check	✅ Passed	All changes remain within scope: documentation updates in flip-flops.md directly address inconsistent terminology and conceptual clarity issues outlined in issue #753; no unrelated modifications are present.
Docstring Coverage	✅ Passed	No functions found in the changed files to evaluate docstring coverage. Skipping docstring coverage check.

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[coderabbitai]

Actionable comments posted: 2

Caution

Some comments are outside the diff and can’t be posted inline due to platform limitations.

⚠️ Outside diff range comments (1)

docs/seq-ssi/flip-flops.md (1)

61-65: ⚠️ Potential issue | 🟠 Major

Unify edge-polarity wording to avoid conceptual contradiction

Line 61/Line 110 say “positive or negative clock transitions,” but Line 65/Line 114 state only positive/rising-edge behavior. Please make this consistent (and explicit to CircuitVerse behavior) to prevent learner confusion.

Suggested doc fix

-SR flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, SR latch operates with enable signal.
+SR flip-flop is edge-triggered (in CircuitVerse, on the positive/rising clock edge), whereas SR latch operates with an enable level.
...
-D flip-flop operates with only positive clock transitions or negative clock transitions. Whereas, D latch operates with enable signal.
+D flip-flop is edge-triggered (in CircuitVerse, on the positive/rising clock edge), whereas D latch operates with an enable level.

Also applies to: 110-114

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ℹ️ Review info

⚙️ Run configuration

Configuration used: Organization UI

Review profile: CHILL

Plan: Pro

Run ID: 2b7a11e8-95c6-4c3d-9d40-ba740cc7940b

📥 Commits

Reviewing files that changed from the base of the PR and between ac91c0a and 71446f7.

📒 Files selected for processing (1)

• docs/seq-ssi/flip-flops.md

[coderabbitai]

♻️ Duplicate comments (1)

docs/seq-ssi/flip-flops.md (1)

312-317: ⚠️ Potential issue | 🟡 Minor

Use “race-around condition” consistently in body text.

Line 316 still uses “race around condition” without hyphenation, while the subsection title is hyphenated.

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ℹ️ Review info

⚙️ Run configuration

Configuration used: Organization UI

Review profile: CHILL

Plan: Pro

Run ID: cd5dc2a2-47bb-4b10-a7db-b19899009688

📥 Commits

Reviewing files that changed from the base of the PR and between 71446f7 and 410f88f.

📒 Files selected for processing (1)

• docs/seq-ssi/flip-flops.md