~ I’m currently working on RTL design projects and a RISC-V based CPU using Verilog and open-source EDA tools.
~ I’m looking to collaborate on VLSI, RISC-V, RTL design, and open-source silicon projects.
~ I’m looking for help with deepening my understanding of STA, physical design, and complete RTL-to-GDSII flows.
~ I’m currently learning OpenLane, Sky130 PDK, Perl, timing analysis, and physical design concepts.
~ Ask me about Verilog, FSMs, RISC-V architecture, OpenLane flow, and digital logic design.
~ Fun fact: I enjoy turning textbook VLSI concepts into working hardware implementations.
