digital-locker-verilog

Digital Locker implemented in Verilog HDL using a Finite State Machine (FSM). Unlocks with sequence 1010, includes simulation, RTL schematic, and documentation.

🔐 Digital Locker using Verilog (Quartus + ModelSim)

This project implements a Digital Locker using Verilog HDL and is designed/tested using Intel Quartus Prime and ModelSim-Altera.
The locker is modeled as a Finite State Machine (FSM) that unlocks when the correct sequence 1010 is entered.
After 3 failed attempts, the system enters a lockout state until reset.

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🛠 Tools Used

• Intel Quartus Prime – for synthesis and RTL generation
• ModelSim-Altera – for simulation and waveform analysis
• FPGA (optional) – design can be implemented on Intel/Altera FPGA boards
• LaTeX – documentation and report

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📂 Repository Contents

Main Verilog source code

• docs/ → Report (LaTeX + PDF) with FSM diagram, flowchart, RTL schematic, and waveforms

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🚀 How to Run (Quartus + ModelSim)

1. Open Quartus Prime → create a new project.
2. Add Locker.v to the project.
3. Compile/synthesize to generate RTL schematic.
4. Launch ModelSim-Altera from Quartus.
5. Add testbench.v + Locker.v → run simulation.
6. Open waveforms in ModelSim Wave window or export to GTKWave.

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📊 FSM States

• Idle → Waiting for input
• S1, S2, S3 → Sequence progress
• Unlocked → Correct sequence entered
• Error → Wrong input (attempt counter increments)
• Lockout → After 3 failed attempts

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📷 Example Outputs

• FSM State Diagram
• RTL Schematic from Quartus
• Simulation Waveform from ModelSim

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📜 License

Licensed under the MIT License – free to use, modify, and share.

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🔑 Keywords

Verilog FSM Digital Locker Quartus ModelSim Altera FPGA RTL Design Sequence Detector