Pinned Loading

1. SDRAM SDRAM Public

   Verilog 1

2. MIG_DDR3_UVM MIG_DDR3_UVM Public

   Verilog 2 1

3. AXI_SRAM AXI_SRAM Public

   SystemVerilog 2

4. uvm_lab uvm_lab Public

   SystemVerilog

5. RV32 RV32 Public

   RISCV-V Soc

   Assembly

6. Dissertation Dissertation Public

   本科的毕业设计，图像边缘检测在FPGA中的设计与实现(Otus)

   Verilog 5