EECS 151/251A FPGA Project Skeleton for Fall 2021

Check out the Project Overview to see the specs.

Checkpoint 1: 3-stage RISC-V (rv32ui) Processor Block Design Diagram

Checkpoint 2: Fully functional 3-stage RISC-V (rv32ui) Processor

Checkpoint 3: Integration of IO Circuits and Design of a SD-DAC and FM Synthesizer

Checkpoint 4: Processor Optimization (100MHz)

Resources:

• RISC-V ISA Manual (Sections 2.2 - 2.6)
• FPGA Labs Fall 2021