Verilator Simulator Option

tools/dynamatic/dynamatic.cpp

@@ -101,7 +101,6 @@ struct FrontendState {
   std::optional<std::string> sourcePath = std::nullopt;
   std::string outputDir = "out";
 
-
   FrontendState(StringRef cwd) : cwd(cwd), dynamaticPath(cwd) {};
 
   bool sourcePathIsSet(StringRef keyword);
@@ -272,14 +271,16 @@ class SetCP : public Command {
 class SetOutputDir : public Command {
 public:
   SetOutputDir(FrontendState &state)
-      : Command("set-output-dir", "Sets the name of the dir to perform HLS in. If not set, defaults to 'out'", state) {
+      : Command("set-output-dir",
+                "Sets the name of the dir to perform HLS in. If not set, "
+                "defaults to 'out'",
+                state) {
     addPositionalArg({"out_dir", "out dir name"});
   }
 
   CommandResult execute(CommandArguments &args) override;
 };
 
-
 class Compile : public Command {
 public:
   static constexpr llvm::StringLiteral FAST_TOKEN_DELIVERY =
@@ -650,7 +651,8 @@ CommandResult SetOutputDir::execute(CommandArguments &args) {
   llvm::StringRef outputDir = args.positionals.front();
 
   // reject trivial bad cases
-  if (outputDir.empty() || outputDir == "." || outputDir == ".." || outputDir.endswith("/"))
+  if (outputDir.empty() || outputDir == "." || outputDir == ".." ||
+      outputDir.endswith("/"))
     return CommandResult::FAIL;
 
   // reject illegal chars
@@ -769,7 +771,7 @@ CommandResult Simulate::execute(CommandArguments &args) {
     } else {
       llvm::errs() << "Unknow Simulator '" << it->second
                    << "', possible options are 'ghdl', "
-                      "'xsim', and 'vsim'.\n";
+                      "'xsim', 'vsim' and 'verilator'.\n";
       return CommandResult::FAIL;
     }
   }

tools/dynamatic/scripts/simulate.sh

@@ -66,9 +66,10 @@ cp "$SRC_DIR/$KERNEL_NAME.h" "$C_SRC_DIR" 2> /dev/null
 # Copy TB supplementary files (memory model, etc.)
 if [ "$HDL_TYPE" = "verilog" ]; then
   cp "$RESOURCE_DIR/templates_verilog/template_tb_join.v" "$COSIM_HDL_SRC_DIR/tb_join.v"
-  cp "$RESOURCE_DIR/templates_verilog/template_two_port_RAM.v" "$COSIM_HDL_SRC_DIR/two_port_RAM.v"
-  cp "$RESOURCE_DIR/templates_verilog/template_single_argument.v" "$COSIM_HDL_SRC_DIR/single_argument.v"
+  cp "$RESOURCE_DIR/templates_verilog/template_two_port_RAM.v" "$COSIM_HDL_SRC_DIR/two_port_RAM.sv"
+  cp "$RESOURCE_DIR/templates_verilog/template_single_argument.v" "$COSIM_HDL_SRC_DIR/single_argument.sv"
   cp "$RESOURCE_DIR/modelsim.ini" "$HLS_VERIFY_DIR/modelsim.ini"
+  cp "$RESOURCE_DIR/verilator_main.cpp" "$HLS_VERIFY_DIR/verilator_main.cpp"
 else
   cp "$RESOURCE_DIR/templates_vhdl/template_tb_join.vhd" "$COSIM_HDL_SRC_DIR/tb_join.vhd"
   cp "$RESOURCE_DIR/templates_vhdl/template_two_port_RAM.vhd" "$COSIM_HDL_SRC_DIR/two_port_RAM.vhd"

tools/hls-verifier/hls-verifier.cpp

@@ -140,7 +140,8 @@ int main(int argc, char **argv) {
       cl::value_desc("vivado-fpu"), cl::init(false));
 
   cl::opt<std::string> simulatorType(
-      "simulator", cl::desc("Simulator of choice (options: xsim, ghdl, vsim)"),
+      "simulator",
+      cl::desc("Simulator of choice (options: xsim, ghdl, vsim, verilator)"),
       cl::value_desc("Simulator of choice"), cl::init("vsim"));
 
   cl::opt<std::string> hdlType("hdl",
@@ -199,6 +200,8 @@ int main(int argc, char **argv) {
     simulator = std::make_unique<VSimSimulator>(&ctx);
   } else if (simulatorType == "xsim") {
     simulator = std::make_unique<XSimSimulator>(&ctx);
+  } else if (simulatorType == "verilator") {
+    simulator = std::make_unique<Verilator>(&ctx);
   } else {
     logErr(LOG_TAG, "Wrong Simulator (use vsim, xsim, ghdl, verilator)");
     return 1;

tools/hls-verifier/include/HlsVhdlTb.h

@@ -401,7 +401,7 @@ static const string RET_VALUE_NAME = "out0";
 // using ConnectedValueType = std::variant<std::string, SpecialSignal>;
 
 struct SignalAssignment {
-  enum AssignmentType { SIGNAL, CONST_ZERO, CONST_ONE, OPEN };
+  enum AssignmentType { SIGNAL, CONST_ZERO, CONST_ONE, CONST_VEC_ZERO, OPEN };
   std::string name = "DEFAULT";
   AssignmentType type = SIGNAL;
   SignalAssignment(const std::string &name) : name(name) {};
@@ -419,6 +419,9 @@ struct SignalAssignment {
     case SignalAssignment::OPEN:
       return ctx.simLanguage == VHDL ? "open" : "";
       break;
+    case SignalAssignment::CONST_VEC_ZERO:
+      return ctx.simLanguage == VHDL ? "(others => '0')" : "0";
+      break;
     case SignalAssignment::SIGNAL:
       return name;
       break;

tools/hls-verifier/include/Simulators.h

@@ -10,6 +10,7 @@
 #ifndef HLS_VERIFIER_SIMULATORS_H
 #define HLS_VERIFIER_SIMULATORS_H
 
+#include "Utilities.h"
 #include "VerificationContext.h"
 #include "dynamatic/Support/System.h"
 #include "mlir/Support/LogicalResult.h"
@@ -53,6 +54,8 @@ class XSimSimulator : public Simulator {
         getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".vhd");
     vector<string> filelistVerilog =
         getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".v");
+    vector<string> fileListSystemVerilog =
+        getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".sv");
 
     std::error_code ec;
     llvm::raw_fd_ostream os(ctx->getXsimPrjFilePath(), ec);
@@ -63,6 +66,9 @@ class XSimSimulator : public Simulator {
     for (auto &it : filelistVerilog)
       os << "verilog work " << it << "\n";
 
+    for (auto &it : fileListSystemVerilog)
+      os << "sv work " << it << "\n";
+
     return mlir::success();
   }
 };
@@ -156,6 +162,8 @@ class VSimSimulator : public Simulator {
         getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".vhd");
     vector<string> filelistVerilog =
         getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".v");
+    vector<string> fileListSystemVerilog =
+        getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".sv");
 
     std::error_code ec;
     llvm::raw_fd_ostream os(ctx->getModelsimDoFilePath(), ec);
@@ -173,6 +181,9 @@ class VSimSimulator : public Simulator {
     for (auto &it : filelistVerilog)
       os << "project addfile " << it << "\n";
 
+    for (auto &it : fileListSystemVerilog)
+      os << "project addfile " << it << "\n";
+
     os << "project calculateorder\n";
     os << "project compileall\n";
     if (ctx->useVivadoFPU()) {
@@ -188,4 +199,45 @@ class VSimSimulator : public Simulator {
   }
 };
 
+class Verilator : public Simulator {
+
+public:
+  Verilator(VerificationContext *context) : Simulator(context) {}
+
+  void execSimulation() const override {
+    exec("bash", ctx->getVerilatorShFilePath());
+  }
+
+  mlir::LogicalResult generateScripts() const override {
+
+    vector<string> filelistVerilog =
+        getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".v");
+    vector<string> fileListSystemVerilog =
+        getListOfFilesInDirectory(ctx->getHdlSrcDir(), ".sv");
+
+    if (filelistVerilog.empty()) {
+      return mlir::failure();
+    }
+
+    std::error_code ec;
+    llvm::raw_fd_ostream os(ctx->getVerilatorShFilePath(), ec);
+
+    os << "verilator --trace -Mdir ./verilator -cc ";
+
+    for (auto &it : filelistVerilog)
+      os << it << " ";
+    for (auto &it : fileListSystemVerilog)
+      os << it << " ";
+
+    os << "--exe verilator_main.cpp --trace-underscore --Wno-UNOPTFLAT "
+          "--top-module tb --timing -Wno-REALCVT\n";
+
+    os << "make -j -C ./verilator/ -f Vtb.mk Vtb\n";
+
+    os << "./verilator/Vtb\n";
+
+    return mlir::success();
+  }
+};
+
 #endif // HLS_VERIFIER_SIMULATORS_H

tools/hls-verifier/include/VerificationContext.h

@@ -29,6 +29,7 @@ static const std::string C_OUT_DIR = "C_OUT";
 static const std::string VSIM_SCRIPT_FILE = "simulation_vsim.do";
 static const std::string GHDL_SCRIPT_FILE = "simulation_ghdl.sh";
 static const std::string XSIM_SCRIPT_FILE = "simulation_xsim.prj";
+static const std::string VERILATOR_SCRIPT_FILE = "simulation_verilator.sh";
 static const std::string HLS_VERIFY_DIR = "HLS_VERIFY";
 
 enum HdlType { VHDL, VERILOG };
@@ -70,6 +71,7 @@ struct VerificationContext {
   std::string getModelsimDoFilePath() const { return VSIM_SCRIPT_FILE; }
   std::string getGhdlShFilePath() const { return GHDL_SCRIPT_FILE; }
   std::string getXsimPrjFilePath() const { return XSIM_SCRIPT_FILE; }
+  std::string getVerilatorShFilePath() const { return VERILATOR_SCRIPT_FILE; }
 
   std::string getCOutDir() const { return simPath + SEP + C_OUT_DIR; }
 

tools/hls-verifier/lib/HlsVhdlTb.cpp

@@ -296,7 +296,7 @@ struct StartToChannelConnector {
     commonSingleArgumentDeclaration(argInst, argName);
     argInst.connect(CE0_PORT, SignalAssignment::CONST_ONE)
         .connect(WE0_PORT, SignalAssignment::CONST_ZERO)
-        .connect(D_IN0_PORT, "(others => '0')");
+        .connect(D_IN0_PORT, SignalAssignment::CONST_VEC_ZERO);
     argInst.emit(os, ctx);
   }