🚀 MiniMIPS - RISC Processor Design and FPGA Deployment Guide

MiniMIPS is a compact and efficient RISC (Reduced Instruction Set Computer) processor inspired by the MIPS architecture.
This project was developed as part of the Computer Organisation and Architecture Lab [CS39001] course.

It provides a step-by-step workflow for:
✔️ Designing in Verilog
✔️ Simulating in Vivado
✔️ Deploying on FPGA

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📑 Table of Contents

• Overview
• Datapath
• Setup Process
• File Descriptions
• Prerequisites
• How to Run
• Contributing
• License

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🔎 Overview

MiniMIPS implements a simplified ISA (Instruction Set Architecture) with a modular design philosophy.
It consists of a datapath, control unit, and memory modules, all integrated into a top-level processor that can be deployed on an FPGA.

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📊 Datapath

The datapath structure of MiniMIPS:

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⚙️ Setup Process

1. Create Instruction & Data Memory

• Open Vivado → create project → add Block Memory Generator (BRAM).
• Configure Instruction Memory & Data Memory.
• Add wrappers: BRAM_Data.v and BRAM_Instructions.v.

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2. Add Datapath Modules

• Copy all modules from DataPath/.
• Verify interfaces, check signal connectivity, and run testbenches.

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3. Add Control Unit

• Import Control Unit & Branch Control.
• Validate opcode decoding and branch logic.

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4. Integrate Processor

• Add Processor.v → connect datapath & control.
• Set as Top Module.
• Run initial synthesis.

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5. Write Assembly Code

• Reference: instruction.s.
• Follow ISA format, comment instructions, and validate against ISA doc.

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6. Generate .coe Files

python3 assembler.py <input_file.s>

• Produces .coe for memory initialization.

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7. Load Memory Modules

• Assign .coe files to BRAMs in Vivado.
• Re-run synthesis.

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8. Simulation

• Add testbench for Processor.v.
• Verify control signals, ALU operations, memory access.

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9. FPGA Wrapper

• Add FPGA_Wrapper.v.
• Map processor I/O to FPGA pins.

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10. Add Constraints

• Define pins in FPGA_XDC.xdc.

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11. Build Flow

• Run Synthesis → Implementation → Bitstream generation.

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12. Program FPGA

• Connect board via USB/JTAG.
• Upload .bit using Vivado.

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13. Debug & Observe

• Input select pins → view ALU output or register bank.
• Debug incorrect outputs by rechecking signals & control logic.

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📂 File Descriptions

Folder / File	Description
DataPath/	Verilog modules for datapath
ControlPath/	Verilog control unit modules
Memory/	BRAM configurations
Processor.v	Top-level integration
FPGA_Wrapper.v	FPGA wrapper
FPGA_XDC.xdc	FPGA pin constraints
assembler.py	Assembly → .coe converter

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🛠️ Prerequisites

• Xilinx Vivado (tested on 2020.2+)
• FPGA Board (e.g., Xilinx Artix-7 / Basys-3)
• Python 3.8+ (for assembler)

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▶️ How to Run

1. Clone repo:

   git clone https://github.com/<your-username>/<your-repo>.git

2. Open Vivado → Import all Verilog files.
3. Run steps from Setup Process.
4. Program FPGA → test assembly code execution.

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🤝 Contributing

Pull requests are welcome!
For major changes, open an issue first to discuss your ideas.

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📜 License

This project is licensed under the MIT License – see the LICENSE file for details.