softcoreA

This is a softcore for implementing a ForwardCom CPU in an FPGA.

Files included	Description
*.sv	source code in SystemVerilog
*.vh	Verilog include file
softcore_A.pdf	manual and documentation for the softcore
softcore_A.tex	Latex source for the manual
license.pdf	CERN open hardware license W version 2
deviceA7100T	Subfolder containing device-specific files for Nexys A7 FPGA board
manual	Subfolder containing softcore manual

Name		Name	Last commit message	Last commit date
Latest commit History 28 Commits
deviceA7100T		deviceA7100T
manual		manual
README.md		README.md
addressgenerator.sv		addressgenerator.sv
alu.sv		alu.sv
call_stack.sv		call_stack.sv
code_memory.sv		code_memory.sv
config_A.vh		config_A.vh
data_memory.sv		data_memory.sv
dataread.sv		dataread.sv
debouncer.sv		debouncer.sv
debug_display.sv		debug_display.sv
debugger.vh		debugger.vh
decoder.sv		decoder.sv
defines.vh		defines.vh
fetch.sv		fetch.sv
in_out_ports.sv		in_out_ports.sv
lcd.sv		lcd.sv
license.pdf		license.pdf
loader.as		loader.as
loader.mem		loader.mem
mul_div.sv		mul_div.sv
register_read.sv		register_read.sv
seg7.sv		seg7.sv
subfunctions.vh		subfunctions.vh
top.sv		top.sv
uart_and_fifo.sv		uart_and_fifo.sv

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