Skip to content

Arm-Cortex-R82: Add MPU support #1347

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
AhmedIsmail02 wants to merge 2 commits into
base: main
Choose a base branch
from
Open

Arm-Cortex-R82: Add MPU support #1347

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
3cca1ec
arm-cortex-r82: Add MPU support
AhmedIsmail02 Jul 31, 2025
8e8d415
cortex-r82: Minor code improvements
AhmedIsmail02 Oct 9, 2025
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
14 changes: 14 additions & 0 deletions .github/.cSpellWords.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -69,6 +69,7 @@ CANTX
capitalisation
cbmc
CBMC
cbnz
cbor
CBOR
CCIE
Expand Down Expand Up @@ -107,6 +108,8 @@ CLKS
CLKSOURCE
CLKSTA
CLRB
clrex
CLREX
CLRF
clrm
CLRPSW
Expand Down Expand Up @@ -378,6 +381,7 @@ IFSR
imajeff
INACK
INDF
initialisations
inpw
INTE
INTFRCH
Expand Down Expand Up @@ -651,18 +655,24 @@ PPUDR
PPUER
PPUSR
ppux
Prbar
PRBAR
PRCR
PREA
PREB
PRIA
Prioritised
PRIS
PRIVDEFENA
Prlar
PRLAR
PROCDLY
PRODH
PRODL
PROGE
Prokic
Prselr
PRSELR
prtmacro
psha
psplim
Expand Down Expand Up @@ -705,6 +715,7 @@ REENT
REGA
RELD
Renesas
restoreallgpregisters
reta
reti
RETP
Expand Down Expand Up @@ -772,6 +783,8 @@ SCBR
SCDR
SCER
SCSR
Sctlr
SCTLR
SDCC
SECU
SENDA
Expand Down Expand Up @@ -929,6 +942,7 @@ UNSUB
UNSUBACK
unsubscriptions
unsuspended
unupdated
UPAC
URAD
URAT
Expand Down
9 changes: 6 additions & 3 deletions include/task.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -68,18 +68,21 @@
#if defined( portARMV8M_MINOR_VERSION ) && ( portARMV8M_MINOR_VERSION >= 1 )
#define tskMPU_REGION_PRIVILEGED_EXECUTE_NEVER ( 1U << 5U )
#endif /* portARMV8M_MINOR_VERSION >= 1 */
#define tskMPU_REGION_NON_SHAREABLE ( 1U << 6U )
#define tskMPU_REGION_OUTER_SHAREABLE ( 1U << 7U )
#define tskMPU_REGION_INNER_SHAREABLE ( 1U << 8U )

/* MPU region permissions stored in MPU settings to
* authorize access requests. */
#define tskMPU_READ_PERMISSION ( 1U << 0U )
#define tskMPU_WRITE_PERMISSION ( 1U << 1U )
#define tskMPU_READ_PERMISSION ( 1U << 0U )
#define tskMPU_WRITE_PERMISSION ( 1U << 1U )

/* The direct to task notification feature used to have only a single notification
* per task. Now there is an array of notifications per task that is dimensioned by
* configTASK_NOTIFICATION_ARRAY_ENTRIES. For backward compatibility, any use of the
* original direct to task notification defaults to using the first index in the
* array. */
#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 )
#define tskDEFAULT_INDEX_TO_NOTIFY ( 0 )

/**
* task. h
Expand Down
4 changes: 3 additions & 1 deletion portable/CMakeLists.txt
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -243,7 +243,8 @@ add_library(freertos_kernel_port OBJECT
# ARMv8-R ports for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM_CR82>:
GCC/ARM_CR82/port.c
GCC/ARM_CR82/portASM.S>
GCC/ARM_CR82/portASM.S
GCC/ARM_CR82/mpu_wrappers_v2_asm.c>

# ARMv4T ARM7TDMI ports for GCC
$<$<STREQUAL:${FREERTOS_PORT},GCC_ARM7_AT91FR40008>:
Expand Down Expand Up @@ -822,6 +823,7 @@ if( FREERTOS_PORT MATCHES "GCC_ARM_CM(3|4)_MPU" OR
FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
FREERTOS_PORT MATCHES "GCC_ARM_CM(23|33|52|55|85)_NONSECURE" OR
FREERTOS_PORT MATCHES "GCC_ARM_CM(33|52|55|85)_TFM" OR
FREERTOS_PORT MATCHES "GCC_ARM_CR82" OR
FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NTZ_NONSECURE" OR
FREERTOS_PORT MATCHES "IAR_ARM_CM(23|33|52|55|85)_NONSECURE" OR
FREERTOS_PORT MATCHES "IAR_ARM_CM(33|52|55|85)_TFM"
Expand Down
8 changes: 7 additions & 1 deletion portable/GCC/ARM_CR82/README.md
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,12 @@ The port is supported and tested on the following toolchains:
- The port does not perform cache maintenance for shared buffers.
- If your hardware or model doesn't support full cache coherency, you must handle cache clean/invalidate operations, memory attributes, and any additional barriers in your BSP/application (especially around shared-memory regions).

# MPU Support

- This port supports the FreeRTOS MPU on both single-core and SMP (multi-core) configurations. Enable via `configENABLE_MPU = 1`; the port programs MPU regions per task on each active core.

- Minimum MPU granularity and alignment: 64 bytes. Ensure any user‑defined region base and size are 64‑byte aligned.

# SMP Multicore Bring-up

For SMP systems using this port, the application only needs to start the scheduler on the primary core and issue an SVC from each secondary core once they are online. The kernel coordinates the rest and ensures all cores are properly managed.
Expand All @@ -39,4 +45,4 @@ Secondary core flow (to be done in each core’s reset handler):
2. Wait for the primary core's signal that shared initialization is complete (i.e., `ucPrimaryCoreInitDoneFlag` set to 1).
3. Update `VBAR_EL1` from the boot vector table to the FreeRTOS vector table.
4. Initialize the GIC redistributor and enable SGIs so interrupts from the primary core are receivable; signal the primary that this secondary is online and ready by setting the its flag in the `ucSecondaryCoresReadyFlags` array.
5. Issue an SVC with immediate value `106` to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.
5. Issue an SVC with immediate value `106` (i.e., `portSVC_START_FIRST_TASK`) to enter `FreeRTOS_SWI_Handler`, which will call `vPortRestoreContext()` based on the SVC number to start scheduling on this core.
Loading