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regalloc#23

Merged
Golf0ned merged 49 commits intomainfrom
regalloc
Feb 11, 2026
Merged

regalloc#23
Golf0ned merged 49 commits intomainfrom
regalloc

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@Golf0ned Golf0ned commented Jan 24, 2026 •
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  • register allocation

Golf0ned added 30 commits January 23, 2026 20:49
@Golf0ned
initial regalloc scaffolding
cc35c03
@Golf0ned
rename backend analysis to passes + blow up regalloc
0e15496
@Golf0ned
clean up test runner + make sure interference doesnt crash
f193ff4
@Golf0ned
start degree < r for coloring
94d89a4
@Golf0ned
finish degree < R
2b05682
@Golf0ned
finish basic coloring algorithm
3d5fcf2
@Golf0ned
more descriptive commenttttttt
34fe7f9
@Golf0ned
handle incorrect basic register push order
08f679e
@Golf0ned
move coloring printing to separate function
f1990d9
@Golf0ned
scaffold precoloring visitor
23f3e6d
@Golf0ned
finish precoloring, for now
eca1572
@Golf0ned
reorder
85d3473
@Golf0ned
operand setters
aa8a7f3
@Golf0ned
commit colors
fa2d77c
@Golf0ned
fix coloring for sized registers
556e80a
@Golf0ned
doubleword in return instruction instead of q
c6cb00c
@Golf0ned
function-wise regalloc passes
7e78182
@Golf0ned
insert missing nodes into interference graph
c699f1b
@Golf0ned
rename some assignment things for my future debugging sanity
a6526a5
@Golf0ned
compute spill costs
1e1c757
@Golf0ned
use Register instead of VirtualRegister because im lazy
566e6ed
@Golf0ned
use spill costs in degree < R
ed2827f
@Golf0ned
scaffold spill lowest cost
92b5e58
@Golf0ned
many reg and shift alone
df4ed78
@Golf0ned
sized virtual registers + move regnum stuff to its own file
9b18c5a
@Golf0ned
update isel with new register sizing
155b8c0
@Golf0ned
update interference to use size flattened colors
4819ce4
@Golf0ned
update interference to use size flattened colors
727432d
@Golf0ned
properly size in spill
00a23ef
@Golf0ned
fix bug in coloring logic
b08a853
Golf0ned added 19 commits February 4, 2026 18:49
@Golf0ned
saturating add
7778426
@Golf0ned
rename color_size to flat_size
496568e
@Golf0ned
we got rid of a loop yippee
6e685b6
@Golf0ned
prevent spilling stack var temporaries
ce1cca1
@Golf0ned
add coloring priority register ordering
e6a1317
@Golf0ned
fix coloring order bug using register ordering
f83b163
@Golf0ned
add manyreg mem2reg only test + regenerate test output for now
f57a9a3
@Golf0ned
scaffold spill code generation
1403409
@Golf0ned
update test runner
d8da61f
@Golf0ned
add setter for stack bytes
587523f
@Golf0ned
generate spill code properly, messily
f866a04
@Golf0ned
make manyreg less reg because i dont want to watch the test runner si…
d53cfaf 
…t for 30 minutes
@Golf0ned
remove debug output + let loop
38a78f8
@Golf0ned
generate spill code correctly
d187fa1
@Golf0ned
updated spill test
de5d37a
@Golf0ned
add ids to operand
ab517db
@Golf0ned
use ids to fix tiebreak order
3d2f734
@Golf0ned
use deterministic order in lowest cost spill
9b09149
@Golf0ned
deterministic degree >= R case handling
2a0e5f4
@Golf0ned Golf0ned marked this pull request as ready for review February 11, 2026 00:56
@Golf0ned Golf0ned merged commit 3f90e02 into main Feb 11, 2026
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@Golf0ned Golf0ned deleted the regalloc branch February 11, 2026 00:57
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