UninaSoC

RISC-V soft-SoC extensible plaftorm for Xilinx FPGAs from University of Naples Federico II.

NOTE: the name is temporary...

Environment and Tools Version

This project was verified on Ubuntu 22.04 and the following tools version:

Tool	Verified version
Vivado	2024.2

This is just because CORE_MICROBLAZEV is supported only in Vivado >= 2024.2.

Architecture

The base architecture of UninaSoC is depicted in the following:

SoC Profiles

The SoC comes in two flavors, hpc and embedded profiles, and support for multiple boards.

Supported boards and associated profiles are:

Profile	Board
embedded (Default)	Nexys A7-100T (Default)
embedded	Nexys A7-50T
hpc	Alveo U250 (Default)
hpc	Alveo U280

NOTE: To use the Alveo U280, Vivado <= 2023.1 is needed because the Alveo U280 is EOL (end of life)

Further support is coming soon for:

• Zybo
• ZCU102
• Alveo U50

Build and Run:

The top-level Makefile can be used to build the platform for the specific target board.

First, setup environment with:

source settings.sh <soc_config> <board>

NOTE: If no input parameter is specificed, we default to embedded profile and the Nexys A7-100T board.

Build defaults with

make all

Alternatively, you can control the individual steps.

1. Configure the SoC:

make config # This is always called when operating from the top Makefile

2. Download rtl sources for non-xilinx IPS:

make units

3. Build the SoC bitstream by running:

make xilinx

4. Build software examples with:

make sw

Architecture

In both hpc and embedded profiles, the SoC architecture and host connection is depicted below:

The host connects to a RISC-V debug module through JTAG and a Sys Master AXI master module, allowing for direct control and read-back over the main bus.

Profiles:

UninaSoC supports the following profiles embedded and hpc.

Physical resources depend on the target board and part number. W.r.t. the default supported boards, the platform offers:

• Profile embedded on Nexys-A7-100T:
  • UART: physical peripheral requires a physical FTDI connection
  • Memory: 8KB BRAM + 128MB DDR (TBD)
  • Sys Master: through JTAG Xilinx hw_server
• Profile hpc on Alveo U250:
  • UART: virtualized over PCIe.
  • Memory: 8KB BRAM + 16GB DDR (per DDR channel)
  • Sys Master: through PCIe BAR addres space.

Documentation Index

Finer-grained documentation and insights to control the building flow, can be found below:

1. Configuration flow: re-configure UninaSoC.
2. Hardware build:
   • Hardware units: prepare external custom IPs.
   • Xilinx FPGA: package IPs, build bitstream, program device and debug platform.
3. Software build: build software for UninaSoC.
4. Simulation (TBD):
   • Unit tests: Verilator
     • Royalty-free, good for students
     • No support for Xilin IPs
   • SoC-level tests, QuestaSim:
     • Requires license
     • Supports Xilinx IPs
     • Students can access a licensed host for simulator access