16-bit RISC Processor with Interrupt Handling

A pipelined RISC (Reduced Instruction Set Computer) processor implementation in VHDL, featuring a 4-stage pipeline architecture and non-preemptive interrupt handling.

📋 Project Overview

This project implements a complete 16-bit RISC processor designed and simulated using Mentor Graphics ModelSim. The processor features a classic pipeline architecture with support for external interrupts, making it suitable for educational purposes and understanding fundamental computer architecture concepts.

✨ Key Features

• 16-bit Instruction Set: 27 instructions including arithmetic, logical, and load/store operations
• 4-Stage Pipeline Architecture: Fetch → Decode → Execute → WriteBack
• Interrupt Support: 4 external interrupt request lines with non-preemptive handling
• Memory Organization:
  • 256 bytes of instruction memory (256 × 16-bit)
  • 256 bytes of data memory (8-bit wide)
  • 16 general-purpose 8-bit registers
• 8-bit Address Bus: All address buses are 8 bits wide

🏗️ Architecture

Pipeline Stages

1. Fetch Stage: Retrieves instructions from instruction memory using the program counter
2. Decode Stage: Decodes instructions and handles interrupt requests
3. Execute Stage: Performs arithmetic, logical, and control operations via ALU
4. WriteBack Stage: Writes results back to registers or data memory

Interrupt Handling

The processor supports 4 external interrupts (IRQ0-IRQ3) with dedicated Interrupt Service Routine (ISR) locations:

• IRQ0: ISR at address 128
• IRQ1: ISR at address 153
• IRQ2: ISR at address 178
• IRQ3: ISR at address 203

The interrupt handler uses a scratchpad memory to preserve CPU state (registers and program counter) during interrupt servicing.

📁 Project Structure

VHDL-Project-16-bit-RISC-Processor/
├── VHDL code/
│   ├── fetch.vhd                    # Fetch stage
│   ├── instruction_memory.vhd       # Instruction memory (256×16)
│   ├── pc.vhd                       # Program counter
│   ├── pcresolution.vhd             # PC resolution logic
│   ├── fetdec.vhd                   # Fetch-Decode latch
│   ├── lafetch.vhd                  # Fetch latch
│   ├── decoder.vhd                  # Decoder stage
│   ├── combo.vhd                    # Combinational logic
│   ├── latchdec.vhd                 # Decode-Execute latch
│   ├── execute.vhd                  # Execute stage
│   ├── ram.vhd                      # Register bank
│   ├── aluvala.vhd                  # ALU
│   ├── laexec.vhd                   # Execute-WriteBack latch
│   ├── writeback.vhd                # WriteBack stage
│   ├── MUX2_1.vhd                   # 2:1 Multiplexer
│   ├── data_mem.vhd                 # Data memory
│   ├── scratchpad.vhd               # Interrupt handler scratchpad
│   ├── interrupttrail1.vhd          # Top-level processor
│   └── pipelined1.vhd               # Pipelined processor entity
├── Waveforms/                       # Simulation waveforms
├── Project Report.pdf               # Detailed project documentation
├── Top Level Block Diagram.jpg      # Architecture diagram
└── README.md                        # This file

🔧 Components Description

Fetch Stage Components

• Program Counter (pc.vhd): Increments on each clock cycle; can be modified by ALU or interrupt handler
• Instruction Memory (instruction_memory.vhd): 256×16-bit ROM storing program instructions

Decode Stage Components

• Decoder (decoder.vhd): Decodes 16-bit instructions based on 4-bit opcode
• Scratchpad (scratchpad.vhd): Saves/restores CPU state during interrupt handling

Execute Stage Components

• ALU (aluvala.vhd): Performs arithmetic and logical operations (ADD, SUB, INC, DEC, SHIFT, etc.)
• Register Bank (ram.vhd): 16 general-purpose 8-bit registers

WriteBack Stage Components

• Data Memory (data_mem.vhd): 256×8-bit RAM for data storage
• Multiplexer (MUX2_1.vhd): Selects between direct and indirect addressing modes

🚀 Getting Started

Prerequisites

• Mentor Graphics ModelSim (or compatible VHDL simulator)
• Basic understanding of VHDL and computer architecture

Simulation

1. Clone this repository
2. Open ModelSim and create a new project
3. Add all VHDL files from the VHDL code/ directory
4. Compile the files in the following order:
   • Basic components (RAM, ALU, MUX, memories)
   • Pipeline stage components
   • Latches
   • Top-level entities
5. Load the testbench and run the simulation
6. View waveforms to verify functionality

📊 Instruction Set

The processor supports 27 instructions including:

• Arithmetic: ADD, SUB, INC, DEC
• Logical: AND, OR, XOR, NOT
• Shift: SHL, SHR
• Data Transfer: LOAD, STORE (direct and indirect)
• Control: JUMP, JZ (Jump if Zero), JNZ (Jump if Not Zero)
• Special: SET, CLEAR, PUSH, POP

Refer to Project Report.pdf for complete instruction set details

📈 Verification

All project requirements have been met and verified through simulation:

• ✅ 16-bit instruction set implemented
• ✅ 4-stage pipeline functioning correctly
• ✅ 4 external interrupts handled properly
• ✅ Non-preemptive interrupt handling verified
• ✅ Register bank operations validated
• ✅ Memory access confirmed

Simulation waveforms are available in the Waveforms/ directory.

👨‍💻 Author

Houssem-eddine Lahmer

📄 License

This project is available for educational purposes.

🙏 Acknowledgments

• Designed as part of a digital systems design course
• Simulated using Mentor Graphics ModelSim