This is an adaptation of the UART16550 at https://opencores.org/projects/uart16550 to the IOb-SoC.
Note: This version has a FIFO with 256 bytes.
Note: This version was modified to use a dedicated hardware based control of RTS/CTS signals (software control of these signals is ignored). Therefore, the software should have hardware flow control disabled to avoid issues.
The Py2HWSW workflow allows to automatically generate verilog components used by the projects core Verilog. It allows to create bus interfaces with ease and use existing Verilog modules. To use Py2HWSW the project should have a core_name.py file in the root directory. The main commands to use the Py2HWSW workflow are:
make setup: creates a build directory in the projects parent directory.make clean: removes the build directory.
An example of cleaning a previous build, creating a new build and simulating the project is:
make clean && make setup && make -C ../iob_uart16550_V0.10 sim-run
A FuseSoC-compatible pre-built version of IOb-uart16550 is available in the repository's release page.
The core's Verilog sources are available in the iob_uart16550/hardware/src/ directory of the compressed tar.gz file in the release page.
To use this pre-built core in FuseSoC, extract the compressed tar.gz file to a FuseSoC library directory.
This core is used as part of the SoCLinux project. This project is funded through NGI Zero Core, a fund established by NLnet with financial support from the European Commission's Next Generation Internet program. Learn more at the NLnet project page.
